1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 30, 2010 27.Dt PMC.UCF 3 28.Os 29.Sh NAME 30.Nm pmc.ucf 31.Nd measurement events for 32.Tn Intel 33uncore fixed function performance counters. 34.Sh LIBRARY 35.Lb libpmc 36.Sh SYNOPSIS 37.In pmc.h 38.Sh DESCRIPTION 39Each fixed-function PMC measures a specific hardware event. 40The number of fixed-function PMCs implemented in a CPU can vary. 41The number of fixed-function PMCs present can be determined at runtime 42by using function 43.Xr pmc_cpuinfo 3 . 44.Pp 45Intel uncore fixed-function PMCs are documented in 46.Rs 47.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 48.%T "Volume 3B: System Programming Guide, Part 2" 49.%N "Order Number: 253669-033US" 50.%D December 2009 51.%Q "Intel Corporation" 52.Re 53.Pp 54.Ss PMC Capabilities 55Fixed-function PMCs support the following capabilities: 56.Bl -column "PMC_CAP_INTERRUPT" "Support" 57.It Em Capability Ta Em Support 58.It PMC_CAP_CASCADE Ta \&No 59.It PMC_CAP_EDGE Ta \&No 60.It PMC_CAP_INTERRUPT Ta \&No 61.It PMC_CAP_INVERT Ta \&No 62.It PMC_CAP_READ Ta Yes 63.It PMC_CAP_PRECISE Ta \&No 64.It PMC_CAP_SYSTEM Ta \&No 65.It PMC_CAP_TAGGING Ta \&No 66.It PMC_CAP_THRESHOLD Ta \&No 67.It PMC_CAP_USER Ta \&No 68.It PMC_CAP_WRITE Ta Yes 69.El 70.Ss Class Name Prefix 71These PMCs are named using a class name prefix of 72.Dq Li ucf- . 73.Ss Event Specifiers (Fixed Function PMCs) 74The fixed function PMCs are selectable using the following 75event names: 76.Bl -tag -width indent 77.It Li UCLOCK 78.Pq Fixed Function Counter 0 79The fixed-function uncore counter increments at the rate of the U-clock. 80The frequency of the uncore clock domain can be determined from the uncore 81clock ratio which is available in the PCI configuration space register at 82offset C0H under device number 0 and Function 0. 83.El 84.Sh SEE ALSO 85.Xr pmc 3 , 86.Xr pmc.atom 3 , 87.Xr pmc.core 3 , 88.Xr pmc.core2 3 , 89.Xr pmc.corei7 3 , 90.Xr pmc.corei7uc 3 , 91.Xr pmc.iaf 3 , 92.Xr pmc.k7 3 , 93.Xr pmc.k8 3 , 94.Xr pmc.p4 3 , 95.Xr pmc.p5 3 , 96.Xr pmc.p6 3 , 97.Xr pmc.soft 3 , 98.Xr pmc.tsc 3 , 99.Xr pmc.westmere 3 , 100.Xr pmc.westmereuc 3 , 101.Xr pmc_cpuinfo 3 , 102.Xr pmclog 3 , 103.Xr hwpmc 4 104.Sh HISTORY 105The 106.Nm pmc 107library first appeared in 108.Fx 6.0 . 109.Sh AUTHORS 110The 111.Lb libpmc 112library was written by 113.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 114