1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd March 30, 2010 25.Dt PMC.UCF 3 26.Os 27.Sh NAME 28.Nm pmc.ucf 29.Nd measurement events for 30.Tn Intel 31uncore fixed function performance counters. 32.Sh LIBRARY 33.Lb libpmc 34.Sh SYNOPSIS 35.In pmc.h 36.Sh DESCRIPTION 37Each fixed-function PMC measures a specific hardware event. 38The number of fixed-function PMCs implemented in a CPU can vary. 39The number of fixed-function PMCs present can be determined at runtime 40by using function 41.Xr pmc_cpuinfo 3 . 42.Pp 43Intel uncore fixed-function PMCs are documented in 44.Rs 45.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 46.%T "Volume 3B: System Programming Guide, Part 2" 47.%N "Order Number: 253669-033US" 48.%D December 2009 49.%Q "Intel Corporation" 50.Re 51.Pp 52.Ss PMC Capabilities 53Fixed-function PMCs support the following capabilities: 54.Bl -column "PMC_CAP_INTERRUPT" "Support" 55.It Em Capability Ta Em Support 56.It PMC_CAP_CASCADE Ta \&No 57.It PMC_CAP_EDGE Ta \&No 58.It PMC_CAP_INTERRUPT Ta \&No 59.It PMC_CAP_INVERT Ta \&No 60.It PMC_CAP_READ Ta Yes 61.It PMC_CAP_PRECISE Ta \&No 62.It PMC_CAP_SYSTEM Ta \&No 63.It PMC_CAP_TAGGING Ta \&No 64.It PMC_CAP_THRESHOLD Ta \&No 65.It PMC_CAP_USER Ta \&No 66.It PMC_CAP_WRITE Ta Yes 67.El 68.Ss Class Name Prefix 69These PMCs are named using a class name prefix of 70.Dq Li ucf- . 71.Ss Event Specifiers (Fixed Function PMCs) 72The fixed function PMCs are selectable using the following 73event names: 74.Bl -tag -width indent 75.It Li UCLOCK 76.Pq Fixed Function Counter 0 77The fixed-function uncore counter increments at the rate of the U-clock. 78The frequency of the uncore clock domain can be determined from the uncore 79clock ratio which is available in the PCI configuration space register at 80offset C0H under device number 0 and Function 0. 81.El 82.Sh SEE ALSO 83.Xr pmc 3 , 84.Xr pmc.amd 3 , 85.Xr pmc.atom 3 , 86.Xr pmc.core 3 , 87.Xr pmc.core2 3 , 88.Xr pmc.corei7 3 , 89.Xr pmc.corei7uc 3 , 90.Xr pmc.iaf 3 , 91.Xr pmc.soft 3 , 92.Xr pmc.tsc 3 , 93.Xr pmc.westmere 3 , 94.Xr pmc.westmereuc 3 , 95.Xr pmc_cpuinfo 3 , 96.Xr pmclog 3 , 97.Xr hwpmc 4 98.Sh HISTORY 99The 100.Nm pmc 101library first appeared in 102.Fx 6.0 . 103.Sh AUTHORS 104The 105.Lb libpmc 106library was written by 107.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 108