1.\" Copyright (c) 2012 Hiren Panchasara <hiren.panchasara@gmail.com> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd October 18, 2012 26.Dt PMC.SANDYBRIDGEXEON 3 27.Os 28.Sh NAME 29.Nm pmc.sandybridgexeon 30.Nd measurement events for 31.Tn Intel 32.Tn Sandy Bridge Xeon 33family CPUs 34.Sh LIBRARY 35.Lb libpmc 36.Sh SYNOPSIS 37.In pmc.h 38.Sh DESCRIPTION 39.Tn Intel 40.Tn "Sandy Bridge Xeon" 41CPUs contain PMCs conforming to version 2 of the 42.Tn Intel 43performance measurement architecture. 44These CPUs may contain up to two classes of PMCs: 45.Bl -tag -width "Li PMC_CLASS_IAP" 46.It Li PMC_CLASS_IAF 47Fixed-function counters that count only one hardware event per counter. 48.It Li PMC_CLASS_IAP 49Programmable counters that may be configured to count one of a defined 50set of hardware events. 51.El 52.Pp 53The number of PMCs available in each class and their widths need to be 54determined at run time by calling 55.Xr pmc_cpuinfo 3 . 56.Pp 57Intel Sandy Bridge Xeon PMCs are documented in 58.Rs 59.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 60.%T "Volume 3B: System Programming Guide, Part 2" 61.%N "Order Number: 253669-043US" 62.%D August 2012 63.%Q "Intel Corporation" 64.Re 65.Ss SANDYBRIDGE XEON FIXED FUNCTION PMCS 66These PMCs and their supported events are documented in 67.Xr pmc.iaf 3 . 68.Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS 69The programmable PMCs support the following capabilities: 70.Bl -column "PMC_CAP_INTERRUPT" "Support" 71.It Em Capability Ta Em Support 72.It PMC_CAP_CASCADE Ta \&No 73.It PMC_CAP_EDGE Ta Yes 74.It PMC_CAP_INTERRUPT Ta Yes 75.It PMC_CAP_INVERT Ta Yes 76.It PMC_CAP_READ Ta Yes 77.It PMC_CAP_PRECISE Ta \&No 78.It PMC_CAP_SYSTEM Ta Yes 79.It PMC_CAP_TAGGING Ta \&No 80.It PMC_CAP_THRESHOLD Ta Yes 81.It PMC_CAP_USER Ta Yes 82.It PMC_CAP_WRITE Ta Yes 83.El 84.Ss Event Qualifiers 85Event specifiers for these PMCs support the following common 86qualifiers: 87.Bl -tag -width indent 88.It Li rsp= Ns Ar value 89Configure the Off-core Response bits. 90.Bl -tag -width indent 91.It Li REQ_DMND_DATA_RD 92Counts the number of demand and DCU prefetch data reads of full and partial 93cachelines as well as demand data page table entry cacheline reads. 94Does not count L2 data read prefetches or instruction fetches. 95.It Li REQ_DMND_RFO 96Counts the number of demand and DCU prefetch reads for ownership (RFO) 97requests generated by a write to data cacheline. 98Does not count L2 RFO prefetches. 99.It Li REQ_DMND_IFETCH 100Counts the number of demand and DCU prefetch instruction cacheline reads. 101Does not count L2 code read prefetches. 102.It Li REQ_WB 103Counts the number of writeback (modified to exclusive) transactions. 104.It Li REQ_PF_DATA_RD 105Counts the number of data cacheline reads generated by L2 prefetchers. 106.It Li REQ_PF_RFO 107Counts the number of RFO requests generated by L2 prefetchers. 108.It Li REQ_PF_IFETCH 109Counts the number of code reads generated by L2 prefetchers. 110.It Li REQ_PF_LLC_DATA_RD 111L2 prefetcher to L3 for loads. 112.It Li REQ_PF_LLC_RFO 113RFO requests generated by L2 prefetcher 114.It Li REQ_PF_LLC_IFETCH 115L2 prefetcher to L3 for instruction fetches. 116.It Li REQ_BUS_LOCKS 117Bus lock and split lock requests. 118.It Li REQ_STRM_ST 119Streaming store requests. 120.It Li REQ_OTHER 121Any other request that crosses IDI, including I/O. 122.It Li RES_ANY 123Catch all value for any response types. 124.It Li RES_SUPPLIER_NO_SUPP 125No Supplier Information available. 126.It Li RES_SUPPLIER_LLC_HITM 127M-state initial lookup stat in L3. 128.It Li RES_SUPPLIER_LLC_HITE 129E-state. 130.It Li RES_SUPPLIER_LLC_HITS 131S-state. 132.It Li RES_SUPPLIER_LLC_HITF 133F-state. 134.It Li RES_SUPPLIER_LOCAL 135Local DRAM Controller. 136.It Li RES_SNOOP_SNP_NONE 137No details on snoop-related information. 138.It Li RES_SNOOP_SNP_NO_NEEDED 139No snoop was needed to satisfy the request. 140.It Li RES_SNOOP_SNP_MISS 141A snoop was needed and it missed all snooped caches: 142-For LLC Hit, ReslHitl was returned by all cores 143-For LLC Miss, Rspl was returned by all sockets and data was returned from 144DRAM. 145.It Li RES_SNOOP_HIT_NO_FWD 146A snoop was needed and it hits in at least one snooped cache. 147Hit denotes a cache-line was valid before snoop effect. 148This includes: 149-Snoop Hit w/ Invalidation (LLC Hit, RFO) 150-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 151-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 152In the LLC Miss case, data is returned from DRAM. 153.It Li RES_SNOOP_HIT_FWD 154A snoop was needed and data was forwarded from a remote socket. 155This includes: 156-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 157.It Li RES_SNOOP_HITM 158A snoop was needed and it HitM-ed in local or remote cache. 159HitM denotes a cache-line was in modified state before effect as a results of snoop. 160This includes: 161-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 162-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 163-Snoop MtoS (LLC Hit, IFetch/Data_RD). 164.It Li RES_NON_DRAM 165Target was non-DRAM system address. 166This includes MMIO transactions. 167.El 168.It Li cmask= Ns Ar value 169Configure the PMC to increment only if the number of configured 170events measured in a cycle is greater than or equal to 171.Ar value . 172.It Li edge 173Configure the PMC to count the number of de-asserted to asserted 174transitions of the conditions expressed by the other qualifiers. 175If specified, the counter will increment only once whenever a 176condition becomes true, irrespective of the number of clocks during 177which the condition remains true. 178.It Li inv 179Invert the sense of comparison when the 180.Dq Li cmask 181qualifier is present, making the counter increment when the number of 182events per cycle is less than the value specified by the 183.Dq Li cmask 184qualifier. 185.It Li os 186Configure the PMC to count events happening at processor privilege 187level 0. 188.It Li usr 189Configure the PMC to count events occurring at privilege levels 1, 2 190or 3. 191.El 192.Pp 193If neither of the 194.Dq Li os 195or 196.Dq Li usr 197qualifiers are specified, the default is to enable both. 198.Ss Event Specifiers (Programmable PMCs) 199Sandy Bridge Xeon programmable PMCs support the following events: 200.Bl -tag -width indent 201.It Li LD_BLOCKS.DATA_UNKNOWN 202.Pq Event 03H , Umask 01H 203blocked loads due to store buffer blocks with unknown data. 204.It Li LD_BLOCKS.STORE_FORWARD 205.Pq Event 03H , Umask 02H 206loads blocked by overlapping with store buffer that cannot 207be forwarded . 208.It Li LD_BLOCKS.NO_SR 209.Pq Event 03H , Umask 08H 210# of Split loads blocked due to resource not available. 211.It Li LD_BLOCKS.ALL_BLOCK 212.Pq Event 03H , Umask 10H 213Number of cases where any load is blocked but has no 214DCU miss. 215.It Li MISALIGN_MEM_REF.LOADS 216.Pq Event 05H , Umask 01H 217Speculative cache-line split load uops dispatched to 218L1D. 219.It Li MISALIGN_MEM_REF.STORES 220.Pq Event 05H , Umask 02H 221Speculative cache-line split Store- address uops 222dispatched to L1D. 223.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 224.Pq Event 07H , Umask 01H 225False dependencies in MOB due to partial compare on 226address. 227.It Li LD_BLOCKS_PARTIAL.ALL_STALL_BLOCK 228.Pq Event 07H , Umask 08H 229The number of times that load operations are temporarily 230blocked because of older stores, with addresses that are 231not yet known. 232A load operation may incur more than one block of this type. 233.It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK 234.Pq Event 08H , Umask 01H 235Misses in all TLB levels that cause a page walk of any 236page size. 237.It Li TLB_LOAD_MISSES.WALK_COMPLETED 238.Pq Event 08H , Umask 02H 239Misses in all TLB levels that caused page walk completed 240of any size. 241.It Li DTLB_LOAD_MISSES.WALK_DURATION 242.Pq Event 08H , Umask 04H 243Cycle PMH is busy with a walk. 244.It Li DTLB_LOAD_MISSES.STLB_HIT 245.Pq Event 08H , Umask 10H 246Number of cache load STLB hits. 247No page walk. 248.It Li INT_MISC.RECOVERY_CYCLES 249.Pq Event 0DH , Umask 03H 250Cycles waiting to recover after Machine Clears or EClear. 251Set Cmask= 1. 252.It Li INT_MISC.RAT_STALL_CYCLES 253.Pq Event 0DH , Umask 40H 254Cycles RAT external stall is sent to IDQ for this thread. 255.It Li UOPS_ISSUED.ANY 256.Pq Event 0EH , Umask 01H 257Increments each cycle the # of Uops issued by the 258RAT to RS. 259Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles 260of this core. 261.It Li FP_COMP_OPS_EXE.X87 262.Pq Event 10H , Umask 01H 263Counts number of X87 uops executed. 264.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE 265.Pq Event 10H , Umask 10H 266Counts number of SSE* double precision FP packed 267uops executed. 268.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE 269.Pq Event 10H , Umask 20H 270Counts number of SSE* single precision FP scalar 271uops executed. 272.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE 273.Pq Event 10H , Umask 40H 274Counts number of SSE* single precision FP packed 275uops executed. 276.It Li FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE 277.Pq Event 10H , Umask 80H 278Counts number of SSE* double precision FP scalar 279uops executed. 280.It Li SIMD_FP_256.PACKED_SINGLE 281.Pq Event 11H , Umask 01H 282Counts 256-bit packed single-precision floating- 283point instructions. 284.It Li SIMD_FP_256.PACKED_DOUBLE 285.Pq Event 11H , Umask 02H 286Counts 256-bit packed double-precision floating- 287point instructions. 288.It Li ARITH.FPU_DIV_ACTIVE 289.Pq Event 14H , Umask 01H 290Cycles that the divider is active, includes INT and FP. 291Set 'edge =1, cmask=1' to count the number of 292divides. 293.It Li INSTS_WRITTEN_TO_IQ.INSTS 294.Pq Event 17H , Umask 01H 295Counts the number of instructions written into the 296IQ every cycle. 297.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 298.Pq Event 24H , Umask 01H 299Demand Data Read requests that hit L2 cache. 300.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 301.Pq Event 24H , Umask 03H 302Counts any demand and L1 HW prefetch data load 303requests to L2. 304.It Li L2_RQSTS.RFO_HITS 305.Pq Event 24H , Umask 04H 306Counts the number of store RFO requests that 307hit the L2 cache. 308.It Li L2_RQSTS.RFO_MISS 309.Pq Event 24H , Umask 08H 310Counts the number of store RFO requests that 311miss the L2 cache. 312.It Li L2_RQSTS.ALL_RFO 313.Pq Event 24H , Umask 0CH 314Counts all L2 store RFO requests. 315.It Li L2_RQSTS.CODE_RD_HIT 316.Pq Event 24H , Umask 10H 317Number of instruction fetches that hit the L2 318cache. 319.It Li L2_RQSTS.CODE_RD_MISS 320.Pq Event 24H , Umask 20H 321Number of instruction fetches that missed the L2 322cache. 323.It Li L2_RQSTS.ALL_CODE_RD 324.Pq Event 24H , Umask 30H 325Counts all L2 code requests. 326.It Li L2_RQSTS.PF_HIT 327.Pq Event 24H , Umask 40H 328Requests from L2 Hardware prefetcher that hit L2. 329.It Li L2_RQSTS.PF_MISS 330.Pq Event 24H , Umask 80H 331Requests from L2 Hardware prefetcher that missed 332L2. 333.It Li L2_RQSTS.ALL_PF 334.Pq Event 24H , Umask C0H 335Any requests from L2 Hardware prefetchers. 336.It Li L2_STORE_LOCK_RQSTS.MISS 337.Pq Event 27H , Umask 01H 338ROs that miss cache lines. 339.It Li L2_STORE_LOCK_RQSTS.HIT_E 340.Pq Event 27H , Umask 04H 341RFOs that hit cache lines in E state. 342.It Li L2_STORE_LOCK_RQSTS.HIT_M 343.Pq Event 27H , Umask 08H 344RFOs that hit cache lines in M state. 345.It Li L2_STORE_LOCK_RQSTS.ALL 346.Pq Event 27H , Umask 0FH 347RFOs that access cache lines in any state. 348.It Li L2_L1D_WB_RQSTS.MISS 349.Pq Event 28H , Umask 01H 350Not rejected writebacks from L1D to L2 cache lines 351that missed L2. 352.It Li L2_L1D_WB_RQSTS.HIT_S 353.Pq Event 28H , Umask 02H 354Not rejected writebacks from L1D to L2 cache lines 355in S state. 356.It Li L2_L1D_WB_RQSTS.HIT_E 357.Pq Event 28H , Umask 04H 358Not rejected writebacks from L1D to L2 cache lines 359in E state. 360.It Li L2_L1D_WB_RQSTS.HIT_M 361.Pq Event 28H , Umask 08H 362Not rejected writebacks from L1D to L2 cache lines 363in M state. 364.It Li L2_L1D_WB_RQSTS.ALL 365.Pq Event 28H , Umask 0FH 366Not rejected writebacks from L1D to L2 cache. 367.It Li LONGEST_LAT_CACHE.REFERENCE 368.Pq Event 2EH , Umask 4FH 369This event counts requests originating from the 370core that reference 371a cache line in the last level cache. 372.It Li LONGEST_LAT_CACHE.MISS 373.Pq Event 2EH , Umask 41H 374This event counts each cache miss condition for 375references to the last level cache. 376.It Li CPU_CLK_UNHALTED.THREAD_P 377.Pq Event 3CH , Umask 00H 378Counts the number of thread cycles while the 379thread is not in a halt state. 380The thread enters the halt state when it is running the HLT 381instruction. 382The core frequency may change from time to time due to power or thermal throttling. 383.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 384.Pq Event 3CH , Umask 01H 385Increments at the frequency of XCLK (100 MHz) 386when not halted. 387.It Li L1D_PEND_MISS.PENDING 388.Pq Event 48H , Umask 01H 389Increments the number of outstanding L1D misses 390every cycle. 391Set Cmaks = 1 and Edge =1 to count occurrences. 392.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 393.Pq Event 49H , Umask 01H 394Miss in all TLB levels causes an page walk of 395any page size (4K/2M/4M/1G). 396.It Li DTLB_STORE_MISSES.WALK_COMPLETED 397.Pq Event 49H , Umask 02H 398Miss in all TLB levels causes a page walk that 399completes of any page size (4K/2M/4M/1G). 400.It Li DTLB_STORE_MISSES.WALK_DURATION 401.Pq Event 49H , Umask 04H 402Cycles PMH is busy with this walk. 403.It Li DTLB_STORE_MISSES.STLB_HIT 404.Pq Event 49H , Umask 10H 405Store operations that miss the first TLB level 406but hit the second and do not cause page walks. 407.It Li LOAD_HIT_PRE.SW_PF 408.Pq Event 4CH , Umask 01H 409Not SW-prefetch load dispatches that hit fill 410buffer allocated for S/W prefetch. 411.It Li LOAD_HIT_PER.HW_PF 412.Pq Event 4CH , Umask 02H 413Not SW-prefetch load dispatches that hit fill 414buffer allocated for H/W prefetch. 415.It Li HW_PRE_REQ.DL1_MISS 416.Pq Event 4EH , Umask 02H 417Hardware Prefetch requests that miss the L1D cache. 418A request is being counted each time it access the cache 419& miss it, including if a block is applicable or if hit the Fill 420Buffer for example. 421.It Li L1D.REPLACEMENT 422.Pq Event 51H , Umask 01H 423Counts the number of lines brought into the 424L1 data cache. 425.It Li L1D.ALLOCATED_IN_M 426.Pq Event 51H , Umask 02H 427Counts the number of allocations of modified 428L1D cache lines. 429.It Li L1D.EVICTION 430.Pq Event 51H , Umask 04H 431Counts the number of modified lines evicted 432from the L1 data cache due to replacement. 433.It Li L1D.ALL_M_REPLACEMENT 434.Pq Event 51H , Umask 08H 435Cache lines in M state evicted out of L1D due 436to Snoop HitM or dirty line replacement. 437.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP 438.Pq Event 59H , Umask 0CH 439Increments the number of flags-merge uops in 440flight each cycle. 441Set Cmask = 1 to count cycles. 442.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW 443.Pq Event 59H , Umask 0FH 444Cycles with at least one slow LEA uop allocated. 445.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP 446.Pq Event 59H , Umask 40H 447Number of Multiply packed/scalar single precision 448uops allocated. 449.It Li RESOURCE_STALLS2.ALL_FL_EMPTY 450.Pq Event 5BH , Umask 0CH 451Cycles stalled due to free list empty. 452.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL 453.Pq Event 5BH , Umask 0FH 454Cycles stalled due to control structures full for 455physical registers. 456.It Li RESOURCE_STALLS2.BOB_FULL 457.Pq Event 5BH , Umask 40H 458Cycles Allocator is stalled due Branch Order Buffer. 459.It Li RESOURCE_STALLS2.OOO_RSRC 460.Pq Event 5BH , Umask 4FH 461Cycles stalled due to out of order resources full. 462.It Li CPL_CYCLES.RING0 463.Pq Event 5CH , Umask 01H 464Unhalted core cycles when the thread is in ring 0. 465.It Li CPL_CYCLES.RING123 466.Pq Event 5CH , Umask 02H 467Unhalted core cycles when the thread is not in ring 4680. 469.It Li RS_EVENTS.EMPTY_CYCLES 470.Pq Event 5EH , Umask 01H 471Cycles the RS is empty for the thread. 472.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 473.Pq Event 60H , Umask 01H 474Offcore outstanding Demand Data Read 475transactions in SQ to uncore. 476Set Cmask=1 to count cycles. 477.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 478.Pq Event 60H , Umask 04H 479Offcore outstanding RFO store transactions in SQ to 480uncore. 481Set Cmask=1 to count cycles. 482.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 483.Pq Event 60H , Umask 08H 484Offcore outstanding cacheable data read 485transactions in SQ to uncore. 486Set Cmask=1 to count cycles. 487.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 488.Pq Event 63H , Umask 01H 489Cycles in which the L1D and L2 are locked, due to a 490UC lock or split lock. 491.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 492.Pq Event 63H , Umask 02H 493Cycles in which the L1D is locked. 494.It Li IDQ.EMPTY 495.Pq Event 79H , Umask 02H 496Counts cycles the IDQ is empty. 497.It Li IDQ.MITE_UOPS 498.Pq Event 79H , Umask 04H 499Increment each cycle # of uops delivered to IDQ 500from MITE path. 501Set Cmask = 1 to count cycles. 502.It Li IDQ.DSB_UOPS 503.Pq Event 79H , Umask 08H 504Increment each cycle. # of uops delivered to IDQ 505from DSB path. 506Set Cmask = 1 to count cycles. 507.It Li IDQ.MS_DSB_UOPS 508.Pq Event 79H , Umask 10H 509Increment each cycle # of uops delivered to IDQ 510when MS busy by DSB. 511Set Cmask = 1 to count cycles MS is busy. 512Set Cmask=1 and Edge =1 to count MS activations. 513.It Li IDQ.MS_MITE_UOPS 514.Pq Event 79H , Umask 20H 515Increment each cycle # of uops delivered to IDQ 516when MS is busy by MITE. 517Set Cmask = 1 to count cycles. 518.It Li IDQ.MS_UOPS 519.Pq Event 79H , Umask 30H 520Increment each cycle # of uops delivered to IDQ 521from MS by either DSB or MITE. 522Set Cmask = 1 to count cycles. 523.It Li ICACHE.MISSES 524.Pq Event 80H , Umask 02H 525Number of Instruction Cache, Streaming Buffer and 526Victim Cache Misses. 527Includes UC accesses. 528.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 529.Pq Event 85H , Umask 01H 530Misses in all ITLB levels that cause page walks. 531.It Li ITLB_MISSES.WALK_COMPLETED 532.Pq Event 85H , Umask 02H 533Misses in all ITLB levels that cause completed page 534walks. 535.It Li ITLB_MISSES.WALK_DURATION 536.Pq Event 85H , Umask 04H 537Cycle PMH is busy with a walk. 538.It Li ITLB_MISSES.STLB_HIT 539.Pq Event 85H , Umask 10H 540Number of cache load STLB hits. 541No page walk. 542.It Li ILD_STALL.LCP 543.Pq Event 87H , Umask 01H 544Stalls caused by changing prefix length of the 545instruction. 546.It Li ILD_STALL.IQ_FULL 547.Pq Event 87H , Umask 04H 548Stall cycles due to IQ is full. 549.It Li BR_INST_EXEC.NONTAKEN_COND 550.Pq Event 88H , Umask 41H 551Count conditional near branch instructions that were executed (but not 552necessarily retired) and not taken. 553.It Li BR_INST_EXEC.TAKEN_COND 554.Pq Event 88H , Umask 81H 555Count conditional near branch instructions that were executed (but not 556necessarily retired) and taken. 557.It Li BR_INST_EXEC.DIRECT_JMP 558.Pq Event 88H , Umask 82H 559Count all unconditional near branch instructions excluding calls and 560indirect branches. 561.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 562.Pq Event 88H , Umask 84H 563Count executed indirect near branch instructions that are not calls nor 564returns. 565.It Li BR_INST_EXEC.RETURN_NEAR 566.Pq Event 88H , Umask 88H 567Count indirect near branches that have a return mnemonic. 568.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 569.Pq Event 88H , Umask 90H 570Count unconditional near call branch instructions, excluding non call 571branch, executed. 572.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 573.Pq Event 88H , Umask A0H 574Count indirect near calls, including both register and memory indirect, 575executed. 576.It Li BR_INST_EXEC.ALL_BRANCHES 577.Pq Event 88H , Umask FFH 578Counts all near executed branches (not necessarily retired). 579.It Li BR_MISP_EXEC.NONTAKEN_COND 580.Pq Event 89H , Umask 41H 581Count conditional near branch instructions mispredicted as nontaken. 582.It Li BR_MISP_EXEC.TAKEN_COND 583.Pq Event 89H , Umask 81H 584Count conditional near branch instructions mispredicted as taken. 585.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 586.Pq Event 89H , Umask 84H 587Count mispredicted indirect near branch instructions that are not calls 588nor returns. 589.It Li BR_MISP_EXEC.RETURN_NEAR 590.Pq Event 89H , Umask 88H 591Count mispredicted indirect near branches that have a return mnemonic. 592.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 593.Pq Event 89H , Umask 90H 594Count mispredicted unconditional near call branch instructions, excluding 595non call branch, executed. 596.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 597.Pq Event 89H , Umask A0H 598Count mispredicted indirect near calls, including both register and memory 599indirect, executed. 600.It Li BR_MISP_EXEC.ALL_BRANCHES 601.Pq Event 89H , Umask FFH 602Counts all mispredicted near executed branches (not necessarily retired). 603.It Li IDQ_UOPS_NOT_DELIVERED.CORE 604.Pq Event 9CH , Umask 01H 605Count number of non-delivered uops to RAT per 606thread. 607.It Li UOPS_DISPATCHED_PORT.PORT_0 608.Pq Event A1H , Umask 01H 609Cycles which a Uop is dispatched on port 0. 610.It Li UOPS_DISPATCHED_PORT.PORT_1 611.Pq Event A1H , Umask 02H 612Cycles which a Uop is dispatched on port 1. 613.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 614.Pq Event A1H , Umask 04H 615Cycles which a load uop is dispatched on port 2. 616.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 617.Pq Event A1H , Umask 08H 618Cycles which a store address uop is dispatched on 619port 2. 620.It Li UOPS_DISPATCHED_PORT.PORT_2 621.Pq Event A1H , Umask 0CH 622Cycles which a Uop is dispatched on port 2. 623.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 624.Pq Event A1H , Umask 10H 625Cycles which a load uop is dispatched on port 3. 626.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 627.Pq Event A1H , Umask 20H 628Cycles which a store address uop is dispatched on 629port 3. 630.It Li UOPS_DISPATCHED_PORT.PORT_3 631.Pq Event A1H , Umask 30H 632Cycles which a Uop is dispatched on port 3. 633.It Li UOPS_DISPATCHED_PORT.PORT_4 634.Pq Event A1H , Umask 40H 635Cycles which a Uop is dispatched on port 4. 636.It Li UOPS_DISPATCHED_PORT.PORT_5 637.Pq Event A1H , Umask 80H 638Cycles which a Uop is dispatched on port 5. 639.It Li RESOURCE_STALLS.ANY 640.Pq Event A2H , Umask 01H 641Cycles Allocation is stalled due to Resource Related 642reason. 643.It Li RESOURCE_STALLS.LB 644.Pq Event A2H , Umask 01H 645Counts the cycles of stall due to lack of load buffers. 646.It Li RESOURCE_STALLS.RS 647.Pq Event A2H , Umask 04H 648Cycles stalled due to no eligible RS entry available. 649.It Li RESOURCE_STALLS.SB 650.Pq Event A2H , Umask 08H 651Cycles stalled due to no store buffers available. 652(not including draining form sync). 653.It Li RESOURCE_STALLS.ROB 654.Pq Event A2H , Umask 10H 655Cycles stalled due to re-order buffer full. 656.It Li RESOURCE_STALLS.FCSW 657.Pq Event A2H , Umask 20H 658Cycles stalled due to writing the FPU control word. 659.It Li RESOURCE_STALLS.MXCSR 660.Pq Event A2H , Umask 40H 661Cycles stalled due to the MXCSR register rename 662occurring to close to a previous MXCSR rename. 663.It Li RESOURCE_STALLS.OTHER 664.Pq Event A2H , Umask 80H 665Cycles stalled while execution was stalled due to 666other resource issues. 667.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 668.Pq Event A3H , Umask 01H 669Cycles with pending L2 miss loads. 670Set AnyThread to count per core. 671.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 672.Pq Event A3H , Umask 02H 673Cycles with pending L1 cache miss loads. 674Set AnyThread to count per core. 675.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH 676.Pq Event A3H , Umask 04H 677Cycles of dispatch stalls. 678Set AnyThread to count per core. 679.It Li DSB2MITE_SWITCHES.COUNT 680.Pq Event ABH , Umask 01H 681Number of DSB to MITE switches. 682.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 683.Pq Event ABH , Umask 02H 684Cycles DSB to MITE switches caused delay. 685.It Li DSB_FILL.OTHER_CANCEL 686.Pq Event ACH , Umask 02H 687Cases of cancelling valid DSB fill not because of 688exceeding way limit. 689.It Li DSB_FILL.EXCEED_DSB_LINES 690.Pq Event ACH , Umask 08H 691DSB Fill encountered > 3 DSB lines. 692.It Li DSB_FILL.ALL_CANCEL 693.Pq Event ACH , Umask 0AH 694Cases of cancelling valid Decode Stream Buffer 695(DSB) fill not because of exceeding way limit. 696.It Li ITLB.ITLB_FLUSH 697.Pq Event AEH , Umask 01H 698Counts the number of ITLB flushes, includes 6994k/2M/4M pages. 700.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 701.Pq Event B0H , Umask 01H 702Demand data read requests sent to uncore. 703.It Li OFFCORE_REQUESTS.DEMAND_RFO 704.Pq Event B0H , Umask 04H 705Demand RFO read requests sent to uncore, including 706regular RFOs, locks, ItoM. 707.It Li OFFCORE_REQUESTS.ALL_DATA_RD 708.Pq Event B0H , Umask 08H 709Data read requests sent to uncore (demand and 710prefetch). 711.It Li UOPS_DISPATCHED.THREAD 712.Pq Event B1H , Umask 01H 713Counts total number of uops to be dispatched per- 714thread each cycle. 715Set Cmask = 1, INV =1 to count stall cycles. 716.It Li UOPS_DISPATCHED.CORE 717.Pq Event B1H , Umask 02H 718Counts total number of uops to be dispatched per- 719core each cycle. 720.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL 721.Pq Event B2H , Umask 01H 722Offcore requests buffer cannot take more entries 723for this thread core. 724.It Li AGU_BYPASS_CANCEL.COUNT 725.Pq Event B6H , Umask 01H 726Counts executed load operations with all the 727following traits: 1. addressing of the format [base + 728offset], 2. the offset is between 1 and 2047, 3. the 729address specified in the base register is in one page 730and the address [base+offset] is in another page. 731.It Li OFF_CORE_RESPONSE_0 732.Pq Event B7H , Umask 01H 733(Event B7H, Umask 01H) Off-core Response Performance 734Monitoring; PMC0 only. 735Requires programming MSR 01A6H 736.It Li OFF_CORE_RESPONSE_1 737.Pq Event BBH , Umask 01H 738(Event BBH, Umask 01H) Off-core Response Performance 739Monitoring; PMC3 only. 740Requires programming MSR 01A7H 741.It Li TLB_FLUSH.DTLB_THREAD 742.Pq Event BDH , Umask 01H 743DTLB flush attempts of the thread-specific entries. 744.It Li TLB_FLUSH.STLB_ANY 745.Pq Event BDH , Umask 20H 746Count number of STLB flush attempts. 747.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES 748.Pq Event BFH , Umask 05H 749Cycles when dispatched loads are cancelled due to 750L1D bank conflicts with other load ports. 751.It Li INST_RETIRED.ANY_P 752.Pq Event C0H , Umask 00H 753Number of instructions at retirement. 754.It Li INST_RETIRED.ALL 755.Pq Event C0H , Umask 01H 756Precise instruction retired event with HW to reduce 757effect of PEBS shadow in IP distribution. 758.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED 759.Pq Event C1H , Umask 02H 760Instructions that experienced an ITLB miss. 761.It Li OTHER_ASSISTS.AVX_STORE 762.Pq Event C1H , Umask 08H 763Number of assists associated with 256-bit AVX 764store operations. 765.It Li OTHER_ASSISTS.AVX_TO_SSE 766.Pq Event C1H , Umask 10H 767Number of transitions from AVX-256 to legacy SSE 768when penalty applicable. 769.It Li OTHER_ASSISTS.SSE_TO_AVX 770.Pq Event C1H , Umask 20H 771Number of transitions from SSE to AVX-256 when 772penalty applicable. 773.It Li UOPS_RETIRED.ALL 774.Pq Event C2H , Umask 01H 775Counts the number of micro-ops retired, Use 776cmask=1 and invert to count active cycles or stalled 777cycles. 778.It Li UOPS_RETIRED.RETIRE_SLOTS 779.Pq Event C2H , Umask 02H 780Counts the number of retirement slots used each 781cycle. 782.It Li MACHINE_CLEARS.MEMORY_ORDERING 783.Pq Event C3H , Umask 02H 784Counts the number of machine clears due to 785memory order conflicts. 786.It Li MACHINE_CLEARS.SMC 787.Pq Event C3H , Umask 04H 788Counts the number of times that a program writes 789to a code section. 790.It Li MACHINE_CLEARS.MASKMOV 791.Pq Event C3H , Umask 20H 792Counts the number of executed AVX masked load 793operations that refer to an illegal address range 794with the mask bits set to 0. 795.It Li BR_INST_RETIRED.ALL_BRANCH 796.Pq Event C4H , Umask 00H 797Branch instructions at retirement. 798.It Li BR_INST_RETIRED.CONDITIONAL 799.Pq Event C4H , Umask 01H 800Counts the number of conditional branch 801instructions retired. 802.It Li BR_INST_RETIRED.NEAR_CALL 803.Pq Event C4H , Umask 02H 804Direct and indirect near call instructions retired. 805.It Li BR_INST_RETIRED.ALL_BRANCHES 806.Pq Event C4H , Umask 04H 807Counts the number of branch instructions retired. 808.It Li BR_INST_RETIRED.NEAR_RETURN 809.Pq Event C4H , Umask 08H 810Counts the number of near return instructions 811retired. 812.It Li BR_INST_RETIRED.NOT_TAKEN 813.Pq Event C4H , Umask 10H 814Counts the number of not taken branch instructions 815retired. 816.It Li BR_INST_RETIRED.NEAR_TAKEN 817.Pq Event C4H , Umask 20H 818Number of near taken branches retired. 819.It Li BR_INST_RETIRED.FAR_BRANCH 820.Pq Event C4H , Umask 40H 821Number of far branches retired. 822.It Li BR_MISP_RETIRED.ALL_BRANCHES 823.Pq Event C5H , Umask 00H 824Mispredicted branch instructions at retirement. 825.It Li BR_MISP_RETIRED.CONDITIONAL 826.Pq Event C5H , Umask 01H 827Mispredicted conditional branch instructions retired. 828.It Li BR_MISP_RETIRED.NEAR_CALL 829.Pq Event C5H , Umask 02H 830Direct and indirect mispredicted near call 831instructions retired. 832.It Li BR_MISP_RETIRED.ALL_BRANCHES 833.Pq Event C5H , Umask 04H 834Mispredicted macro branch instructions retired. 835.It Li BR_MISP_RETIRED.NOT_TAKEN 836.Pq Event C5H , Umask 10H 837Mispredicted not taken branch instructions retired. 838.It Li BR_MISP_RETIRED.TAKEN 839.Pq Event C5H , Umask 20H 840Mispredicted taken branch instructions retired. 841.It Li FP_ASSIST.X87_OUTPUT 842.Pq Event CAH , Umask 02H 843Number of X87 assists due to output value. 844.It Li FP_ASSIST.X87_INPUT 845.Pq Event CAH , Umask 04H 846Number of X87 assists due to input value. 847.It Li FP_ASSIST.SIMD_OUTPUT 848.Pq Event CAH , Umask 08H 849 Number of SIMD FP assists due to output values. 850.It Li FP_ASSIST.SIMD_INPUT 851.Pq Event CAH , Umask 10H 852Number of SIMD FP assists due to input values. 853.It Li FP_ASSIST.ANY 1EH 854.Pq Event CAH , Umask 855Cycles with any input/output SSE* or FP assists. 856.It Li ROB_MISC_EVENTS.LBR_INSERTS 857.Pq Event CCH , Umask 20H 858Count cases of saving new LBR records by 859hardware. 860.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 861.Pq Event CDH , Umask 01H 862Sample loads with specified latency threshold. 863PMC3 only. 864.It Li MEM_TRANS_RETIRED.PRECISE_STORE 865.Pq Event CDH , Umask 02H 866Sample stores and collect precise store operation 867via PEBS record. 868PMC3 only. 869.It Li MEM_UOP_RETIRED.LOADS 870.Pq Event D0H , Umask 10H 871Qualify retired memory uops that are loads. 872Combine with umask 10H, 20H, 40H, 80H. 873.It Li MEM_UOP_RETIRED.STORES 874.Pq Event D0H , Umask 02H 875Qualify retired memory uops that are stores. 876Combine with umask 10H, 20H, 40H, 80H. 877.It Li MEM_UOP_RETIRED.STLB_MISS 878.Pq Event D0H , Umask 879Qualify retired memory uops with STLB miss. 880Must combine with umask 01H, 02H, to produce counts. 881.It Li MEM_UOP_RETIRED.LOCK 882.Pq Event D0H , Umask 883Qualify retired memory uops with lock. 884Must combine with umask 01H, 02H, to produce counts. 885.It Li MEM_UOP_RETIRED.SPLIT 886.Pq Event D0H , Umask 887Qualify retired memory uops with line split. 888Must combine with umask 01H, 02H, to produce counts. 889.It Li MEM_UOP_RETIRED_ALL 890.Pq Event D0H , Umask 891Qualify any retired memory uops. 892Must combine with umask 01H, 02H, to produce counts. 893.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 894.Pq Event D1H , Umask 01H 895Retired load uops with L1 cache hits as data 896sources. 897.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 898.Pq Event D1H , Umask 02H 899Retired load uops with L2 cache hits as data 900sources. 901.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 902.Pq Event D1H , Umask 04H 903Retired load uops which data sources were data hits 904in LLC without snoops required. 905.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS 906.Pq Event D1H , Umask 20H 907Retired load uops which data sources were data 908missed LLC (excluding unknown data source). 909.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 910.Pq Event D1H , Umask 40H 911Retired load uops which data sources were load 912uops missed L1 but hit FB due to preceding miss to 913the same cache line with data not ready. 914.It Li MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS 915.Pq Event D4H , Umask 02H 916Retired load uops with unknown information as data 917source in cache serviced the load. 918.It Li BACLEARS.ANY 919.Pq Event E6H , Umask 01H 920Counts the number of times the front end is re- 921steered, mainly when the BPU cannot provide a 922correct prediction and this is corrected by other 923branch handling mechanisms at the front end. 924.It Li L2_TRANS.DEMAND_DATA_RD 925.Pq Event F0H , Umask 01H 926Demand Data Read requests that access L2 cache. 927.It Li L2_TRANS.RFO 928.Pq Event F0H , Umask 02H 929RFO requests that access L2 cache. 930.It Li L2_TRANS.CODE_RD 931.Pq Event F0H , Umask 04H 932L2 cache accesses when fetching instructions. 933.It Li L2_TRANS.ALL_PF 934.Pq Event F0H , Umask 08H 935L2 or LLC HW prefetches that access L2 cache. 936.It Li L2_TRANS.L1D_WB 937.Pq Event F0H , Umask 10H 938L1D writebacks that access L2 cache. 939.It Li L2_TRANS.L2_FILL 940.Pq Event F0H , Umask 20H 941L2 fill requests that access L2 cache. 942.It Li L2_TRANS.L2_WB 943.Pq Event F0H , Umask 40H 944L2 writebacks that access L2 cache. 945.It Li L2_TRANS.ALL_REQUESTS 946.Pq Event F0H , Umask 80H 947Transactions accessing L2 pipe. 948.It Li L2_LINES_IN.I 949.Pq Event F1H , Umask 01H 950L2 cache lines in I state filling L2. 951.It Li L2_LINES_IN.S 952.Pq Event F1H , Umask 02H 953L2 cache lines in S state filling L2. 954.It Li L2_LINES_IN.E 955.Pq Event F1H , Umask 04H 956L2 cache lines in E state filling L2. 957.It Li L2_LINES-IN.ALL 958.Pq Event F1H , Umask 07H 959L2 cache lines filling L2. 960.It Li L2_LINES_OUT.DEMAND_CLEAN 961.Pq Event F2H , Umask 01H 962Clean L2 cache lines evicted by demand. 963.It Li L2_LINES_OUT.DEMAND_DIRTY 964.Pq Event F2H , Umask 02H 965Dirty L2 cache lines evicted by demand. 966.It Li L2_LINES_OUT.PF_CLEAN 967.Pq Event F2H , Umask 04H 968Clean L2 cache lines evicted by L2 prefetch. 969.It Li L2_LINES_OUT.PF_DIRTY 970.Pq Event F2H , Umask 08H 971Dirty L2 cache lines evicted by L2 prefetch. 972.It Li L2_LINES_OUT.DIRTY_ALL 973.Pq Event F2H , Umask 0AH 974Dirty L2 cache lines filling the L2. 975.It Li SQ_MISC.SPLIT_LOCK 976.Pq Event F4H , Umask 10H 977Split locks in SQ. 978.El 979.Sh SEE ALSO 980.Xr pmc 3 , 981.Xr pmc.amd 3 , 982.Xr pmc.atom 3 , 983.Xr pmc.core 3 , 984.Xr pmc.corei7 3 , 985.Xr pmc.corei7uc 3 , 986.Xr pmc.haswelluc 3 , 987.Xr pmc.iaf 3 , 988.Xr pmc.ivybridge 3 , 989.Xr pmc.ivybridgexeon 3 , 990.Xr pmc.sandybridge 3 , 991.Xr pmc.sandybridgeuc 3 , 992.Xr pmc.soft 3 , 993.Xr pmc.tsc 3 , 994.Xr pmc.ucf 3 , 995.Xr pmc.westmere 3 , 996.Xr pmc.westmereuc 3 , 997.Xr pmc_cpuinfo 3 , 998.Xr pmclog 3 , 999.Xr hwpmc 4 1000.Sh HISTORY 1001The 1002.Nm pmc 1003library first appeared in 1004.Fx 6.0 . 1005.Sh AUTHORS 1006.An -nosplit 1007The 1008.Lb libpmc 1009library was written by 1010.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1011The support for the Sandy Bridge Xeon 1012microarchitecture was written by 1013.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 1014