1fabe02f5SSean Bruno.\" Copyright (c) 2012 Hiren Panchasara <hiren.panchasara@gmail.com> 2fabe02f5SSean Bruno.\" All rights reserved. 3fabe02f5SSean Bruno.\" 4fabe02f5SSean Bruno.\" Redistribution and use in source and binary forms, with or without 5fabe02f5SSean Bruno.\" modification, are permitted provided that the following conditions 6fabe02f5SSean Bruno.\" are met: 7fabe02f5SSean Bruno.\" 1. Redistributions of source code must retain the above copyright 8fabe02f5SSean Bruno.\" notice, this list of conditions and the following disclaimer. 9fabe02f5SSean Bruno.\" 2. Redistributions in binary form must reproduce the above copyright 10fabe02f5SSean Bruno.\" notice, this list of conditions and the following disclaimer in the 11fabe02f5SSean Bruno.\" documentation and/or other materials provided with the distribution. 12fabe02f5SSean Bruno.\" 13fabe02f5SSean Bruno.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14fabe02f5SSean Bruno.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15fabe02f5SSean Bruno.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16fabe02f5SSean Bruno.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17fabe02f5SSean Bruno.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18fabe02f5SSean Bruno.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19fabe02f5SSean Bruno.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20fabe02f5SSean Bruno.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21fabe02f5SSean Bruno.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22fabe02f5SSean Bruno.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23fabe02f5SSean Bruno.\" SUCH DAMAGE. 24fabe02f5SSean Bruno.\" 25fabe02f5SSean Bruno.\" $FreeBSD$ 26fabe02f5SSean Bruno.\" 27fabe02f5SSean Bruno.Dd October 18, 2012 28fabe02f5SSean Bruno.Dt PMC.SANDYBRIDGEXEON 3 29fabe02f5SSean Bruno.Os 30fabe02f5SSean Bruno.Sh NAME 31fabe02f5SSean Bruno.Nm pmc.sandybridgexeon 32fabe02f5SSean Bruno.Nd measurement events for 33fabe02f5SSean Bruno.Tn Intel 34fabe02f5SSean Bruno.Tn Sandy Bridge Xeon 35fabe02f5SSean Brunofamily CPUs 36fabe02f5SSean Bruno.Sh LIBRARY 37fabe02f5SSean Bruno.Lb libpmc 38fabe02f5SSean Bruno.Sh SYNOPSIS 39fabe02f5SSean Bruno.In pmc.h 40fabe02f5SSean Bruno.Sh DESCRIPTION 41fabe02f5SSean Bruno.Tn Intel 42fabe02f5SSean Bruno.Tn "Sandy Bridge Xeon" 43fabe02f5SSean BrunoCPUs contain PMCs conforming to version 2 of the 44fabe02f5SSean Bruno.Tn Intel 45fabe02f5SSean Brunoperformance measurement architecture. 46fabe02f5SSean BrunoThese CPUs may contain up to two classes of PMCs: 47fabe02f5SSean Bruno.Bl -tag -width "Li PMC_CLASS_IAP" 48fabe02f5SSean Bruno.It Li PMC_CLASS_IAF 49fabe02f5SSean BrunoFixed-function counters that count only one hardware event per counter. 50fabe02f5SSean Bruno.It Li PMC_CLASS_IAP 51fabe02f5SSean BrunoProgrammable counters that may be configured to count one of a defined 52fabe02f5SSean Brunoset of hardware events. 53fabe02f5SSean Bruno.El 54fabe02f5SSean Bruno.Pp 55fabe02f5SSean BrunoThe number of PMCs available in each class and their widths need to be 56fabe02f5SSean Brunodetermined at run time by calling 57fabe02f5SSean Bruno.Xr pmc_cpuinfo 3 . 58fabe02f5SSean Bruno.Pp 59fabe02f5SSean BrunoIntel Sandy Bridge Xeon PMCs are documented in 60fabe02f5SSean Bruno.Rs 61fabe02f5SSean Bruno.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62fabe02f5SSean Bruno.%T "Volume 3B: System Programming Guide, Part 2" 63fabe02f5SSean Bruno.%N "Order Number: 253669-043US" 64fabe02f5SSean Bruno.%D August 2012 65fabe02f5SSean Bruno.%Q "Intel Corporation" 66fabe02f5SSean Bruno.Re 67fabe02f5SSean Bruno.Ss SANDYBRIDGE XEON FIXED FUNCTION PMCS 68fabe02f5SSean BrunoThese PMCs and their supported events are documented in 69fabe02f5SSean Bruno.Xr pmc.iaf 3 . 70fabe02f5SSean Bruno.Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS 71fabe02f5SSean BrunoThe programmable PMCs support the following capabilities: 72fabe02f5SSean Bruno.Bl -column "PMC_CAP_INTERRUPT" "Support" 73fabe02f5SSean Bruno.It Em Capability Ta Em Support 74fabe02f5SSean Bruno.It PMC_CAP_CASCADE Ta \&No 75fabe02f5SSean Bruno.It PMC_CAP_EDGE Ta Yes 76fabe02f5SSean Bruno.It PMC_CAP_INTERRUPT Ta Yes 77fabe02f5SSean Bruno.It PMC_CAP_INVERT Ta Yes 78fabe02f5SSean Bruno.It PMC_CAP_READ Ta Yes 79fabe02f5SSean Bruno.It PMC_CAP_PRECISE Ta \&No 80fabe02f5SSean Bruno.It PMC_CAP_SYSTEM Ta Yes 81fabe02f5SSean Bruno.It PMC_CAP_TAGGING Ta \&No 82fabe02f5SSean Bruno.It PMC_CAP_THRESHOLD Ta Yes 83fabe02f5SSean Bruno.It PMC_CAP_USER Ta Yes 84fabe02f5SSean Bruno.It PMC_CAP_WRITE Ta Yes 85fabe02f5SSean Bruno.El 86fabe02f5SSean Bruno.Ss Event Qualifiers 87fabe02f5SSean BrunoEvent specifiers for these PMCs support the following common 88fabe02f5SSean Brunoqualifiers: 89fabe02f5SSean Bruno.Bl -tag -width indent 90fabe02f5SSean Bruno.It Li rsp= Ns Ar value 91fabe02f5SSean BrunoConfigure the Off-core Response bits. 92fabe02f5SSean Bruno.Bl -tag -width indent 93fabe02f5SSean Bruno.It Li REQ_DMND_DATA_RD 94fabe02f5SSean BrunoCounts the number of demand and DCU prefetch data reads of full and partial 95fabe02f5SSean Brunocachelines as well as demand data page table entry cacheline reads. Does not 96fabe02f5SSean Brunocount L2 data read prefetches or instruction fetches. 97fabe02f5SSean Bruno.It Li REQ_DMND_RFO 98fabe02f5SSean BrunoCounts the number of demand and DCU prefetch reads for ownership (RFO) 99fabe02f5SSean Brunorequests generated by a write to data cacheline. Does not count L2 RFO 100fabe02f5SSean Brunoprefetches. 101fabe02f5SSean Bruno.It Li REQ_DMND_IFETCH 102fabe02f5SSean BrunoCounts the number of demand and DCU prefetch instruction cacheline reads. 103fabe02f5SSean BrunoDoes not count L2 code read prefetches. 104fabe02f5SSean Bruno.It Li REQ_WB 105fabe02f5SSean BrunoCounts the number of writeback (modified to exclusive) transactions. 106fabe02f5SSean Bruno.It Li REQ_PF_DATA_RD 107fabe02f5SSean BrunoCounts the number of data cacheline reads generated by L2 prefetchers. 108fabe02f5SSean Bruno.It Li REQ_PF_RFO 109fabe02f5SSean BrunoCounts the number of RFO requests generated by L2 prefetchers. 110fabe02f5SSean Bruno.It Li REQ_PF_IFETCH 111fabe02f5SSean BrunoCounts the number of code reads generated by L2 prefetchers. 112fabe02f5SSean Bruno.It Li REQ_PF_LLC_DATA_RD 113fabe02f5SSean BrunoL2 prefetcher to L3 for loads. 114fabe02f5SSean Bruno.It Li REQ_PF_LLC_RFO 115fabe02f5SSean BrunoRFO requests generated by L2 prefetcher 116fabe02f5SSean Bruno.It Li REQ_PF_LLC_IFETCH 117fabe02f5SSean BrunoL2 prefetcher to L3 for instruction fetches. 118fabe02f5SSean Bruno.It Li REQ_BUS_LOCKS 119fabe02f5SSean BrunoBus lock and split lock requests. 120fabe02f5SSean Bruno.It Li REQ_STRM_ST 121fabe02f5SSean BrunoStreaming store requests. 122fabe02f5SSean Bruno.It Li REQ_OTHER 123fabe02f5SSean BrunoAny other request that crosses IDI, including I/O. 124fabe02f5SSean Bruno.It Li RES_ANY 125fabe02f5SSean BrunoCatch all value for any response types. 126fabe02f5SSean Bruno.It Li RES_SUPPLIER_NO_SUPP 127fabe02f5SSean BrunoNo Supplier Information available. 128fabe02f5SSean Bruno.It Li RES_SUPPLIER_LLC_HITM 129fabe02f5SSean BrunoM-state initial lookup stat in L3. 130fabe02f5SSean Bruno.It Li RES_SUPPLIER_LLC_HITE 131fabe02f5SSean BrunoE-state. 132fabe02f5SSean Bruno.It Li RES_SUPPLIER_LLC_HITS 133fabe02f5SSean BrunoS-state. 134fabe02f5SSean Bruno.It Li RES_SUPPLIER_LLC_HITF 135fabe02f5SSean BrunoF-state. 136fabe02f5SSean Bruno.It Li RES_SUPPLIER_LOCAL 137fabe02f5SSean BrunoLocal DRAM Controller. 138cdfd0cc8SSean Bruno.It Li RES_SNOOP_SNP_NONE 139fabe02f5SSean BrunoNo details on snoop-related information. 140fabe02f5SSean Bruno.It Li RES_SNOOP_SNP_NO_NEEDED 141fabe02f5SSean BrunoNo snoop was needed to satisfy the request. 142fabe02f5SSean Bruno.It Li RES_SNOOP_SNP_MISS 143fabe02f5SSean BrunoA snoop was needed and it missed all snooped caches: 144fabe02f5SSean Bruno-For LLC Hit, ReslHitl was returned by all cores 145fabe02f5SSean Bruno-For LLC Miss, Rspl was returned by all sockets and data was returned from 146fabe02f5SSean BrunoDRAM. 147fabe02f5SSean Bruno.It Li RES_SNOOP_HIT_NO_FWD 148fabe02f5SSean BrunoA snoop was needed and it hits in at least one snooped cache. Hit denotes a 149fabe02f5SSean Brunocache-line was valid before snoop effect. This includes: 150fabe02f5SSean Bruno-Snoop Hit w/ Invalidation (LLC Hit, RFO) 151fabe02f5SSean Bruno-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 152fabe02f5SSean Bruno-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 153fabe02f5SSean BrunoIn the LLC Miss case, data is returned from DRAM. 154fabe02f5SSean Bruno.It Li RES_SNOOP_HIT_FWD 155fabe02f5SSean BrunoA snoop was needed and data was forwarded from a remote socket. 156fabe02f5SSean BrunoThis includes: 157fabe02f5SSean Bruno-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 158fabe02f5SSean Bruno.It Li RES_SNOOP_HITM 159fabe02f5SSean BrunoA snoop was needed and it HitM-ed in local or remote cache. HitM denotes a 160fabe02f5SSean Brunocache-line was in modified state before effect as a results of snoop. This 161fabe02f5SSean Brunoincludes: 162fabe02f5SSean Bruno-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 163fabe02f5SSean Bruno-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 164fabe02f5SSean Bruno-Snoop MtoS (LLC Hit, IFetch/Data_RD). 165fabe02f5SSean Bruno.It Li RES_NON_DRAM 166fabe02f5SSean BrunoTarget was non-DRAM system address. This includes MMIO transactions. 167fabe02f5SSean Bruno.El 168fabe02f5SSean Bruno.It Li cmask= Ns Ar value 169fabe02f5SSean BrunoConfigure the PMC to increment only if the number of configured 170fabe02f5SSean Brunoevents measured in a cycle is greater than or equal to 171fabe02f5SSean Bruno.Ar value . 172fabe02f5SSean Bruno.It Li edge 173fabe02f5SSean BrunoConfigure the PMC to count the number of de-asserted to asserted 174fabe02f5SSean Brunotransitions of the conditions expressed by the other qualifiers. 175fabe02f5SSean BrunoIf specified, the counter will increment only once whenever a 176fabe02f5SSean Brunocondition becomes true, irrespective of the number of clocks during 177fabe02f5SSean Brunowhich the condition remains true. 178fabe02f5SSean Bruno.It Li inv 179fabe02f5SSean BrunoInvert the sense of comparison when the 180fabe02f5SSean Bruno.Dq Li cmask 181fabe02f5SSean Brunoqualifier is present, making the counter increment when the number of 182fabe02f5SSean Brunoevents per cycle is less than the value specified by the 183fabe02f5SSean Bruno.Dq Li cmask 184fabe02f5SSean Brunoqualifier. 185fabe02f5SSean Bruno.It Li os 186fabe02f5SSean BrunoConfigure the PMC to count events happening at processor privilege 187fabe02f5SSean Brunolevel 0. 188fabe02f5SSean Bruno.It Li usr 189fabe02f5SSean BrunoConfigure the PMC to count events occurring at privilege levels 1, 2 190fabe02f5SSean Brunoor 3. 191fabe02f5SSean Bruno.El 192fabe02f5SSean Bruno.Pp 193fabe02f5SSean BrunoIf neither of the 194fabe02f5SSean Bruno.Dq Li os 195fabe02f5SSean Brunoor 196fabe02f5SSean Bruno.Dq Li usr 197fabe02f5SSean Brunoqualifiers are specified, the default is to enable both. 198fabe02f5SSean Bruno.Ss Event Specifiers (Programmable PMCs) 199fabe02f5SSean BrunoSandy Bridge Xeon programmable PMCs support the following events: 200fabe02f5SSean Bruno.Bl -tag -width indent 201fabe02f5SSean Bruno.It Li LD_BLOCKS.DATA_UNKNOWN 202fabe02f5SSean Bruno.Pq Event 03H , Umask 01H 203fabe02f5SSean Brunoblocked loads due to store buffer blocks with unknown data. 204fabe02f5SSean Bruno.It Li LD_BLOCKS.STORE_FORWARD 205fabe02f5SSean Bruno.Pq Event 03H , Umask 02H 206fabe02f5SSean Brunoloads blocked by overlapping with store buffer that cannot 207fabe02f5SSean Brunobe forwarded . 208fabe02f5SSean Bruno.It Li LD_BLOCKS.NO_SR 209fabe02f5SSean Bruno.Pq Event 03H , Umask 08H 210fabe02f5SSean Bruno# of Split loads blocked due to resource not available. 211fabe02f5SSean Bruno.It Li LD_BLOCKS.ALL_BLOCK 212fabe02f5SSean Bruno.Pq Event 03H , Umask 10H 213fabe02f5SSean BrunoNumber of cases where any load is blocked but has no 214fabe02f5SSean BrunoDCU miss. 215fabe02f5SSean Bruno.It Li MISALIGN_MEM_REF.LOADS 216fabe02f5SSean Bruno.Pq Event 05H , Umask 01H 217fabe02f5SSean BrunoSpeculative cache-line split load uops dispatched to 218fabe02f5SSean BrunoL1D. 219fabe02f5SSean Bruno.It Li MISALIGN_MEM_REF.STORES 220fabe02f5SSean Bruno.Pq Event 05H , Umask 02H 221fabe02f5SSean BrunoSpeculative cache-line split Store- address uops 222fabe02f5SSean Brunodispatched to L1D. 223fabe02f5SSean Bruno.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 224fabe02f5SSean Bruno.Pq Event 07H , Umask 01H 225fabe02f5SSean BrunoFalse dependencies in MOB due to partial compare on 226fabe02f5SSean Brunoaddress. 227fabe02f5SSean Bruno.It Li LD_BLOCKS_PARTIAL.ALL_STALL_BLOCK 228fabe02f5SSean Bruno.Pq Event 07H , Umask 08H 229fabe02f5SSean BrunoThe number of times that load operations are temporarily 230fabe02f5SSean Brunoblocked because of older stores, with addresses that are 231fabe02f5SSean Brunonot yet known. A load operation may incur more than one 232fabe02f5SSean Brunoblock of this type. 233fabe02f5SSean Bruno.It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK 234fabe02f5SSean Bruno.Pq Event 08H , Umask 01H 235fabe02f5SSean BrunoMisses in all TLB levels that cause a page walk of any 236fabe02f5SSean Brunopage size. 237fabe02f5SSean Bruno.It Li TLB_LOAD_MISSES.WALK_COMPLETED 238fabe02f5SSean Bruno.Pq Event 08H , Umask 02H 239fabe02f5SSean BrunoMisses in all TLB levels that caused page walk completed 240fabe02f5SSean Brunoof any size. 241fabe02f5SSean Bruno.It Li DTLB_LOAD_MISSES.WALK_DURATION 242fabe02f5SSean Bruno.Pq Event 08H , Umask 04H 243fabe02f5SSean BrunoCycle PMH is busy with a walk. 244fabe02f5SSean Bruno.It Li DTLB_LOAD_MISSES.STLB_HIT 245fabe02f5SSean Bruno.Pq Event 08H , Umask 10H 246fabe02f5SSean BrunoNumber of cache load STLB hits. No page walk. 247fabe02f5SSean Bruno.It Li INT_MISC.RECOVERY_CYCLES 248fabe02f5SSean Bruno.Pq Event 0DH , Umask 03H 249fabe02f5SSean BrunoCycles waiting to recover after Machine Clears or EClear. 250fabe02f5SSean BrunoSet Cmask= 1. 251fabe02f5SSean Bruno.It Li INT_MISC.RAT_STALL_CYCLES 252fabe02f5SSean Bruno.Pq Event 0DH , Umask 40H 253fabe02f5SSean BrunoCycles RAT external stall is sent to IDQ for this thread. 254fabe02f5SSean Bruno.It Li UOPS_ISSUED.ANY 255fabe02f5SSean Bruno.Pq Event 0EH , Umask 01H 256fabe02f5SSean BrunoIncrements each cycle the # of Uops issued by the 257fabe02f5SSean BrunoRAT to RS. 258fabe02f5SSean BrunoSet Cmask = 1, Inv = 1, Any= 1to count stalled cycles 259fabe02f5SSean Brunoof this core. 260fabe02f5SSean Bruno.It Li FP_COMP_OPS_EXE.X87 261fabe02f5SSean Bruno.Pq Event 10H , Umask 01H 262fabe02f5SSean BrunoCounts number of X87 uops executed. 263fabe02f5SSean Bruno.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE 264fabe02f5SSean Bruno.Pq Event 10H , Umask 10H 265fabe02f5SSean BrunoCounts number of SSE* double precision FP packed 266fabe02f5SSean Brunouops executed. 267fabe02f5SSean Bruno.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE 268fabe02f5SSean Bruno.Pq Event 10H , Umask 20H 269fabe02f5SSean BrunoCounts number of SSE* single precision FP scalar 270fabe02f5SSean Brunouops executed. 271fabe02f5SSean Bruno.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE 272fabe02f5SSean Bruno.Pq Event 10H , Umask 40H 273fabe02f5SSean BrunoCounts number of SSE* single precision FP packed 274fabe02f5SSean Brunouops executed. 275fabe02f5SSean Bruno.It Li FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE 276fabe02f5SSean Bruno.Pq Event 10H , Umask 80H 277fabe02f5SSean BrunoCounts number of SSE* double precision FP scalar 278fabe02f5SSean Brunouops executed. 279fabe02f5SSean Bruno.It Li SIMD_FP_256.PACKED_SINGLE 280fabe02f5SSean Bruno.Pq Event 11H , Umask 01H 281fabe02f5SSean BrunoCounts 256-bit packed single-precision floating- 282fabe02f5SSean Brunopoint instructions. 283fabe02f5SSean Bruno.It Li SIMD_FP_256.PACKED_DOUBLE 284fabe02f5SSean Bruno.Pq Event 11H , Umask 02H 285fabe02f5SSean BrunoCounts 256-bit packed double-precision floating- 286fabe02f5SSean Brunopoint instructions. 287fabe02f5SSean Bruno.It Li ARITH.FPU_DIV_ACTIVE 288fabe02f5SSean Bruno.Pq Event 14H , Umask 01H 289fabe02f5SSean BrunoCycles that the divider is active, includes INT and FP. 290fabe02f5SSean BrunoSet 'edge =1, cmask=1' to count the number of 291fabe02f5SSean Brunodivides. 292fabe02f5SSean Bruno.It Li INSTS_WRITTEN_TO_IQ.INSTS 293fabe02f5SSean Bruno.Pq Event 17H , Umask 01H 294fabe02f5SSean BrunoCounts the number of instructions written into the 295fabe02f5SSean BrunoIQ every cycle. 296fabe02f5SSean Bruno.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 297fabe02f5SSean Bruno.Pq Event 24H , Umask 01H 298fabe02f5SSean BrunoDemand Data Read requests that hit L2 cache. 299fabe02f5SSean Bruno.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 300fabe02f5SSean Bruno.Pq Event 24H , Umask 03H 301fabe02f5SSean BrunoCounts any demand and L1 HW prefetch data load 302fabe02f5SSean Brunorequests to L2. 303fabe02f5SSean Bruno.It Li L2_RQSTS.RFO_HITS 304fabe02f5SSean Bruno.Pq Event 24H , Umask 04H 305fabe02f5SSean BrunoCounts the number of store RFO requests that 306fabe02f5SSean Brunohit the L2 cache. 307fabe02f5SSean Bruno.It Li L2_RQSTS.RFO_MISS 308fabe02f5SSean Bruno.Pq Event 24H , Umask 08H 309fabe02f5SSean BrunoCounts the number of store RFO requests that 310fabe02f5SSean Brunomiss the L2 cache. 311fabe02f5SSean Bruno.It Li L2_RQSTS.ALL_RFO 312fabe02f5SSean Bruno.Pq Event 24H , Umask 0CH 313fabe02f5SSean BrunoCounts all L2 store RFO requests. 314fabe02f5SSean Bruno.It Li L2_RQSTS.CODE_RD_HIT 315fabe02f5SSean Bruno.Pq Event 24H , Umask 10H 316fabe02f5SSean BrunoNumber of instruction fetches that hit the L2 317fabe02f5SSean Brunocache. 318fabe02f5SSean Bruno.It Li L2_RQSTS.CODE_RD_MISS 319fabe02f5SSean Bruno.Pq Event 24H , Umask 20H 320fabe02f5SSean BrunoNumber of instruction fetches that missed the L2 321fabe02f5SSean Brunocache. 322fabe02f5SSean Bruno.It Li L2_RQSTS.ALL_CODE_RD 323fabe02f5SSean Bruno.Pq Event 24H , Umask 30H 324fabe02f5SSean BrunoCounts all L2 code requests. 325fabe02f5SSean Bruno.It Li L2_RQSTS.PF_HIT 326fabe02f5SSean Bruno.Pq Event 24H , Umask 40H 327fabe02f5SSean BrunoRequests from L2 Hardware prefetcher that hit L2. 328fabe02f5SSean Bruno.It Li L2_RQSTS.PF_MISS 329fabe02f5SSean Bruno.Pq Event 24H , Umask 80H 330fabe02f5SSean BrunoRequests from L2 Hardware prefetcher that missed 331fabe02f5SSean BrunoL2. 332fabe02f5SSean Bruno.It Li L2_RQSTS.ALL_PF 333fabe02f5SSean Bruno.Pq Event 24H , Umask C0H 334fabe02f5SSean BrunoAny requests from L2 Hardware prefetchers. 335fabe02f5SSean Bruno.It Li L2_STORE_LOCK_RQSTS.MISS 336fabe02f5SSean Bruno.Pq Event 27H , Umask 01H 337fabe02f5SSean BrunoROs that miss cache lines. 338fabe02f5SSean Bruno.It Li L2_STORE_LOCK_RQSTS.HIT_E 339fabe02f5SSean Bruno.Pq Event 27H , Umask 04H 340fabe02f5SSean BrunoRFOs that hit cache lines in E state. 341fabe02f5SSean Bruno.It Li L2_STORE_LOCK_RQSTS.HIT_M 342fabe02f5SSean Bruno.Pq Event 27H , Umask 08H 343fabe02f5SSean BrunoRFOs that hit cache lines in M state. 344fabe02f5SSean Bruno.It Li L2_STORE_LOCK_RQSTS.ALL 345fabe02f5SSean Bruno.Pq Event 27H , Umask 0FH 346fabe02f5SSean BrunoRFOs that access cache lines in any state. 347fabe02f5SSean Bruno.It Li L2_L1D_WB_RQSTS.MISS 348fabe02f5SSean Bruno.Pq Event 28H , Umask 01H 349fabe02f5SSean BrunoNot rejected writebacks from L1D to L2 cache lines 350fabe02f5SSean Brunothat missed L2. 351fabe02f5SSean Bruno.It Li L2_L1D_WB_RQSTS.HIT_S 352fabe02f5SSean Bruno.Pq Event 28H , Umask 02H 353fabe02f5SSean BrunoNot rejected writebacks from L1D to L2 cache lines 354fabe02f5SSean Brunoin S state. 355fabe02f5SSean Bruno.It Li L2_L1D_WB_RQSTS.HIT_E 356fabe02f5SSean Bruno.Pq Event 28H , Umask 04H 357fabe02f5SSean BrunoNot rejected writebacks from L1D to L2 cache lines 358fabe02f5SSean Brunoin E state. 359fabe02f5SSean Bruno.It Li L2_L1D_WB_RQSTS.HIT_M 360fabe02f5SSean Bruno.Pq Event 28H , Umask 08H 361fabe02f5SSean BrunoNot rejected writebacks from L1D to L2 cache lines 362fabe02f5SSean Brunoin M state. 363fabe02f5SSean Bruno.It Li L2_L1D_WB_RQSTS.ALL 364fabe02f5SSean Bruno.Pq Event 28H , Umask 0FH 365fabe02f5SSean BrunoNot rejected writebacks from L1D to L2 cache. 366fabe02f5SSean Bruno.It Li LONGEST_LAT_CACHE.REFERENCE 367fabe02f5SSean Bruno.Pq Event 2EH , Umask 4FH 368fabe02f5SSean BrunoThis event counts requests originating from the 369fabe02f5SSean Brunocore that reference 370fabe02f5SSean Brunoa cache line in the last level cache. 371fabe02f5SSean Bruno.It Li LONGEST_LAT_CACHE.MISS 372fabe02f5SSean Bruno.Pq Event 2EH , Umask 41H 373fabe02f5SSean BrunoThis event counts each cache miss condition for 374fabe02f5SSean Brunoreferences to the last level cache. 375fabe02f5SSean Bruno.It Li CPU_CLK_UNHALTED.THREAD_P 376fabe02f5SSean Bruno.Pq Event 3CH , Umask 00H 377fabe02f5SSean BrunoCounts the number of thread cycles while the 378fabe02f5SSean Brunothread is not in a halt state. The thread enters 379fabe02f5SSean Brunothe halt state when it is running the HLT 380fabe02f5SSean Brunoinstruction. The core frequency may change from 381fabe02f5SSean Brunotime to time due to power or thermal throttling. 382fabe02f5SSean Bruno.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 383fabe02f5SSean Bruno.Pq Event 3CH , Umask 01H 384fabe02f5SSean BrunoIncrements at the frequency of XCLK (100 MHz) 385fabe02f5SSean Brunowhen not halted. 386fabe02f5SSean Bruno.It Li L1D_PEND_MISS.PENDING 387fabe02f5SSean Bruno.Pq Event 48H , Umask 01H 388fabe02f5SSean BrunoIncrements the number of outstanding L1D misses 389fabe02f5SSean Brunoevery cycle. 390fabe02f5SSean BrunoSet Cmaks = 1 and Edge =1 to count occurrences. 391fabe02f5SSean Bruno.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 392fabe02f5SSean Bruno.Pq Event 49H , Umask 01H 393fabe02f5SSean BrunoMiss in all TLB levels causes an page walk of 394fabe02f5SSean Brunoany page size (4K/2M/4M/1G). 395fabe02f5SSean Bruno.It Li DTLB_STORE_MISSES.WALK_COMPLETED 396fabe02f5SSean Bruno.Pq Event 49H , Umask 02H 397fabe02f5SSean BrunoMiss in all TLB levels causes a page walk that 398fabe02f5SSean Brunocompletes of any page size (4K/2M/4M/1G). 399fabe02f5SSean Bruno.It Li DTLB_STORE_MISSES.WALK_DURATION 400fabe02f5SSean Bruno.Pq Event 49H , Umask 04H 401fabe02f5SSean BrunoCycles PMH is busy with this walk. 402fabe02f5SSean Bruno.It Li DTLB_STORE_MISSES.STLB_HIT 403fabe02f5SSean Bruno.Pq Event 49H , Umask 10H 404fabe02f5SSean BrunoStore operations that miss the first TLB level 405fabe02f5SSean Brunobut hit the second and do not cause page walks. 406fabe02f5SSean Bruno.It Li LOAD_HIT_PRE.SW_PF 407fabe02f5SSean Bruno.Pq Event 4CH , Umask 01H 408fabe02f5SSean BrunoNot SW-prefetch load dispatches that hit fill 409fabe02f5SSean Brunobuffer allocated for S/W prefetch. 410fabe02f5SSean Bruno.It Li LOAD_HIT_PER.HW_PF 411fabe02f5SSean Bruno.Pq Event 4CH , Umask 02H 412fabe02f5SSean BrunoNot SW-prefetch load dispatches that hit fill 413fabe02f5SSean Brunobuffer allocated for H/W prefetch. 414fabe02f5SSean Bruno.It Li HW_PRE_REQ.DL1_MISS 415fabe02f5SSean Bruno.Pq Event 4EH , Umask 02H 416fabe02f5SSean BrunoHardware Prefetch requests that miss the L1D 417fabe02f5SSean Brunocache. A request is being counted each time 418fabe02f5SSean Brunoit access the cache & miss it, including if 419fabe02f5SSean Brunoa block is applicable or if hit the Fill 420fabe02f5SSean BrunoBuffer for example. 421fabe02f5SSean Bruno.It Li L1D.REPLACEMENT 422fabe02f5SSean Bruno.Pq Event 51H , Umask 01H 423fabe02f5SSean BrunoCounts the number of lines brought into the 424fabe02f5SSean BrunoL1 data cache. 425fabe02f5SSean Bruno.It Li L1D.ALLOCATED_IN_M 426fabe02f5SSean Bruno.Pq Event 51H , Umask 02H 427fabe02f5SSean BrunoCounts the number of allocations of modified 428fabe02f5SSean BrunoL1D cache lines. 429fabe02f5SSean Bruno.It Li L1D.EVICTION 430fabe02f5SSean Bruno.Pq Event 51H , Umask 04H 431fabe02f5SSean BrunoCounts the number of modified lines evicted 432fabe02f5SSean Brunofrom the L1 data cache due to replacement. 433fabe02f5SSean Bruno.It Li L1D.ALL_M_REPLACEMENT 434fabe02f5SSean Bruno.Pq Event 51H , Umask 08H 435fabe02f5SSean BrunoCache lines in M state evicted out of L1D due 436fabe02f5SSean Brunoto Snoop HitM or dirty line replacement. 437fabe02f5SSean Bruno.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP 438fabe02f5SSean Bruno.Pq Event 59H , Umask 0CH 439fabe02f5SSean BrunoIncrements the number of flags-merge uops in 440fabe02f5SSean Brunoflight each cycle. 441fabe02f5SSean BrunoSet Cmask = 1 to count cycles. 442fabe02f5SSean Bruno.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW 443fabe02f5SSean Bruno.Pq Event 59H , Umask 0FH 444fabe02f5SSean BrunoCycles with at least one slow LEA uop allocated. 445fabe02f5SSean Bruno.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP 446fabe02f5SSean Bruno.Pq Event 59H , Umask 40H 447fabe02f5SSean BrunoNumber of Multiply packed/scalar single precision 448fabe02f5SSean Brunouops allocated. 449fabe02f5SSean Bruno.It Li RESOURCE_STALLS2.ALL_FL_EMPTY 450fabe02f5SSean Bruno.Pq Event 5BH , Umask 0CH 451fabe02f5SSean BrunoCycles stalled due to free list empty. 452fabe02f5SSean Bruno.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL 453fabe02f5SSean Bruno.Pq Event 5BH , Umask 0FH 454fabe02f5SSean BrunoCycles stalled due to control structures full for 455fabe02f5SSean Brunophysical registers. 456fabe02f5SSean Bruno.It Li RESOURCE_STALLS2.BOB_FULL 457fabe02f5SSean Bruno.Pq Event 5BH , Umask 40H 458fabe02f5SSean BrunoCycles Allocator is stalled due Branch Order Buffer. 459fabe02f5SSean Bruno.It Li RESOURCE_STALLS2.OOO_RSRC 460fabe02f5SSean Bruno.Pq Event 5BH , Umask 4FH 461fabe02f5SSean BrunoCycles stalled due to out of order resources full. 462fabe02f5SSean Bruno.It Li CPL_CYCLES.RING0 463fabe02f5SSean Bruno.Pq Event 5CH , Umask 01H 464fabe02f5SSean BrunoUnhalted core cycles when the thread is in ring 0. 465fabe02f5SSean Bruno.It Li CPL_CYCLES.RING123 466fabe02f5SSean Bruno.Pq Event 5CH , Umask 02H 467fabe02f5SSean BrunoUnhalted core cycles when the thread is not in ring 468fabe02f5SSean Bruno0. 469fabe02f5SSean Bruno.It Li RS_EVENTS.EMPTY_CYCLES 470fabe02f5SSean Bruno.Pq Event 5EH , Umask 01H 471fabe02f5SSean BrunoCycles the RS is empty for the thread. 472fabe02f5SSean Bruno.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 473fabe02f5SSean Bruno.Pq Event 60H , Umask 01H 474fabe02f5SSean BrunoOffcore outstanding Demand Data Read 475fabe02f5SSean Brunotransactions in SQ to uncore. Set Cmask=1 to count 476fabe02f5SSean Brunocycles. 477fabe02f5SSean Bruno.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 478fabe02f5SSean Bruno.Pq Event 60H , Umask 04H 479fabe02f5SSean BrunoOffcore outstanding RFO store transactions in SQ to 480fabe02f5SSean Brunouncore. Set Cmask=1 to count cycles. 481fabe02f5SSean Bruno.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 482fabe02f5SSean Bruno.Pq Event 60H , Umask 08H 483fabe02f5SSean BrunoOffcore outstanding cacheable data read 484fabe02f5SSean Brunotransactions in SQ to uncore. Set Cmask=1 to count 485fabe02f5SSean Brunocycles. 486fabe02f5SSean Bruno.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 487fabe02f5SSean Bruno.Pq Event 63H , Umask 01H 488fabe02f5SSean BrunoCycles in which the L1D and L2 are locked, due to a 489fabe02f5SSean BrunoUC lock or split lock. 490fabe02f5SSean Bruno.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 491fabe02f5SSean Bruno.Pq Event 63H , Umask 02H 492fabe02f5SSean BrunoCycles in which the L1D is locked. 493fabe02f5SSean Bruno.It Li IDQ.EMPTY 494fabe02f5SSean Bruno.Pq Event 79H , Umask 02H 495fabe02f5SSean BrunoCounts cycles the IDQ is empty. 496fabe02f5SSean Bruno.It Li IDQ.MITE_UOPS 497fabe02f5SSean Bruno.Pq Event 79H , Umask 04H 498fabe02f5SSean BrunoIncrement each cycle # of uops delivered to IDQ 499fabe02f5SSean Brunofrom MITE path. 500fabe02f5SSean BrunoSet Cmask = 1 to count cycles. 501fabe02f5SSean Bruno.It Li IDQ.DSB_UOPS 502fabe02f5SSean Bruno.Pq Event 79H , Umask 08H 503fabe02f5SSean BrunoIncrement each cycle. # of uops delivered to IDQ 504fabe02f5SSean Brunofrom DSB path. 505fabe02f5SSean BrunoSet Cmask = 1 to count cycles. 506fabe02f5SSean Bruno.It Li IDQ.MS_DSB_UOPS 507fabe02f5SSean Bruno.Pq Event 79H , Umask 10H 508fabe02f5SSean BrunoIncrement each cycle # of uops delivered to IDQ 509fabe02f5SSean Brunowhen MS busy by DSB. Set Cmask = 1 to count 510fabe02f5SSean Brunocycles MS is busy. Set Cmask=1 and Edge =1 to 511fabe02f5SSean Brunocount MS activations. 512fabe02f5SSean Bruno.It Li IDQ.MS_MITE_UOPS 513fabe02f5SSean Bruno.Pq Event 79H , Umask 20H 514fabe02f5SSean BrunoIncrement each cycle # of uops delivered to IDQ 515fabe02f5SSean Brunowhen MS is busy by MITE. Set Cmask = 1 to count 516fabe02f5SSean Brunocycles. 517fabe02f5SSean Bruno.It Li IDQ.MS_UOPS 518fabe02f5SSean Bruno.Pq Event 79H , Umask 30H 519fabe02f5SSean BrunoIncrement each cycle # of uops delivered to IDQ 520fabe02f5SSean Brunofrom MS by either DSB or MITE. Set Cmask = 1 to 521fabe02f5SSean Brunocount cycles. 522fabe02f5SSean Bruno.It Li ICACHE.MISSES 523fabe02f5SSean Bruno.Pq Event 80H , Umask 02H 524fabe02f5SSean BrunoNumber of Instruction Cache, Streaming Buffer and 525fabe02f5SSean BrunoVictim Cache Misses. Includes UC accesses. 526fabe02f5SSean Bruno.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 527fabe02f5SSean Bruno.Pq Event 85H , Umask 01H 528fabe02f5SSean BrunoMisses in all ITLB levels that cause page walks. 529fabe02f5SSean Bruno.It Li ITLB_MISSES.WALK_COMPLETED 530fabe02f5SSean Bruno.Pq Event 85H , Umask 02H 531fabe02f5SSean BrunoMisses in all ITLB levels that cause completed page 532fabe02f5SSean Brunowalks. 533fabe02f5SSean Bruno.It Li ITLB_MISSES.WALK_DURATION 534fabe02f5SSean Bruno.Pq Event 85H , Umask 04H 535fabe02f5SSean BrunoCycle PMH is busy with a walk. 536fabe02f5SSean Bruno.It Li ITLB_MISSES.STLB_HIT 537fabe02f5SSean Bruno.Pq Event 85H , Umask 10H 538fabe02f5SSean BrunoNumber of cache load STLB hits. No page walk. 539fabe02f5SSean Bruno.It Li ILD_STALL.LCP 540fabe02f5SSean Bruno.Pq Event 87H , Umask 01H 541fabe02f5SSean BrunoStalls caused by changing prefix length of the 542fabe02f5SSean Brunoinstruction. 543fabe02f5SSean Bruno.It Li ILD_STALL.IQ_FULL 544fabe02f5SSean Bruno.Pq Event 87H , Umask 04H 545fabe02f5SSean BrunoStall cycles due to IQ is full. 546*9e60f3acSRyan Stone.It Li BR_INST_EXEC.NONTAKEN_COND 547*9e60f3acSRyan Stone.Pq Event 88H , Umask 41H 548*9e60f3acSRyan StoneCount conditional near branch instructions that were executed (but not 549*9e60f3acSRyan Stonenecessarily retired) and not taken. 550*9e60f3acSRyan Stone.It Li BR_INST_EXEC.TAKEN_COND 551*9e60f3acSRyan Stone.Pq Event 88H , Umask 81H 552*9e60f3acSRyan StoneCount conditional near branch instructions that were executed (but not 553*9e60f3acSRyan Stonenecessarily retired) and taken. 554fabe02f5SSean Bruno.It Li BR_INST_EXEC.DIRECT_JMP 555*9e60f3acSRyan Stone.Pq Event 88H , Umask 82H 556*9e60f3acSRyan StoneCount all unconditional near branch instructions excluding calls and 557*9e60f3acSRyan Stoneindirect branches. 558fabe02f5SSean Bruno.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 559*9e60f3acSRyan Stone.Pq Event 88H , Umask 84H 560*9e60f3acSRyan StoneCount executed indirect near branch instructions that are not calls nor 561*9e60f3acSRyan Stonereturns. 562fabe02f5SSean Bruno.It Li BR_INST_EXEC.RETURN_NEAR 563*9e60f3acSRyan Stone.Pq Event 88H , Umask 88H 564*9e60f3acSRyan StoneCount indirect near branches that have a return mnemonic. 565fabe02f5SSean Bruno.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 566*9e60f3acSRyan Stone.Pq Event 88H , Umask 90H 567*9e60f3acSRyan StoneCount unconditional near call branch instructions, excluding non call 568*9e60f3acSRyan Stonebranch, executed. 569fabe02f5SSean Bruno.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 570*9e60f3acSRyan Stone.Pq Event 88H , Umask A0H 571*9e60f3acSRyan StoneCount indirect near calls, including both register and memory indirect, 572*9e60f3acSRyan Stoneexecuted. 573*9e60f3acSRyan Stone.It Li BR_INST_EXEC.ALL_BRANCHES 574fabe02f5SSean Bruno.Pq Event 88H , Umask FFH 575*9e60f3acSRyan StoneCounts all near executed branches (not necessarily retired). 576*9e60f3acSRyan Stone.It Li BR_MISP_EXEC.NONTAKEN_COND 577*9e60f3acSRyan Stone.Pq Event 89H , Umask 41H 578*9e60f3acSRyan StoneCount conditional near branch instructions mispredicted as nontaken. 579*9e60f3acSRyan Stone.It Li BR_MISP_EXEC.TAKEN_COND 580*9e60f3acSRyan Stone.Pq Event 89H , Umask 81H 581*9e60f3acSRyan StoneCount conditional near branch instructions mispredicted as taken. 582fabe02f5SSean Bruno.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 583*9e60f3acSRyan Stone.Pq Event 89H , Umask 84H 584*9e60f3acSRyan StoneCount mispredicted indirect near branch instructions that are not calls 585*9e60f3acSRyan Stonenor returns. 586fabe02f5SSean Bruno.It Li BR_MISP_EXEC.RETURN_NEAR 587*9e60f3acSRyan Stone.Pq Event 89H , Umask 88H 588*9e60f3acSRyan StoneCount mispredicted indirect near branches that have a return mnemonic. 589fabe02f5SSean Bruno.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 590*9e60f3acSRyan Stone.Pq Event 89H , Umask 90H 591*9e60f3acSRyan StoneCount mispredicted unconditional near call branch instructions, excluding 592*9e60f3acSRyan Stonenon call branch, executed. 593fabe02f5SSean Bruno.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 594*9e60f3acSRyan Stone.Pq Event 89H , Umask A0H 595*9e60f3acSRyan StoneCount mispredicted indirect near calls, including both register and memory 596*9e60f3acSRyan Stoneindirect, executed. 597fabe02f5SSean Bruno.It Li BR_MISP_EXEC.ALL_BRANCHES 598fabe02f5SSean Bruno.Pq Event 89H , Umask FFH 599*9e60f3acSRyan StoneCounts all mispredicted near executed branches (not necessarily retired). 600fabe02f5SSean Bruno.It Li IDQ_UOPS_NOT_DELIVERED.CORE 601fabe02f5SSean Bruno.Pq Event 9CH , Umask 01H 602fabe02f5SSean BrunoCount number of non-delivered uops to RAT per 603fabe02f5SSean Brunothread. 604fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_0 605fabe02f5SSean Bruno.Pq Event A1H , Umask 01H 606fabe02f5SSean BrunoCycles which a Uop is dispatched on port 0. 607fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_1 608fabe02f5SSean Bruno.Pq Event A1H , Umask 02H 609fabe02f5SSean BrunoCycles which a Uop is dispatched on port 1. 610fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 611fabe02f5SSean Bruno.Pq Event A1H , Umask 04H 612fabe02f5SSean BrunoCycles which a load uop is dispatched on port 2. 613fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 614fabe02f5SSean Bruno.Pq Event A1H , Umask 08H 615fabe02f5SSean BrunoCycles which a store address uop is dispatched on 616fabe02f5SSean Brunoport 2. 617fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_2 618fabe02f5SSean Bruno.Pq Event A1H , Umask 0CH 619fabe02f5SSean BrunoCycles which a Uop is dispatched on port 2. 620fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 621fabe02f5SSean Bruno.Pq Event A1H , Umask 10H 622fabe02f5SSean BrunoCycles which a load uop is dispatched on port 3. 623fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 624fabe02f5SSean Bruno.Pq Event A1H , Umask 20H 625fabe02f5SSean BrunoCycles which a store address uop is dispatched on 626fabe02f5SSean Brunoport 3. 627fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_3 628fabe02f5SSean Bruno.Pq Event A1H , Umask 30H 629fabe02f5SSean BrunoCycles which a Uop is dispatched on port 3. 630fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_4 631fabe02f5SSean Bruno.Pq Event A1H , Umask 40H 632fabe02f5SSean BrunoCycles which a Uop is dispatched on port 4. 633fabe02f5SSean Bruno.It Li UOPS_DISPATCHED_PORT.PORT_5 634fabe02f5SSean Bruno.Pq Event A1H , Umask 80H 635fabe02f5SSean BrunoCycles which a Uop is dispatched on port 5. 636fabe02f5SSean Bruno.It Li RESOURCE_STALLS.ANY 637fabe02f5SSean Bruno.Pq Event A2H , Umask 01H 638fabe02f5SSean BrunoCycles Allocation is stalled due to Resource Related 639fabe02f5SSean Brunoreason. 640fabe02f5SSean Bruno.It Li RESOURCE_STALLS.LB 641fabe02f5SSean Bruno.Pq Event A2H , Umask 01H 642fabe02f5SSean BrunoCounts the cycles of stall due to lack of load buffers. 643fabe02f5SSean Bruno.It Li RESOURCE_STALLS.RS 644fabe02f5SSean Bruno.Pq Event A2H , Umask 04H 645fabe02f5SSean BrunoCycles stalled due to no eligible RS entry available. 646fabe02f5SSean Bruno.It Li RESOURCE_STALLS.SB 647fabe02f5SSean Bruno.Pq Event A2H , Umask 08H 648fabe02f5SSean BrunoCycles stalled due to no store buffers available. (not 649fabe02f5SSean Brunoincluding draining form sync). 650fabe02f5SSean Bruno.It Li RESOURCE_STALLS.ROB 651fabe02f5SSean Bruno.Pq Event A2H , Umask 10H 652fabe02f5SSean BrunoCycles stalled due to re-order buffer full. 653fabe02f5SSean Bruno.It Li RESOURCE_STALLS.FCSW 654fabe02f5SSean Bruno.Pq Event A2H , Umask 20H 655fabe02f5SSean BrunoCycles stalled due to writing the FPU control word. 656fabe02f5SSean Bruno.It Li RESOURCE_STALLS.MXCSR 657fabe02f5SSean Bruno.Pq Event A2H , Umask 40H 658fabe02f5SSean BrunoCycles stalled due to the MXCSR register rename 659fabe02f5SSean Brunooccurring to close to a previous MXCSR rename. 660fabe02f5SSean Bruno.It Li RESOURCE_STALLS.OTHER 661fabe02f5SSean Bruno.Pq Event A2H , Umask 80H 662fabe02f5SSean BrunoCycles stalled while execution was stalled due to 663fabe02f5SSean Brunoother resource issues. 664fabe02f5SSean Bruno.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 665fabe02f5SSean Bruno.Pq Event A3H , Umask 01H 666fabe02f5SSean BrunoCycles with pending L2 miss loads. Set AnyThread 667fabe02f5SSean Brunoto count per core. 668fabe02f5SSean Bruno.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 669fabe02f5SSean Bruno.Pq Event A3H , Umask 02H 670fabe02f5SSean BrunoCycles with pending L1 cache miss loads.Set 671fabe02f5SSean BrunoAnyThread to count per core. 672fabe02f5SSean Bruno.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH 673fabe02f5SSean Bruno.Pq Event A3H , Umask 04H 674fabe02f5SSean BrunoCycles of dispatch stalls. Set AnyThread to count per 675fabe02f5SSean Brunocore. 676fabe02f5SSean Bruno.It Li DSB2MITE_SWITCHES.COUNT 677fabe02f5SSean Bruno.Pq Event ABH , Umask 01H 678fabe02f5SSean BrunoNumber of DSB to MITE switches. 679fabe02f5SSean Bruno.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 680fabe02f5SSean Bruno.Pq Event ABH , Umask 02H 681fabe02f5SSean BrunoCycles DSB to MITE switches caused delay. 682fabe02f5SSean Bruno.It Li DSB_FILL.OTHER_CANCEL 683fabe02f5SSean Bruno.Pq Event ACH , Umask 02H 684fabe02f5SSean BrunoCases of cancelling valid DSB fill not because of 685fabe02f5SSean Brunoexceeding way limit. 686fabe02f5SSean Bruno.It Li DSB_FILL.EXCEED_DSB_LINES 687fabe02f5SSean Bruno.Pq Event ACH , Umask 08H 688fabe02f5SSean BrunoDSB Fill encountered > 3 DSB lines. 689fabe02f5SSean Bruno.It Li DSB_FILL.ALL_CANCEL 690fabe02f5SSean Bruno.Pq Event ACH , Umask 0AH 691fabe02f5SSean BrunoCases of cancelling valid Decode Stream Buffer 692fabe02f5SSean Bruno(DSB) fill not because of exceeding way limit. 693fabe02f5SSean Bruno.It Li ITLB.ITLB_FLUSH 694fabe02f5SSean Bruno.Pq Event AEH , Umask 01H 695fabe02f5SSean BrunoCounts the number of ITLB flushes, includes 696fabe02f5SSean Bruno4k/2M/4M pages. 697fabe02f5SSean Bruno.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 698fabe02f5SSean Bruno.Pq Event B0H , Umask 01H 699fabe02f5SSean BrunoDemand data read requests sent to uncore. 700fabe02f5SSean Bruno.It Li OFFCORE_REQUESTS.DEMAND_RFO 701fabe02f5SSean Bruno.Pq Event B0H , Umask 04H 702fabe02f5SSean BrunoDemand RFO read requests sent to uncore, including 703fabe02f5SSean Brunoregular RFOs, locks, ItoM. 704fabe02f5SSean Bruno.It Li OFFCORE_REQUESTS.ALL_DATA_RD 705fabe02f5SSean Bruno.Pq Event B0H , Umask 08H 706fabe02f5SSean BrunoData read requests sent to uncore (demand and 707fabe02f5SSean Brunoprefetch). 708fabe02f5SSean Bruno.It Li UOPS_DISPATCHED.THREAD 709fabe02f5SSean Bruno.Pq Event B1H , Umask 01H 710fabe02f5SSean BrunoCounts total number of uops to be dispatched per- 711fabe02f5SSean Brunothread each cycle. Set Cmask = 1, INV =1 to count 712fabe02f5SSean Brunostall cycles. 713fabe02f5SSean Bruno.It Li UOPS_DISPATCHED.CORE 714fabe02f5SSean Bruno.Pq Event B1H , Umask 02H 715fabe02f5SSean BrunoCounts total number of uops to be dispatched per- 716fabe02f5SSean Brunocore each cycle. 717fabe02f5SSean Bruno.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL 718fabe02f5SSean Bruno.Pq Event B2H , Umask 01H 719fabe02f5SSean BrunoOffcore requests buffer cannot take more entries 720fabe02f5SSean Brunofor this thread core. 721fabe02f5SSean Bruno.It Li AGU_BYPASS_CANCEL.COUNT 722fabe02f5SSean Bruno.Pq Event B6H , Umask 01H 723fabe02f5SSean BrunoCounts executed load operations with all the 724fabe02f5SSean Brunofollowing traits: 1. addressing of the format [base + 725fabe02f5SSean Brunooffset], 2. the offset is between 1 and 2047, 3. the 726fabe02f5SSean Brunoaddress specified in the base register is in one page 727fabe02f5SSean Brunoand the address [base+offset] is in another page. 728fabe02f5SSean Bruno.It Li OFF_CORE_RESPONSE_0 729fabe02f5SSean Bruno.Pq Event B7H , Umask 01H 730fabe02f5SSean Bruno(Event B7H, Umask 01H) Off-core Response Performance 731fabe02f5SSean BrunoMonitoring; PMC0 only. Requires programming MSR 01A6H 732fabe02f5SSean Bruno.It Li OFF_CORE_RESPONSE_1 733fabe02f5SSean Bruno.Pq Event BBH , Umask 01H 734fabe02f5SSean Bruno(Event BBH, Umask 01H) Off-core Response Performance 735fabe02f5SSean BrunoMonitoring; PMC3 only. Requires programming MSR 01A7H 736fabe02f5SSean Bruno.It Li TLB_FLUSH.DTLB_THREAD 737fabe02f5SSean Bruno.Pq Event BDH , Umask 01H 738fabe02f5SSean BrunoDTLB flush attempts of the thread-specific entries. 739fabe02f5SSean Bruno.It Li TLB_FLUSH.STLB_ANY 740fabe02f5SSean Bruno.Pq Event BDH , Umask 20H 741fabe02f5SSean BrunoCount number of STLB flush attempts. 742fabe02f5SSean Bruno.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES 743fabe02f5SSean Bruno.Pq Event BFH , Umask 05H 744fabe02f5SSean BrunoCycles when dispatched loads are cancelled due to 745fabe02f5SSean BrunoL1D bank conflicts with other load ports. 746fabe02f5SSean Bruno.It Li INST_RETIRED.ANY_P 747fabe02f5SSean Bruno.Pq Event C0H , Umask 00H 748fabe02f5SSean BrunoNumber of instructions at retirement. 749fabe02f5SSean Bruno.It Li INST_RETIRED.ALL 750fabe02f5SSean Bruno.Pq Event C0H , Umask 01H 751fabe02f5SSean BrunoPrecise instruction retired event with HW to reduce 752fabe02f5SSean Brunoeffect of PEBS shadow in IP distribution. 753fabe02f5SSean Bruno.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED 754fabe02f5SSean Bruno.Pq Event C1H , Umask 02H 755fabe02f5SSean BrunoInstructions that experienced an ITLB miss. 756fabe02f5SSean Bruno.It Li OTHER_ASSISTS.AVX_STORE 757fabe02f5SSean Bruno.Pq Event C1H , Umask 08H 758fabe02f5SSean BrunoNumber of assists associated with 256-bit AVX 759fabe02f5SSean Brunostore operations. 760fabe02f5SSean Bruno.It Li OTHER_ASSISTS.AVX_TO_SSE 761fabe02f5SSean Bruno.Pq Event C1H , Umask 10H 762fabe02f5SSean BrunoNumber of transitions from AVX-256 to legacy SSE 763fabe02f5SSean Brunowhen penalty applicable. 764fabe02f5SSean Bruno.It Li OTHER_ASSISTS.SSE_TO_AVX 765fabe02f5SSean Bruno.Pq Event C1H , Umask 20H 766fabe02f5SSean BrunoNumber of transitions from SSE to AVX-256 when 767fabe02f5SSean Brunopenalty applicable. 768fabe02f5SSean Bruno.It Li UOPS_RETIRED.ALL 769fabe02f5SSean Bruno.Pq Event C2H , Umask 01H 770fabe02f5SSean BrunoCounts the number of micro-ops retired, Use 771fabe02f5SSean Brunocmask=1 and invert to count active cycles or stalled 772fabe02f5SSean Brunocycles. 773fabe02f5SSean Bruno.It Li UOPS_RETIRED.RETIRE_SLOTS 774fabe02f5SSean Bruno.Pq Event C2H , Umask 02H 775fabe02f5SSean BrunoCounts the number of retirement slots used each 776fabe02f5SSean Brunocycle. 777fabe02f5SSean Bruno.It Li MACHINE_CLEARS.MEMORY_ORDERING 778fabe02f5SSean Bruno.Pq Event C3H , Umask 02H 779fabe02f5SSean BrunoCounts the number of machine clears due to 780fabe02f5SSean Brunomemory order conflicts. 781fabe02f5SSean Bruno.It Li MACHINE_CLEARS.SMC 782fabe02f5SSean Bruno.Pq Event C3H , Umask 04H 783fabe02f5SSean BrunoCounts the number of times that a program writes 784fabe02f5SSean Brunoto a code section. 785fabe02f5SSean Bruno.It Li MACHINE_CLEARS.MASKMOV 786fabe02f5SSean Bruno.Pq Event C3H , Umask 20H 787fabe02f5SSean BrunoCounts the number of executed AVX masked load 788fabe02f5SSean Brunooperations that refer to an illegal address range 789fabe02f5SSean Brunowith the mask bits set to 0. 790fabe02f5SSean Bruno.It Li BR_INST_RETIRED.ALL_BRANCH 791fabe02f5SSean Bruno.Pq Event C4H , Umask 00H 792fabe02f5SSean BrunoBranch instructions at retirement. 793fabe02f5SSean Bruno.It Li BR_INST_RETIRED.CONDITIONAL 794fabe02f5SSean Bruno.Pq Event C4H , Umask 01H 795fabe02f5SSean BrunoCounts the number of conditional branch 796fabe02f5SSean Brunoinstructions retired. 797fabe02f5SSean Bruno.It Li BR_INST_RETIRED.NEAR_CALL 798fabe02f5SSean Bruno.Pq Event C4H , Umask 02H 799fabe02f5SSean BrunoDirect and indirect near call instructions retired. 800fabe02f5SSean Bruno.It Li BR_INST_RETIRED.ALL_BRANCHES 801fabe02f5SSean Bruno.Pq Event C4H , Umask 04H 802fabe02f5SSean BrunoCounts the number of branch instructions retired. 803fabe02f5SSean Bruno.It Li BR_INST_RETIRED.NEAR_RETURN 804fabe02f5SSean Bruno.Pq Event C4H , Umask 08H 805fabe02f5SSean BrunoCounts the number of near return instructions 806fabe02f5SSean Brunoretired. 807fabe02f5SSean Bruno.It Li BR_INST_RETIRED.NOT_TAKEN 808fabe02f5SSean Bruno.Pq Event C4H , Umask 10H 809fabe02f5SSean BrunoCounts the number of not taken branch instructions 810fabe02f5SSean Brunoretired. 811fabe02f5SSean Bruno.It Li BR_INST_RETIRED.NEAR_TAKEN 812fabe02f5SSean Bruno.Pq Event C4H , Umask 20H 813fabe02f5SSean BrunoNumber of near taken branches retired. 814fabe02f5SSean Bruno.It Li BR_INST_RETIRED.FAR_BRANCH 815fabe02f5SSean Bruno.Pq Event C4H , Umask 40H 816fabe02f5SSean BrunoNumber of far branches retired. 817fabe02f5SSean Bruno.It Li BR_MISP_RETIRED.ALL_BRANCHES 818fabe02f5SSean Bruno.Pq Event C5H , Umask 00H 819fabe02f5SSean BrunoMispredicted branch instructions at retirement. 820fabe02f5SSean Bruno.It Li BR_MISP_RETIRED.CONDITIONAL 821fabe02f5SSean Bruno.Pq Event C5H , Umask 01H 822fabe02f5SSean BrunoMispredicted conditional branch instructions retired. 823fabe02f5SSean Bruno.It Li BR_MISP_RETIRED.NEAR_CALL 824fabe02f5SSean Bruno.Pq Event C5H , Umask 02H 825fabe02f5SSean BrunoDirect and indirect mispredicted near call 826fabe02f5SSean Brunoinstructions retired. 827fabe02f5SSean Bruno.It Li BR_MISP_RETIRED.ALL_BRANCHES 828fabe02f5SSean Bruno.Pq Event C5H , Umask 04H 829fabe02f5SSean BrunoMispredicted macro branch instructions retired. 830fabe02f5SSean Bruno.It Li BR_MISP_RETIRED.NOT_TAKEN 831fabe02f5SSean Bruno.Pq Event C5H , Umask 10H 832fabe02f5SSean BrunoMispredicted not taken branch instructions retired. 833fabe02f5SSean Bruno.It Li BR_MISP_RETIRED.TAKEN 834fabe02f5SSean Bruno.Pq Event C5H , Umask 20H 835fabe02f5SSean BrunoMispredicted taken branch instructions retired. 836fabe02f5SSean Bruno.It Li FP_ASSIST.X87_OUTPUT 837fabe02f5SSean Bruno.Pq Event CAH , Umask 02H 838fabe02f5SSean BrunoNumber of X87 assists due to output value. 839fabe02f5SSean Bruno.It Li FP_ASSIST.X87_INPUT 840fabe02f5SSean Bruno.Pq Event CAH , Umask 04H 841fabe02f5SSean BrunoNumber of X87 assists due to input value. 842fabe02f5SSean Bruno.It Li FP_ASSIST.SIMD_OUTPUT 843fabe02f5SSean Bruno.Pq Event CAH , Umask 08H 844fabe02f5SSean Bruno Number of SIMD FP assists due to output values. 845fabe02f5SSean Bruno.It Li FP_ASSIST.SIMD_INPUT 846fabe02f5SSean Bruno.Pq Event CAH , Umask 10H 847fabe02f5SSean BrunoNumber of SIMD FP assists due to input values. 848fabe02f5SSean Bruno.It Li FP_ASSIST.ANY 1EH 849fabe02f5SSean Bruno.Pq Event CAH , Umask 850fabe02f5SSean BrunoCycles with any input/output SSE* or FP assists. 851fabe02f5SSean Bruno.It Li ROB_MISC_EVENTS.LBR_INSERTS 852fabe02f5SSean Bruno.Pq Event CCH , Umask 20H 853fabe02f5SSean BrunoCount cases of saving new LBR records by 854fabe02f5SSean Brunohardware. 855fabe02f5SSean Bruno.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 856fabe02f5SSean Bruno.Pq Event CDH , Umask 01H 857fabe02f5SSean BrunoSample loads with specified latency threshold. 858fabe02f5SSean BrunoPMC3 only. 859fabe02f5SSean Bruno.It Li MEM_TRANS_RETIRED.PRECISE_STORE 860fabe02f5SSean Bruno.Pq Event CDH , Umask 02H 861fabe02f5SSean BrunoSample stores and collect precise store operation 862fabe02f5SSean Brunovia PEBS record. PMC3 only. 863fabe02f5SSean Bruno.It Li MEM_UOP_RETIRED.LOADS 864fabe02f5SSean Bruno.Pq Event D0H , Umask 10H 865fabe02f5SSean BrunoQualify retired memory uops that are loads. 866fabe02f5SSean BrunoCombine with umask 10H, 20H, 40H, 80H. 867fabe02f5SSean Bruno.It Li MEM_UOP_RETIRED.STORES 868fabe02f5SSean Bruno.Pq Event D0H , Umask 02H 869fabe02f5SSean BrunoQualify retired memory uops that are stores. 870fabe02f5SSean BrunoCombine with umask 10H, 20H, 40H, 80H. 871fabe02f5SSean Bruno.It Li MEM_UOP_RETIRED.STLB_MISS 872fabe02f5SSean Bruno.Pq Event D0H , Umask 873fabe02f5SSean BrunoQualify retired memory uops with STLB miss. Must 874fabe02f5SSean Brunocombine with umask 01H, 02H, to produce counts. 875fabe02f5SSean Bruno.It Li MEM_UOP_RETIRED.LOCK 876fabe02f5SSean Bruno.Pq Event D0H , Umask 877fabe02f5SSean BrunoQualify retired memory uops with lock. Must 878fabe02f5SSean Brunocombine with umask 01H, 02H, to produce counts. 879fabe02f5SSean Bruno.It Li MEM_UOP_RETIRED.SPLIT 880fabe02f5SSean Bruno.Pq Event D0H , Umask 881fabe02f5SSean BrunoQualify retired memory uops with line split. Must 882fabe02f5SSean Brunocombine with umask 01H, 02H, to produce counts. 883fabe02f5SSean Bruno.It Li MEM_UOP_RETIRED_ALL 884fabe02f5SSean Bruno.Pq Event D0H , Umask 885fabe02f5SSean BrunoQualify any retired memory uops. Must combine 886fabe02f5SSean Brunowith umask 01H, 02H, to produce counts. 887fabe02f5SSean Bruno.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 888fabe02f5SSean Bruno.Pq Event D1H , Umask 01H 889fabe02f5SSean BrunoRetired load uops with L1 cache hits as data 890fabe02f5SSean Brunosources. 891fabe02f5SSean Bruno.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 892fabe02f5SSean Bruno.Pq Event D1H , Umask 02H 893fabe02f5SSean BrunoRetired load uops with L2 cache hits as data 894fabe02f5SSean Brunosources. 895fabe02f5SSean Bruno.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 896fabe02f5SSean Bruno.Pq Event D1H , Umask 04H 897fabe02f5SSean BrunoRetired load uops which data sources were data hits 898fabe02f5SSean Brunoin LLC without snoops required. 899fabe02f5SSean Bruno.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS 900fabe02f5SSean Bruno.Pq Event D1H , Umask 20H 901fabe02f5SSean BrunoRetired load uops which data sources were data 902fabe02f5SSean Brunomissed LLC (excluding unknown data source). 903fabe02f5SSean Bruno.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 904fabe02f5SSean Bruno.Pq Event D1H , Umask 40H 905fabe02f5SSean BrunoRetired load uops which data sources were load 906fabe02f5SSean Brunouops missed L1 but hit FB due to preceding miss to 907fabe02f5SSean Brunothe same cache line with data not ready. 908fabe02f5SSean Bruno.It Li MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS 909fabe02f5SSean Bruno.Pq Event D4H , Umask 02H 910fabe02f5SSean BrunoRetired load uops with unknown information as data 911fabe02f5SSean Brunosource in cache serviced the load. 912fabe02f5SSean Bruno.It Li BACLEARS.ANY 913fabe02f5SSean Bruno.Pq Event E6H , Umask 01H 914fabe02f5SSean BrunoCounts the number of times the front end is re- 915fabe02f5SSean Brunosteered, mainly when the BPU cannot provide a 916fabe02f5SSean Brunocorrect prediction and this is corrected by other 917fabe02f5SSean Brunobranch handling mechanisms at the front end. 918fabe02f5SSean Bruno.It Li L2_TRANS.DEMAND_DATA_RD 919fabe02f5SSean Bruno.Pq Event F0H , Umask 01H 920fabe02f5SSean BrunoDemand Data Read requests that access L2 cache. 921fabe02f5SSean Bruno.It Li L2_TRANS.RFO 922fabe02f5SSean Bruno.Pq Event F0H , Umask 02H 923fabe02f5SSean BrunoRFO requests that access L2 cache. 924fabe02f5SSean Bruno.It Li L2_TRANS.CODE_RD 925fabe02f5SSean Bruno.Pq Event F0H , Umask 04H 926fabe02f5SSean BrunoL2 cache accesses when fetching instructions. 927fabe02f5SSean Bruno.It Li L2_TRANS.ALL_PF 928fabe02f5SSean Bruno.Pq Event F0H , Umask 08H 929fabe02f5SSean BrunoL2 or LLC HW prefetches that access L2 cache. 930fabe02f5SSean Bruno.It Li L2_TRANS.L1D_WB 931fabe02f5SSean Bruno.Pq Event F0H , Umask 10H 932fabe02f5SSean BrunoL1D writebacks that access L2 cache. 933fabe02f5SSean Bruno.It Li L2_TRANS.L2_FILL 934fabe02f5SSean Bruno.Pq Event F0H , Umask 20H 935fabe02f5SSean BrunoL2 fill requests that access L2 cache. 936fabe02f5SSean Bruno.It Li L2_TRANS.L2_WB 937fabe02f5SSean Bruno.Pq Event F0H , Umask 40H 938fabe02f5SSean BrunoL2 writebacks that access L2 cache. 939fabe02f5SSean Bruno.It Li L2_TRANS.ALL_REQUESTS 940fabe02f5SSean Bruno.Pq Event F0H , Umask 80H 941fabe02f5SSean BrunoTransactions accessing L2 pipe. 942fabe02f5SSean Bruno.It Li L2_LINES_IN.I 943fabe02f5SSean Bruno.Pq Event F1H , Umask 01H 944fabe02f5SSean BrunoL2 cache lines in I state filling L2. 945fabe02f5SSean Bruno.It Li L2_LINES_IN.S 946fabe02f5SSean Bruno.Pq Event F1H , Umask 02H 947fabe02f5SSean BrunoL2 cache lines in S state filling L2. 948fabe02f5SSean Bruno.It Li L2_LINES_IN.E 949fabe02f5SSean Bruno.Pq Event F1H , Umask 04H 950fabe02f5SSean BrunoL2 cache lines in E state filling L2. 951fabe02f5SSean Bruno.It Li L2_LINES-IN.ALL 952fabe02f5SSean Bruno.Pq Event F1H , Umask 07H 953fabe02f5SSean BrunoL2 cache lines filling L2. 954fabe02f5SSean Bruno.It Li L2_LINES_OUT.DEMAND_CLEAN 955fabe02f5SSean Bruno.Pq Event F2H , Umask 01H 956fabe02f5SSean BrunoClean L2 cache lines evicted by demand. 957fabe02f5SSean Bruno.It Li L2_LINES_OUT.DEMAND_DIRTY 958fabe02f5SSean Bruno.Pq Event F2H , Umask 02H 959fabe02f5SSean BrunoDirty L2 cache lines evicted by demand. 960fabe02f5SSean Bruno.It Li L2_LINES_OUT.PF_CLEAN 961fabe02f5SSean Bruno.Pq Event F2H , Umask 04H 962fabe02f5SSean BrunoClean L2 cache lines evicted by L2 prefetch. 963fabe02f5SSean Bruno.It Li L2_LINES_OUT.PF_DIRTY 964fabe02f5SSean Bruno.Pq Event F2H , Umask 08H 965fabe02f5SSean BrunoDirty L2 cache lines evicted by L2 prefetch. 966fabe02f5SSean Bruno.It Li L2_LINES_OUT.DIRTY_ALL 967fabe02f5SSean Bruno.Pq Event F2H , Umask 0AH 968fabe02f5SSean BrunoDirty L2 cache lines filling the L2. 969fabe02f5SSean Bruno.It Li SQ_MISC.SPLIT_LOCK 970fabe02f5SSean Bruno.Pq Event F4H , Umask 10H 971fabe02f5SSean BrunoSplit locks in SQ. 972fabe02f5SSean Bruno.El 973fabe02f5SSean Bruno.Sh SEE ALSO 974fabe02f5SSean Bruno.Xr pmc 3 , 975fabe02f5SSean Bruno.Xr pmc.atom 3 , 976fabe02f5SSean Bruno.Xr pmc.core 3 , 97773461c24SJoel Dahl.Xr pmc.corei7 3 , 97873461c24SJoel Dahl.Xr pmc.corei7uc 3 , 97973461c24SJoel Dahl.Xr pmc.haswelluc 3 , 980fabe02f5SSean Bruno.Xr pmc.iaf 3 , 98173461c24SJoel Dahl.Xr pmc.ivybridge 3 , 98273461c24SJoel Dahl.Xr pmc.ivybridgexeon 3 , 983fabe02f5SSean Bruno.Xr pmc.k7 3 , 984fabe02f5SSean Bruno.Xr pmc.k8 3 , 985fabe02f5SSean Bruno.Xr pmc.p4 3 , 986fabe02f5SSean Bruno.Xr pmc.p5 3 , 987fabe02f5SSean Bruno.Xr pmc.p6 3 , 988fabe02f5SSean Bruno.Xr pmc.sandybridge 3 , 989fabe02f5SSean Bruno.Xr pmc.sandybridgeuc 3 , 990fabe02f5SSean Bruno.Xr pmc.soft 3 , 991fabe02f5SSean Bruno.Xr pmc.tsc 3 , 99273461c24SJoel Dahl.Xr pmc.ucf 3 , 99373461c24SJoel Dahl.Xr pmc.westmere 3 , 99473461c24SJoel Dahl.Xr pmc.westmereuc 3 , 995fabe02f5SSean Bruno.Xr pmc_cpuinfo 3 , 996fabe02f5SSean Bruno.Xr pmclog 3 , 997fabe02f5SSean Bruno.Xr hwpmc 4 998fabe02f5SSean Bruno.Sh HISTORY 999fabe02f5SSean BrunoThe 1000fabe02f5SSean Bruno.Nm pmc 1001fabe02f5SSean Brunolibrary first appeared in 1002fabe02f5SSean Bruno.Fx 6.0 . 1003fabe02f5SSean Bruno.Sh AUTHORS 10042b7af31cSBaptiste Daroussin.An -nosplit 1005fabe02f5SSean BrunoThe 1006fabe02f5SSean Bruno.Lb libpmc 1007fabe02f5SSean Brunolibrary was written by 10082b7af31cSBaptiste Daroussin.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1009fabe02f5SSean BrunoThe support for the Sandy Bridge Xeon 1010fabe02f5SSean Brunomicroarchitecture was written by 10112b7af31cSBaptiste Daroussin.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 1012