1.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd October 19, 2012 26.Dt PMC.SANDYBRIDGEUC 3 27.Os 28.Sh NAME 29.Nm pmc.sandybridgeuc 30.Nd uncore measurement events for 31.Tn Intel 32.Tn Sandy Bridge 33family CPUs 34.Sh LIBRARY 35.Lb libpmc 36.Sh SYNOPSIS 37.In pmc.h 38.Sh DESCRIPTION 39.Tn Intel 40.Tn "Sandy Bridge" 41CPUs contain PMCs conforming to version 3 of the 42.Tn Intel 43performance measurement architecture. 44These CPUs contain two classes of PMCs: 45.Bl -tag -width "Li PMC_CLASS_UCP" 46.It Li PMC_CLASS_UCF 47Fixed-function counters that count only one hardware event per counter. 48.It Li PMC_CLASS_UCP 49Programmable counters that may be configured to count one of a defined 50set of hardware events. 51.El 52.Pp 53The number of PMCs available in each class and their widths need to be 54determined at run time by calling 55.Xr pmc_cpuinfo 3 . 56.Pp 57Intel Sandy Bridge PMCs are documented in 58.Rs 59.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 60.%T "Volume 3B: System Programming Guide, Part 2" 61.%N "Order Number: 253669-039US" 62.%D May 2011 63.%Q "Intel Corporation" 64.Re 65.Ss SANDYBRIDGE UNCORE FIXED FUNCTION PMCS 66These PMCs and their supported events are documented in 67.Xr pmc.ucf 3 . 68Not all CPUs in this family implement fixed-function counters. 69.Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta \&No 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta \&No 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta \&No 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li cmask= Ns Ar value 90Configure the PMC to increment only if the number of configured 91events measured in a cycle is greater than or equal to 92.Ar value . 93.It Li edge 94Configure the PMC to count the number of de-asserted to asserted 95transitions of the conditions expressed by the other qualifiers. 96If specified, the counter will increment only once whenever a 97condition becomes true, irrespective of the number of clocks during 98which the condition remains true. 99.It Li inv 100Invert the sense of comparison when the 101.Dq Li cmask 102qualifier is present, making the counter increment when the number of 103events per cycle is less than the value specified by the 104.Dq Li cmask 105qualifier. 106.El 107.Ss Event Specifiers (Programmable PMCs) 108Sandy Bridge programmable PMCs support the following events: 109.Bl -tag -width indent 110.It Li CBO_XSNP_RESPONSE.RSPIHITI 111.Pq Event 22H, Umask 01H 112Snoop responses received from processor cores to requests initiated by this 113Cbox. 114Must combine with one of the umask values of 20H, 40H, 80H 115.It Li CBO_XSNP_RESPONSE.RSPIHITFSE 116.Pq Event 22H, Umask 02H 117Must combine with one of the umask values of 20H, 40H, 80H 118.It Li CBO_XSNP_RESPONSE.RSPSHITFSE 119.Pq Event 22H, Umask 04H 120Must combine with one of the umask values of 20H, 40H, 80H 121.It Li CBO_XSNP_RESPONSE.RSPSFWDM 122.Pq Event 22H, Umask 08H 123.It Li CBO_XSNP_RESPONSE.RSPIFWDM 124.Pq Event 22H, Umask 01H 125.It Li CBO_XSNP_RESPONSE.AND_EXTERNAL 126.Pq Event 22H, Umask 20H 127Filter on cross-core snoops resulted in external snoop request. 128Must combine with at least one of 01H, 02H, 04H, 08H, 10H 129.It Li CBO_XSNP_RESPONSE.AND_XCORE 130.Pq Event 22H, Umask 40H 131Filter on cross-core snoops resulted in core request. 132Must combine with at least one of 01H, 02H, 04H, 08H, 10H 133.It Li CBO_XSNP_RESPONSE.AND_XCORE 134.Pq Event 22H, Umask 80H 135Filter on cross-core snoops resulted in LLC evictions. 136Must combine with at least one of 01H, 02H, 04H, 08H, 10H 137.It Li CBO_CACHE_LOOKUP.M 138.Pq Event 34H, Umask 01H 139LLC lookup request that access cache and found line in M-state. 140Must combine with one of the umask values of 10H, 20H, 40H, 80H 141.It Li CBO_CACHE_LOOKUP.E 142.Pq Event 34H, Umask 02H 143LLC lookup request that access cache and found line in E-state. 144Must combine with one of the umask values of 10H, 20H, 40H, 80H 145.It Li CBO_CACHE_LOOKUP.S 146.Pq Event 34H, Umask 04H 147LLC lookup request that access cache and found line in S-state. 148Must combine with one of the umask values of 10H, 20H, 40H, 80H 149.It Li CBO_CACHE_LOOKUP.I 150.Pq Event 34H, Umask 08H 151LLC lookup request that access cache and found line in I-state. 152Must combine with one of the umask values of 10H, 20H, 40H, 80H 153.It Li CBO_CACHE_LOOKUP.AND_READ 154.Pq Event 34H, Umask 10H 155Filter on processor core initiated cacheable read requests. 156Must combine with at least one of 01H, 02H, 04H, 08H 157.It Li CBO_CACHE_LOOKUP_AND_READ2 158.Pq Event 34H, Umask 20H 159Filter on processor core initiated cacheable write requests. 160Must combine with at least one of 01H, 02H, 04H, 08H 161.It Li CBO_CACHE_LOOKUP.AND_EXTSNP 162.Pq Event 34H, Umask 40H 163Filter on external snoop requests. 164Must combine with at least one of 01H, 02H, 04H, 08H 165.It Li CBO_CACHE_LOOKUP.AND_ANY 166.Pq Event 34H, Umask 80H 167Filter on any IRQ or IPQ initiated requests including uncacheable, 168noncoherent requests. 169Must combine with at least one of 01H, 02H, 04H, 08H 170.It Li IMPH_CBO_TRK_OCCUPANCY.ALL 171.Pq Event 80H, Umask 01H 172Counts cycles weighted by the number of core-outgoing valid entries. 173Valid entries are between allocation to the first of IDIO or DRSO messages. 174Accounts for coherent and incoherent traffic. 175Counter 0 only 176.It Li IMPH_CBO_TRK_REQUEST.ALL 177.Pq Event 81H, Umask 01H 178Counts the number of core-outgoing entries. 179Accounts for coherent and incoherent traffic. 180.It Li IMPH_CBO_TRK_REQUEST.WRITES 181.Pq Event 81H, Umask 20H 182Counts the number of allocated write entries, include full, partial, and 183evictions. 184.It Li IMPH_CBO_TRK_REQUEST.EVICTIONS 185.Pq Event 81H, Umask 80H 186Counts the number of evictions allocated. 187.It Li IMPH_COH_TRK_OCCUPANCY.ALL 188.Pq Event 83H, Umask 01H 189Counts cycles weighted by the 190number of core-outgoing valid entries in the coherent tracker queue. 191Counter 0 only 192.It Li IMPH_COH_TRK_REQUEST.ALL 193.Pq Event 84H, Umask 01H 194Counts the number of core-outgoing entries in the coherent tracker queue. 195.El 196.Sh SEE ALSO 197.Xr pmc 3 , 198.Xr pmc.amd 3 , 199.Xr pmc.atom 3 , 200.Xr pmc.core 3 , 201.Xr pmc.corei7 3 , 202.Xr pmc.corei7uc 3 , 203.Xr pmc.iaf 3 , 204.Xr pmc.sandybridge 3 , 205.Xr pmc.sandybridgexeon 3 , 206.Xr pmc.soft 3 , 207.Xr pmc.tsc 3 , 208.Xr pmc.ucf 3 , 209.Xr pmc.westmere 3 , 210.Xr pmc.westmereuc 3 , 211.Xr pmc_cpuinfo 3 , 212.Xr pmclog 3 , 213.Xr hwpmc 4 214.Sh HISTORY 215The 216.Nm pmc 217library first appeared in 218.Fx 6.0 . 219.Sh AUTHORS 220.An -nosplit 221The 222.Lb libpmc 223library was written by 224.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 225The support for the Sandy Bridge 226microarchitecture was added by 227.An Davide Italiano Aq Mt davide@FreeBSD.org . 228