1.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd October 19, 2012 28.Dt PMC.SANDYBRIDGEUC 3 29.Os 30.Sh NAME 31.Nm pmc.sandybridgeuc 32.Nd uncore measurement events for 33.Tn Intel 34.Tn Sandy Bridge 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Sandy Bridge" 43CPUs contain PMCs conforming to version 3 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs contain two classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_UCP" 48.It Li PMC_CLASS_UCF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_UCP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.El 54.Pp 55The number of PMCs available in each class and their widths need to be 56determined at run time by calling 57.Xr pmc_cpuinfo 3 . 58.Pp 59Intel Sandy Bridge PMCs are documented in 60.Rs 61.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 62.%T "Volume 3B: System Programming Guide, Part 2" 63.%N "Order Number: 253669-039US" 64.%D May 2011 65.%Q "Intel Corporation" 66.Re 67.Ss SANDYBRIDGE UNCORE FIXED FUNCTION PMCS 68These PMCs and their supported events are documented in 69.Xr pmc.ucf 3 . 70Not all CPUs in this family implement fixed-function counters. 71.Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS 72The programmable PMCs support the following capabilities: 73.Bl -column "PMC_CAP_INTERRUPT" "Support" 74.It Em Capability Ta Em Support 75.It PMC_CAP_CASCADE Ta \&No 76.It PMC_CAP_EDGE Ta Yes 77.It PMC_CAP_INTERRUPT Ta \&No 78.It PMC_CAP_INVERT Ta Yes 79.It PMC_CAP_READ Ta Yes 80.It PMC_CAP_PRECISE Ta \&No 81.It PMC_CAP_SYSTEM Ta \&No 82.It PMC_CAP_TAGGING Ta \&No 83.It PMC_CAP_THRESHOLD Ta Yes 84.It PMC_CAP_USER Ta \&No 85.It PMC_CAP_WRITE Ta Yes 86.El 87.Ss Event Qualifiers 88Event specifiers for these PMCs support the following common 89qualifiers: 90.Bl -tag -width indent 91.It Li cmask= Ns Ar value 92Configure the PMC to increment only if the number of configured 93events measured in a cycle is greater than or equal to 94.Ar value . 95.It Li edge 96Configure the PMC to count the number of de-asserted to asserted 97transitions of the conditions expressed by the other qualifiers. 98If specified, the counter will increment only once whenever a 99condition becomes true, irrespective of the number of clocks during 100which the condition remains true. 101.It Li inv 102Invert the sense of comparison when the 103.Dq Li cmask 104qualifier is present, making the counter increment when the number of 105events per cycle is less than the value specified by the 106.Dq Li cmask 107qualifier. 108.El 109.Ss Event Specifiers (Programmable PMCs) 110Sandy Bridge programmable PMCs support the following events: 111.Bl -tag -width indent 112.It Li CBO_XSNP_RESPONSE.RSPIHITI 113.Pq Event 22H, Umask 01H 114Snoop responses received from processor cores to requests initiated by this 115Cbox. 116Must combine with one of the umask values of 20H, 40H, 80H 117.It Li CBO_XSNP_RESPONSE.RSPIHITFSE 118.Pq Event 22H, Umask 02H 119Must combine with one of the umask values of 20H, 40H, 80H 120.It Li CBO_XSNP_RESPONSE.RSPSHITFSE 121.Pq Event 22H, Umask 04H 122Must combine with one of the umask values of 20H, 40H, 80H 123.It Li CBO_XSNP_RESPONSE.RSPSFWDM 124.Pq Event 22H, Umask 08H 125.It Li CBO_XSNP_RESPONSE.RSPIFWDM 126.Pq Event 22H, Umask 01H 127.It Li CBO_XSNP_RESPONSE.AND_EXTERNAL 128.Pq Event 22H, Umask 20H 129Filter on cross-core snoops resulted in external snoop request. 130Must combine with at least one of 01H, 02H, 04H, 08H, 10H 131.It Li CBO_XSNP_RESPONSE.AND_XCORE 132.Pq Event 22H, Umask 40H 133Filter on cross-core snoops resulted in core request. 134Must combine with at least one of 01H, 02H, 04H, 08H, 10H 135.It Li CBO_XSNP_RESPONSE.AND_XCORE 136.Pq Event 22H, Umask 80H 137Filter on cross-core snoops resulted in LLC evictions. 138Must combine with at least one of 01H, 02H, 04H, 08H, 10H 139.It Li CBO_CACHE_LOOKUP.M 140.Pq Event 34H, Umask 01H 141LLC lookup request that access cache and found line in M-state. 142Must combine with one of the umask values of 10H, 20H, 40H, 80H 143.It Li CBO_CACHE_LOOKUP.E 144.Pq Event 34H, Umask 02H 145LLC lookup request that access cache and found line in E-state. 146Must combine with one of the umask values of 10H, 20H, 40H, 80H 147.It Li CBO_CACHE_LOOKUP.S 148.Pq Event 34H, Umask 04H 149LLC lookup request that access cache and found line in S-state. 150Must combine with one of the umask values of 10H, 20H, 40H, 80H 151.It Li CBO_CACHE_LOOKUP.I 152.Pq Event 34H, Umask 08H 153LLC lookup request that access cache and found line in I-state. 154Must combine with one of the umask values of 10H, 20H, 40H, 80H 155.It Li CBO_CACHE_LOOKUP.AND_READ 156.Pq Event 34H, Umask 10H 157Filter on processor core initiated cacheable read requests. 158Must combine with at least one of 01H, 02H, 04H, 08H 159.It Li CBO_CACHE_LOOKUP_AND_READ2 160.Pq Event 34H, Umask 20H 161Filter on processor core initiated cacheable write requests. 162Must combine with at least one of 01H, 02H, 04H, 08H 163.It Li CBO_CACHE_LOOKUP.AND_EXTSNP 164.Pq Event 34H, Umask 40H 165Filter on external snoop requests. 166Must combine with at least one of 01H, 02H, 04H, 08H 167.It Li CBO_CACHE_LOOKUP.AND_ANY 168.Pq Event 34H, Umask 80H 169Filter on any IRQ or IPQ initiated requests including uncacheable, 170noncoherent requests. 171Must combine with at least one of 01H, 02H, 04H, 08H 172.It Li IMPH_CBO_TRK_OCCUPANCY.ALL 173.Pq Event 80H, Umask 01H 174Counts cycles weighted by the number of core-outgoing valid entries. 175Valid entries are between allocation to the first of IDIO or DRSO messages. 176Accounts for coherent and incoherent traffic. 177Counter 0 only 178.It Li IMPH_CBO_TRK_REQUEST.ALL 179.Pq Event 81H, Umask 01H 180Counts the number of core-outgoing entries. 181Accounts for coherent and incoherent traffic. 182.It Li IMPH_CBO_TRK_REQUEST.WRITES 183.Pq Event 81H, Umask 20H 184Counts the number of allocated write entries, include full, partial, and 185evictions. 186.It Li IMPH_CBO_TRK_REQUEST.EVICTIONS 187.Pq Event 81H, Umask 80H 188Counts the number of evictions allocated. 189.It Li IMPH_COH_TRK_OCCUPANCY.ALL 190.Pq Event 83H, Umask 01H 191Counts cycles weighted by the 192number of core-outgoing valid entries in the coherent tracker queue. 193Counter 0 only 194.It Li IMPH_COH_TRK_REQUEST.ALL 195.Pq Event 84H, Umask 01H 196Counts the number of core-outgoing entries in the coherent tracker queue. 197.El 198.Sh SEE ALSO 199.Xr pmc 3 , 200.Xr pmc.atom 3 , 201.Xr pmc.core 3 , 202.Xr pmc.corei7 3 , 203.Xr pmc.corei7uc 3 , 204.Xr pmc.iaf 3 , 205.Xr pmc.k7 3 , 206.Xr pmc.k8 3 , 207.Xr pmc.sandybridge 3 , 208.Xr pmc.sandybridgexeon 3 , 209.Xr pmc.soft 3 , 210.Xr pmc.tsc 3 , 211.Xr pmc.ucf 3 , 212.Xr pmc.westmere 3 , 213.Xr pmc.westmereuc 3 , 214.Xr pmc_cpuinfo 3 , 215.Xr pmclog 3 , 216.Xr hwpmc 4 217.Sh HISTORY 218The 219.Nm pmc 220library first appeared in 221.Fx 6.0 . 222.Sh AUTHORS 223.An -nosplit 224The 225.Lb libpmc 226library was written by 227.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 228The support for the Sandy Bridge 229microarchitecture was added by 230.An Davide Italiano Aq Mt davide@FreeBSD.org . 231