1.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd February 12, 2012 28.Dt PMC.SANDYBRIDGE 3 29.Os 30.Sh NAME 31.Nm pmc.sandybridge 32.Nd measurement events for 33.Tn Intel 34.Tn Sandy Bridge 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Sandy Bridge" 43CPUs contain PMCs conforming to the version 3 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs may contain up to three classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_IAP" 48.It Li PMC_CLASS_IAF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_IAP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.It Li PMC_CLASS_TSC 54These PMCs are documented in 55.Xr pmc.tsc 3 . 56.El 57.Pp 58The number of PMCs available in each class and their widths need to be 59determined at run time by calling 60.Xr pmc_cpuinfo 3 . 61.Pp 62Intel Sandy Bridge PMCs are documented in 63.Rs 64.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 65.%T "Volume 3B: System Programming Guide, Part 2" 66.%N "Order Number: 253669-039US" 67.%D May 2011 68.%Q "Intel Corporation" 69.Re 70.Ss SANDY BRIDGE FIXED FUNCTION PMCS 71These PMCs and their supported events are documented in 72.Xr pmc.iaf 3 . 73.Ss SANDY BRIDGE PROGRAMMABLE PMCS 74The programmable PMCs support the following capabilities: 75.Bl -column "PMC_CAP_INTERRUPT" "Support" 76.It Em Capability Ta Em Support 77.It PMC_CAP_CASCADE Ta \&No 78.It PMC_CAP_EDGE Ta Yes 79.It PMC_CAP_INTERRUPT Ta Yes 80.It PMC_CAP_INVERT Ta Yes 81.It PMC_CAP_READ Ta Yes 82.It PMC_CAP_PRECISE Ta \&No 83.It PMC_CAP_SYSTEM Ta Yes 84.It PMC_CAP_TAGGING Ta \&No 85.It PMC_CAP_THRESHOLD Ta Yes 86.It PMC_CAP_USER Ta Yes 87.It PMC_CAP_WRITE Ta Yes 88.El 89.Ss Event Qualifiers 90Event specifiers for these PMCs support the following common 91qualifiers: 92.Bl -tag -width indent 93.It Li rsp= Ns Ar value 94Configure the Off-core Response bits. 95.Bl -tag -width indent 96.It Li DMND_DATA_RD 97Counts the number of demand and DCU prefetch data reads of full 98and partial cachelines as well as demand data page table entry 99cacheline reads. 100Does not count L2 data read prefetches or instruction fetches. 101.It Li DMND_RFO 102Counts the number of demand and DCU prefetch reads for ownership 103(RFO) requests generated by a write to data cacheline. 104Does not count L2 RFO. 105.It Li DMND_IFETCH 106Counts the number of demand and DCU prefetch instruction cacheline 107reads. 108Does not count L2 code read prefetches. 109.It Li WB 110Counts the number of writeback (modified to exclusive) transactions. 111.It Li PF_DATA_RD 112Counts the number of data cacheline reads generated by L2 prefetchers. 113.It Li PF_RFO 114Counts the number of RFO requests generated by L2 prefetchers. 115.It Li PF_IFETCH 116Counts the number of code reads generated by L2 prefetchers. 117.It Li OTHER 118Counts one of the following transaction types, including L3 invalidate, 119I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, 120lock, unlock, split lock. 121.It Li UNCORE_HIT 122L3 Hit: local or remote home requests that hit L3 cache in the uncore 123with no coherency actions required (snooping). 124.It Li OTHER_CORE_HIT_SNP 125L3 Hit: local or remote home requests that hit L3 cache in the uncore 126and was serviced by another core with a cross core snoop where no modified 127copies were found (clean). 128.It Li OTHER_CORE_HITM 129L3 Hit: local or remote home requests that hit L3 cache in the uncore 130and was serviced by another core with a cross core snoop where modified 131copies were found (HITM). 132.It Li REMOTE_CACHE_FWD 133L3 Miss: local homed requests that missed the L3 cache and was serviced 134by forwarded data following a cross package snoop where no modified 135copies found. 136(Remote home requests are not counted) 137.It Li REMOTE_DRAM 138L3 Miss: remote home requests that missed the L3 cache and were serviced 139by remote DRAM. 140.It Li LOCAL_DRAM 141L3 Miss: local home requests that missed the L3 cache and were serviced 142by local DRAM. 143.It Li NON_DRAM 144Non-DRAM requests that were serviced by IOH. 145.El 146.It Li cmask= Ns Ar value 147Configure the PMC to increment only if the number of configured 148events measured in a cycle is greater than or equal to 149.Ar value . 150.It Li edge 151Configure the PMC to count the number of de-asserted to asserted 152transitions of the conditions expressed by the other qualifiers. 153If specified, the counter will increment only once whenever a 154condition becomes true, irrespective of the number of clocks during 155which the condition remains true. 156.It Li inv 157Invert the sense of comparison when the 158.Dq Li cmask 159qualifier is present, making the counter increment when the number of 160events per cycle is less than the value specified by the 161.Dq Li cmask 162qualifier. 163.It Li os 164Configure the PMC to count events happening at processor privilege 165level 0. 166.It Li usr 167Configure the PMC to count events occurring at privilege levels 1, 2 168or 3. 169.El 170.Pp 171If neither of the 172.Dq Li os 173or 174.Dq Li usr 175qualifiers are specified, the default is to enable both. 176.Ss Event Specifiers (Programmable PMCs) 177Sandy Bridge programmable PMCs support the following events: 178.Bl -tag -width indent 179.It Li LD_BLOCKS.DATA_UNKNOWN 180.Pq EVENT_03H, Umask 01H 181Blocked loads due to store buffer blocks with unknown data. 182.It Li LD_BLOCKS.STORE_FORWARD 183.Pq Event 03H, Umask 02H 184Loads blocked by overlapping with store buffer that cannot be forwarded. 185.It Li LD_BLOCKS.NO_SR 186.Pq Event 03H, Umask 08H 187# of Split loads blocked due to resource not available. 188.It Li LD_BLOCKS.ALL_BLOCK 189.Pq EVENT_03H, Umask 10H 190Number of cases where any load is blocked but has no DCU miss. 191.It Li MISALIGN_MEM_REF.LOADS 192.Pq Event 05H, Umask 01H 193Speculative cache-line split load uops dispatched to L1D. 194.It Li MISALIGN_MEM_REF.STORES 195.Pq Event 05H, Umask 02H 196Speculative cache-line split Store-address uops dispatched to L1D. 197.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 198.Pq Event 07H, Umask 01H 199False dependencies in MOB due to partial compare on address. 200.It Li LD_BLOCKS_PARTIAL.ALL_STA_BLOCK 201.Pq Event 07H, Umask 08H 202The number of times that load operations are temporarily blocked because of 203older stores, with addresses that are not yet known. 204A load operation may incur more than one block of this type. 205.It LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK 206.Pq Event 08H, Umask 01H 207Misses in all TLB levels that cause a page walk of any page size. 208.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 209.Pq Event 08H, Umask 02H 210Misses in all TLB levels that caused page walk completed of any size. 211.It Li DTLB_LOAD_MISSES.WALK_DURATION 212.Pq Event 08H, Umask 04H 213Cycle PMH is busy with a walk. 214.It Li DTLB_LOAD_MISSES.STLB_HIT 215.Pq Event 08H, Umask 10H 216Number of cache load STLB hits. 217No page walk. 218.It Li INT_MISC.RECOVERY_CYCLES 219.Pq Event 0DH, Umask 03H 220Cycles waiting to recover after Machine Clears or JEClear. 221Set Cmask = 1. 222Set Edge to count occurrences 223.It Li INT_MISC.RAT_STALL_CYCLES 224.Pq Event 0DH, Umask 40H 225Cycles RAT external stall is sent to IDQ for this thread. 226.It Li UOPS_ISSUED.ANY 227.Pq Event 0EH, Umask 01H 228Increments each cycle the # of Uops issued by the RAT to RS. 229Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core. 230Set Cmask = 1, Inv = 1 to count stalled cycles 231.It Li FP_COMP_OPS_EXE.X87 232.Pq Event 10H, Umask 01H 233Counts number of X87 uops executed. 234.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE 235.Pq Event 10H, Umask 10H 236Counts number of SSE* double precision FP packed uops executed. 237.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE 238.Pq Event 10H, Umask 20H 239Counts number of SSE* single precision FP scalar uops executed. 240.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE 241.Pq Event 10H, Umask 40H 242Counts number of SSE* single precision FP packed uops executed. 243.It LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE 244.Pq Event 10H, Umask 80H 245Counts number of SSE* double precision FP scalar uops executed. 246.It Li SIMD_FP_256.PACKED_SINGLE 247.Pq Event 11H, Umask 01H 248Counts 256-bit packed single-precision floating-point instructions. 249.It Li SIMD_FP_256.PACKED_DOUBLE 250.Pq Event 11H, Umask 02H 251Counts 256-bit packed double-precision floating-point instructions. 252.It Li ARITH.FPU_DIV_ACTIVE 253.Pq Event 14H, Umask 01H 254Cycles that the divider is active, includes INT and FP. 255Set 'edge =1, cmask=1' to count the number of divides. 256.It Li INSTS_WRITTEN_TO_IQ.INSTS 257.Pq Event 17H, Umask 01H 258Counts the number of instructions written into the IQ every cycle. 259.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 260.Pq Event 24H, Umask 01H 261Demand Data Read requests that hit L2 cache. 262.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 263.Pq Event 24H, Umask 03H 264Counts any demand and L1 HW prefetch data load requests to L2. 265.It Li L2_RQSTS.RFO_HITS 266.Pq Event 24H, Umask 04H 267Counts the number of store RFO requests that hit the L2 cache. 268.It Li L2_RQSTS.RFO_MISS 269.Pq Event 24H, Umask 08H 270Counts the number of store RFO requests that miss the L2 cache. 271.It Li L2_RQSTS.ALL_RFO 272.Pq Event 24H, Umask 0CH 273Counts all L2 store RFO requests. 274.It Li L2_RQSTS.CODE_RD_HIT 275.Pq Event 24H, Umask 10H 276Number of instruction fetches that hit the L2 cache. 277.It Li L2_RQSTS.CODE_RD_MISS 278.Pq Event 24H, Umask 20H 279Number of instruction fetches that missed the L2 cache. 280.It Li L2_RQSTS.ALL_CODE_RD 281.Pq Event 24H, Umask 30H 282Counts all L2 code requests. 283.It Li L2_RQSTS.PF_HIT 284.Pq Event 24H, Umask 40H 285Requests from L2 Hardware prefetcher that hit L2. 286.It Li L2_RQSTS.PF_MISS 287.Pq Event 24H, Umask 80H 288Requests from L2 Hardware prefetcher that missed L2. 289.It Li L2_RQSTS.ALL_PF 290.Pq Event 24H, Umask C0H 291Any requests from L2 Hardware prefetchers. 292.It Li L2_STORE_LOCK_RQSTS.MISS 293.Pq Event 27H, Umask 01H 294RFOs that miss cache lines. 295.It Li L2_STORE_LOCK_RQSTS.HIT_E 296.Pq Event 27H, Umask 04H 297RFOs that hit cache lines in E state. 298.It Li L2_STORE_LOCK_RQSTS.HIT_M 299.Pq EVENT_27H, Umask 08H 300RFOs that hit cache lines in M state. 301.It Li L2_STORE_LOCK_RQSTS.ALL 302.Pq EVENT_27H, Umask 0FH 303RFOs that access cache lines in any state. 304.It Li L2_L1D_WB_RQSTS.HIT_E 305.Pq Event 28H, Umask 04H 306Not rejected writebacks from L1D to L2 cache lines in E state. 307.It Li L2_L1D_WB_RQSTS.HIT_M 308.Pq Event 28H, Umask 08H 309Not rejected writebacks from L1D to L2 cache lines in M state. 310.It Li LONGEST_LAT_CACHE.REFERENCE 311.Pq Event 2EH, Umask 4FH 312This event counts requests originating from the core that reference a cache 313line in the last level cache. 314.It Li LONGEST_LAT_CACHE.MISS 315.Pq Event 2EH, Umask 41H 316This event counts each cache miss condition for references to the last level 317cache. 318.It Li CPU_CLK_UNHALTED.THREAD_P 319.Pq Event 3CH, Umask 00H 320Counts the number of thread cycles while the thread is not in a halt state. 321The thread enters the halt state when it is running the HLT instruction. 322The core frequency may change from time to time due to power or thermal 323throttling. 324.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 325.Pq Event 3CH, Umask 01H 326Increments at the frequency of XCLK (100 MHz) when not halted. 327.It Li L1D_PEND_MISS.PENDING 328.Pq Event 48H, Umask 01H 329Increments the number of outstanding L1D misses every cycle. 330Set Cmask = 1 and Edge =1 to count occurrences. 331Counter 2 only; Set Cmask = 1 to count cycles. 332.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 333.Pq Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any 334page size (4K/2M/4M/1G). 335.It Li DTLB_STORE_MISSES.WALK_COMPLETED 336.Pq Event 49H, Umask 02H 337Miss in all TLB levels causes a page walk that completes of any page size 338(4K/2M/4M/1G). 339.It Li DTLB_STORE_MISSES.WALK_DURATION 340.Pq Event 49H, Umask 04H 341Cycles PMH is busy with this walk. 342.It Li DTLB_STORE_MISSES.STLB_HIT 343.Pq Event 49H, Umask 10H 344Store operations that miss the first TLB level but hit the second and do not 345cause page walks. 346.It Li LOAD_HIT_PRE.SW_PF 347.Pq Event 4CH, Umask 01H 348Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. 349.It Li LOAD_HIT_PER.HW_PF 350.Pq Event 4CH, Umask 02H 351Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. 352.It Li HW_PRE_REQ.DL1_MISS 353.Pq Event 4EH, Umask 02H 354Hardware Prefetch requests that miss the L1D cache. 355A request is being counted each time it access the cache & miss it, including 356if a block is applicable or if hit the Fill Buffer for example. 357This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. 358.It Li L1D.REPLACEMENT 359.Pq Event 51H, Umask 01H 360Counts the number of lines brought into the L1 data cache. 361.It Li L1D.ALLOCATED_IN_M 362.Pq Event 51H, Umask 02H 363Counts the number of allocations of modified L1D cache lines. 364.It Li L1D.EVICTION 365.Pq Event 51H, Umask 04H 366Counts the number of modified lines evicted from the L1 data cache due to 367replacement. 368.It Li L1D.ALL_M_REPLACEMENT 369.Pq Event 51H, Umask 08H 370Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line 371replacement. 372.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP 373.Pq Event 59H, Umask 20H 374Increments the number of flags-merge uops in flight each cycle. 375Set Cmask = 1 to count cycles. 376.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW 377.Pq Event 59H, Umask 40H 378Cycles with at least one slow LEA uop allocated. 379.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP 380.Pq Event 59H, Umask 80H 381Number of Multiply packed/scalar single precision uops allocated. 382.It Li RESOURCE_STALLS2.ALL_FL_EMPTY 383.Pq Event 5BH, Umask 0CH 384Cycles stalled due to free list empty. 385.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL 386.Pq Event 5BH, Umask 0FH 387Cycles stalled due to control structures full for physical registers. 388.It Li RESOURCE_STALLS2.BOB_FULL 389.Pq Event 5BH, Umask 40H 390Cycles Allocator is stalled due to Branch Order Buffer. 391.It Li RESOURCE_STALLS2.OOO_RSRC 392.Pq Event 5BH, Umask 4FH 393Cycles stalled due to out of order resources full. 394.It Li CPL_CYCLES.RING0 395.Pq Event 5CH, Umask 01H 396Unhalted core cycles when the thread is in ring 0. 397Use Edge to count transition 398.It Li CPL_CYCLES.RING123 399.Pq Event 5CH, Umask 02H 400Unhalted core cycles when the thread is not in ring 0. 401.It Li RS_EVENTS.EMPTY_CYCLES 402.Pq Event 5EH, Umask 01H 403Cycles the RS is empty for the thread. 404.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 405.Pq Event 60H, Umask 01H 406Offcore outstanding Demand Data Read transactions in SQ to uncore. 407Set Cmask=1 to count cycles. 408.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 409.Pq Event 60H, Umask 04H 410Offcore outstanding RFO store transactions in SQ to uncore. 411Set Cmask=1 to count cycles. 412.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 413.Pq Event 60H, Umask 08H 414Offcore outstanding cacheable data read transactions in SQ to uncore. 415Set Cmask=1 to count cycles. 416.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 417.Pq Event 63H, Umask 01H 418Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 419.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 420.Pq Event 63H, Umask 02H 421Cycles in which the L1D is locked. 422.It Li IDQ.EMPTY 423.Pq Event 79H, Umask 02H 424Counts cycles the IDQ is empty. 425.It Li IQD.MITE_UOPS 426.Pq Event 79H, Umask 04H 427Increment each cycle # of uops delivered to IDQ from MITE path. 428Set Cmask = 1 to count cycles. 429Can combine Umask 04H and 20H 430.It Li IDQ.DSB_UOPS 431.Pq Event 79H, Umask 08H 432Increment each cycle. 433# of uops delivered to IDQ from DSB path. 434Set Cmask = 1 to count cycles. 435Can combine Umask 08H and 10H 436.It Li IDQ.MS_DSB_UOPS 437.Pq Event 79H, Umask 10H 438Increment each cycle # of uops delivered to IDQ when MS busy by DSB. 439Set Cmask = 1 to count cycles MS is busy. 440Set Cmask=1 and Edge=1 to count MS activations. 441Can combine Umask 08H and 10H 442.It Li IDQ.MS_MITE_UOPS 443.Pq Event 79H, Umask 20H 444Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. 445Set Cmask = 1 to count cycles. 446Can combine Umask 04H and 20H 447.It Li IDQ.MS_UOPS 448.Pq Event 79H, Umask 30H 449Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. 450Set Cmask = 1 to count cycles. 451Can combine Umask 04H, 08H and 30H 452.It Li ICACHE.MISSES 453.Pq Event 80H, Umask 02H 454Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 455Includes UC accesses. 456.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 457.Pq Event 85H, Umask 01H 458Misses in all ITLB levels that cause page walks. 459.It Li ITLB_MISSES.WALK_COMPLETED 460.Pq Event 85H, Umask 02H 461Misses in all ITLB levels that cause completed page walks. 462.It Li ITLB_MISSES.WALK_DURATION 463.Pq Event 85H, Umask 04H 464Cycle PMH is busy with a walk. 465.It Li ITLB_MISSES.STLB_HIT 466.Pq Event 85H, Umask 10H 467Number of cache load STLB hits. 468No page walk. 469.It Li ILD_STALL.LCP 470.Pq Event 87H, Umask 01H 471Stalls caused by changing prefix length of the instruction. 472.It Li ILD_STALL.IQ_FULL 473.Pq Event 87H, Umask 04H 474Stall cycles due to IQ is full. 475.It Li BR_INST_EXEC.COND 476.Pq Event 88H, Umask 01H 477Qualify conditional near branch instructions executed, but not necessarily 478retired. 479Must combine with umask 40H, 80H 480.It Li BR_INST_EXEC.DIRECT_JMP 481.Pq Event 88H, Umask 02H 482Qualify all unconditional near branch instructions excluding calls and indirect 483branches. 484Must combine with umask 80H 485.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 486.Pq Event 88H, Umask 04H 487Qualify executed indirect near branch instructions that are not calls nor 488returns. 489Must combine with umask 80H 490.It Li BR_INST_EXEC.RETURN_NEAR 491.Pq Event 88H, Umask 08H 492Qualify indirect near branches that have a return mnemonic. 493Must combine with umask 80H 494.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 495.Pq Event 88H, Umask 10H 496Qualify unconditional near call branch instructions, excluding non call branch, 497executed. 498Must combine with umask 80H 499.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 500.Pq Event 88H, Umask 20H 501Qualify indirect near calls, including both register and memory indirect, 502executed. 503Must combine with umask 80H 504.It Li BR_INST_EXEC.NONTAKEN 505.Pq Event 88H, Umask 40H 506Qualify non-taken near branches executed. 507Applicable to umask 01H only 508.It Li BR_INST_EXEC.TAKEN 509.Pq Event 88H, Umask 80H 510Qualify taken near branches executed. 511Must combine with 01H,02H, 04H, 08H, 10H, 20H 512.It Li BR_INST_EXE.ALL_BRANCHES 513.Pq Event 88H, Umask FFH 514Counts all near executed branches (not necessarily retired). 515.It Li BR_MISP_EXEC.COND 516.Pq Event 89H, Umask 01H 517Qualify conditional near branch instructions mispredicted. 518Must combine with umask 40H, 80H 519.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 520.Pq Event 89H, Umask 04H 521Qualify mispredicted indirect near branch instructions that are not calls nor 522returns. 523Must combine with umask 80H 524.It Li BR_MISP_EXEC.RETURN_NEAR 525.Pq Event 89H, Umask 08H 526Qualify mispredicted indirect near branches that have a return mnemonic. 527Must combine with umask 80H 528.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 529.Pq Event 89H, Umask 10H 530Qualify mispredicted unconditional near call branch instructions, excluding non 531call branch, executed. 532Must combine with umask 80H 533.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 534.Pq Event 89H, Umask 20H 535Qualify mispredicted indirect near calls, including both register and memory 536indirect, executed. 537Must combine with umask 80H 538.It Li BR_MISP_EXEC.NONTAKEN 539.Pq Event 89H, Umask 40H 540Qualify mispredicted non-taken near branches executed. 541Applicable to umask 01H only 542.It Li BR_MISP_EXEC.TAKEN 543.Pq Event 89H, Umask 80H 544Qualify mispredicted taken near branches executed. 545Must combine with 01H,02H, 04H, 08H, 10H, 20H 546.It Li BR_MISP_EXEC.ALL_BRANCHES 547.Pq Event 89H, Umask FFH 548Counts all near executed branches (not necessarily retired). 549.It Li IDQ_UOPS_NOT_DELIVERED.CORE 550.Pq Event 9CH, Umask 01H 551Count number of non-delivered uops to RAT per thread. 552Use Cmask to qualify uop b/w 553.It Li UOPS_DISPATCHED_PORT.PORT_0 554.Pq Event A1H, Umask 01H 555Cycles which a Uop is dispatched on port 0. 556.It Li UOPS_DISPATCHED_PORT.PORT_1 557.Pq Event A1H, Umask 02H 558Cycles which a Uop is dispatched on port 1. 559.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 560.Pq Event A1H, Umask 04H 561Cycles which a load uop is dispatched on port 2. 562.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 563.Pq Event A1H, Umask 08H 564Cycles which a store address uop is dispatched on port 2. 565.It Li UOPS_DISPATCHED_PORT.PORT_2 566.Pq Event A1H, Umask 0CH 567Cycles which a Uop is dispatched on port 2. 568.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 569.Pq Event A1H, Umask 10H 570Cycles which a load uop is dispatched on port 3. 571.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 572.Pq Event A1H, Umask 20H 573Cycles which a store address uop is dispatched on port 3. 574.It Li UOPS_DISPATCHED_PORT.PORT_3 575.Pq Event A1H, Umask 30H 576.Pq Cycles which a Uop is dispatched on port 3. 577.It Li UOPS_DISPATCHED_PORT.PORT_4 578.Pq Event A1H, Umask 40H 579Cycles which a Uop is dispatched on port 4. 580.It Li UOPS_DISPATCHED_PORT.PORT_5 581.Pq Event A1H, Umask 80H 582Cycles which a Uop is dispatched on port 5. 583.It Li RESOURCE_STALLS.ANY 584.Pq Event A2H, Umask 01H 585Cycles Allocation is stalled due to Resource Related reason. 586.It Li RESOURCE_STALLS.LB 587.Pq Event A2H, Umask 02H 588Counts the cycles of stall due to lack of load buffers. 589.It Li RESOURCE_STALLS.LB 590.Pq Event A2H, Umask 04H 591Cycles stalled due to no eligible RS entry available. 592.It Li RESOURCE_STALLS.SB 593.Pq Event A2H, Umask 08H 594Cycles stalled due to no store buffers available. 595(not including draining form sync) 596.It Li RESOURCE_STALLS.ROB 597.Pq Event A2H, Umask 10H 598Cycles stalled due to re-order buffer full. 599.It Li RESOURCE_STALLS.FCSW 600.Pq Event A2H, Umask 20H 601Cycles stalled due to writing the FPU control word. 602.It Li RESOURCE_STALLS.MXCSR 603.Pq Event A2H, Umask 40H 604Cycles stalled due to the MXCSR register rename occurring to close to a previous 605MXCSR rename. 606.It Li RESOURCE_STALLS.OTHER 607.Pq Event A2H, Umask 80H 608Cycles stalled while execution was stalled due to other resource issues. 609.It Li DSB2MITE_SWITCHES.COUNT 610.Pq Event ABH, Umask 01H 611Number of DSB to MITE switches. 612.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 613.Pq Event ABH, Umask 02H 614Cycles DSB to MITE switches caused delay. 615.It Li DSB_FILL.OTHER_CANCEL 616.Pq Event ACH, Umask 02H 617Cases of cancelling valid DSB fill not because of exceeding way limit. 618.It Li DSB_FILL.EXCEED_DSB_LINES 619.Pq Event ACH, Umask 08H 620DSB Fill encountered > 3 DSB lines. 621.It Li DSB_FILL.ALL_CANCEL 622.Pq Event ACH, Umask 0AH 623Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding 624way limit. 625.It Li ITLB.ITLB_FLUSH 626.Pq Event AEH, Umask 01H 627Counts the number of ITLB flushes, includes 4k/2M/4M pages. 628.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 629.Pq Event B0H, Umask 01H 630Demand data read requests sent to uncore. 631.It Li OFFCORE_REQUESTS.DEMAND_RFO 632.Pq Event B0H, Umask 04H 633Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. 634.It Li OFFCORE_REQUESTS.ALL_DATA_RD 635.Pq Event B0H, Umask 08H 636Data read requests sent to uncore (demand and prefetch). 637.It Li UOPS_DISPATCHED.THREAD 638.Pq Event B1H, Umask 01H 639Counts total number of uops to be dispatched per-thread each cycle. 640Set Cmask = 1, INV =1 to count stall cycles. 641.It Li UOPS_DISPATCHED.CORE 642.Pq Event B1H, Umask 02H 643Counts total number of uops to be dispatched per-core each cycle. 644Do not need to set ANY 645.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL 646.Pq Event B2H, Umask 01H 647Offcore requests buffer cannot take more entries for this thread core. 648.It Li AGU_BYPASS_CANCEL.COUNT 649.Pq Event B6H, Umask 01H 650Counts executed load operations with all the following traits: 1. addressing 651of the format [base + offset], 2. the offset is between 1 and 2047, 3. the 652address specified in the base register is in one page and the address 653[base+offset] is in another page. 654.It Li OFF_CORE_RESPONSE_0 655.Pq Event B7H, Umask 01H 656Off-core Response Performance Monitoring; PMC0 only. 657Requires programming MSR 01A6H 658.It Li OFF_CORE_RESPONSE_1 659.Pq Event BBH, Umask 01H 660Off-core Response Performance Monitoring. PMC3 only. 661Requires programming MSR 01A7H 662.It Li TLB_FLUSH.DTLB_THREAD 663.Pq Event BDH, Umask 01H 664DTLB flush attempts of the thread-specific entries. 665.It Li TLB_FLUSH.STLB_ANY 666.Pq Event BDH, Umask 20H 667Count number of STLB flush attempts. 668.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES 669.Pq Event BFH, Umask 05H 670Cycles when dispatched loads are cancelled due to L1D bank conflicts with other 671load ports. 672cmask=1 673.It Li INST_RETIRED.ANY_P 674.Pq Event C0H, Umask 00H 675Number of instructions at retirement. 676.It Li INST_RETIRED.PREC_DIST 677.Pq Event C0H, Umask 01H 678Precise instruction retired event with HW to reduce effect of PEBS shadow in IP 679distribution PMC1 only; Must quiesce other PMCs. 680.It Li INST_RETIRED.X87 681.Pq Event C0H, Umask 02H 682X87 instruction retired event. 683.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED 684.Pq Event C1H, Umask 02H 685Instructions that experienced an ITLB miss. 686.It Li OTHER_ASSISTS.AVX_STORE 687.Pq Event C1H, Umask 08H 688Number of assists associated with 256-bit AVX store operations. 689.It Li OTHER_ASSISTS.AVX_TO_SSE 690.Pq Event C1H, Umask 10H 691Number of transitions from AVX256 to legacy SSE when penalty applicable. 692.It Li OTHER_ASSISTS.SSE_TO_AVX 693.Pq Event C1H, Umask 20H 694Number of transitions from SSE to AVX-256 when penalty applicable. 695.It Li UOPS_RETIRED.ALL 696.Pq Event C2H, Umask 01H 697Counts the number of micro-ops retired. 698Use cmask=1 and invert to count active cycles or stalled cycles. 699.It Li UOPS_RETIRED.RETIRE_SLOTS 700.Pq Event C2H, Umask 02H 701Counts the number of retirement slots used each cycle. 702.It Li MACHINE_CLEARS.MEMORY_ORDERING 703.Pq Event C3H, Umask 02H 704Counts the number of machine clears due to memory order conflicts. 705.It Li MACHINE_CLEARS.SMC 706.Pq Event C3H, Umask 04H 707Counts the number of times that a program writes to a code section. 708.It Li MACHINE_CLEARS.MASKMOV 709.Pq Event C3H, Umask 20H 710Counts the number of executed AVX masked load operations that refer to an 711illegal address range with the mask bits set to 0. 712.It Li BR_INST_RETIRED.ALL_BRANCH 713.Pq Event C4H, Umask 00H 714Branch instructions at retirement. 715.It Li BR_INST_RETIRED.CONDITIONAL 716.Pq Event C4H, Umask 01H 717Counts the number of conditional branch instructions retired. 718.It Li BR_INST_RETIRED.NEAR_CALL 719.Pq Event C4H, Umask 02H 720Direct and indirect near call instructions retired. 721.It Li BR_INST_RETIRED.ALL_BRANCHES 722.Pq Event C4H, Umask 04H 723Counts the number of branch instructions retired. 724.It Li BR_INST_RETIRED.NEAR_RETURN 725.Pq Event C4H, Umask 08H 726Counts the number of near return instructions retired. 727.It Li BR_INST_RETIRED.NOT_TAKEN 728.Pq Event C4H, Umask 10H 729Counts the number of not taken branch instructions retired. 730.It Li BR_INST_RETIRED.NEAR_TAKEN 731.Pq Event C4H, Umask 20H 732Number of near taken branches retired. 733.It Li BR_INST_RETIRED.FAR_BRANCH 734.Pq Event C4H, Umask 40H 735Number of far branches retired. 736.It Li BR_MISP_RETIRED.ALL_BRANCHES 737.Pq Event C5H, Umask 00H 738Mispredicted branch instructions at retirement. 739.It Li BR_MISP_RETIRED.CONDITIONAL 740.Pq Event C5H, Umask 01H 741Mispredicted conditional branch instructions retired. 742.It Li BR_MISP_RETIRED.NEAR_CALL 743.Pq Event C5H, Umask 02H 744Direct and indirect mispredicted near call instructions retired. 745.It Li BR_MISP_RETIRED.ALL_BRANCH 746.Pq Event C5H, Umask 04H 747Mispredicted macro branch instructions retired. 748.It Li BR_MISP_RETIRED.NOT_TAKEN 749.Pq Event C5H, Umask 10H 750Mispredicted not taken branch instructions retired. 751.It Li BR_MISP_RETIRED.TAKEN 752.Pq Event C5H, Umask 20H 753Mispredicted taken branch instructions retired. 754.It Li FP_ASSIST.X87_OUTPUT 755.Pq Event CAH, Umask 02H 756Number of X87 assists due to output value. 757.It Li FP_ASSIST.X87_INPUT 758.Pq Event CAH, Umask 04H 759Number of X87 assists due to input value. 760.It Li FP_ASSIST.SIMD_OUTPUT 761.Pq Event CAH, Umask 08H 762Number of SIMD FP assists due to Output values. 763.It Li FP_ASSIST.SIMD_INPUT 764.Pq Event CAH, Umask 10H 765Number of SIMD FP assists due to input values. 766.It Li FP_ASSIST.ANY 767.Pq Event CAH, Umask 1EH 768Cycles with any input/output SSE* or FP assists. 769.It Li ROB_MISC_EVENTS.LBR_INSERTS 770.Pq Event CCH, Umask 20H 771Count cases of saving new LBR records by hardware. 772.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 773.Pq Event CDH, Umask 01H 774Sample loads with specified latency threshold. 775PMC3 only. 776Specify threshold in MSR 0x3F6. 777.It Li MEM_TRANS_RETIRED.PRECISE_STORE 778.Pq Event CDH, Umask 02H 779Sample stores and collect precise store operation via PEBS record. 780PMC3 only. 781.It Li MEM_UOP_RETIRED.LOADS 782.Pq Event D0H, Umask 01H 783Qualify retired memory uops that are loads. 784Combine with umask 10H, 20H, 40H, 80H. 785.It Li MEM_UOP_RETIRED.STORES 786.Pq Event D0H, Umask 02H 787Qualify retired memory uops that are stores. 788Combine with umask 10H, 20H, 40H, 80H. 789.It Li MEM_UOP_RETIRED.STLB_MISS 790.Pq Event D0H, Umask 10H 791Qualify retired memory uops with STLB miss. 792Must combine with umask 01H, 02H, to produce counts. 793.It Li MEM_UOP_RETIRED.LOCK 794.Pq Event D0H, Umask 20H 795Qualify retired memory uops with lock. 796Must combine with umask 01H, 02H, to produce counts. 797.It Li MEM_UOP_RETIRED.SPLIT 798.Pq Event D0H, Umask 40H 799Qualify retired memory uops with line split. 800Must combine with umask 01H, 02H, to produce counts. 801.It Li MEM_UOP_RETIRED_ALL 802.Pq Event D0H, Umask 80H 803Qualify any retired memory uops. 804Must combine with umask 01H, 02H, to produce counts. 805.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 806.Pq Event D1H, Umask 01H 807Retired load uops with L1 cache hits as data sources. 808Must combine with umask 01H, 02H, to produce counts. 809.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 810.Pq Event D1H, Umask 02H 811Retired load uops with L2 cache hits as data sources. 812.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 813.Pq Event D1H, Umask 04H 814Retired load uops which data sources were data hits in LLC without snoops 815required. 816.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 817.Pq Event D1H, Umask 40H 818Retired load uops which data sources were load uops missed L1 but hit FB due 819to preceding miss to the same cache line with data not ready. 820.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 821.Pq Event D2H, Umask 01H 822Retired load uops which data sources were LLC hit and cross-core snoop missed in 823on-pkg core cache. 824.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 825.Pq Event D2H, Umask 02H 826Retired load uops which data sources were LLC and cross-core snoop hits in 827on-pkg core cache. 828.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 829.Pq Event D2H, Umask 04H 830Retired load uops which data sources were HitM responses from shared LLC. 831.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 832.Pq Event D2H, Umask 08H 833Retired load uops which data sources were hits in LLC without snoops required. 834.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS 835.Pq Event D4H, Umask 02H 836Retired load uops with unknown information as data source in cache serviced the load. 837.It Li L2_TRANS.DEMAND_DATA_RD 838.Pq Event F0H, Umask 01H 839Demand Data Read requests that access L2 cache. 840.It Li L2_TRANS.RF0 841.Pq Event F0H, Umask 02H 842RFO requests that access L2 cache. 843.It Li L2_TRANS.CODE_RD 844.Pq Event F0H, Umask 04H 845L2 cache accesses when fetching instructions. 846.It Li L2_TRANS.ALL_PF 847.Pq Event F0H, Umask 08H 848L2 or LLC HW prefetches that access L2 cache. 849.It Li L2_TRANS.L1D_WB 850.Pq Event F0H, Umask 10H 851L1D writebacks that access L2 cache. 852.It Li L2_TRANS.L2_FILL 853.Pq Event F0H, Umask 20H 854L2 fill requests that access L2 cache. 855.It Li L2_TRANS.L2_WB 856.Pq Event F0H, Umask 40H 857L2 writebacks that access L2 cache. 858.It Li L2_TRANS.ALL_REQUESTS 859.Pq Event F0H, Umask 80H 860Transactions accessing L2 pipe. 861.It Li L2_LINES_IN.I 862.Pq Event F1H, Umask 01H 863L2 cache lines in I state filling L2. 864Counting does not cover rejects. 865.It Li L2_LINES_IN.S 866.Pq Event F1H, Umask 02H 867L2 cache lines in S state filling L2. 868Counting does not cover rejects. 869.It Li L2_LINES_IN.E 870.Pq Event F1H, Umask 04H 871L2 cache lines in E state filling L2. 872Counting does not cover rejects. 873.It Li L2_LINES-IN.ALL 874.Pq Event F1H, Umask 07H 875L2 cache lines filling L2. 876Counting does not cover rejects. 877.It Li L2_LINES_OUT.DEMAND_CLEAN 878.Pq Event F2H, Umask 01H 879Clean L2 cache lines evicted by demand. 880.It Li L2_LINES_OUT.DEMAND_DIRTY 881.Pq Event F2H, Umask 02H 882Dirty L2 cache lines evicted by demand. 883.It Li L2_LINES_OUT.PF_CLEAN 884.Pq Event F2H, Umask 04H 885Clean L2 cache lines evicted by L2 prefetch. 886.It Li L2_LINES_OUT.PF_DIRTY 887.Pq Event F2H, Umask 08H 888Dirty L2 cache lines evicted by L2 prefetch. 889.It Li L2_LINES_OUT.DIRTY_ALL 890.Pq Event F2H, Umask 0AH 891Dirty L2 cache lines filling the L2. 892Counting does not cover rejects. 893.It Li SQ_MISC.SPLIT_LOCK 894.Pq Event F4H, Umask 10H 895Split locks in SQ. 896.El 897.Sh SEE ALSO 898.Xr pmc 3 , 899.Xr pmc.atom 3 , 900.Xr pmc.core 3 , 901.Xr pmc.corei7 3 , 902.Xr pmc.corei7uc 3 , 903.Xr pmc.iaf 3 , 904.Xr pmc.k7 3 , 905.Xr pmc.k8 3 , 906.Xr pmc.p4 3 , 907.Xr pmc.p5 3 , 908.Xr pmc.p6 3 , 909.Xr pmc.sandybridgeuc 3 , 910.Xr pmc.soft 3 , 911.Xr pmc.tsc 3 , 912.Xr pmc.ucf 3 , 913.Xr pmc.westmere 3 , 914.Xr pmc.westmereuc 3 , 915.Xr pmc_cpuinfo 3 , 916.Xr pmclog 3 , 917.Xr hwpmc 4 918.Sh HISTORY 919The 920.Nm pmc 921library first appeared in 922.Fx 6.0 . 923.Sh AUTHORS 924The 925.Lb libpmc 926library was written by 927.An "Joseph Koshy" 928.Aq jkoshy@FreeBSD.org. 929The support for the Sandy Bridge 930microarchitecture was written by 931.An "Davide Italiano" 932.Aq davide@FreeBSD.org . 933