1.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd October 19, 2012 28.Dt PMC.SANDYBRIDGE 3 29.Os 30.Sh NAME 31.Nm pmc.sandybridge 32.Nd measurement events for 33.Tn Intel 34.Tn Sandy Bridge 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Sandy Bridge" 43CPUs contain PMCs conforming to the version 3 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs may contain up to three classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_IAP" 48.It Li PMC_CLASS_IAF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_IAP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.It Li PMC_CLASS_TSC 54These PMCs are documented in 55.Xr pmc.tsc 3 . 56.El 57.Pp 58The number of PMCs available in each class and their widths need to be 59determined at run time by calling 60.Xr pmc_cpuinfo 3 . 61.Pp 62Intel Sandy Bridge PMCs are documented in 63.Rs 64.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 65.%T "Volume 3B: System Programming Guide, Part 2" 66.%N "Order Number: 253669-039US" 67.%D May 2011 68.%Q "Intel Corporation" 69.Re 70.Ss SANDY BRIDGE FIXED FUNCTION PMCS 71These PMCs and their supported events are documented in 72.Xr pmc.iaf 3 . 73.Ss SANDY BRIDGE PROGRAMMABLE PMCS 74The programmable PMCs support the following capabilities: 75.Bl -column "PMC_CAP_INTERRUPT" "Support" 76.It Em Capability Ta Em Support 77.It PMC_CAP_CASCADE Ta \&No 78.It PMC_CAP_EDGE Ta Yes 79.It PMC_CAP_INTERRUPT Ta Yes 80.It PMC_CAP_INVERT Ta Yes 81.It PMC_CAP_READ Ta Yes 82.It PMC_CAP_PRECISE Ta \&No 83.It PMC_CAP_SYSTEM Ta Yes 84.It PMC_CAP_TAGGING Ta \&No 85.It PMC_CAP_THRESHOLD Ta Yes 86.It PMC_CAP_USER Ta Yes 87.It PMC_CAP_WRITE Ta Yes 88.El 89.Ss Event Qualifiers 90Event specifiers for these PMCs support the following common 91qualifiers: 92.Bl -tag -width indent 93.It Li rsp= Ns Ar value 94Configure the Off-core Response bits. 95.Bl -tag -width indent 96.It Li REQ_DMND_DATA_RD 97Counts the number of demand and DCU prefetch data reads of full and partial 98cachelines as well as demand data page table entry cacheline reads. 99Does not count L2 data read prefetches or instruction fetches. 100.It Li REQ_DMND_RFO 101Counts the number of demand and DCU prefetch reads for ownership (RFO) 102requests generated by a write to data cacheline. 103Does not count L2 RFO prefetches. 104.It Li REQ_DMND_IFETCH 105Counts the number of demand and DCU prefetch instruction cacheline reads. 106Does not count L2 code read prefetches. 107.It Li REQ_WB 108Counts the number of writeback (modified to exclusive) transactions. 109.It Li REQ_PF_DATA_RD 110Counts the number of data cacheline reads generated by L2 prefetchers. 111.It Li REQ_PF_RFO 112Counts the number of RFO requests generated by L2 prefetchers. 113.It Li REQ_PF_IFETCH 114Counts the number of code reads generated by L2 prefetchers. 115.It Li REQ_PF_LLC_DATA_RD 116L2 prefetcher to L3 for loads. 117.It Li REQ_PF_LLC_RFO 118RFO requests generated by L2 prefetcher 119.It Li REQ_PF_LLC_IFETCH 120L2 prefetcher to L3 for instruction fetches. 121.It Li REQ_BUS_LOCKS 122Bus lock and split lock requests. 123.It Li REQ_STRM_ST 124Streaming store requests. 125.It Li REQ_OTHER 126Any other request that crosses IDI, including I/O. 127.It Li RES_ANY 128Catch all value for any response types. 129.It Li RES_SUPPLIER_NO_SUPP 130No Supplier Information available. 131.It Li RES_SUPPLIER_LLC_HITM 132M-state initial lookup stat in L3. 133.It Li RES_SUPPLIER_LLC_HITE 134E-state. 135.It Li RES_SUPPLIER_LLC_HITS 136S-state. 137.It Li RES_SUPPLIER_LLC_HITF 138F-state. 139.It Li RES_SUPPLIER_LOCAL 140Local DRAM Controller. 141.It Li RES_SNOOP_SNP_NONE 142No details on snoop-related information. 143.It Li RES_SNOOP_SNP_NO_NEEDED 144No snoop was needed to satisfy the request. 145.It Li RES_SNOOP_SNP_MISS 146A snoop was needed and it missed all snooped caches: 147-For LLC Hit, ReslHitl was returned by all cores 148-For LLC Miss, Rspl was returned by all sockets and data was returned from 149DRAM. 150.It Li RES_SNOOP_HIT_NO_FWD 151A snoop was needed and it hits in at least one snooped cache. 152Hit denotes a cache-line was valid before snoop effect. 153This includes: 154-Snoop Hit w/ Invalidation (LLC Hit, RFO) 155-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 156-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 157In the LLC Miss case, data is returned from DRAM. 158.It Li RES_SNOOP_HIT_FWD 159A snoop was needed and data was forwarded from a remote socket. 160This includes: 161-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 162.It Li RES_SNOOP_HITM 163A snoop was needed and it HitM-ed in local or remote cache. 164HitM denotes a cache-line was in modified state before effect as a results of snoop. 165This includes: 166-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 167-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 168-Snoop MtoS (LLC Hit, IFetch/Data_RD). 169.It Li RES_NON_DRAM 170Target was non-DRAM system address. 171This includes MMIO transactions. 172.El 173.It Li cmask= Ns Ar value 174Configure the PMC to increment only if the number of configured 175events measured in a cycle is greater than or equal to 176.Ar value . 177.It Li edge 178Configure the PMC to count the number of de-asserted to asserted 179transitions of the conditions expressed by the other qualifiers. 180If specified, the counter will increment only once whenever a 181condition becomes true, irrespective of the number of clocks during 182which the condition remains true. 183.It Li inv 184Invert the sense of comparison when the 185.Dq Li cmask 186qualifier is present, making the counter increment when the number of 187events per cycle is less than the value specified by the 188.Dq Li cmask 189qualifier. 190.It Li os 191Configure the PMC to count events happening at processor privilege 192level 0. 193.It Li usr 194Configure the PMC to count events occurring at privilege levels 1, 2 195or 3. 196.El 197.Pp 198If neither of the 199.Dq Li os 200or 201.Dq Li usr 202qualifiers are specified, the default is to enable both. 203.Ss Event Specifiers (Programmable PMCs) 204Sandy Bridge programmable PMCs support the following events: 205.Bl -tag -width indent 206.It Li LD_BLOCKS.DATA_UNKNOWN 207.Pq EVENT_03H, Umask 01H 208Blocked loads due to store buffer blocks with unknown data. 209.It Li LD_BLOCKS.STORE_FORWARD 210.Pq Event 03H, Umask 02H 211Loads blocked by overlapping with store buffer that cannot be forwarded. 212.It Li LD_BLOCKS.NO_SR 213.Pq Event 03H, Umask 08H 214# of Split loads blocked due to resource not available. 215.It Li LD_BLOCKS.ALL_BLOCK 216.Pq EVENT_03H, Umask 10H 217Number of cases where any load is blocked but has no DCU miss. 218.It Li MISALIGN_MEM_REF.LOADS 219.Pq Event 05H, Umask 01H 220Speculative cache-line split load uops dispatched to L1D. 221.It Li MISALIGN_MEM_REF.STORES 222.Pq Event 05H, Umask 02H 223Speculative cache-line split Store-address uops dispatched to L1D. 224.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 225.Pq Event 07H, Umask 01H 226False dependencies in MOB due to partial compare on address. 227.It Li LD_BLOCKS_PARTIAL.ALL_STA_BLOCK 228.Pq Event 07H, Umask 08H 229The number of times that load operations are temporarily blocked because of 230older stores, with addresses that are not yet known. 231A load operation may incur more than one block of this type. 232.It LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK 233.Pq Event 08H, Umask 01H 234Misses in all TLB levels that cause a page walk of any page size. 235.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 236.Pq Event 08H, Umask 02H 237Misses in all TLB levels that caused page walk completed of any size. 238.It Li DTLB_LOAD_MISSES.WALK_DURATION 239.Pq Event 08H, Umask 04H 240Cycle PMH is busy with a walk. 241.It Li DTLB_LOAD_MISSES.STLB_HIT 242.Pq Event 08H, Umask 10H 243Number of cache load STLB hits. 244No page walk. 245.It Li INT_MISC.RECOVERY_CYCLES 246.Pq Event 0DH, Umask 03H 247Cycles waiting to recover after Machine Clears or JEClear. 248Set Cmask = 1. 249Set Edge to count occurrences 250.It Li INT_MISC.RAT_STALL_CYCLES 251.Pq Event 0DH, Umask 40H 252Cycles RAT external stall is sent to IDQ for this thread. 253.It Li UOPS_ISSUED.ANY 254.Pq Event 0EH, Umask 01H 255Increments each cycle the # of Uops issued by the RAT to RS. 256Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core. 257Set Cmask = 1, Inv = 1 to count stalled cycles 258.It Li FP_COMP_OPS_EXE.X87 259.Pq Event 10H, Umask 01H 260Counts number of X87 uops executed. 261.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE 262.Pq Event 10H, Umask 10H 263Counts number of SSE* double precision FP packed uops executed. 264.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE 265.Pq Event 10H, Umask 20H 266Counts number of SSE* single precision FP scalar uops executed. 267.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE 268.Pq Event 10H, Umask 40H 269Counts number of SSE* single precision FP packed uops executed. 270.It LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE 271.Pq Event 10H, Umask 80H 272Counts number of SSE* double precision FP scalar uops executed. 273.It Li SIMD_FP_256.PACKED_SINGLE 274.Pq Event 11H, Umask 01H 275Counts 256-bit packed single-precision floating-point instructions. 276.It Li SIMD_FP_256.PACKED_DOUBLE 277.Pq Event 11H, Umask 02H 278Counts 256-bit packed double-precision floating-point instructions. 279.It Li ARITH.FPU_DIV_ACTIVE 280.Pq Event 14H, Umask 01H 281Cycles that the divider is active, includes INT and FP. 282Set 'edge =1, cmask=1' to count the number of divides. 283.It Li INSTS_WRITTEN_TO_IQ.INSTS 284.Pq Event 17H, Umask 01H 285Counts the number of instructions written into the IQ every cycle. 286.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 287.Pq Event 24H, Umask 01H 288Demand Data Read requests that hit L2 cache. 289.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 290.Pq Event 24H, Umask 03H 291Counts any demand and L1 HW prefetch data load requests to L2. 292.It Li L2_RQSTS.RFO_HITS 293.Pq Event 24H, Umask 04H 294Counts the number of store RFO requests that hit the L2 cache. 295.It Li L2_RQSTS.RFO_MISS 296.Pq Event 24H, Umask 08H 297Counts the number of store RFO requests that miss the L2 cache. 298.It Li L2_RQSTS.ALL_RFO 299.Pq Event 24H, Umask 0CH 300Counts all L2 store RFO requests. 301.It Li L2_RQSTS.CODE_RD_HIT 302.Pq Event 24H, Umask 10H 303Number of instruction fetches that hit the L2 cache. 304.It Li L2_RQSTS.CODE_RD_MISS 305.Pq Event 24H, Umask 20H 306Number of instruction fetches that missed the L2 cache. 307.It Li L2_RQSTS.ALL_CODE_RD 308.Pq Event 24H, Umask 30H 309Counts all L2 code requests. 310.It Li L2_RQSTS.PF_HIT 311.Pq Event 24H, Umask 40H 312Requests from L2 Hardware prefetcher that hit L2. 313.It Li L2_RQSTS.PF_MISS 314.Pq Event 24H, Umask 80H 315Requests from L2 Hardware prefetcher that missed L2. 316.It Li L2_RQSTS.ALL_PF 317.Pq Event 24H, Umask C0H 318Any requests from L2 Hardware prefetchers. 319.It Li L2_STORE_LOCK_RQSTS.MISS 320.Pq Event 27H, Umask 01H 321RFOs that miss cache lines. 322.It Li L2_STORE_LOCK_RQSTS.HIT_E 323.Pq Event 27H, Umask 04H 324RFOs that hit cache lines in E state. 325.It Li L2_STORE_LOCK_RQSTS.HIT_M 326.Pq EVENT_27H, Umask 08H 327RFOs that hit cache lines in M state. 328.It Li L2_STORE_LOCK_RQSTS.ALL 329.Pq EVENT_27H, Umask 0FH 330RFOs that access cache lines in any state. 331.It Li L2_L1D_WB_RQSTS.HIT_E 332.Pq Event 28H, Umask 04H 333Not rejected writebacks from L1D to L2 cache lines in E state. 334.It Li L2_L1D_WB_RQSTS.HIT_M 335.Pq Event 28H, Umask 08H 336Not rejected writebacks from L1D to L2 cache lines in M state. 337.It Li LONGEST_LAT_CACHE.REFERENCE 338.Pq Event 2EH, Umask 4FH 339This event counts requests originating from the core that reference a cache 340line in the last level cache. 341.It Li LONGEST_LAT_CACHE.MISS 342.Pq Event 2EH, Umask 41H 343This event counts each cache miss condition for references to the last level 344cache. 345.It Li CPU_CLK_UNHALTED.THREAD_P 346.Pq Event 3CH, Umask 00H 347Counts the number of thread cycles while the thread is not in a halt state. 348The thread enters the halt state when it is running the HLT instruction. 349The core frequency may change from time to time due to power or thermal 350throttling. 351.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 352.Pq Event 3CH, Umask 01H 353Increments at the frequency of XCLK (100 MHz) when not halted. 354.It Li L1D_PEND_MISS.PENDING 355.Pq Event 48H, Umask 01H 356Increments the number of outstanding L1D misses every cycle. 357Set Cmask = 1 and Edge =1 to count occurrences. 358Counter 2 only; Set Cmask = 1 to count cycles. 359.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 360.Pq Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any 361page size (4K/2M/4M/1G). 362.It Li DTLB_STORE_MISSES.WALK_COMPLETED 363.Pq Event 49H, Umask 02H 364Miss in all TLB levels causes a page walk that completes of any page size 365(4K/2M/4M/1G). 366.It Li DTLB_STORE_MISSES.WALK_DURATION 367.Pq Event 49H, Umask 04H 368Cycles PMH is busy with this walk. 369.It Li DTLB_STORE_MISSES.STLB_HIT 370.Pq Event 49H, Umask 10H 371Store operations that miss the first TLB level but hit the second and do not 372cause page walks. 373.It Li LOAD_HIT_PRE.SW_PF 374.Pq Event 4CH, Umask 01H 375Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. 376.It Li LOAD_HIT_PER.HW_PF 377.Pq Event 4CH, Umask 02H 378Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. 379.It Li HW_PRE_REQ.DL1_MISS 380.Pq Event 4EH, Umask 02H 381Hardware Prefetch requests that miss the L1D cache. 382A request is being counted each time it access the cache & miss it, including 383if a block is applicable or if hit the Fill Buffer for example. 384This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. 385.It Li L1D.REPLACEMENT 386.Pq Event 51H, Umask 01H 387Counts the number of lines brought into the L1 data cache. 388.It Li L1D.ALLOCATED_IN_M 389.Pq Event 51H, Umask 02H 390Counts the number of allocations of modified L1D cache lines. 391.It Li L1D.EVICTION 392.Pq Event 51H, Umask 04H 393Counts the number of modified lines evicted from the L1 data cache due to 394replacement. 395.It Li L1D.ALL_M_REPLACEMENT 396.Pq Event 51H, Umask 08H 397Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line 398replacement. 399.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP 400.Pq Event 59H, Umask 20H 401Increments the number of flags-merge uops in flight each cycle. 402Set Cmask = 1 to count cycles. 403.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW 404.Pq Event 59H, Umask 40H 405Cycles with at least one slow LEA uop allocated. 406.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP 407.Pq Event 59H, Umask 80H 408Number of Multiply packed/scalar single precision uops allocated. 409.It Li RESOURCE_STALLS2.ALL_FL_EMPTY 410.Pq Event 5BH, Umask 0CH 411Cycles stalled due to free list empty. 412.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL 413.Pq Event 5BH, Umask 0FH 414Cycles stalled due to control structures full for physical registers. 415.It Li RESOURCE_STALLS2.BOB_FULL 416.Pq Event 5BH, Umask 40H 417Cycles Allocator is stalled due to Branch Order Buffer. 418.It Li RESOURCE_STALLS2.OOO_RSRC 419.Pq Event 5BH, Umask 4FH 420Cycles stalled due to out of order resources full. 421.It Li CPL_CYCLES.RING0 422.Pq Event 5CH, Umask 01H 423Unhalted core cycles when the thread is in ring 0. 424Use Edge to count transition 425.It Li CPL_CYCLES.RING123 426.Pq Event 5CH, Umask 02H 427Unhalted core cycles when the thread is not in ring 0. 428.It Li RS_EVENTS.EMPTY_CYCLES 429.Pq Event 5EH, Umask 01H 430Cycles the RS is empty for the thread. 431.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 432.Pq Event 60H, Umask 01H 433Offcore outstanding Demand Data Read transactions in SQ to uncore. 434Set Cmask=1 to count cycles. 435.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 436.Pq Event 60H, Umask 04H 437Offcore outstanding RFO store transactions in SQ to uncore. 438Set Cmask=1 to count cycles. 439.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 440.Pq Event 60H, Umask 08H 441Offcore outstanding cacheable data read transactions in SQ to uncore. 442Set Cmask=1 to count cycles. 443.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 444.Pq Event 63H, Umask 01H 445Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 446.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 447.Pq Event 63H, Umask 02H 448Cycles in which the L1D is locked. 449.It Li IDQ.EMPTY 450.Pq Event 79H, Umask 02H 451Counts cycles the IDQ is empty. 452.It Li IQD.MITE_UOPS 453.Pq Event 79H, Umask 04H 454Increment each cycle # of uops delivered to IDQ from MITE path. 455Set Cmask = 1 to count cycles. 456Can combine Umask 04H and 20H 457.It Li IDQ.DSB_UOPS 458.Pq Event 79H, Umask 08H 459Increment each cycle. 460# of uops delivered to IDQ from DSB path. 461Set Cmask = 1 to count cycles. 462Can combine Umask 08H and 10H 463.It Li IDQ.MS_DSB_UOPS 464.Pq Event 79H, Umask 10H 465Increment each cycle # of uops delivered to IDQ when MS busy by DSB. 466Set Cmask = 1 to count cycles MS is busy. 467Set Cmask=1 and Edge=1 to count MS activations. 468Can combine Umask 08H and 10H 469.It Li IDQ.MS_MITE_UOPS 470.Pq Event 79H, Umask 20H 471Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. 472Set Cmask = 1 to count cycles. 473Can combine Umask 04H and 20H 474.It Li IDQ.MS_UOPS 475.Pq Event 79H, Umask 30H 476Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. 477Set Cmask = 1 to count cycles. 478Can combine Umask 04H, 08H and 30H 479.It Li ICACHE.MISSES 480.Pq Event 80H, Umask 02H 481Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 482Includes UC accesses. 483.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 484.Pq Event 85H, Umask 01H 485Misses in all ITLB levels that cause page walks. 486.It Li ITLB_MISSES.WALK_COMPLETED 487.Pq Event 85H, Umask 02H 488Misses in all ITLB levels that cause completed page walks. 489.It Li ITLB_MISSES.WALK_DURATION 490.Pq Event 85H, Umask 04H 491Cycle PMH is busy with a walk. 492.It Li ITLB_MISSES.STLB_HIT 493.Pq Event 85H, Umask 10H 494Number of cache load STLB hits. 495No page walk. 496.It Li ILD_STALL.LCP 497.Pq Event 87H, Umask 01H 498Stalls caused by changing prefix length of the instruction. 499.It Li ILD_STALL.IQ_FULL 500.Pq Event 87H, Umask 04H 501Stall cycles due to IQ is full. 502.It Li BR_INST_EXEC.NONTAKEN_COND 503.Pq Event 88H , Umask 41H 504Count conditional near branch instructions that were executed (but not 505necessarily retired) and not taken. 506.It Li BR_INST_EXEC.TAKEN_COND 507.Pq Event 88H , Umask 81H 508Count conditional near branch instructions that were executed (but not 509necessarily retired) and taken. 510.It Li BR_INST_EXEC.DIRECT_JMP 511.Pq Event 88H , Umask 82H 512Count all unconditional near branch instructions excluding calls and 513indirect branches. 514.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 515.Pq Event 88H , Umask 84H 516Count executed indirect near branch instructions that are not calls nor 517returns. 518.It Li BR_INST_EXEC.RETURN_NEAR 519.Pq Event 88H , Umask 88H 520Count indirect near branches that have a return mnemonic. 521.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 522.Pq Event 88H , Umask 90H 523Count unconditional near call branch instructions, excluding non call 524branch, executed. 525.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 526.Pq Event 88H , Umask A0H 527Count indirect near calls, including both register and memory indirect, 528executed. 529.It Li BR_INST_EXEC.ALL_BRANCHES 530.Pq Event 88H , Umask FFH 531Counts all near executed branches (not necessarily retired). 532.It Li BR_MISP_EXEC.NONTAKEN_COND 533.Pq Event 89H , Umask 41H 534Count conditional near branch instructions mispredicted as nontaken. 535.It Li BR_MISP_EXEC.TAKEN_COND 536.Pq Event 89H , Umask 81H 537Count conditional near branch instructions mispredicted as taken. 538.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 539.Pq Event 89H , Umask 84H 540Count mispredicted indirect near branch instructions that are not calls 541nor returns. 542.It Li BR_MISP_EXEC.RETURN_NEAR 543.Pq Event 89H , Umask 88H 544Count mispredicted indirect near branches that have a return mnemonic. 545.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 546.Pq Event 89H , Umask 90H 547Count mispredicted unconditional near call branch instructions, excluding 548non call branch, executed. 549.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 550.Pq Event 89H , Umask A0H 551Count mispredicted indirect near calls, including both register and memory 552indirect, executed. 553.It Li BR_MISP_EXEC.ALL_BRANCHES 554.Pq Event 89H , Umask FFH 555Counts all mispredicted near executed branches (not necessarily retired). 556.It Li IDQ_UOPS_NOT_DELIVERED.CORE 557.Pq Event 9CH, Umask 01H 558Count number of non-delivered uops to RAT per thread. 559Use Cmask to qualify uop b/w 560.It Li UOPS_DISPATCHED_PORT.PORT_0 561.Pq Event A1H, Umask 01H 562Cycles which a Uop is dispatched on port 0. 563.It Li UOPS_DISPATCHED_PORT.PORT_1 564.Pq Event A1H, Umask 02H 565Cycles which a Uop is dispatched on port 1. 566.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 567.Pq Event A1H, Umask 04H 568Cycles which a load uop is dispatched on port 2. 569.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 570.Pq Event A1H, Umask 08H 571Cycles which a store address uop is dispatched on port 2. 572.It Li UOPS_DISPATCHED_PORT.PORT_2 573.Pq Event A1H, Umask 0CH 574Cycles which a Uop is dispatched on port 2. 575.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 576.Pq Event A1H, Umask 10H 577Cycles which a load uop is dispatched on port 3. 578.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 579.Pq Event A1H, Umask 20H 580Cycles which a store address uop is dispatched on port 3. 581.It Li UOPS_DISPATCHED_PORT.PORT_3 582.Pq Event A1H, Umask 30H 583.Pq Cycles which a Uop is dispatched on port 3. 584.It Li UOPS_DISPATCHED_PORT.PORT_4 585.Pq Event A1H, Umask 40H 586Cycles which a Uop is dispatched on port 4. 587.It Li UOPS_DISPATCHED_PORT.PORT_5 588.Pq Event A1H, Umask 80H 589Cycles which a Uop is dispatched on port 5. 590.It Li RESOURCE_STALLS.ANY 591.Pq Event A2H, Umask 01H 592Cycles Allocation is stalled due to Resource Related reason. 593.It Li RESOURCE_STALLS.LB 594.Pq Event A2H, Umask 02H 595Counts the cycles of stall due to lack of load buffers. 596.It Li RESOURCE_STALLS.LB 597.Pq Event A2H, Umask 04H 598Cycles stalled due to no eligible RS entry available. 599.It Li RESOURCE_STALLS.SB 600.Pq Event A2H, Umask 08H 601Cycles stalled due to no store buffers available. 602(not including draining form sync) 603.It Li RESOURCE_STALLS.ROB 604.Pq Event A2H, Umask 10H 605Cycles stalled due to re-order buffer full. 606.It Li RESOURCE_STALLS.FCSW 607.Pq Event A2H, Umask 20H 608Cycles stalled due to writing the FPU control word. 609.It Li RESOURCE_STALLS.MXCSR 610.Pq Event A2H, Umask 40H 611Cycles stalled due to the MXCSR register rename occurring to close to a previous 612MXCSR rename. 613.It Li RESOURCE_STALLS.OTHER 614.Pq Event A2H, Umask 80H 615Cycles stalled while execution was stalled due to other resource issues. 616.It Li DSB2MITE_SWITCHES.COUNT 617.Pq Event ABH, Umask 01H 618Number of DSB to MITE switches. 619.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 620.Pq Event ABH, Umask 02H 621Cycles DSB to MITE switches caused delay. 622.It Li DSB_FILL.OTHER_CANCEL 623.Pq Event ACH, Umask 02H 624Cases of cancelling valid DSB fill not because of exceeding way limit. 625.It Li DSB_FILL.EXCEED_DSB_LINES 626.Pq Event ACH, Umask 08H 627DSB Fill encountered > 3 DSB lines. 628.It Li DSB_FILL.ALL_CANCEL 629.Pq Event ACH, Umask 0AH 630Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding 631way limit. 632.It Li ITLB.ITLB_FLUSH 633.Pq Event AEH, Umask 01H 634Counts the number of ITLB flushes, includes 4k/2M/4M pages. 635.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 636.Pq Event B0H, Umask 01H 637Demand data read requests sent to uncore. 638.It Li OFFCORE_REQUESTS.DEMAND_RFO 639.Pq Event B0H, Umask 04H 640Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. 641.It Li OFFCORE_REQUESTS.ALL_DATA_RD 642.Pq Event B0H, Umask 08H 643Data read requests sent to uncore (demand and prefetch). 644.It Li UOPS_DISPATCHED.THREAD 645.Pq Event B1H, Umask 01H 646Counts total number of uops to be dispatched per-thread each cycle. 647Set Cmask = 1, INV =1 to count stall cycles. 648.It Li UOPS_DISPATCHED.CORE 649.Pq Event B1H, Umask 02H 650Counts total number of uops to be dispatched per-core each cycle. 651Do not need to set ANY 652.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL 653.Pq Event B2H, Umask 01H 654Offcore requests buffer cannot take more entries for this thread core. 655.It Li AGU_BYPASS_CANCEL.COUNT 656.Pq Event B6H, Umask 01H 657Counts executed load operations with all the following traits: 1. addressing 658of the format [base + offset], 2. the offset is between 1 and 2047, 3. the 659address specified in the base register is in one page and the address 660[base+offset] is in another page. 661.It Li OFF_CORE_RESPONSE_0 662.Pq Event B7H, Umask 01H 663Off-core Response Performance Monitoring; PMC0 only. 664Requires programming MSR 01A6H 665.It Li OFF_CORE_RESPONSE_1 666.Pq Event BBH, Umask 01H 667Off-core Response Performance Monitoring. 668PMC3 only. 669Requires programming MSR 01A7H 670.It Li TLB_FLUSH.DTLB_THREAD 671.Pq Event BDH, Umask 01H 672DTLB flush attempts of the thread-specific entries. 673.It Li TLB_FLUSH.STLB_ANY 674.Pq Event BDH, Umask 20H 675Count number of STLB flush attempts. 676.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES 677.Pq Event BFH, Umask 05H 678Cycles when dispatched loads are cancelled due to L1D bank conflicts with other 679load ports. 680cmask=1 681.It Li INST_RETIRED.ANY_P 682.Pq Event C0H, Umask 00H 683Number of instructions at retirement. 684.It Li INST_RETIRED.PREC_DIST 685.Pq Event C0H, Umask 01H 686Precise instruction retired event with HW to reduce effect of PEBS shadow in IP 687distribution PMC1 only; Must quiesce other PMCs. 688.It Li INST_RETIRED.X87 689.Pq Event C0H, Umask 02H 690X87 instruction retired event. 691.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED 692.Pq Event C1H, Umask 02H 693Instructions that experienced an ITLB miss. 694.It Li OTHER_ASSISTS.AVX_STORE 695.Pq Event C1H, Umask 08H 696Number of assists associated with 256-bit AVX store operations. 697.It Li OTHER_ASSISTS.AVX_TO_SSE 698.Pq Event C1H, Umask 10H 699Number of transitions from AVX256 to legacy SSE when penalty applicable. 700.It Li OTHER_ASSISTS.SSE_TO_AVX 701.Pq Event C1H, Umask 20H 702Number of transitions from SSE to AVX-256 when penalty applicable. 703.It Li UOPS_RETIRED.ALL 704.Pq Event C2H, Umask 01H 705Counts the number of micro-ops retired. 706Use cmask=1 and invert to count active cycles or stalled cycles. 707.It Li UOPS_RETIRED.RETIRE_SLOTS 708.Pq Event C2H, Umask 02H 709Counts the number of retirement slots used each cycle. 710.It Li MACHINE_CLEARS.MEMORY_ORDERING 711.Pq Event C3H, Umask 02H 712Counts the number of machine clears due to memory order conflicts. 713.It Li MACHINE_CLEARS.SMC 714.Pq Event C3H, Umask 04H 715Counts the number of times that a program writes to a code section. 716.It Li MACHINE_CLEARS.MASKMOV 717.Pq Event C3H, Umask 20H 718Counts the number of executed AVX masked load operations that refer to an 719illegal address range with the mask bits set to 0. 720.It Li BR_INST_RETIRED.ALL_BRANCH 721.Pq Event C4H, Umask 00H 722Branch instructions at retirement. 723.It Li BR_INST_RETIRED.CONDITIONAL 724.Pq Event C4H, Umask 01H 725Counts the number of conditional branch instructions retired. 726.It Li BR_INST_RETIRED.NEAR_CALL 727.Pq Event C4H, Umask 02H 728Direct and indirect near call instructions retired. 729.It Li BR_INST_RETIRED.ALL_BRANCHES 730.Pq Event C4H, Umask 04H 731Counts the number of branch instructions retired. 732.It Li BR_INST_RETIRED.NEAR_RETURN 733.Pq Event C4H, Umask 08H 734Counts the number of near return instructions retired. 735.It Li BR_INST_RETIRED.NOT_TAKEN 736.Pq Event C4H, Umask 10H 737Counts the number of not taken branch instructions retired. 738.It Li BR_INST_RETIRED.NEAR_TAKEN 739.Pq Event C4H, Umask 20H 740Number of near taken branches retired. 741.It Li BR_INST_RETIRED.FAR_BRANCH 742.Pq Event C4H, Umask 40H 743Number of far branches retired. 744.It Li BR_MISP_RETIRED.ALL_BRANCHES 745.Pq Event C5H, Umask 00H 746Mispredicted branch instructions at retirement. 747.It Li BR_MISP_RETIRED.CONDITIONAL 748.Pq Event C5H, Umask 01H 749Mispredicted conditional branch instructions retired. 750.It Li BR_MISP_RETIRED.NEAR_CALL 751.Pq Event C5H, Umask 02H 752Direct and indirect mispredicted near call instructions retired. 753.It Li BR_MISP_RETIRED.ALL_BRANCH 754.Pq Event C5H, Umask 04H 755Mispredicted macro branch instructions retired. 756.It Li BR_MISP_RETIRED.NOT_TAKEN 757.Pq Event C5H, Umask 10H 758Mispredicted not taken branch instructions retired. 759.It Li BR_MISP_RETIRED.TAKEN 760.Pq Event C5H, Umask 20H 761Mispredicted taken branch instructions retired. 762.It Li FP_ASSIST.X87_OUTPUT 763.Pq Event CAH, Umask 02H 764Number of X87 assists due to output value. 765.It Li FP_ASSIST.X87_INPUT 766.Pq Event CAH, Umask 04H 767Number of X87 assists due to input value. 768.It Li FP_ASSIST.SIMD_OUTPUT 769.Pq Event CAH, Umask 08H 770Number of SIMD FP assists due to Output values. 771.It Li FP_ASSIST.SIMD_INPUT 772.Pq Event CAH, Umask 10H 773Number of SIMD FP assists due to input values. 774.It Li FP_ASSIST.ANY 775.Pq Event CAH, Umask 1EH 776Cycles with any input/output SSE* or FP assists. 777.It Li ROB_MISC_EVENTS.LBR_INSERTS 778.Pq Event CCH, Umask 20H 779Count cases of saving new LBR records by hardware. 780.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 781.Pq Event CDH, Umask 01H 782Sample loads with specified latency threshold. 783PMC3 only. 784Specify threshold in MSR 0x3F6. 785.It Li MEM_TRANS_RETIRED.PRECISE_STORE 786.Pq Event CDH, Umask 02H 787Sample stores and collect precise store operation via PEBS record. 788PMC3 only. 789.It Li MEM_UOP_RETIRED.LOADS 790.Pq Event D0H, Umask 01H 791Qualify retired memory uops that are loads. 792Combine with umask 10H, 20H, 40H, 80H. 793.It Li MEM_UOP_RETIRED.STORES 794.Pq Event D0H, Umask 02H 795Qualify retired memory uops that are stores. 796Combine with umask 10H, 20H, 40H, 80H. 797.It Li MEM_UOP_RETIRED.STLB_MISS 798.Pq Event D0H, Umask 10H 799Qualify retired memory uops with STLB miss. 800Must combine with umask 01H, 02H, to produce counts. 801.It Li MEM_UOP_RETIRED.LOCK 802.Pq Event D0H, Umask 20H 803Qualify retired memory uops with lock. 804Must combine with umask 01H, 02H, to produce counts. 805.It Li MEM_UOP_RETIRED.SPLIT 806.Pq Event D0H, Umask 40H 807Qualify retired memory uops with line split. 808Must combine with umask 01H, 02H, to produce counts. 809.It Li MEM_UOP_RETIRED_ALL 810.Pq Event D0H, Umask 80H 811Qualify any retired memory uops. 812Must combine with umask 01H, 02H, to produce counts. 813.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 814.Pq Event D1H, Umask 01H 815Retired load uops with L1 cache hits as data sources. 816Must combine with umask 01H, 02H, to produce counts. 817.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 818.Pq Event D1H, Umask 02H 819Retired load uops with L2 cache hits as data sources. 820.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 821.Pq Event D1H, Umask 04H 822Retired load uops which data sources were data hits in LLC without snoops 823required. 824.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 825.Pq Event D1H, Umask 40H 826Retired load uops which data sources were load uops missed L1 but hit FB due 827to preceding miss to the same cache line with data not ready. 828.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 829.Pq Event D2H, Umask 01H 830Retired load uops which data sources were LLC hit and cross-core snoop missed in 831on-pkg core cache. 832.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 833.Pq Event D2H, Umask 02H 834Retired load uops which data sources were LLC and cross-core snoop hits in 835on-pkg core cache. 836.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 837.Pq Event D2H, Umask 04H 838Retired load uops which data sources were HitM responses from shared LLC. 839.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 840.Pq Event D2H, Umask 08H 841Retired load uops which data sources were hits in LLC without snoops required. 842.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS 843.Pq Event D4H, Umask 02H 844Retired load uops with unknown information as data source in cache serviced the load. 845.It Li L2_TRANS.DEMAND_DATA_RD 846.Pq Event F0H, Umask 01H 847Demand Data Read requests that access L2 cache. 848.It Li L2_TRANS.RF0 849.Pq Event F0H, Umask 02H 850RFO requests that access L2 cache. 851.It Li L2_TRANS.CODE_RD 852.Pq Event F0H, Umask 04H 853L2 cache accesses when fetching instructions. 854.It Li L2_TRANS.ALL_PF 855.Pq Event F0H, Umask 08H 856L2 or LLC HW prefetches that access L2 cache. 857.It Li L2_TRANS.L1D_WB 858.Pq Event F0H, Umask 10H 859L1D writebacks that access L2 cache. 860.It Li L2_TRANS.L2_FILL 861.Pq Event F0H, Umask 20H 862L2 fill requests that access L2 cache. 863.It Li L2_TRANS.L2_WB 864.Pq Event F0H, Umask 40H 865L2 writebacks that access L2 cache. 866.It Li L2_TRANS.ALL_REQUESTS 867.Pq Event F0H, Umask 80H 868Transactions accessing L2 pipe. 869.It Li L2_LINES_IN.I 870.Pq Event F1H, Umask 01H 871L2 cache lines in I state filling L2. 872Counting does not cover rejects. 873.It Li L2_LINES_IN.S 874.Pq Event F1H, Umask 02H 875L2 cache lines in S state filling L2. 876Counting does not cover rejects. 877.It Li L2_LINES_IN.E 878.Pq Event F1H, Umask 04H 879L2 cache lines in E state filling L2. 880Counting does not cover rejects. 881.It Li L2_LINES-IN.ALL 882.Pq Event F1H, Umask 07H 883L2 cache lines filling L2. 884Counting does not cover rejects. 885.It Li L2_LINES_OUT.DEMAND_CLEAN 886.Pq Event F2H, Umask 01H 887Clean L2 cache lines evicted by demand. 888.It Li L2_LINES_OUT.DEMAND_DIRTY 889.Pq Event F2H, Umask 02H 890Dirty L2 cache lines evicted by demand. 891.It Li L2_LINES_OUT.PF_CLEAN 892.Pq Event F2H, Umask 04H 893Clean L2 cache lines evicted by L2 prefetch. 894.It Li L2_LINES_OUT.PF_DIRTY 895.Pq Event F2H, Umask 08H 896Dirty L2 cache lines evicted by L2 prefetch. 897.It Li L2_LINES_OUT.DIRTY_ALL 898.Pq Event F2H, Umask 0AH 899Dirty L2 cache lines filling the L2. 900Counting does not cover rejects. 901.It Li SQ_MISC.SPLIT_LOCK 902.Pq Event F4H, Umask 10H 903Split locks in SQ. 904.El 905.Sh SEE ALSO 906.Xr pmc 3 , 907.Xr pmc.atom 3 , 908.Xr pmc.core 3 , 909.Xr pmc.corei7 3 , 910.Xr pmc.corei7uc 3 , 911.Xr pmc.iaf 3 , 912.Xr pmc.ivybridge 3 , 913.Xr pmc.ivybridgexeon 3 , 914.Xr pmc.k7 3 , 915.Xr pmc.k8 3 , 916.Xr pmc.sandybridgeuc 3 , 917.Xr pmc.sandybridgexeon 3 , 918.Xr pmc.soft 3 , 919.Xr pmc.tsc 3 , 920.Xr pmc.ucf 3 , 921.Xr pmc.westmere 3 , 922.Xr pmc.westmereuc 3 , 923.Xr pmc_cpuinfo 3 , 924.Xr pmclog 3 , 925.Xr hwpmc 4 926.Sh HISTORY 927The 928.Nm pmc 929library first appeared in 930.Fx 6.0 . 931.Sh AUTHORS 932.An -nosplit 933The 934.Lb libpmc 935library was written by 936.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 937The support for the Sandy Bridge 938microarchitecture was written by 939.An Davide Italiano Aq Mt davide@FreeBSD.org . 940