1.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd October 19, 2012 28.Dt PMC.SANDYBRIDGE 3 29.Os 30.Sh NAME 31.Nm pmc.sandybridge 32.Nd measurement events for 33.Tn Intel 34.Tn Sandy Bridge 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Sandy Bridge" 43CPUs contain PMCs conforming to the version 3 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs may contain up to three classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_IAP" 48.It Li PMC_CLASS_IAF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_IAP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.It Li PMC_CLASS_TSC 54These PMCs are documented in 55.Xr pmc.tsc 3 . 56.El 57.Pp 58The number of PMCs available in each class and their widths need to be 59determined at run time by calling 60.Xr pmc_cpuinfo 3 . 61.Pp 62Intel Sandy Bridge PMCs are documented in 63.Rs 64.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 65.%T "Volume 3B: System Programming Guide, Part 2" 66.%N "Order Number: 253669-039US" 67.%D May 2011 68.%Q "Intel Corporation" 69.Re 70.Ss SANDY BRIDGE FIXED FUNCTION PMCS 71These PMCs and their supported events are documented in 72.Xr pmc.iaf 3 . 73.Ss SANDY BRIDGE PROGRAMMABLE PMCS 74The programmable PMCs support the following capabilities: 75.Bl -column "PMC_CAP_INTERRUPT" "Support" 76.It Em Capability Ta Em Support 77.It PMC_CAP_CASCADE Ta \&No 78.It PMC_CAP_EDGE Ta Yes 79.It PMC_CAP_INTERRUPT Ta Yes 80.It PMC_CAP_INVERT Ta Yes 81.It PMC_CAP_READ Ta Yes 82.It PMC_CAP_PRECISE Ta \&No 83.It PMC_CAP_SYSTEM Ta Yes 84.It PMC_CAP_TAGGING Ta \&No 85.It PMC_CAP_THRESHOLD Ta Yes 86.It PMC_CAP_USER Ta Yes 87.It PMC_CAP_WRITE Ta Yes 88.El 89.Ss Event Qualifiers 90Event specifiers for these PMCs support the following common 91qualifiers: 92.Bl -tag -width indent 93.It Li rsp= Ns Ar value 94Configure the Off-core Response bits. 95.Bl -tag -width indent 96.It Li REQ_DMND_DATA_RD 97Counts the number of demand and DCU prefetch data reads of full and partial 98cachelines as well as demand data page table entry cacheline reads. Does not 99count L2 data read prefetches or instruction fetches. 100.It Li REQ_DMND_RFO 101Counts the number of demand and DCU prefetch reads for ownership (RFO) 102requests generated by a write to data cacheline. Does not count L2 RFO 103prefetches. 104.It Li REQ_DMND_IFETCH 105Counts the number of demand and DCU prefetch instruction cacheline reads. 106Does not count L2 code read prefetches. 107.It Li REQ_WB 108Counts the number of writeback (modified to exclusive) transactions. 109.It Li REQ_PF_DATA_RD 110Counts the number of data cacheline reads generated by L2 prefetchers. 111.It Li REQ_PF_RFO 112Counts the number of RFO requests generated by L2 prefetchers. 113.It Li REQ_PF_IFETCH 114Counts the number of code reads generated by L2 prefetchers. 115.It Li REQ_PF_LLC_DATA_RD 116L2 prefetcher to L3 for loads. 117.It Li REQ_PF_LLC_RFO 118RFO requests generated by L2 prefetcher 119.It Li REQ_PF_LLC_IFETCH 120L2 prefetcher to L3 for instruction fetches. 121.It Li REQ_BUS_LOCKS 122Bus lock and split lock requests. 123.It Li REQ_STRM_ST 124Streaming store requests. 125.It Li REQ_OTHER 126Any other request that crosses IDI, including I/O. 127.It Li RES_ANY 128Catch all value for any response types. 129.It Li RES_SUPPLIER_NO_SUPP 130No Supplier Information available. 131.It Li RES_SUPPLIER_LLC_HITM 132M-state initial lookup stat in L3. 133.It Li RES_SUPPLIER_LLC_HITE 134E-state. 135.It Li RES_SUPPLIER_LLC_HITS 136S-state. 137.It Li RES_SUPPLIER_LLC_HITF 138F-state. 139.It Li RES_SUPPLIER_LOCAL 140Local DRAM Controller. 141.It Li RES_SNOOP_SNP_NONE 142No details on snoop-related information. 143.It Li RES_SNOOP_SNP_NO_NEEDED 144No snoop was needed to satisfy the request. 145.It Li RES_SNOOP_SNP_MISS 146A snoop was needed and it missed all snooped caches: 147-For LLC Hit, ReslHitl was returned by all cores 148-For LLC Miss, Rspl was returned by all sockets and data was returned from 149DRAM. 150.It Li RES_SNOOP_HIT_NO_FWD 151A snoop was needed and it hits in at least one snooped cache. Hit denotes a 152cache-line was valid before snoop effect. This includes: 153-Snoop Hit w/ Invalidation (LLC Hit, RFO) 154-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 155-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 156In the LLC Miss case, data is returned from DRAM. 157.It Li RES_SNOOP_HIT_FWD 158A snoop was needed and data was forwarded from a remote socket. 159This includes: 160-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 161.It Li RES_SNOOP_HITM 162A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a 163cache-line was in modified state before effect as a results of snoop. This 164includes: 165-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 166-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 167-Snoop MtoS (LLC Hit, IFetch/Data_RD). 168.It Li RES_NON_DRAM 169Target was non-DRAM system address. This includes MMIO transactions. 170.El 171.It Li cmask= Ns Ar value 172Configure the PMC to increment only if the number of configured 173events measured in a cycle is greater than or equal to 174.Ar value . 175.It Li edge 176Configure the PMC to count the number of de-asserted to asserted 177transitions of the conditions expressed by the other qualifiers. 178If specified, the counter will increment only once whenever a 179condition becomes true, irrespective of the number of clocks during 180which the condition remains true. 181.It Li inv 182Invert the sense of comparison when the 183.Dq Li cmask 184qualifier is present, making the counter increment when the number of 185events per cycle is less than the value specified by the 186.Dq Li cmask 187qualifier. 188.It Li os 189Configure the PMC to count events happening at processor privilege 190level 0. 191.It Li usr 192Configure the PMC to count events occurring at privilege levels 1, 2 193or 3. 194.El 195.Pp 196If neither of the 197.Dq Li os 198or 199.Dq Li usr 200qualifiers are specified, the default is to enable both. 201.Ss Event Specifiers (Programmable PMCs) 202Sandy Bridge programmable PMCs support the following events: 203.Bl -tag -width indent 204.It Li LD_BLOCKS.DATA_UNKNOWN 205.Pq EVENT_03H, Umask 01H 206Blocked loads due to store buffer blocks with unknown data. 207.It Li LD_BLOCKS.STORE_FORWARD 208.Pq Event 03H, Umask 02H 209Loads blocked by overlapping with store buffer that cannot be forwarded. 210.It Li LD_BLOCKS.NO_SR 211.Pq Event 03H, Umask 08H 212# of Split loads blocked due to resource not available. 213.It Li LD_BLOCKS.ALL_BLOCK 214.Pq EVENT_03H, Umask 10H 215Number of cases where any load is blocked but has no DCU miss. 216.It Li MISALIGN_MEM_REF.LOADS 217.Pq Event 05H, Umask 01H 218Speculative cache-line split load uops dispatched to L1D. 219.It Li MISALIGN_MEM_REF.STORES 220.Pq Event 05H, Umask 02H 221Speculative cache-line split Store-address uops dispatched to L1D. 222.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 223.Pq Event 07H, Umask 01H 224False dependencies in MOB due to partial compare on address. 225.It Li LD_BLOCKS_PARTIAL.ALL_STA_BLOCK 226.Pq Event 07H, Umask 08H 227The number of times that load operations are temporarily blocked because of 228older stores, with addresses that are not yet known. 229A load operation may incur more than one block of this type. 230.It LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK 231.Pq Event 08H, Umask 01H 232Misses in all TLB levels that cause a page walk of any page size. 233.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 234.Pq Event 08H, Umask 02H 235Misses in all TLB levels that caused page walk completed of any size. 236.It Li DTLB_LOAD_MISSES.WALK_DURATION 237.Pq Event 08H, Umask 04H 238Cycle PMH is busy with a walk. 239.It Li DTLB_LOAD_MISSES.STLB_HIT 240.Pq Event 08H, Umask 10H 241Number of cache load STLB hits. 242No page walk. 243.It Li INT_MISC.RECOVERY_CYCLES 244.Pq Event 0DH, Umask 03H 245Cycles waiting to recover after Machine Clears or JEClear. 246Set Cmask = 1. 247Set Edge to count occurrences 248.It Li INT_MISC.RAT_STALL_CYCLES 249.Pq Event 0DH, Umask 40H 250Cycles RAT external stall is sent to IDQ for this thread. 251.It Li UOPS_ISSUED.ANY 252.Pq Event 0EH, Umask 01H 253Increments each cycle the # of Uops issued by the RAT to RS. 254Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core. 255Set Cmask = 1, Inv = 1 to count stalled cycles 256.It Li FP_COMP_OPS_EXE.X87 257.Pq Event 10H, Umask 01H 258Counts number of X87 uops executed. 259.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE 260.Pq Event 10H, Umask 10H 261Counts number of SSE* double precision FP packed uops executed. 262.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE 263.Pq Event 10H, Umask 20H 264Counts number of SSE* single precision FP scalar uops executed. 265.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE 266.Pq Event 10H, Umask 40H 267Counts number of SSE* single precision FP packed uops executed. 268.It LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE 269.Pq Event 10H, Umask 80H 270Counts number of SSE* double precision FP scalar uops executed. 271.It Li SIMD_FP_256.PACKED_SINGLE 272.Pq Event 11H, Umask 01H 273Counts 256-bit packed single-precision floating-point instructions. 274.It Li SIMD_FP_256.PACKED_DOUBLE 275.Pq Event 11H, Umask 02H 276Counts 256-bit packed double-precision floating-point instructions. 277.It Li ARITH.FPU_DIV_ACTIVE 278.Pq Event 14H, Umask 01H 279Cycles that the divider is active, includes INT and FP. 280Set 'edge =1, cmask=1' to count the number of divides. 281.It Li INSTS_WRITTEN_TO_IQ.INSTS 282.Pq Event 17H, Umask 01H 283Counts the number of instructions written into the IQ every cycle. 284.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 285.Pq Event 24H, Umask 01H 286Demand Data Read requests that hit L2 cache. 287.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 288.Pq Event 24H, Umask 03H 289Counts any demand and L1 HW prefetch data load requests to L2. 290.It Li L2_RQSTS.RFO_HITS 291.Pq Event 24H, Umask 04H 292Counts the number of store RFO requests that hit the L2 cache. 293.It Li L2_RQSTS.RFO_MISS 294.Pq Event 24H, Umask 08H 295Counts the number of store RFO requests that miss the L2 cache. 296.It Li L2_RQSTS.ALL_RFO 297.Pq Event 24H, Umask 0CH 298Counts all L2 store RFO requests. 299.It Li L2_RQSTS.CODE_RD_HIT 300.Pq Event 24H, Umask 10H 301Number of instruction fetches that hit the L2 cache. 302.It Li L2_RQSTS.CODE_RD_MISS 303.Pq Event 24H, Umask 20H 304Number of instruction fetches that missed the L2 cache. 305.It Li L2_RQSTS.ALL_CODE_RD 306.Pq Event 24H, Umask 30H 307Counts all L2 code requests. 308.It Li L2_RQSTS.PF_HIT 309.Pq Event 24H, Umask 40H 310Requests from L2 Hardware prefetcher that hit L2. 311.It Li L2_RQSTS.PF_MISS 312.Pq Event 24H, Umask 80H 313Requests from L2 Hardware prefetcher that missed L2. 314.It Li L2_RQSTS.ALL_PF 315.Pq Event 24H, Umask C0H 316Any requests from L2 Hardware prefetchers. 317.It Li L2_STORE_LOCK_RQSTS.MISS 318.Pq Event 27H, Umask 01H 319RFOs that miss cache lines. 320.It Li L2_STORE_LOCK_RQSTS.HIT_E 321.Pq Event 27H, Umask 04H 322RFOs that hit cache lines in E state. 323.It Li L2_STORE_LOCK_RQSTS.HIT_M 324.Pq EVENT_27H, Umask 08H 325RFOs that hit cache lines in M state. 326.It Li L2_STORE_LOCK_RQSTS.ALL 327.Pq EVENT_27H, Umask 0FH 328RFOs that access cache lines in any state. 329.It Li L2_L1D_WB_RQSTS.HIT_E 330.Pq Event 28H, Umask 04H 331Not rejected writebacks from L1D to L2 cache lines in E state. 332.It Li L2_L1D_WB_RQSTS.HIT_M 333.Pq Event 28H, Umask 08H 334Not rejected writebacks from L1D to L2 cache lines in M state. 335.It Li LONGEST_LAT_CACHE.REFERENCE 336.Pq Event 2EH, Umask 4FH 337This event counts requests originating from the core that reference a cache 338line in the last level cache. 339.It Li LONGEST_LAT_CACHE.MISS 340.Pq Event 2EH, Umask 41H 341This event counts each cache miss condition for references to the last level 342cache. 343.It Li CPU_CLK_UNHALTED.THREAD_P 344.Pq Event 3CH, Umask 00H 345Counts the number of thread cycles while the thread is not in a halt state. 346The thread enters the halt state when it is running the HLT instruction. 347The core frequency may change from time to time due to power or thermal 348throttling. 349.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 350.Pq Event 3CH, Umask 01H 351Increments at the frequency of XCLK (100 MHz) when not halted. 352.It Li L1D_PEND_MISS.PENDING 353.Pq Event 48H, Umask 01H 354Increments the number of outstanding L1D misses every cycle. 355Set Cmask = 1 and Edge =1 to count occurrences. 356Counter 2 only; Set Cmask = 1 to count cycles. 357.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 358.Pq Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any 359page size (4K/2M/4M/1G). 360.It Li DTLB_STORE_MISSES.WALK_COMPLETED 361.Pq Event 49H, Umask 02H 362Miss in all TLB levels causes a page walk that completes of any page size 363(4K/2M/4M/1G). 364.It Li DTLB_STORE_MISSES.WALK_DURATION 365.Pq Event 49H, Umask 04H 366Cycles PMH is busy with this walk. 367.It Li DTLB_STORE_MISSES.STLB_HIT 368.Pq Event 49H, Umask 10H 369Store operations that miss the first TLB level but hit the second and do not 370cause page walks. 371.It Li LOAD_HIT_PRE.SW_PF 372.Pq Event 4CH, Umask 01H 373Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. 374.It Li LOAD_HIT_PER.HW_PF 375.Pq Event 4CH, Umask 02H 376Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. 377.It Li HW_PRE_REQ.DL1_MISS 378.Pq Event 4EH, Umask 02H 379Hardware Prefetch requests that miss the L1D cache. 380A request is being counted each time it access the cache & miss it, including 381if a block is applicable or if hit the Fill Buffer for example. 382This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. 383.It Li L1D.REPLACEMENT 384.Pq Event 51H, Umask 01H 385Counts the number of lines brought into the L1 data cache. 386.It Li L1D.ALLOCATED_IN_M 387.Pq Event 51H, Umask 02H 388Counts the number of allocations of modified L1D cache lines. 389.It Li L1D.EVICTION 390.Pq Event 51H, Umask 04H 391Counts the number of modified lines evicted from the L1 data cache due to 392replacement. 393.It Li L1D.ALL_M_REPLACEMENT 394.Pq Event 51H, Umask 08H 395Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line 396replacement. 397.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP 398.Pq Event 59H, Umask 20H 399Increments the number of flags-merge uops in flight each cycle. 400Set Cmask = 1 to count cycles. 401.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW 402.Pq Event 59H, Umask 40H 403Cycles with at least one slow LEA uop allocated. 404.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP 405.Pq Event 59H, Umask 80H 406Number of Multiply packed/scalar single precision uops allocated. 407.It Li RESOURCE_STALLS2.ALL_FL_EMPTY 408.Pq Event 5BH, Umask 0CH 409Cycles stalled due to free list empty. 410.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL 411.Pq Event 5BH, Umask 0FH 412Cycles stalled due to control structures full for physical registers. 413.It Li RESOURCE_STALLS2.BOB_FULL 414.Pq Event 5BH, Umask 40H 415Cycles Allocator is stalled due to Branch Order Buffer. 416.It Li RESOURCE_STALLS2.OOO_RSRC 417.Pq Event 5BH, Umask 4FH 418Cycles stalled due to out of order resources full. 419.It Li CPL_CYCLES.RING0 420.Pq Event 5CH, Umask 01H 421Unhalted core cycles when the thread is in ring 0. 422Use Edge to count transition 423.It Li CPL_CYCLES.RING123 424.Pq Event 5CH, Umask 02H 425Unhalted core cycles when the thread is not in ring 0. 426.It Li RS_EVENTS.EMPTY_CYCLES 427.Pq Event 5EH, Umask 01H 428Cycles the RS is empty for the thread. 429.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 430.Pq Event 60H, Umask 01H 431Offcore outstanding Demand Data Read transactions in SQ to uncore. 432Set Cmask=1 to count cycles. 433.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 434.Pq Event 60H, Umask 04H 435Offcore outstanding RFO store transactions in SQ to uncore. 436Set Cmask=1 to count cycles. 437.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 438.Pq Event 60H, Umask 08H 439Offcore outstanding cacheable data read transactions in SQ to uncore. 440Set Cmask=1 to count cycles. 441.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 442.Pq Event 63H, Umask 01H 443Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 444.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 445.Pq Event 63H, Umask 02H 446Cycles in which the L1D is locked. 447.It Li IDQ.EMPTY 448.Pq Event 79H, Umask 02H 449Counts cycles the IDQ is empty. 450.It Li IQD.MITE_UOPS 451.Pq Event 79H, Umask 04H 452Increment each cycle # of uops delivered to IDQ from MITE path. 453Set Cmask = 1 to count cycles. 454Can combine Umask 04H and 20H 455.It Li IDQ.DSB_UOPS 456.Pq Event 79H, Umask 08H 457Increment each cycle. 458# of uops delivered to IDQ from DSB path. 459Set Cmask = 1 to count cycles. 460Can combine Umask 08H and 10H 461.It Li IDQ.MS_DSB_UOPS 462.Pq Event 79H, Umask 10H 463Increment each cycle # of uops delivered to IDQ when MS busy by DSB. 464Set Cmask = 1 to count cycles MS is busy. 465Set Cmask=1 and Edge=1 to count MS activations. 466Can combine Umask 08H and 10H 467.It Li IDQ.MS_MITE_UOPS 468.Pq Event 79H, Umask 20H 469Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. 470Set Cmask = 1 to count cycles. 471Can combine Umask 04H and 20H 472.It Li IDQ.MS_UOPS 473.Pq Event 79H, Umask 30H 474Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. 475Set Cmask = 1 to count cycles. 476Can combine Umask 04H, 08H and 30H 477.It Li ICACHE.MISSES 478.Pq Event 80H, Umask 02H 479Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 480Includes UC accesses. 481.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 482.Pq Event 85H, Umask 01H 483Misses in all ITLB levels that cause page walks. 484.It Li ITLB_MISSES.WALK_COMPLETED 485.Pq Event 85H, Umask 02H 486Misses in all ITLB levels that cause completed page walks. 487.It Li ITLB_MISSES.WALK_DURATION 488.Pq Event 85H, Umask 04H 489Cycle PMH is busy with a walk. 490.It Li ITLB_MISSES.STLB_HIT 491.Pq Event 85H, Umask 10H 492Number of cache load STLB hits. 493No page walk. 494.It Li ILD_STALL.LCP 495.Pq Event 87H, Umask 01H 496Stalls caused by changing prefix length of the instruction. 497.It Li ILD_STALL.IQ_FULL 498.Pq Event 87H, Umask 04H 499Stall cycles due to IQ is full. 500.It Li BR_INST_EXEC.NONTAKEN_COND 501.Pq Event 88H , Umask 41H 502Count conditional near branch instructions that were executed (but not 503necessarily retired) and not taken. 504.It Li BR_INST_EXEC.TAKEN_COND 505.Pq Event 88H , Umask 81H 506Count conditional near branch instructions that were executed (but not 507necessarily retired) and taken. 508.It Li BR_INST_EXEC.DIRECT_JMP 509.Pq Event 88H , Umask 82H 510Count all unconditional near branch instructions excluding calls and 511indirect branches. 512.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 513.Pq Event 88H , Umask 84H 514Count executed indirect near branch instructions that are not calls nor 515returns. 516.It Li BR_INST_EXEC.RETURN_NEAR 517.Pq Event 88H , Umask 88H 518Count indirect near branches that have a return mnemonic. 519.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 520.Pq Event 88H , Umask 90H 521Count unconditional near call branch instructions, excluding non call 522branch, executed. 523.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 524.Pq Event 88H , Umask A0H 525Count indirect near calls, including both register and memory indirect, 526executed. 527.It Li BR_INST_EXEC.ALL_BRANCHES 528.Pq Event 88H , Umask FFH 529Counts all near executed branches (not necessarily retired). 530.It Li BR_MISP_EXEC.NONTAKEN_COND 531.Pq Event 89H , Umask 41H 532Count conditional near branch instructions mispredicted as nontaken. 533.It Li BR_MISP_EXEC.TAKEN_COND 534.Pq Event 89H , Umask 81H 535Count conditional near branch instructions mispredicted as taken. 536.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 537.Pq Event 89H , Umask 84H 538Count mispredicted indirect near branch instructions that are not calls 539nor returns. 540.It Li BR_MISP_EXEC.RETURN_NEAR 541.Pq Event 89H , Umask 88H 542Count mispredicted indirect near branches that have a return mnemonic. 543.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 544.Pq Event 89H , Umask 90H 545Count mispredicted unconditional near call branch instructions, excluding 546non call branch, executed. 547.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 548.Pq Event 89H , Umask A0H 549Count mispredicted indirect near calls, including both register and memory 550indirect, executed. 551.It Li BR_MISP_EXEC.ALL_BRANCHES 552.Pq Event 89H , Umask FFH 553Counts all mispredicted near executed branches (not necessarily retired). 554.It Li IDQ_UOPS_NOT_DELIVERED.CORE 555.Pq Event 9CH, Umask 01H 556Count number of non-delivered uops to RAT per thread. 557Use Cmask to qualify uop b/w 558.It Li UOPS_DISPATCHED_PORT.PORT_0 559.Pq Event A1H, Umask 01H 560Cycles which a Uop is dispatched on port 0. 561.It Li UOPS_DISPATCHED_PORT.PORT_1 562.Pq Event A1H, Umask 02H 563Cycles which a Uop is dispatched on port 1. 564.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 565.Pq Event A1H, Umask 04H 566Cycles which a load uop is dispatched on port 2. 567.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 568.Pq Event A1H, Umask 08H 569Cycles which a store address uop is dispatched on port 2. 570.It Li UOPS_DISPATCHED_PORT.PORT_2 571.Pq Event A1H, Umask 0CH 572Cycles which a Uop is dispatched on port 2. 573.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 574.Pq Event A1H, Umask 10H 575Cycles which a load uop is dispatched on port 3. 576.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 577.Pq Event A1H, Umask 20H 578Cycles which a store address uop is dispatched on port 3. 579.It Li UOPS_DISPATCHED_PORT.PORT_3 580.Pq Event A1H, Umask 30H 581.Pq Cycles which a Uop is dispatched on port 3. 582.It Li UOPS_DISPATCHED_PORT.PORT_4 583.Pq Event A1H, Umask 40H 584Cycles which a Uop is dispatched on port 4. 585.It Li UOPS_DISPATCHED_PORT.PORT_5 586.Pq Event A1H, Umask 80H 587Cycles which a Uop is dispatched on port 5. 588.It Li RESOURCE_STALLS.ANY 589.Pq Event A2H, Umask 01H 590Cycles Allocation is stalled due to Resource Related reason. 591.It Li RESOURCE_STALLS.LB 592.Pq Event A2H, Umask 02H 593Counts the cycles of stall due to lack of load buffers. 594.It Li RESOURCE_STALLS.LB 595.Pq Event A2H, Umask 04H 596Cycles stalled due to no eligible RS entry available. 597.It Li RESOURCE_STALLS.SB 598.Pq Event A2H, Umask 08H 599Cycles stalled due to no store buffers available. 600(not including draining form sync) 601.It Li RESOURCE_STALLS.ROB 602.Pq Event A2H, Umask 10H 603Cycles stalled due to re-order buffer full. 604.It Li RESOURCE_STALLS.FCSW 605.Pq Event A2H, Umask 20H 606Cycles stalled due to writing the FPU control word. 607.It Li RESOURCE_STALLS.MXCSR 608.Pq Event A2H, Umask 40H 609Cycles stalled due to the MXCSR register rename occurring to close to a previous 610MXCSR rename. 611.It Li RESOURCE_STALLS.OTHER 612.Pq Event A2H, Umask 80H 613Cycles stalled while execution was stalled due to other resource issues. 614.It Li DSB2MITE_SWITCHES.COUNT 615.Pq Event ABH, Umask 01H 616Number of DSB to MITE switches. 617.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 618.Pq Event ABH, Umask 02H 619Cycles DSB to MITE switches caused delay. 620.It Li DSB_FILL.OTHER_CANCEL 621.Pq Event ACH, Umask 02H 622Cases of cancelling valid DSB fill not because of exceeding way limit. 623.It Li DSB_FILL.EXCEED_DSB_LINES 624.Pq Event ACH, Umask 08H 625DSB Fill encountered > 3 DSB lines. 626.It Li DSB_FILL.ALL_CANCEL 627.Pq Event ACH, Umask 0AH 628Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding 629way limit. 630.It Li ITLB.ITLB_FLUSH 631.Pq Event AEH, Umask 01H 632Counts the number of ITLB flushes, includes 4k/2M/4M pages. 633.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 634.Pq Event B0H, Umask 01H 635Demand data read requests sent to uncore. 636.It Li OFFCORE_REQUESTS.DEMAND_RFO 637.Pq Event B0H, Umask 04H 638Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. 639.It Li OFFCORE_REQUESTS.ALL_DATA_RD 640.Pq Event B0H, Umask 08H 641Data read requests sent to uncore (demand and prefetch). 642.It Li UOPS_DISPATCHED.THREAD 643.Pq Event B1H, Umask 01H 644Counts total number of uops to be dispatched per-thread each cycle. 645Set Cmask = 1, INV =1 to count stall cycles. 646.It Li UOPS_DISPATCHED.CORE 647.Pq Event B1H, Umask 02H 648Counts total number of uops to be dispatched per-core each cycle. 649Do not need to set ANY 650.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL 651.Pq Event B2H, Umask 01H 652Offcore requests buffer cannot take more entries for this thread core. 653.It Li AGU_BYPASS_CANCEL.COUNT 654.Pq Event B6H, Umask 01H 655Counts executed load operations with all the following traits: 1. addressing 656of the format [base + offset], 2. the offset is between 1 and 2047, 3. the 657address specified in the base register is in one page and the address 658[base+offset] is in another page. 659.It Li OFF_CORE_RESPONSE_0 660.Pq Event B7H, Umask 01H 661Off-core Response Performance Monitoring; PMC0 only. 662Requires programming MSR 01A6H 663.It Li OFF_CORE_RESPONSE_1 664.Pq Event BBH, Umask 01H 665Off-core Response Performance Monitoring. PMC3 only. 666Requires programming MSR 01A7H 667.It Li TLB_FLUSH.DTLB_THREAD 668.Pq Event BDH, Umask 01H 669DTLB flush attempts of the thread-specific entries. 670.It Li TLB_FLUSH.STLB_ANY 671.Pq Event BDH, Umask 20H 672Count number of STLB flush attempts. 673.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES 674.Pq Event BFH, Umask 05H 675Cycles when dispatched loads are cancelled due to L1D bank conflicts with other 676load ports. 677cmask=1 678.It Li INST_RETIRED.ANY_P 679.Pq Event C0H, Umask 00H 680Number of instructions at retirement. 681.It Li INST_RETIRED.PREC_DIST 682.Pq Event C0H, Umask 01H 683Precise instruction retired event with HW to reduce effect of PEBS shadow in IP 684distribution PMC1 only; Must quiesce other PMCs. 685.It Li INST_RETIRED.X87 686.Pq Event C0H, Umask 02H 687X87 instruction retired event. 688.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED 689.Pq Event C1H, Umask 02H 690Instructions that experienced an ITLB miss. 691.It Li OTHER_ASSISTS.AVX_STORE 692.Pq Event C1H, Umask 08H 693Number of assists associated with 256-bit AVX store operations. 694.It Li OTHER_ASSISTS.AVX_TO_SSE 695.Pq Event C1H, Umask 10H 696Number of transitions from AVX256 to legacy SSE when penalty applicable. 697.It Li OTHER_ASSISTS.SSE_TO_AVX 698.Pq Event C1H, Umask 20H 699Number of transitions from SSE to AVX-256 when penalty applicable. 700.It Li UOPS_RETIRED.ALL 701.Pq Event C2H, Umask 01H 702Counts the number of micro-ops retired. 703Use cmask=1 and invert to count active cycles or stalled cycles. 704.It Li UOPS_RETIRED.RETIRE_SLOTS 705.Pq Event C2H, Umask 02H 706Counts the number of retirement slots used each cycle. 707.It Li MACHINE_CLEARS.MEMORY_ORDERING 708.Pq Event C3H, Umask 02H 709Counts the number of machine clears due to memory order conflicts. 710.It Li MACHINE_CLEARS.SMC 711.Pq Event C3H, Umask 04H 712Counts the number of times that a program writes to a code section. 713.It Li MACHINE_CLEARS.MASKMOV 714.Pq Event C3H, Umask 20H 715Counts the number of executed AVX masked load operations that refer to an 716illegal address range with the mask bits set to 0. 717.It Li BR_INST_RETIRED.ALL_BRANCH 718.Pq Event C4H, Umask 00H 719Branch instructions at retirement. 720.It Li BR_INST_RETIRED.CONDITIONAL 721.Pq Event C4H, Umask 01H 722Counts the number of conditional branch instructions retired. 723.It Li BR_INST_RETIRED.NEAR_CALL 724.Pq Event C4H, Umask 02H 725Direct and indirect near call instructions retired. 726.It Li BR_INST_RETIRED.ALL_BRANCHES 727.Pq Event C4H, Umask 04H 728Counts the number of branch instructions retired. 729.It Li BR_INST_RETIRED.NEAR_RETURN 730.Pq Event C4H, Umask 08H 731Counts the number of near return instructions retired. 732.It Li BR_INST_RETIRED.NOT_TAKEN 733.Pq Event C4H, Umask 10H 734Counts the number of not taken branch instructions retired. 735.It Li BR_INST_RETIRED.NEAR_TAKEN 736.Pq Event C4H, Umask 20H 737Number of near taken branches retired. 738.It Li BR_INST_RETIRED.FAR_BRANCH 739.Pq Event C4H, Umask 40H 740Number of far branches retired. 741.It Li BR_MISP_RETIRED.ALL_BRANCHES 742.Pq Event C5H, Umask 00H 743Mispredicted branch instructions at retirement. 744.It Li BR_MISP_RETIRED.CONDITIONAL 745.Pq Event C5H, Umask 01H 746Mispredicted conditional branch instructions retired. 747.It Li BR_MISP_RETIRED.NEAR_CALL 748.Pq Event C5H, Umask 02H 749Direct and indirect mispredicted near call instructions retired. 750.It Li BR_MISP_RETIRED.ALL_BRANCH 751.Pq Event C5H, Umask 04H 752Mispredicted macro branch instructions retired. 753.It Li BR_MISP_RETIRED.NOT_TAKEN 754.Pq Event C5H, Umask 10H 755Mispredicted not taken branch instructions retired. 756.It Li BR_MISP_RETIRED.TAKEN 757.Pq Event C5H, Umask 20H 758Mispredicted taken branch instructions retired. 759.It Li FP_ASSIST.X87_OUTPUT 760.Pq Event CAH, Umask 02H 761Number of X87 assists due to output value. 762.It Li FP_ASSIST.X87_INPUT 763.Pq Event CAH, Umask 04H 764Number of X87 assists due to input value. 765.It Li FP_ASSIST.SIMD_OUTPUT 766.Pq Event CAH, Umask 08H 767Number of SIMD FP assists due to Output values. 768.It Li FP_ASSIST.SIMD_INPUT 769.Pq Event CAH, Umask 10H 770Number of SIMD FP assists due to input values. 771.It Li FP_ASSIST.ANY 772.Pq Event CAH, Umask 1EH 773Cycles with any input/output SSE* or FP assists. 774.It Li ROB_MISC_EVENTS.LBR_INSERTS 775.Pq Event CCH, Umask 20H 776Count cases of saving new LBR records by hardware. 777.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 778.Pq Event CDH, Umask 01H 779Sample loads with specified latency threshold. 780PMC3 only. 781Specify threshold in MSR 0x3F6. 782.It Li MEM_TRANS_RETIRED.PRECISE_STORE 783.Pq Event CDH, Umask 02H 784Sample stores and collect precise store operation via PEBS record. 785PMC3 only. 786.It Li MEM_UOP_RETIRED.LOADS 787.Pq Event D0H, Umask 01H 788Qualify retired memory uops that are loads. 789Combine with umask 10H, 20H, 40H, 80H. 790.It Li MEM_UOP_RETIRED.STORES 791.Pq Event D0H, Umask 02H 792Qualify retired memory uops that are stores. 793Combine with umask 10H, 20H, 40H, 80H. 794.It Li MEM_UOP_RETIRED.STLB_MISS 795.Pq Event D0H, Umask 10H 796Qualify retired memory uops with STLB miss. 797Must combine with umask 01H, 02H, to produce counts. 798.It Li MEM_UOP_RETIRED.LOCK 799.Pq Event D0H, Umask 20H 800Qualify retired memory uops with lock. 801Must combine with umask 01H, 02H, to produce counts. 802.It Li MEM_UOP_RETIRED.SPLIT 803.Pq Event D0H, Umask 40H 804Qualify retired memory uops with line split. 805Must combine with umask 01H, 02H, to produce counts. 806.It Li MEM_UOP_RETIRED_ALL 807.Pq Event D0H, Umask 80H 808Qualify any retired memory uops. 809Must combine with umask 01H, 02H, to produce counts. 810.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 811.Pq Event D1H, Umask 01H 812Retired load uops with L1 cache hits as data sources. 813Must combine with umask 01H, 02H, to produce counts. 814.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 815.Pq Event D1H, Umask 02H 816Retired load uops with L2 cache hits as data sources. 817.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 818.Pq Event D1H, Umask 04H 819Retired load uops which data sources were data hits in LLC without snoops 820required. 821.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 822.Pq Event D1H, Umask 40H 823Retired load uops which data sources were load uops missed L1 but hit FB due 824to preceding miss to the same cache line with data not ready. 825.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 826.Pq Event D2H, Umask 01H 827Retired load uops which data sources were LLC hit and cross-core snoop missed in 828on-pkg core cache. 829.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 830.Pq Event D2H, Umask 02H 831Retired load uops which data sources were LLC and cross-core snoop hits in 832on-pkg core cache. 833.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 834.Pq Event D2H, Umask 04H 835Retired load uops which data sources were HitM responses from shared LLC. 836.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 837.Pq Event D2H, Umask 08H 838Retired load uops which data sources were hits in LLC without snoops required. 839.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS 840.Pq Event D4H, Umask 02H 841Retired load uops with unknown information as data source in cache serviced the load. 842.It Li L2_TRANS.DEMAND_DATA_RD 843.Pq Event F0H, Umask 01H 844Demand Data Read requests that access L2 cache. 845.It Li L2_TRANS.RF0 846.Pq Event F0H, Umask 02H 847RFO requests that access L2 cache. 848.It Li L2_TRANS.CODE_RD 849.Pq Event F0H, Umask 04H 850L2 cache accesses when fetching instructions. 851.It Li L2_TRANS.ALL_PF 852.Pq Event F0H, Umask 08H 853L2 or LLC HW prefetches that access L2 cache. 854.It Li L2_TRANS.L1D_WB 855.Pq Event F0H, Umask 10H 856L1D writebacks that access L2 cache. 857.It Li L2_TRANS.L2_FILL 858.Pq Event F0H, Umask 20H 859L2 fill requests that access L2 cache. 860.It Li L2_TRANS.L2_WB 861.Pq Event F0H, Umask 40H 862L2 writebacks that access L2 cache. 863.It Li L2_TRANS.ALL_REQUESTS 864.Pq Event F0H, Umask 80H 865Transactions accessing L2 pipe. 866.It Li L2_LINES_IN.I 867.Pq Event F1H, Umask 01H 868L2 cache lines in I state filling L2. 869Counting does not cover rejects. 870.It Li L2_LINES_IN.S 871.Pq Event F1H, Umask 02H 872L2 cache lines in S state filling L2. 873Counting does not cover rejects. 874.It Li L2_LINES_IN.E 875.Pq Event F1H, Umask 04H 876L2 cache lines in E state filling L2. 877Counting does not cover rejects. 878.It Li L2_LINES-IN.ALL 879.Pq Event F1H, Umask 07H 880L2 cache lines filling L2. 881Counting does not cover rejects. 882.It Li L2_LINES_OUT.DEMAND_CLEAN 883.Pq Event F2H, Umask 01H 884Clean L2 cache lines evicted by demand. 885.It Li L2_LINES_OUT.DEMAND_DIRTY 886.Pq Event F2H, Umask 02H 887Dirty L2 cache lines evicted by demand. 888.It Li L2_LINES_OUT.PF_CLEAN 889.Pq Event F2H, Umask 04H 890Clean L2 cache lines evicted by L2 prefetch. 891.It Li L2_LINES_OUT.PF_DIRTY 892.Pq Event F2H, Umask 08H 893Dirty L2 cache lines evicted by L2 prefetch. 894.It Li L2_LINES_OUT.DIRTY_ALL 895.Pq Event F2H, Umask 0AH 896Dirty L2 cache lines filling the L2. 897Counting does not cover rejects. 898.It Li SQ_MISC.SPLIT_LOCK 899.Pq Event F4H, Umask 10H 900Split locks in SQ. 901.El 902.Sh SEE ALSO 903.Xr pmc 3 , 904.Xr pmc.atom 3 , 905.Xr pmc.core 3 , 906.Xr pmc.corei7 3 , 907.Xr pmc.corei7uc 3 , 908.Xr pmc.iaf 3 , 909.Xr pmc.ivybridge 3 , 910.Xr pmc.ivybridgexeon 3 , 911.Xr pmc.k7 3 , 912.Xr pmc.k8 3 , 913.Xr pmc.p4 3 , 914.Xr pmc.p5 3 , 915.Xr pmc.p6 3 , 916.Xr pmc.sandybridgeuc 3 , 917.Xr pmc.sandybridgexeon 3 , 918.Xr pmc.soft 3 , 919.Xr pmc.tsc 3 , 920.Xr pmc.ucf 3 , 921.Xr pmc.westmere 3 , 922.Xr pmc.westmereuc 3 , 923.Xr pmc_cpuinfo 3 , 924.Xr pmclog 3 , 925.Xr hwpmc 4 926.Sh HISTORY 927The 928.Nm pmc 929library first appeared in 930.Fx 6.0 . 931.Sh AUTHORS 932.An -nosplit 933The 934.Lb libpmc 935library was written by 936.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 937The support for the Sandy Bridge 938microarchitecture was written by 939.An Davide Italiano Aq Mt davide@FreeBSD.org . 940