1.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd January 25, 2013 26.Dt PMC.IVYBRIDGEXEON 3 27.Os 28.Sh NAME 29.Nm pmc.ivybridgexeon 30.Nd measurement events for 31.Tn Intel 32.Tn Ivy Bridge Xeon 33family CPUs 34.Sh LIBRARY 35.Lb libpmc 36.Sh SYNOPSIS 37.In pmc.h 38.Sh DESCRIPTION 39.Tn Intel 40.Tn "Ivy Bridge Xeon" 41CPUs contain PMCs conforming to version 2 of the 42.Tn Intel 43performance measurement architecture. 44These CPUs may contain up to three classes of PMCs: 45.Bl -tag -width "Li PMC_CLASS_IAP" 46.It Li PMC_CLASS_IAF 47Fixed-function counters that count only one hardware event per counter. 48.It Li PMC_CLASS_IAP 49Programmable counters that may be configured to count one of a defined 50set of hardware events. 51.El 52.Pp 53The number of PMCs available in each class and their widths need to be 54determined at run time by calling 55.Xr pmc_cpuinfo 3 . 56.Pp 57Intel Ivy Bridge Xeon PMCs are documented in 58.Rs 59.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 60.%N "Order Number: 325462-045US" 61.%D January 2013 62.%Q "Intel Corporation" 63.Re 64.Ss IVYBRIDGE FIXED FUNCTION PMCS 65These PMCs and their supported events are documented in 66.Xr pmc.iaf 3 . 67.Ss IVYBRIDGE PROGRAMMABLE PMCS 68The programmable PMCs support the following capabilities: 69.Bl -column "PMC_CAP_INTERRUPT" "Support" 70.It Em Capability Ta Em Support 71.It PMC_CAP_CASCADE Ta \&No 72.It PMC_CAP_EDGE Ta Yes 73.It PMC_CAP_INTERRUPT Ta Yes 74.It PMC_CAP_INVERT Ta Yes 75.It PMC_CAP_READ Ta Yes 76.It PMC_CAP_PRECISE Ta \&No 77.It PMC_CAP_SYSTEM Ta Yes 78.It PMC_CAP_TAGGING Ta \&No 79.It PMC_CAP_THRESHOLD Ta Yes 80.It PMC_CAP_USER Ta Yes 81.It PMC_CAP_WRITE Ta Yes 82.El 83.Ss Event Qualifiers 84Event specifiers for these PMCs support the following common 85qualifiers: 86.Bl -tag -width indent 87.It Li rsp= Ns Ar value 88Configure the Off-core Response bits. 89.Bl -tag -width indent 90.It Li REQ_DMND_DATA_RD 91Counts the number of demand and DCU prefetch data reads of full and partial 92cachelines as well as demand data page table entry cacheline reads. 93Does not count L2 data read prefetches or instruction fetches. 94.It Li REQ_DMND_RFO 95Counts the number of demand and DCU prefetch reads for ownership (RFO) 96requests generated by a write to data cacheline. 97Does not count L2 RFO prefetches. 98.It Li REQ_DMND_IFETCH 99Counts the number of demand and DCU prefetch instruction cacheline reads. 100Does not count L2 code read prefetches. 101.It Li REQ_WB 102Counts the number of writeback (modified to exclusive) transactions. 103.It Li REQ_PF_DATA_RD 104Counts the number of data cacheline reads generated by L2 prefetchers. 105.It Li REQ_PF_RFO 106Counts the number of RFO requests generated by L2 prefetchers. 107.It Li REQ_PF_IFETCH 108Counts the number of code reads generated by L2 prefetchers. 109.It Li REQ_PF_LLC_DATA_RD 110L2 prefetcher to L3 for loads. 111.It Li REQ_PF_LLC_RFO 112RFO requests generated by L2 prefetcher 113.It Li REQ_PF_LLC_IFETCH 114L2 prefetcher to L3 for instruction fetches. 115.It Li REQ_BUS_LOCKS 116Bus lock and split lock requests. 117.It Li REQ_STRM_ST 118Streaming store requests. 119.It Li REQ_OTHER 120Any other request that crosses IDI, including I/O. 121.It Li RES_ANY 122Catch all value for any response types. 123.It Li RES_SUPPLIER_NO_SUPP 124No Supplier Information available. 125.It Li RES_SUPPLIER_LLC_HITM 126M-state initial lookup stat in L3. 127.It Li RES_SUPPLIER_LLC_HITE 128E-state. 129.It Li RES_SUPPLIER_LLC_HITS 130S-state. 131.It Li RES_SUPPLIER_LLC_HITF 132F-state. 133.It Li RES_SUPPLIER_LOCAL 134Local DRAM Controller. 135.It Li RES_SNOOP_SNP_NONE 136No details on snoop-related information. 137.It Li RES_SNOOP_SNP_NO_NEEDED 138No snoop was needed to satisfy the request. 139.It Li RES_SNOOP_SNP_MISS 140A snoop was needed and it missed all snooped caches: 141-For LLC Hit, ReslHitl was returned by all cores 142-For LLC Miss, Rspl was returned by all sockets and data was returned from 143DRAM. 144.It Li RES_SNOOP_HIT_NO_FWD 145A snoop was needed and it hits in at least one snooped cache. 146Hit denotes a cache-line was valid before snoop effect. 147This includes: 148-Snoop Hit w/ Invalidation (LLC Hit, RFO) 149-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 150-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 151In the LLC Miss case, data is returned from DRAM. 152.It Li RES_SNOOP_HIT_FWD 153A snoop was needed and data was forwarded from a remote socket. 154This includes: 155-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 156.It Li RES_SNOOP_HITM 157A snoop was needed and it HitM-ed in local or remote cache. 158HitM denotes a cache-line was in modified state before effect as a results of snoop. 159This includes: 160-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 161-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 162-Snoop MtoS (LLC Hit, IFetch/Data_RD). 163.It Li RES_NON_DRAM 164Target was non-DRAM system address. 165This includes MMIO transactions. 166.El 167.It Li cmask= Ns Ar value 168Configure the PMC to increment only if the number of configured 169events measured in a cycle is greater than or equal to 170.Ar value . 171.It Li edge 172Configure the PMC to count the number of de-asserted to asserted 173transitions of the conditions expressed by the other qualifiers. 174If specified, the counter will increment only once whenever a 175condition becomes true, irrespective of the number of clocks during 176which the condition remains true. 177.It Li inv 178Invert the sense of comparison when the 179.Dq Li cmask 180qualifier is present, making the counter increment when the number of 181events per cycle is less than the value specified by the 182.Dq Li cmask 183qualifier. 184.It Li os 185Configure the PMC to count events happening at processor privilege 186level 0. 187.It Li usr 188Configure the PMC to count events occurring at privilege levels 1, 2 189or 3. 190.El 191.Pp 192If neither of the 193.Dq Li os 194or 195.Dq Li usr 196qualifiers are specified, the default is to enable both. 197.Ss Event Specifiers (Programmable PMCs) 198Ivy Bridge programmable PMCs support the following events: 199.Bl -tag -width indent 200.It Li LD_BLOCKS.STORE_FORWARD 201.Pq Event 03H , Umask 02H 202loads blocked by overlapping with store buffer that cannot be forwarded . 203.It Li MISALIGN_MEM_REF.LOADS 204.Pq Event 05H , Umask 01H 205Speculative cache-line split load uops dispatched to L1D. 206.It Li MISALIGN_MEM_REF.STORES 207.Pq Event 05H , Umask 02H 208Speculative cache-line split Store- address uops dispatched to L1D. 209.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 210.Pq Event 07H , Umask 01H 211False dependencies in MOB due to partial compare on address. 212.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK 213.Pq Event 08H , Umask 81H 214Misses in all TLB levels that cause a page walk of any page size from demand loads. 215.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED 216.Pq Event 08H , Umask 82H 217Misses in all TLB levels that caused page walk completed of any size by demand loads. 218.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION 219.Pq Event 08H , Umask 84H 220Cycle PMH is busy with a walk due to demand loads. 221.It Li UOPS_ISSUED.ANY 222.Pq Event 0EH , Umask 01H 223Increments each cycle the # of Uops issued by the RAT to RS. 224Set Cmask = 1, Inv = 1to count stalled cycles. 225Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. 226.It Li UOPS_ISSUED.FLAGS_MERGE 227.Pq Event 0EH , Umask 10H 228Number of flags-merge uops allocated. 229Such uops adds delay. 230.It Li UOPS_ISSUED.SLOW_LEA 231.Pq Event 0EH , Umask 20H 232Number of slow LEA or similar uops allocated. 233Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. 234.It Li UOPS_ISSUED.SINGLE_MUL 235.Pq Event 0EH , Umask 40H 236Number of multiply packed/scalar single precision uops allocated. 237.It Li ARITH.FPU_DIV_ACTIVE 238.Pq Event 14H , Umask 01H 239Cycles that the divider is active, includes INT and FP. 240Set 'edge =1, cmask=1' to count the number of divides. 241.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 242.Pq Event 24H , Umask 01H 243Demand Data Read requests that hit L2 cache. 244.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 245.Pq Event 24H , Umask 03H 246Counts any demand and L1 HW prefetch data load requests to L2. 247.It Li L2_RQSTS.RFO_HITS 248.Pq Event 24H , Umask 04H 249Counts the number of store RFO requests that hit the L2 cache. 250.It Li L2_RQSTS.RFO_MISS 251.Pq Event 24H , Umask 08H 252Counts the number of store RFO requests that miss the L2 cache. 253.It Li L2_RQSTS.ALL_RFO 254.Pq Event 24H , Umask 0CH 255Counts all L2 store RFO requests. 256.It Li L2_RQSTS.CODE_RD_HIT 257.Pq Event 24H , Umask 10H 258Number of instruction fetches that hit the L2 cache. 259.It Li L2_RQSTS.CODE_RD_MISS 260.Pq Event 24H , Umask 20H 261Number of instruction fetches that missed the L2 cache. 262.It Li L2_RQSTS.ALL_CODE_RD 263.Pq Event 24H , Umask 30H 264Counts all L2 code requests. 265.It Li L2_RQSTS.PF_HIT 266.Pq Event 24H , Umask 40H 267Counts all L2 HW prefetcher requests that hit L2. 268.It Li L2_RQSTS.PF_MISS 269.Pq Event 24H , Umask 80H 270Counts all L2 HW prefetcher requests that missed L2. 271.It Li L2_RQSTS.ALL_PF 272.Pq Event 24H , Umask C0H 273Counts all L2 HW prefetcher requests. 274.It Li L2_STORE_LOCK_RQSTS.MISS 275.Pq Event 27H , Umask 01H 276RFOs that miss cache lines. 277.It Li L2_STORE_LOCK_RQSTS.HIT_M 278.Pq Event 27H , Umask 08H 279RFOs that hit cache lines in M state. 280.It Li L2_STORE_LOCK_RQSTS.ALL 281.Pq Event 27H , Umask 0FH 282RFOs that access cache lines in any state. 283.It Li L2_L1D_WB_RQSTS.MISS 284.Pq Event 28H , Umask 01H 285Not rejected writebacks that missed LLC. 286.It Li L2_L1D_WB_RQSTS.HIT_E 287.Pq Event 28H , Umask 04H 288Not rejected writebacks from L1D to L2 cache lines in E state. 289.It Li L2_L1D_WB_RQSTS.HIT_M 290.Pq Event 28H , Umask 08H 291Not rejected writebacks from L1D to L2 cache lines in M state. 292.It Li L2_L1D_WB_RQSTS.ALL 293.Pq Event 28H , Umask 0FH 294Not rejected writebacks from L1D to L2 cache lines in any state. 295.It Li LONGEST_LAT_CACHE.REFERENCE 296.Pq Event 2EH , Umask 4FH 297This event counts requests originating from the core that reference a cache 298line in the last level cache. 299.It Li LONGEST_LAT_CACHE.MISS 300.Pq Event 2EH , Umask 41H 301This event counts each cache miss condition for references to the last level 302cache. 303.It Li CPU_CLK_UNHALTED.THREAD_P 304.Pq Event 3CH , Umask 00H 305Counts the number of thread cycles while the thread is not in a halt state. 306The thread enters the halt state when it is running the HLT instruction. 307The core frequency may change from time to time due to power or thermal throttling. 308.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 309.Pq Event 3CH , Umask 01H 310Increments at the frequency of XCLK (100 MHz) when not halted. 311.It Li L1D_PEND_MISS.PENDING 312.Pq Event 48H , Umask 01H 313Increments the number of outstanding L1D misses every cycle. 314Set Cmaks = 1 and Edge =1 to count occurrences. 315Counter 2 only. 316Set Cmask = 1 to count cycles. 317.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 318.Pq Event 49H , Umask 01H 319Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). 320.It Li DTLB_STORE_MISSES.WALK_COMPLETED 321.Pq Event 49H , Umask 02H 322Miss in all TLB levels causes a page walk that completes of any page size 323(4K/2M/4M/1G). 324.It Li DTLB_STORE_MISSES.WALK_DURATION 325.Pq Event 49H , Umask 04H 326Cycles PMH is busy with this walk. 327.It Li DTLB_STORE_MISSES.STLB_HIT 328.Pq Event 49H , Umask 10H 329Store operations that miss the first TLB level but hit the second and do not 330cause page walks. 331.It Li LOAD_HIT_PRE.SW_PF 332.Pq Event 4CH , Umask 01H 333Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. 334.It Li LOAD_HIT_PRE.HW_PF 335.Pq Event 4CH , Umask 02H 336Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. 337.It Li L1D.REPLACEMENT 338.Pq Event 51H , Umask 01H 339Counts the number of lines brought into the L1 data cache. 340.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 341.Pq Event 58H , Umask 01H 342Number of integer Move Elimination candidate uops that were not eliminated. 343.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED 344.Pq Event 58H , Umask 02H 345Number of SIMD Move Elimination candidate uops that were not eliminated. 346.It Li MOVE_ELIMINATION.INT_ELIMINATED 347.Pq Event 58H , Umask 04H 348Number of integer Move Elimination candidate uops that were eliminated. 349.It Li MOVE_ELIMINATION.SIMD_ELIMINATED 350.Pq Event 58H , Umask 08H 351Number of SIMD Move Elimination candidate uops that were eliminated. 352.It Li CPL_CYCLES.RING0 353.Pq Event 5CH , Umask 01H 354Unhalted core cycles when the thread is in ring 0. 355Use Edge to count transition. 356.It Li CPL_CYCLES.RING123 357.Pq Event 5CH , Umask 02H 358Unhalted core cycles when the thread is not in ring 0. 359.It Li RS_EVENTS.EMPTY_CYCLES 360.Pq Event 5EH , Umask 01H 361Cycles the RS is empty for the thread. 362.It Li DTLB_LOAD_MISSES.STLB_HIT 363.Pq Event 5FH , Umask 04H 364Counts load operations that missed 1st level DTLB but hit the 2nd level. 365.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 366.Pq Event 60H , Umask 01H 367Offcore outstanding Demand Data Read transactions in SQ to uncore. 368Set Cmask=1 to count cycles. 369.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD 370.Pq Event 60H , Umask 02H 371Offcore outstanding Demand Code Read transactions in SQ to uncore. 372Set Cmask=1 to count cycles. 373.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 374.Pq Event 60H , Umask 04H 375Offcore outstanding RFO store transactions in SQ to uncore. 376Set Cmask=1 to count cycles. 377.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 378.Pq Event 60H , Umask 08H 379Offcore outstanding cacheable data read transactions in SQ to uncore. 380Set Cmask=1 to count cycles. 381.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 382.Pq Event 63H , Umask 01H 383Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 384.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 385.Pq Event 63H , Umask 02H 386Cycles in which the L1D is locked. 387.It Li IDQ.EMPTY 388.Pq Event 79H , Umask 02H 389Counts cycles the IDQ is empty. 390.It Li IDQ.MITE_UOPS 391.Pq Event 79H , Umask 04H 392Increment each cycle # of uops delivered to IDQ from MITE path. 393Can combine Umask 04H and 20H. 394Set Cmask = 1 to count cycles. 395.It Li IDQ.DSB_UOPS 396.Pq Event 79H , Umask 08H 397Increment each cycle. # of uops delivered to IDQ from DSB path. 398Can combine Umask 08H and 10H 399Set Cmask = 1 to count cycles. 400.It Li IDQ.MS_DSB_UOPS 401.Pq Event 79H , Umask 10H 402Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. 403Set Cmask = 1 to count cycles. 404Add Edge=1 to count # of delivery. 405Can combine Umask 04H, 08H. 406.It Li IDQ.MS_MITE_UOPS 407.Pq Event 79H , Umask 20H 408Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. 409Set Cmask = 1 to count cycles. 410Can combine Umask 04H, 08H. 411.It Li IDQ.MS_UOPS 412.Pq Event 79H , Umask 30H 413Increment each cycle # of uops delivered to IDQ from MS by either DSB or 414MITE. 415Set Cmask = 1 to count cycles. 416Can combine Umask 04H, 08H. 417.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 418.Pq Event 79H , Umask 18H 419Counts cycles DSB is delivered at least one uops. 420Set Cmask = 1. 421.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 422.Pq Event 79H , Umask 18H 423Counts cycles DSB is delivered four uops. 424Set Cmask = 4. 425.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 426.Pq Event 79H , Umask 24H 427Counts cycles MITE is delivered at least one uops. 428Set Cmask = 1. 429.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 430.Pq Event 79H , Umask 24H 431Counts cycles MITE is delivered four uops. 432Set Cmask = 4. 433.It Li IDQ.MITE_ALL_UOPS 434.Pq Event 79H , Umask 3CH 435# of uops delivered to IDQ from any path. 436.It Li ICACHE.MISSES 437.Pq Event 80H , Umask 02H 438Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 439Includes UC accesses. 440.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 441.Pq Event 85H , Umask 01H 442Misses in all ITLB levels that cause page walks. 443.It Li ITLB_MISSES.WALK_COMPLETED 444.Pq Event 85H , Umask 02H 445Misses in all ITLB levels that cause completed page walks. 446.It Li ITLB_MISSES.WALK_DURATION 447.Pq Event 85H , Umask 04H 448Cycle PMH is busy with a walk. 449.It Li ITLB_MISSES.STLB_HIT 450.Pq Event 85H , Umask 10H 451Number of cache load STLB hits. 452No page walk. 453.It Li ILD_STALL.LCP 454.Pq Event 87H , Umask 01H 455Stalls caused by changing prefix length of the instruction. 456.It Li ILD_STALL.IQ_FULL 457.Pq Event 87H , Umask 04H 458Stall cycles due to IQ is full. 459.It Li BR_INST_EXEC.NONTAKEN_COND 460.Pq Event 88H , Umask 41H 461Count conditional near branch instructions that were executed (but not 462necessarily retired) and not taken. 463.It Li BR_INST_EXEC.TAKEN_COND 464.Pq Event 88H , Umask 81H 465Count conditional near branch instructions that were executed (but not 466necessarily retired) and taken. 467.It Li BR_INST_EXEC.DIRECT_JMP 468.Pq Event 88H , Umask 82H 469Count all unconditional near branch instructions excluding calls and 470indirect branches. 471.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 472.Pq Event 88H , Umask 84H 473Count executed indirect near branch instructions that are not calls nor 474returns. 475.It Li BR_INST_EXEC.RETURN_NEAR 476.Pq Event 88H , Umask 88H 477Count indirect near branches that have a return mnemonic. 478.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 479.Pq Event 88H , Umask 90H 480Count unconditional near call branch instructions, excluding non call 481branch, executed. 482.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 483.Pq Event 88H , Umask A0H 484Count indirect near calls, including both register and memory indirect, 485executed. 486.It Li BR_INST_EXEC.ALL_BRANCHES 487.Pq Event 88H , Umask FFH 488Counts all near executed branches (not necessarily retired). 489.It Li BR_MISP_EXEC.NONTAKEN_COND 490.Pq Event 89H , Umask 41H 491Count conditional near branch instructions mispredicted as nontaken. 492.It Li BR_MISP_EXEC.TAKEN_COND 493.Pq Event 89H , Umask 81H 494Count conditional near branch instructions mispredicted as taken. 495.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 496.Pq Event 89H , Umask 84H 497Count mispredicted indirect near branch instructions that are not calls 498nor returns. 499.It Li BR_MISP_EXEC.RETURN_NEAR 500.Pq Event 89H , Umask 88H 501Count mispredicted indirect near branches that have a return mnemonic. 502.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 503.Pq Event 89H , Umask 90H 504Count mispredicted unconditional near call branch instructions, excluding 505non call branch, executed. 506.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 507.Pq Event 89H , Umask A0H 508Count mispredicted indirect near calls, including both register and memory 509indirect, executed. 510.It Li BR_MISP_EXEC.ALL_BRANCHES 511.Pq Event 89H , Umask FFH 512Counts all mispredicted near executed branches (not necessarily retired). 513.It Li IDQ_UOPS_NOT_DELIVERED.CORE 514.Pq Event 9CH , Umask 01H 515Count number of non-delivered uops to RAT per thread. 516Use Cmask to qualify uop b/w. 517.It Li UOPS_DISPATCHED_PORT.PORT_0 518.Pq Event A1H , Umask 01H 519Cycles which a Uop is dispatched on port 0. 520.It Li UOPS_DISPATCHED_PORT.PORT_1 521.Pq Event A1H , Umask 02H 522Cycles which a Uop is dispatched on port 1. 523.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 524.Pq Event A1H , Umask 04H 525Cycles which a load uop is dispatched on port 2. 526.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 527.Pq Event A1H , Umask 08H 528Cycles which a store address uop is dispatched on port 2. 529.It Li UOPS_DISPATCHED_PORT.PORT_2 530.Pq Event A1H , Umask 0CH 531Cycles which a Uop is dispatched on port 2. 532.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 533.Pq Event A1H , Umask 10H 534Cycles which a load uop is dispatched on port 3. 535.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 536.Pq Event A1H , Umask 20H 537Cycles which a store address uop is dispatched on port 3. 538.It Li UOPS_DISPATCHED_PORT.PORT_3 539.Pq Event A1H , Umask 30H 540Cycles which a Uop is dispatched on port 3. 541.It Li UOPS_DISPATCHED_PORT.PORT_4 542.Pq Event A1H , Umask 40H 543Cycles which a Uop is dispatched on port 4. 544.It Li UOPS_DISPATCHED_PORT.PORT_5 545.Pq Event A1H , Umask 80H 546Cycles which a Uop is dispatched on port 5. 547.It Li RESOURCE_STALLS.ANY 548.Pq Event A2H , Umask 01H 549Cycles Allocation is stalled due to Resource Related reason. 550.It Li RESOURCE_STALLS.RS 551.Pq Event A2H , Umask 04H 552Cycles stalled due to no eligible RS entry available. 553.It Li RESOURCE_STALLS.SB 554.Pq Event A2H , Umask 08H 555Cycles stalled due to no store buffers available. (not including draining 556form sync). 557.It Li RESOURCE_STALLS.ROB 558.Pq Event A2H , Umask 10H 559Cycles stalled due to re-order buffer full. 560.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 561.Pq Event A3H , Umask 01H 562Cycles with pending L2 miss loads. 563Set AnyThread to count per core. 564.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING 565.Pq Event A3H , Umask 02H 566Cycles with pending memory loads. 567Set AnyThread to count per core. 568.It Li CYCLE_ACTIVITY.CYCLES_NO_EXECUTE 569.Pq Event A3H , Umask 04H 570Cycles of dispatch stalls. 571Set AnyThread to count per core. 572.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 573.Pq Event A3H , Umask 08H 574Cycles with pending L1 cache miss loads. 575Set AnyThread to count per core. 576.It Li DSB2MITE_SWITCHES.COUNT 577.Pq Event ABH , Umask 01H 578Number of DSB to MITE switches. 579.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 580.Pq Event ABH , Umask 02H 581Cycles DSB to MITE switches caused delay. 582.It Li DSB_FILL.EXCEED_DSB_LINES 583.Pq Event ACH , Umask 08H 584DSB Fill encountered > 3 DSB lines. 585.It Li ITLB.ITLB_FLUSH 586.Pq Event AEH , Umask 01H 587Counts the number of ITLB flushes, includes 4k/2M/4M pages. 588.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 589.Pq Event B0H , Umask 01H 590Demand data read requests sent to uncore. 591.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 592.Pq Event B0H , Umask 02H 593Demand code read requests sent to uncore. 594.It Li OFFCORE_REQUESTS.DEMAND_RFO 595.Pq Event B0H , Umask 04H 596Demand RFO read requests sent to uncore, including regular RFOs, locks, 597ItoM. 598.It Li OFFCORE_REQUESTS.ALL_DATA_RD 599.Pq Event B0H , Umask 08H 600Data read requests sent to uncore (demand and prefetch). 601.It Li UOPS_EXECUTED.THREAD 602.Pq Event B1H , Umask 01H 603Counts total number of uops to be executed per-thread each cycle. 604Set Cmask = 1, INV =1 to count stall cycles. 605.It Li UOPS_EXECUTED.CORE 606.Pq Event B1H , Umask 02H 607Counts total number of uops to be executed per-core each cycle. 608Do not need to set ANY. 609.It Li OFF_CORE_RESPONSE_0 610.Pq Event B7H , Umask 01H 611Off-core Response Performance Monitoring. 612PMC0 only. 613Requires programming MSR 01A6H. 614.It Li OFF_CORE_RESPONSE_1 615.Pq Event BBH , Umask 01H 616Off-core Response Performance Monitoring. 617PMC3 only. 618Requires programming MSR 01A7H. 619.It Li TLB_FLUSH.DTLB_THREAD 620.Pq Event BDH , Umask 01H 621DTLB flush attempts of the thread- specific entries. 622.It Li TLB_FLUSH.STLB_ANY 623.Pq Event BDH , Umask 20H 624Count number of STLB flush attempts. 625.It Li INST_RETIRED.ANY_P 626.Pq Event C0H , Umask 00H 627Number of instructions at retirement. 628.It Li INST_RETIRED.ALL 629.Pq Event C0H , Umask 01H 630Precise instruction retired event with HW to reduce effect of PEBS shadow in 631IP distribution. 632PMC1 only. 633Must quiesce other PMCs. 634.It Li OTHER_ASSISTS.AVX_STORE 635.Pq Event C1H , Umask 08H 636Number of assists associated with 256-bit AVX store operations. 637.It Li OTHER_ASSISTS.AVX_TO_SSE 638.Pq Event C1H , Umask 10H 639Number of transitions from AVX- 256 to legacy SSE when penalty applicable. 640.It Li OTHER_ASSISTS.SSE_TO_AVX 641.Pq Event C1H , Umask 20H 642Number of transitions from SSE to AVX-256 when penalty applicable. 643.It Li UOPS_RETIRED.ALL 644.Pq Event C2H , Umask 01H 645Counts the number of micro-ops retired, Use cmask=1 and invert to count 646active cycles or stalled cycles. 647Supports PEBS, use Any=1 for core granular. 648.It Li UOPS_RETIRED.RETIRE_SLOTS 649.Pq Event C2H , Umask 02H 650Counts the number of retirement slots used each cycle. 651.It Li MACHINE_CLEARS.MEMORY_ORDERING 652.Pq Event C3H , Umask 02H 653Counts the number of machine clears due to memory order conflicts. 654.It Li MACHINE_CLEARS.SMC 655.Pq Event C3H , Umask 04H 656Number of self-modifying-code machine clears detected. 657.It Li MACHINE_CLEARS.MASKMOV 658.Pq Event C3H , Umask 20H 659Counts the number of executed AVX masked load operations that refer to an 660illegal address range with the mask bits set to 0. 661.It Li BR_INST_RETIRED.ALL_BRANCHES 662.Pq Event C4H , Umask 00H 663Branch instructions at retirement. 664.It Li BR_INST_RETIRED.CONDITIONAL 665.Pq Event C4H , Umask 01H 666Counts the number of conditional branch instructions retired. 667Supports PEBS. 668.It Li BR_INST_RETIRED.NEAR_CALL 669.Pq Event C4H , Umask 02H 670Direct and indirect near call instructions retired. 671.It Li BR_INST_RETIRED.ALL_BRANCHES 672.Pq Event C4H , Umask 04H 673Counts the number of branch instructions retired. 674.It Li BR_INST_RETIRED.NEAR_RETURN 675.Pq Event C4H , Umask 08H 676Counts the number of near return instructions retired. 677.It Li BR_INST_RETIRED.NOT_TAKEN 678.Pq Event C4H , Umask 10H 679Counts the number of not taken branch instructions retired. 680.It Li BR_INST_RETIRED.NEAR_TAKEN 681.Pq Event C4H , Umask 20H 682Number of near taken branches retired. 683.It Li BR_INST_RETIRED.FAR_BRANCH 684.Pq Event C4H , Umask 40H 685Number of far branches retired. 686.It Li BR_MISP_RETIRED.ALL_BRANCHES 687.Pq Event C5H , Umask 00H 688Mispredicted branch instructions at retirement. 689.It Li BR_MISP_RETIRED.CONDITIONAL 690.Pq Event C5H , Umask 01H 691Mispredicted conditional branch instructions retired. 692Supports PEBS. 693.It Li BR_MISP_RETIRED.NEAR_CALL 694.Pq Event C5H , Umask 02H 695Direct and indirect mispredicted near call instructions retired. 696.It Li BR_MISP_RETIRED.ALL_BRANCHES 697.Pq Event C5H , Umask 04H 698Mispredicted macro branch instructions retired. 699.It Li BR_MISP_RETIRED.NOT_TAKEN 700.Pq Event C5H , Umask 10H 701Mispredicted not taken branch instructions retired. 702.It Li BR_MISP_RETIRED.TAKEN 703.Pq Event C5H , Umask 20H 704Mispredicted taken branch instructions retired. 705.It Li FP_ASSIST.X87_OUTPUT 706.Pq Event CAH , Umask 02H 707Number of X87 FP assists due to Output values. 708.It Li FP_ASSIST.X87_INPUT 709.Pq Event CAH , Umask 04H 710Number of X87 FP assists due to input values. 711.It Li FP_ASSIST.SIMD_OUTPUT 712.Pq Event CAH , Umask 08H 713Number of SIMD FP assists due to Output values. 714.It Li FP_ASSIST.SIMD_INPUT 715.Pq Event CAH , Umask 10H 716Number of SIMD FP assists due to input values. 717.It Li FP_ASSIST.ANY 718.Pq Event CAH , Umask 1EH 719Cycles with any input/output SSE* or FP assists. 720.It Li ROB_MISC_EVENTS.LBR_INSERTS 721.Pq Event CCH , Umask 20H 722Count cases of saving new LBR records by hardware. 723.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 724.Pq Event CDH , Umask 01H 725Sample loads with specified latency threshold. 726PMC3 only. 727Specify threshold in MSR 0x3F6. 728.It Li MEM_TRANS_RETIRED.PRECISE_STORE 729.Pq Event CDH , Umask 02H 730Sample stores and collect precise store operation via PEBS record. 731PMC3 only. 732.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS 733.Pq Event D0H , Umask 11H 734Count retired load uops that missed the STLB. 735.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES 736.Pq Event D0H , Umask 12H 737Count retired store uops that missed the STLB. 738.It Li MEM_UOPS_RETIRED.SPLIT_LOADS 739.Pq Event D0H , Umask 41H 740Count retired load uops that were split across a cache line. 741.It Li MEM_UOPS_RETIRED.SPLIT_STORES 742.Pq Event D0H , Umask 42H 743Count retired store uops that were split across a cache line. 744.It Li MEM_UOPS_RETIRED.ALL_LOADS 745.Pq Event D0H , Umask 81H 746Count all retired load uops. 747.It Li MEM_UOPS_RETIRED.ALL_STORES 748.Pq Event D0H , Umask 82H 749Count all retired store uops. 750.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 751.Pq Event D1H , Umask 01H 752Retired load uops with L1 cache hits as data sources. 753Supports PEBS. 754.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 755.Pq Event D1H , Umask 02H 756Retired load uops with L2 cache hits as data sources. 757.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 758.Pq Event D1H , Umask 04H 759Retired load uops whose data source was LLC hit with no snoop required. 760.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS 761.Pq Event D1H , Umask 20H 762Retired load uops whose data source is LLC miss. 763.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 764.Pq Event D1H , Umask 40H 765Retired load uops which data sources were load uops missed L1 but hit FB due 766to preceding miss to the same cache line with data not ready. 767.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 768.Pq Event D2H , Umask 01H 769Retired load uops which data sources were LLC hit and cross-core snoop 770missed in on-pkg core cache. 771Supports PEBS. 772.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 773.Pq Event D2H , Umask 02H 774Retired load uops which data sources were LLC and cross-core snoop hits in 775on-pkg core cache. 776Supports PEBS. 777.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 778.Pq Event D2H , Umask 04H 779Retired load uops which data sources were HitM responses from shared LLC. 780.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 781.Pq Event D2H , Umask 08H 782Retired load uops which data sources were hits in LLC without snoops 783required. 784.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 785.Pq Event D3H , Umask 01H 786Retired load uops which data sources missed LLC but serviced from local 787dram. 788Supports PEBS. 789.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM 790.Pq Event D3H , Umask 04H 791Retired load uops whose data source was remote DRAM. 792.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM 793.Pq Event D3H , Umask 10H 794Retired load uops whose data source was remote HITM. 795.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD 796.Pq Event D3H , Umask 20H 797Retired load uops whose data source was forwards from a remote cache. 798.It Li BACLEARS.ANY 799.Pq Event E6H , Umask 1FH 800Number of front end re-steers due to BPU misprediction. 801.It Li L2_TRANS.DEMAND_DATA_RD 802.Pq Event F0H , Umask 01H 803Demand Data Read requests that access L2 cache. 804.It Li L2_TRANS.RFO 805.Pq Event F0H , Umask 02H 806RFO requests that access L2 cache. 807.It Li L2_TRANS.CODE_RD 808.Pq Event F0H , Umask 04H 809L2 cache accesses when fetching instructions. 810.It Li L2_TRANS.ALL_PF 811.Pq Event F0H , Umask 08H 812Any MLC or LLC HW prefetch accessing L2, including rejects. 813.It Li L2_TRANS.L1D_WB 814.Pq Event F0H , Umask 10H 815L1D writebacks that access L2 cache. 816.It Li L2_TRANS.L2_FILL 817.Pq Event F0H , Umask 20H 818L2 fill requests that access L2 cache. 819.It Li L2_TRANS.L2_WB 820.Pq Event F0H , Umask 40H 821L2 writebacks that access L2 cache. 822.It Li L2_TRANS.ALL_REQUESTS 823.Pq Event F0H , Umask 80H 824Transactions accessing L2 pipe. 825.It Li L2_LINES_IN.I 826.Pq Event F1H , Umask 01H 827L2 cache lines in I state filling L2. 828Counting does not cover rejects. 829.It Li L2_LINES_IN.S 830.Pq Event F1H , Umask 02H 831L2 cache lines in S state filling L2. 832Counting does not cover rejects. 833.It Li L2_LINES_IN.E 834.Pq Event F1H , Umask 04H 835L2 cache lines in E state filling L2. 836Counting does not cover rejects. 837.It Li L2_LINES_IN.ALL 838.Pq Event F1H , Umask 07H 839L2 cache lines filling L2. 840Counting does not cover rejects. 841.It Li L2_LINES_OUT.DEMAND_CLEAN 842.Pq Event F2H , Umask 01H 843Clean L2 cache lines evicted by demand. 844.It Li L2_LINES_OUT.DEMAND_DIRTY 845.Pq Event F2H , Umask 02H 846Dirty L2 cache lines evicted by demand. 847.It Li L2_LINES_OUT.PF_CLEAN 848.Pq Event F2H , Umask 04H 849Clean L2 cache lines evicted by the MLC prefetcher. 850.It Li L2_LINES_OUT.PF_DIRTY 851.Pq Event F2H , Umask 08H 852Dirty L2 cache lines evicted by the MLC prefetcher. 853.It Li L2_LINES_OUT.DIRTY_ALL 854.Pq Event F2H , Umask 0AH 855Dirty L2 cache lines filling the L2. 856.El 857.Sh SEE ALSO 858.Xr pmc 3 , 859.Xr pmc.amd 3 , 860.Xr pmc.atom 3 , 861.Xr pmc.core 3 , 862.Xr pmc.corei7 3 , 863.Xr pmc.corei7uc 3 , 864.Xr pmc.iaf 3 , 865.Xr pmc.ivybridge 3 , 866.Xr pmc.sandybridge 3 , 867.Xr pmc.sandybridgeuc 3 , 868.Xr pmc.sandybridgexeon 3 , 869.Xr pmc.soft 3 , 870.Xr pmc.tsc 3 , 871.Xr pmc.ucf 3 , 872.Xr pmc.westmere 3 , 873.Xr pmc.westmereuc 3 , 874.Xr pmc_cpuinfo 3 , 875.Xr pmclog 3 , 876.Xr hwpmc 4 877.Sh HISTORY 878The 879.Nm pmc 880library first appeared in 881.Fx 6.0 . 882.Sh AUTHORS 883.An -nosplit 884The 885.Lb libpmc 886library was written by 887.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 888The support for the Ivy Bridge Xeon 889microarchitecture was written by 890.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 891