1.\" Copyright (c) 2012 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd October 19, 2012 25.Dt PMC.IVYBRIDGE 3 26.Os 27.Sh NAME 28.Nm pmc.ivybridge 29.Nd measurement events for 30.Tn Intel 31.Tn Ivy Bridge 32family CPUs 33.Sh LIBRARY 34.Lb libpmc 35.Sh SYNOPSIS 36.In pmc.h 37.Sh DESCRIPTION 38.Tn Intel 39.Tn "Ivy Bridge" 40CPUs contain PMCs conforming to version 2 of the 41.Tn Intel 42performance measurement architecture. 43These CPUs may contain up to three classes of PMCs: 44.Bl -tag -width "Li PMC_CLASS_IAP" 45.It Li PMC_CLASS_IAF 46Fixed-function counters that count only one hardware event per counter. 47.It Li PMC_CLASS_IAP 48Programmable counters that may be configured to count one of a defined 49set of hardware events. 50.El 51.Pp 52The number of PMCs available in each class and their widths need to be 53determined at run time by calling 54.Xr pmc_cpuinfo 3 . 55.Pp 56Intel Ivy Bridge PMCs are documented in 57.Rs 58.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 59.%T "Volume 3B: System Programming Guide, Part 2" 60.%N "Order Number: 253669-043US" 61.%D May 2012 62.%Q "Intel Corporation" 63.Re 64.Ss IVYBRIDGE FIXED FUNCTION PMCS 65These PMCs and their supported events are documented in 66.Xr pmc.iaf 3 . 67.Ss IVYBRIDGE PROGRAMMABLE PMCS 68The programmable PMCs support the following capabilities: 69.Bl -column "PMC_CAP_INTERRUPT" "Support" 70.It Em Capability Ta Em Support 71.It PMC_CAP_CASCADE Ta \&No 72.It PMC_CAP_EDGE Ta Yes 73.It PMC_CAP_INTERRUPT Ta Yes 74.It PMC_CAP_INVERT Ta Yes 75.It PMC_CAP_READ Ta Yes 76.It PMC_CAP_PRECISE Ta \&No 77.It PMC_CAP_SYSTEM Ta Yes 78.It PMC_CAP_TAGGING Ta \&No 79.It PMC_CAP_THRESHOLD Ta Yes 80.It PMC_CAP_USER Ta Yes 81.It PMC_CAP_WRITE Ta Yes 82.El 83.Ss Event Qualifiers 84Event specifiers for these PMCs support the following common 85qualifiers: 86.Bl -tag -width indent 87.It Li rsp= Ns Ar value 88Configure the Off-core Response bits. 89.Bl -tag -width indent 90.It Li REQ_DMND_DATA_RD 91Counts the number of demand and DCU prefetch data reads of full and partial 92cachelines as well as demand data page table entry cacheline reads. 93Does not count L2 data read prefetches or instruction fetches. 94.It Li REQ_DMND_RFO 95Counts the number of demand and DCU prefetch reads for ownership (RFO) 96requests generated by a write to data cacheline. 97Does not count L2 RFO prefetches. 98.It Li REQ_DMND_IFETCH 99Counts the number of demand and DCU prefetch instruction cacheline reads. 100Does not count L2 code read prefetches. 101.It Li REQ_WB 102Counts the number of writeback (modified to exclusive) transactions. 103.It Li REQ_PF_DATA_RD 104Counts the number of data cacheline reads generated by L2 prefetchers. 105.It Li REQ_PF_RFO 106Counts the number of RFO requests generated by L2 prefetchers. 107.It Li REQ_PF_IFETCH 108Counts the number of code reads generated by L2 prefetchers. 109.It Li REQ_PF_LLC_DATA_RD 110L2 prefetcher to L3 for loads. 111.It Li REQ_PF_LLC_RFO 112RFO requests generated by L2 prefetcher 113.It Li REQ_PF_LLC_IFETCH 114L2 prefetcher to L3 for instruction fetches. 115.It Li REQ_BUS_LOCKS 116Bus lock and split lock requests. 117.It Li REQ_STRM_ST 118Streaming store requests. 119.It Li REQ_OTHER 120Any other request that crosses IDI, including I/O. 121.It Li RES_ANY 122Catch all value for any response types. 123.It Li RES_SUPPLIER_NO_SUPP 124No Supplier Information available. 125.It Li RES_SUPPLIER_LLC_HITM 126M-state initial lookup stat in L3. 127.It Li RES_SUPPLIER_LLC_HITE 128E-state. 129.It Li RES_SUPPLIER_LLC_HITS 130S-state. 131.It Li RES_SUPPLIER_LLC_HITF 132F-state. 133.It Li RES_SUPPLIER_LOCAL 134Local DRAM Controller. 135.It Li RES_SNOOP_SNP_NONE 136No details on snoop-related information. 137.It Li RES_SNOOP_SNP_NO_NEEDED 138No snoop was needed to satisfy the request. 139.It Li RES_SNOOP_SNP_MISS 140A snoop was needed and it missed all snooped caches: 141-For LLC Hit, ReslHitl was returned by all cores 142-For LLC Miss, Rspl was returned by all sockets and data was returned from 143DRAM. 144.It Li RES_SNOOP_HIT_NO_FWD 145A snoop was needed and it hits in at least one snooped cache. 146Hit denotes a cache-line was valid before snoop effect. 147This includes: 148-Snoop Hit w/ Invalidation (LLC Hit, RFO) 149-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 150-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 151In the LLC Miss case, data is returned from DRAM. 152.It Li RES_SNOOP_HIT_FWD 153A snoop was needed and data was forwarded from a remote socket. 154This includes: 155-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 156.It Li RES_SNOOP_HITM 157A snoop was needed and it HitM-ed in local or remote cache. 158HitM denotes a cache-line was in modified state before effect as a results of snoop. 159This includes: 160-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 161-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 162-Snoop MtoS (LLC Hit, IFetch/Data_RD). 163.It Li RES_NON_DRAM 164Target was non-DRAM system address. 165This includes MMIO transactions. 166.El 167.It Li cmask= Ns Ar value 168Configure the PMC to increment only if the number of configured 169events measured in a cycle is greater than or equal to 170.Ar value . 171.It Li edge 172Configure the PMC to count the number of de-asserted to asserted 173transitions of the conditions expressed by the other qualifiers. 174If specified, the counter will increment only once whenever a 175condition becomes true, irrespective of the number of clocks during 176which the condition remains true. 177.It Li inv 178Invert the sense of comparison when the 179.Dq Li cmask 180qualifier is present, making the counter increment when the number of 181events per cycle is less than the value specified by the 182.Dq Li cmask 183qualifier. 184.It Li os 185Configure the PMC to count events happening at processor privilege 186level 0. 187.It Li usr 188Configure the PMC to count events occurring at privilege levels 1, 2 189or 3. 190.El 191.Pp 192If neither of the 193.Dq Li os 194or 195.Dq Li usr 196qualifiers are specified, the default is to enable both. 197.Ss Event Specifiers (Programmable PMCs) 198Ivy Bridge programmable PMCs support the following events: 199.Bl -tag -width indent 200.It Li LD_BLOCKS.STORE_FORWARD 201.Pq Event 03H , Umask 02H 202loads blocked by overlapping with store buffer that cannot be forwarded . 203.It Li MISALIGN_MEM_REF.LOADS 204.Pq Event 05H , Umask 01H 205Speculative cache-line split load uops dispatched to L1D. 206.It Li MISALIGN_MEM_REF.STORES 207.Pq Event 05H , Umask 02H 208Speculative cache-line split Store- address uops dispatched to L1D. 209.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 210.Pq Event 07H , Umask 01H 211False dependencies in MOB due to partial compare on address. 212.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK 213.Pq Event 08H , Umask 81H 214Misses in all TLB levels that cause a page walk of any page size from demand loads. 215.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED 216.Pq Event 08H , Umask 82H 217Misses in all TLB levels that caused page walk completed of any size by demand loads. 218.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION 219.Pq Event 08H , Umask 84H 220Cycle PMH is busy with a walk due to demand loads. 221.It Li UOPS_ISSUED.ANY 222.Pq Event 0EH , Umask 01H 223Increments each cycle the # of Uops issued by the RAT to RS. 224Set Cmask = 1, Inv = 1to count stalled cycles. 225Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. 226.It Li UOPS_ISSUED.FLAGS_MERGE 227.Pq Event 0EH , Umask 10H 228Number of flags-merge uops allocated. 229Such uops adds delay. 230.It Li UOPS_ISSUED.SLOW_LEA 231.Pq Event 0EH , Umask 20H 232Number of slow LEA or similar uops allocated. 233Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. 234.It Li UOPS_ISSUED.SINGLE_MUL 235.Pq Event 0EH , Umask 40H 236Number of multiply packed/scalar single precision uops allocated. 237.It Li ARITH.FPU_DIV_ACTIVE 238.Pq Event 14H , Umask 01H 239Cycles that the divider is active, includes INT and FP. 240Set 'edge =1, cmask=1' to count the number of divides. 241.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 242.Pq Event 24H , Umask 01H 243Demand Data Read requests that hit L2 cache. 244.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 245.Pq Event 24H , Umask 03H 246Counts any demand and L1 HW prefetch data load requests to L2. 247.It Li L2_RQSTS.RFO_HITS 248.Pq Event 24H , Umask 04H 249Counts the number of store RFO requests that hit the L2 cache. 250.It Li L2_RQSTS.RFO_MISS 251.Pq Event 24H , Umask 08H 252Counts the number of store RFO requests that miss the L2 cache. 253.It Li L2_RQSTS.ALL_RFO 254.Pq Event 24H , Umask 0CH 255Counts all L2 store RFO requests. 256.It Li L2_RQSTS.CODE_RD_HIT 257.Pq Event 24H , Umask 10H 258Number of instruction fetches that hit the L2 cache. 259.It Li L2_RQSTS.CODE_RD_MISS 260.Pq Event 24H , Umask 20H 261Number of instruction fetches that missed the L2 cache. 262.It Li L2_RQSTS.ALL_CODE_RD 263.Pq Event 24H , Umask 30H 264Counts all L2 code requests. 265.It Li L2_RQSTS.PF_HIT 266.Pq Event 24H , Umask 40H 267Counts all L2 HW prefetcher requests that hit L2. 268.It Li L2_RQSTS.PF_MISS 269.Pq Event 24H , Umask 80H 270Counts all L2 HW prefetcher requests that missed L2. 271.It Li L2_RQSTS.ALL_PF 272.Pq Event 24H , Umask C0H 273Counts all L2 HW prefetcher requests. 274.It Li L2_STORE_LOCK_RQSTS.MISS 275.Pq Event 27H , Umask 01H 276RFOs that miss cache lines. 277.It Li L2_STORE_LOCK_RQSTS.HIT_M 278.Pq Event 27H , Umask 08H 279RFOs that hit cache lines in M state. 280.It Li L2_STORE_LOCK_RQSTS.ALL 281.Pq Event 27H , Umask 0FH 282RFOs that access cache lines in any state. 283.It Li L2_L1D_WB_RQSTS.MISS 284.Pq Event 28H , Umask 01H 285Not rejected writebacks that missed LLC. 286.It Li L2_L1D_WB_RQSTS.HIT_E 287.Pq Event 28H , Umask 04H 288Not rejected writebacks from L1D to L2 cache lines in E state. 289.It Li L2_L1D_WB_RQSTS.HIT_M 290.Pq Event 28H , Umask 08H 291Not rejected writebacks from L1D to L2 cache lines in M state. 292.It Li L2_L1D_WB_RQSTS.ALL 293.Pq Event 28H , Umask 0FH 294Not rejected writebacks from L1D to L2 cache lines in any state. 295.It Li LONGEST_LAT_CACHE.REFERENCE 296.Pq Event 2EH , Umask 4FH 297This event counts requests originating from the core that reference a cache 298line in the last level cache. 299.It Li LONGEST_LAT_CACHE.MISS 300.Pq Event 2EH , Umask 41H 301This event counts each cache miss condition for references to the last level 302cache. 303.It Li CPU_CLK_UNHALTED.THREAD_P 304.Pq Event 3CH , Umask 00H 305Counts the number of thread cycles while the thread is not in a halt state. 306The thread enters the halt state when it is running the HLT instruction. 307The core frequency may change from time to time due to power or thermal 308throttling. 309.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 310.Pq Event 3CH , Umask 01H 311Increments at the frequency of XCLK (100 MHz) when not halted. 312.It Li L1D_PEND_MISS.PENDING 313.Pq Event 48H , Umask 01H 314Increments the number of outstanding L1D misses every cycle. 315Set Cmaks = 1 and Edge =1 to count occurrences. 316Counter 2 only. 317Set Cmask = 1 to count cycles. 318.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 319.Pq Event 49H , Umask 01H 320Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). 321.It Li DTLB_STORE_MISSES.WALK_COMPLETED 322.Pq Event 49H , Umask 02H 323Miss in all TLB levels causes a page walk that completes of any page size 324(4K/2M/4M/1G). 325.It Li DTLB_STORE_MISSES.WALK_DURATION 326.Pq Event 49H , Umask 04H 327Cycles PMH is busy with this walk. 328.It Li DTLB_STORE_MISSES.STLB_HIT 329.Pq Event 49H , Umask 10H 330Store operations that miss the first TLB level but hit the second and do not 331cause page walks. 332.It Li LOAD_HIT_PRE.SW_PF 333.Pq Event 4CH , Umask 01H 334Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. 335.It Li LOAD_HIT_PRE.HW_PF 336.Pq Event 4CH , Umask 02H 337Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. 338.It Li L1D.REPLACEMENT 339.Pq Event 51H , Umask 01H 340Counts the number of lines brought into the L1 data cache. 341.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 342.Pq Event 58H , Umask 01H 343Number of integer Move Elimination candidate uops that were not eliminated. 344.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED 345.Pq Event 58H , Umask 02H 346Number of SIMD Move Elimination candidate uops that were not eliminated. 347.It Li MOVE_ELIMINATION.INT_ELIMINATED 348.Pq Event 58H , Umask 04H 349Number of integer Move Elimination candidate uops that were eliminated. 350.It Li MOVE_ELIMINATION.SIMD_ELIMINATED 351.Pq Event 58H , Umask 08H 352Number of SIMD Move Elimination candidate uops that were eliminated. 353.It Li CPL_CYCLES.RING0 354.Pq Event 5CH , Umask 01H 355Unhalted core cycles when the thread is in ring 0. 356Use Edge to count transition. 357.It Li CPL_CYCLES.RING123 358.Pq Event 5CH , Umask 02H 359Unhalted core cycles when the thread is not in ring 0. 360.It Li RS_EVENTS.EMPTY_CYCLES 361.Pq Event 5EH , Umask 01H 362Cycles the RS is empty for the thread. 363.It Li TLB_ACCESS.LOAD_STLB_HIT 364.Pq Event 5FH , Umask 01H 365Counts load operations that missed 1st level DTLB but hit the 2nd level. 366.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 367.Pq Event 60H , Umask 01H 368Offcore outstanding Demand Data Read transactions in SQ to uncore. 369Set Cmask=1 to count cycles. 370.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD 371.Pq Event 60H , Umask 02H 372Offcore outstanding Demand Code Read transactions in SQ to uncore. 373Set Cmask=1 to count cycles. 374.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 375.Pq Event 60H , Umask 04H 376Offcore outstanding RFO store transactions in SQ to uncore. 377Set Cmask=1 to count cycles. 378.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 379.Pq Event 60H , Umask 08H 380Offcore outstanding cacheable data read transactions in SQ to uncore. 381Set Cmask=1 to count cycles. 382.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 383.Pq Event 63H , Umask 01H 384Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 385.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 386.Pq Event 63H , Umask 02H 387Cycles in which the L1D is locked. 388.It Li IDQ.EMPTY 389.Pq Event 79H , Umask 02H 390Counts cycles the IDQ is empty. 391.It Li IDQ.MITE_UOPS 392.Pq Event 79H , Umask 04H 393Increment each cycle # of uops delivered to IDQ from MITE path. 394Can combine Umask 04H and 20H. 395Set Cmask = 1 to count cycles. 396.It Li IDQ.DSB_UOPS 397.Pq Event 79H , Umask 08H 398Increment each cycle. # of uops delivered to IDQ from DSB path. 399Can combine Umask 08H and 10H 400Set Cmask = 1 to count cycles. 401.It Li IDQ.MS_DSB_UOPS 402.Pq Event 79H , Umask 10H 403Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. 404Set Cmask = 1 to count cycles. 405Add Edge=1 to count # of delivery. 406Can combine Umask 04H, 08H. 407.It Li IDQ.MS_MITE_UOPS 408.Pq Event 79H , Umask 20H 409Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. 410Set Cmask = 1 to count cycles. 411Can combine Umask 04H, 08H. 412.It Li IDQ.MS_UOPS 413.Pq Event 79H , Umask 30H 414Increment each cycle # of uops delivered to IDQ from MS by either DSB or 415MITE. 416Set Cmask = 1 to count cycles. 417Can combine Umask 04H, 08H. 418.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 419.Pq Event 79H , Umask 18H 420Counts cycles DSB is delivered at least one uops. 421Set Cmask = 1. 422.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 423.Pq Event 79H , Umask 18H 424Counts cycles DSB is delivered four uops. 425Set Cmask = 4. 426.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 427.Pq Event 79H , Umask 24H 428Counts cycles MITE is delivered at least one uops. 429Set Cmask = 1. 430.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 431.Pq Event 79H , Umask 24H 432Counts cycles MITE is delivered four uops. 433Set Cmask = 4. 434.It Li IDQ.MITE_ALL_UOPS 435.Pq Event 79H , Umask 3CH 436# of uops delivered to IDQ from any path. 437.It Li ICACHE.MISSES 438.Pq Event 80H , Umask 02H 439Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 440Includes UC accesses. 441.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 442.Pq Event 85H , Umask 01H 443Misses in all ITLB levels that cause page walks. 444.It Li ITLB_MISSES.WALK_COMPLETED 445.Pq Event 85H , Umask 02H 446Misses in all ITLB levels that cause completed page walks. 447.It Li ITLB_MISSES.WALK_DURATION 448.Pq Event 85H , Umask 04H 449Cycle PMH is busy with a walk. 450.It Li ITLB_MISSES.STLB_HIT 451.Pq Event 85H , Umask 10H 452Number of cache load STLB hits. 453No page walk. 454.It Li ILD_STALL.LCP 455.Pq Event 87H , Umask 01H 456Stalls caused by changing prefix length of the instruction. 457.It Li ILD_STALL.IQ_FULL 458.Pq Event 87H , Umask 04H 459Stall cycles due to IQ is full. 460.It Li BR_INST_EXEC.NONTAKEN_COND 461.Pq Event 88H , Umask 41H 462Count conditional near branch instructions that were executed (but not 463necessarily retired) and not taken. 464.It Li BR_INST_EXEC.TAKEN_COND 465.Pq Event 88H , Umask 81H 466Count conditional near branch instructions that were executed (but not 467necessarily retired) and taken. 468.It Li BR_INST_EXEC.DIRECT_JMP 469.Pq Event 88H , Umask 82H 470Count all unconditional near branch instructions excluding calls and 471indirect branches. 472.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 473.Pq Event 88H , Umask 84H 474Count executed indirect near branch instructions that are not calls nor 475returns. 476.It Li BR_INST_EXEC.RETURN_NEAR 477.Pq Event 88H , Umask 88H 478Count indirect near branches that have a return mnemonic. 479.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 480.Pq Event 88H , Umask 90H 481Count unconditional near call branch instructions, excluding non call 482branch, executed. 483.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 484.Pq Event 88H , Umask A0H 485Count indirect near calls, including both register and memory indirect, 486executed. 487.It Li BR_INST_EXEC.ALL_BRANCHES 488.Pq Event 88H , Umask FFH 489Counts all near executed branches (not necessarily retired). 490.It Li BR_MISP_EXEC.NONTAKEN_COND 491.Pq Event 89H , Umask 41H 492Count conditional near branch instructions mispredicted as nontaken. 493.It Li BR_MISP_EXEC.TAKEN_COND 494.Pq Event 89H , Umask 81H 495Count conditional near branch instructions mispredicted as taken. 496.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 497.Pq Event 89H , Umask 84H 498Count mispredicted indirect near branch instructions that are not calls 499nor returns. 500.It Li BR_MISP_EXEC.RETURN_NEAR 501.Pq Event 89H , Umask 88H 502Count mispredicted indirect near branches that have a return mnemonic. 503.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 504.Pq Event 89H , Umask 90H 505Count mispredicted unconditional near call branch instructions, excluding 506non call branch, executed. 507.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 508.Pq Event 89H , Umask A0H 509Count mispredicted indirect near calls, including both register and memory 510indirect, executed. 511.It Li BR_MISP_EXEC.ALL_BRANCHES 512.Pq Event 89H , Umask FFH 513Counts all mispredicted near executed branches (not necessarily retired). 514.It Li IDQ_UOPS_NOT_DELIVERED.CORE 515.Pq Event 9CH , Umask 01H 516Count number of non-delivered uops to RAT per thread. 517Use Cmask to qualify uop b/w. 518.It Li UOPS_DISPATCHED_PORT.PORT_0 519.Pq Event A1H , Umask 01H 520Cycles which a Uop is dispatched on port 0. 521.It Li UOPS_DISPATCHED_PORT.PORT_1 522.Pq Event A1H , Umask 02H 523Cycles which a Uop is dispatched on port 1. 524.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 525.Pq Event A1H , Umask 04H 526Cycles which a load uop is dispatched on port 2. 527.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 528.Pq Event A1H , Umask 08H 529Cycles which a store address uop is dispatched on port 2. 530.It Li UOPS_DISPATCHED_PORT.PORT_2 531.Pq Event A1H , Umask 0CH 532Cycles which a Uop is dispatched on port 2. 533.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 534.Pq Event A1H , Umask 10H 535Cycles which a load uop is dispatched on port 3. 536.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 537.Pq Event A1H , Umask 20H 538Cycles which a store address uop is dispatched on port 3. 539.It Li UOPS_DISPATCHED_PORT.PORT_3 540.Pq Event A1H , Umask 30H 541Cycles which a Uop is dispatched on port 3. 542.It Li UOPS_DISPATCHED_PORT.PORT_4 543.Pq Event A1H , Umask 40H 544Cycles which a Uop is dispatched on port 4. 545.It Li UOPS_DISPATCHED_PORT.PORT_5 546.Pq Event A1H , Umask 80H 547Cycles which a Uop is dispatched on port 5. 548.It Li RESOURCE_STALLS.ANY 549.Pq Event A2H , Umask 01H 550Cycles Allocation is stalled due to Resource Related reason. 551.It Li RESOURCE_STALLS.RS 552.Pq Event A2H , Umask 04H 553Cycles stalled due to no eligible RS entry available. 554.It Li RESOURCE_STALLS.SB 555.Pq Event A2H , Umask 08H 556Cycles stalled due to no store buffers available. (not including draining 557form sync). 558.It Li RESOURCE_STALLS.ROB 559.Pq Event A2H , Umask 10H 560Cycles stalled due to re-order buffer full. 561.It Li DSB2MITE_SWITCHES.COUNT 562.Pq Event ABH , Umask 01H 563Number of DSB to MITE switches. 564.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 565.Pq Event ABH , Umask 02H 566Cycles DSB to MITE switches caused delay. 567.It Li DSB_FILL.EXCEED_DSB_LINES 568.Pq Event ACH , Umask 08H 569DSB Fill encountered > 3 DSB lines. 570.It Li ITLB.ITLB_FLUSH 571.Pq Event AEH , Umask 01H 572Counts the number of ITLB flushes, includes 4k/2M/4M pages. 573.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 574.Pq Event B0H , Umask 01H 575Demand data read requests sent to uncore. 576.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 577.Pq Event B0H , Umask 02H 578Demand code read requests sent to uncore. 579.It Li OFFCORE_REQUESTS.DEMAND_RFO 580.Pq Event B0H , Umask 04H 581Demand RFO read requests sent to uncore, including regular RFOs, locks, 582ItoM. 583.It Li OFFCORE_REQUESTS.ALL_DATA_RD 584.Pq Event B0H , Umask 08H 585Data read requests sent to uncore (demand and prefetch). 586.It Li UOPS_EXECUTED.THREAD 587.Pq Event B1H , Umask 01H 588Counts total number of uops to be executed per-thread each cycle. 589Set Cmask = 1, INV =1 to count stall cycles. 590.It Li UOPS_EXECUTED.CORE 591.Pq Event B1H , Umask 02H 592Counts total number of uops to be executed per-core each cycle. 593Do not need to set ANY. 594.It Li OFF_CORE_RESPONSE_0 595.Pq Event B7H , Umask 01H 596Off-core Response Performance Monitoring. 597PMC0 only. 598Requires programming MSR 01A6H. 599.It Li OFF_CORE_RESPONSE_1 600.Pq Event BBH , Umask 01H 601Off-core Response Performance Monitoring. 602PMC3 only. 603Requires programming MSR 01A7H. 604.It Li TLB_FLUSH.DTLB_THREAD 605.Pq Event BDH , Umask 01H 606DTLB flush attempts of the thread- specific entries. 607.It Li TLB_FLUSH.STLB_ANY 608.Pq Event BDH , Umask 20H 609Count number of STLB flush attempts. 610.It Li INST_RETIRED.ANY_P 611.Pq Event C0H , Umask 00H 612Number of instructions at retirement. 613.It Li INST_RETIRED.ALL 614.Pq Event C0H , Umask 01H 615Precise instruction retired event with HW to reduce effect of PEBS shadow in 616IP distribution. 617PMC1 only. 618Must quiesce other PMCs. 619.It Li OTHER_ASSISTS.AVX_STORE 620.Pq Event C1H , Umask 08H 621Number of assists associated with 256-bit AVX store operations. 622.It Li OTHER_ASSISTS.AVX_TO_SSE 623.Pq Event C1H , Umask 10H 624Number of transitions from AVX- 256 to legacy SSE when penalty applicable. 625.It Li OTHER_ASSISTS.SSE_TO_AVX 626.Pq Event C1H , Umask 20H 627Number of transitions from SSE to AVX-256 when penalty applicable. 628.It Li UOPS_RETIRED.ALL 629.Pq Event C2H , Umask 01H 630Counts the number of micro-ops retired, Use cmask=1 and invert to count 631active cycles or stalled cycles. 632Supports PEBS, use Any=1 for core granular. 633.It Li UOPS_RETIRED.RETIRE_SLOTS 634.Pq Event C2H , Umask 02H 635Counts the number of retirement slots used each cycle. 636.It Li MACHINE_CLEARS.MEMORY_ORDERING 637.Pq Event C3H , Umask 02H 638Counts the number of machine clears due to memory order conflicts. 639.It Li MACHINE_CLEARS.SMC 640.Pq Event C3H , Umask 04H 641Number of self-modifying-code machine clears detected. 642.It Li MACHINE_CLEARS.MASKMOV 643.Pq Event C3H , Umask 20H 644Counts the number of executed AVX masked load operations that refer to an 645illegal address range with the mask bits set to 0. 646.It Li BR_INST_RETIRED.ALL_BRANCHES 647.Pq Event C4H , Umask 00H 648Branch instructions at retirement. 649.It Li BR_INST_RETIRED.CONDITIONAL 650.Pq Event C4H , Umask 01H 651Counts the number of conditional branch instructions retired. 652Supports PEBS. 653.It Li BR_INST_RETIRED.NEAR_CALL 654.Pq Event C4H , Umask 02H 655Direct and indirect near call instructions retired. 656.It Li BR_INST_RETIRED.ALL_BRANCHES 657.Pq Event C4H , Umask 04H 658Counts the number of branch instructions retired. 659.It Li BR_INST_RETIRED.NEAR_RETURN 660.Pq Event C4H , Umask 08H 661Counts the number of near return instructions retired. 662.It Li BR_INST_RETIRED.NOT_TAKEN 663.Pq Event C4H , Umask 10H 664Counts the number of not taken branch instructions retired. 665.It Li BR_INST_RETIRED.NEAR_TAKEN 666.Pq Event C4H , Umask 20H 667Number of near taken branches retired. 668.It Li BR_INST_RETIRED.FAR_BRANCH 669.Pq Event C4H , Umask 40H 670Number of far branches retired. 671.It Li BR_MISP_RETIRED.ALL_BRANCHES 672.Pq Event C5H , Umask 00H 673Mispredicted branch instructions at retirement. 674.It Li BR_MISP_RETIRED.CONDITIONAL 675.Pq Event C5H , Umask 01H 676Mispredicted conditional branch instructions retired. 677Supports PEBS. 678.It Li BR_MISP_RETIRED.NEAR_CALL 679.Pq Event C5H , Umask 02H 680Direct and indirect mispredicted near call instructions retired. 681.It Li BR_MISP_RETIRED.ALL_BRANCHES 682.Pq Event C5H , Umask 04H 683Mispredicted macro branch instructions retired. 684.It Li BR_MISP_RETIRED.NOT_TAKEN 685.Pq Event C5H , Umask 10H 686Mispredicted not taken branch instructions retired. 687.It Li BR_MISP_RETIRED.TAKEN 688.Pq Event C5H , Umask 20H 689Mispredicted taken branch instructions retired. 690.It Li FP_ASSIST.X87_OUTPUT 691.Pq Event CAH , Umask 02H 692Number of X87 FP assists due to Output values. 693.It Li FP_ASSIST.X87_INPUT 694.Pq Event CAH , Umask 04H 695Number of X87 FP assists due to input values. 696.It Li FP_ASSIST.SIMD_OUTPUT 697.Pq Event CAH , Umask 08H 698Number of SIMD FP assists due to Output values. 699.It Li FP_ASSIST.SIMD_INPUT 700.Pq Event CAH , Umask 10H 701Number of SIMD FP assists due to input values. 702.It Li FP_ASSIST.ANY 703.Pq Event CAH , Umask 1EH 704Cycles with any input/output SSE* or FP assists. 705.It Li ROB_MISC_EVENTS.LBR_INSERTS 706.Pq Event CCH , Umask 20H 707Count cases of saving new LBR records by hardware. 708.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 709.Pq Event CDH , Umask 01H 710Sample loads with specified latency threshold. 711PMC3 only. 712Specify threshold in MSR 0x3F6. 713.It Li MEM_TRANS_RETIRED.PRECISE_STORE 714.Pq Event CDH , Umask 02H 715Sample stores and collect precise store operation via PEBS record. 716PMC3 only. 717.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS 718.Pq Event D0H , Umask 11H 719Count retired load uops that missed the STLB. 720.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES 721.Pq Event D0H , Umask 12H 722Count retired store uops that missed the STLB. 723.It Li MEM_UOPS_RETIRED.SPLIT_LOADS 724.Pq Event D0H , Umask 41H 725Count retired load uops that were split across a cache line. 726.It Li MEM_UOPS_RETIRED.SPLIT_STORES 727.Pq Event D0H , Umask 42H 728Count retired store uops that were split across a cache line. 729.It Li MEM_UOPS_RETIRED.ALL_LOADS 730.Pq Event D0H , Umask 81H 731Count all retired load uops. 732.It Li MEM_UOPS_RETIRED.ALL_STORES 733.Pq Event D0H , Umask 82H 734Count all retired store uops. 735.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 736.Pq Event D1H , Umask 01H 737Retired load uops with L1 cache hits as data sources. 738Supports PEBS. 739.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 740.Pq Event D1H , Umask 02H 741Retired load uops with L2 cache hits as data sources. 742.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 743.Pq Event D1H , Umask 04H 744Retired load uops with LLC cache hits as data sources. 745.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 746.Pq Event D1H , Umask 40H 747Retired load uops which data sources were load uops missed L1 but hit FB due 748to preceding miss to the same cache line with data not ready. 749.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 750.Pq Event D2H , Umask 01H 751Retired load uops which data sources were LLC hit and cross-core snoop 752missed in on-pkg core cache. 753Supports PEBS. 754.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 755.Pq Event D2H , Umask 02H 756Retired load uops which data sources were LLC and cross-core snoop hits in 757on-pkg core cache. 758Supports PEBS. 759.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 760.Pq Event D2H , Umask 04H 761Retired load uops which data sources were HitM responses from shared LLC. 762.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 763.Pq Event D2H , Umask 08H 764Retired load uops which data sources were hits in LLC without snoops 765required. 766.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 767.Pq Event D3H , Umask 01H 768Retired load uops which data sources missed LLC but serviced from local 769dram. 770Supports PEBS. 771.It Li L2_TRANS.DEMAND_DATA_RD 772.Pq Event F0H , Umask 01H 773Demand Data Read requests that access L2 cache. 774.It Li L2_TRANS.RFO 775.Pq Event F0H , Umask 02H 776RFO requests that access L2 cache. 777.It Li L2_TRANS.CODE_RD 778.Pq Event F0H , Umask 04H 779L2 cache accesses when fetching instructions. 780.It Li L2_TRANS.ALL_PF 781.Pq Event F0H , Umask 08H 782Any MLC or LLC HW prefetch accessing L2, including rejects. 783.It Li L2_TRANS.L1D_WB 784.Pq Event F0H , Umask 10H 785L1D writebacks that access L2 cache. 786.It Li L2_TRANS.L2_FILL 787.Pq Event F0H , Umask 20H 788L2 fill requests that access L2 cache. 789.It Li L2_TRANS.L2_WB 790.Pq Event F0H , Umask 40H 791L2 writebacks that access L2 cache. 792.It Li L2_TRANS.ALL_REQUESTS 793.Pq Event F0H , Umask 80H 794Transactions accessing L2 pipe. 795.It Li L2_LINES_IN.I 796.Pq Event F1H , Umask 01H 797L2 cache lines in I state filling L2. 798Counting does not cover rejects. 799.It Li L2_LINES_IN.S 800.Pq Event F1H , Umask 02H 801L2 cache lines in S state filling L2. 802Counting does not cover rejects. 803.It Li L2_LINES_IN.E 804.Pq Event F1H , Umask 04H 805L2 cache lines in E state filling L2. 806Counting does not cover rejects. 807.It Li L2_LINES_IN.ALL 808.Pq Event F1H , Umask 07H 809L2 cache lines filling L2. 810Counting does not cover rejects. 811.It Li L2_LINES_OUT.DEMAND_CLEAN 812.Pq Event F2H , Umask 01H 813Clean L2 cache lines evicted by demand. 814.It Li L2_LINES_OUT.DEMAND_DIRTY 815.Pq Event F2H , Umask 02H 816Dirty L2 cache lines evicted by demand. 817.It Li L2_LINES_OUT.PF_CLEAN 818.Pq Event F2H , Umask 04H 819Clean L2 cache lines evicted by the MLC prefetcher. 820.It Li L2_LINES_OUT.PF_DIRTY 821.Pq Event F2H , Umask 08H 822Dirty L2 cache lines evicted by the MLC prefetcher. 823.El 824.Sh SEE ALSO 825.Xr pmc 3 , 826.Xr pmc.amd 3 , 827.Xr pmc.atom 3 , 828.Xr pmc.core 3 , 829.Xr pmc.corei7 3 , 830.Xr pmc.corei7uc 3 , 831.Xr pmc.iaf 3 , 832.Xr pmc.ivybridgexeon 3 , 833.Xr pmc.sandybridge 3 , 834.Xr pmc.sandybridgeuc 3 , 835.Xr pmc.sandybridgexeon 3 , 836.Xr pmc.soft 3 , 837.Xr pmc.tsc 3 , 838.Xr pmc.ucf 3 , 839.Xr pmc.westmere 3 , 840.Xr pmc.westmereuc 3 , 841.Xr pmc_cpuinfo 3 , 842.Xr pmclog 3 , 843.Xr hwpmc 4 844.Sh HISTORY 845The 846.Nm pmc 847library first appeared in 848.Fx 6.0 . 849.Sh AUTHORS 850.An -nosplit 851The 852.Lb libpmc 853library was written by 854.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 855The support for the Ivy Bridge 856microarchitecture was written by 857.An Fabien Thomas Aq Mt fabient@FreeBSD.org . 858