1.\" Copyright (c) 2012 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd October 19, 2012 27.Dt PMC.IVYBRIDGE 3 28.Os 29.Sh NAME 30.Nm pmc.ivybridge 31.Nd measurement events for 32.Tn Intel 33.Tn Ivy Bridge 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Ivy Bridge" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs may contain up to three classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Ivy Bridge PMCs are documented in 59.Rs 60.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61.%T "Volume 3B: System Programming Guide, Part 2" 62.%N "Order Number: 253669-043US" 63.%D May 2012 64.%Q "Intel Corporation" 65.Re 66.Ss IVYBRIDGE FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69.Ss IVYBRIDGE PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta Yes 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta Yes 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta Yes 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li rsp= Ns Ar value 90Configure the Off-core Response bits. 91.Bl -tag -width indent 92.It Li REQ_DMND_DATA_RD 93Counts the number of demand and DCU prefetch data reads of full and partial 94cachelines as well as demand data page table entry cacheline reads. 95Does not count L2 data read prefetches or instruction fetches. 96.It Li REQ_DMND_RFO 97Counts the number of demand and DCU prefetch reads for ownership (RFO) 98requests generated by a write to data cacheline. 99Does not count L2 RFO prefetches. 100.It Li REQ_DMND_IFETCH 101Counts the number of demand and DCU prefetch instruction cacheline reads. 102Does not count L2 code read prefetches. 103.It Li REQ_WB 104Counts the number of writeback (modified to exclusive) transactions. 105.It Li REQ_PF_DATA_RD 106Counts the number of data cacheline reads generated by L2 prefetchers. 107.It Li REQ_PF_RFO 108Counts the number of RFO requests generated by L2 prefetchers. 109.It Li REQ_PF_IFETCH 110Counts the number of code reads generated by L2 prefetchers. 111.It Li REQ_PF_LLC_DATA_RD 112L2 prefetcher to L3 for loads. 113.It Li REQ_PF_LLC_RFO 114RFO requests generated by L2 prefetcher 115.It Li REQ_PF_LLC_IFETCH 116L2 prefetcher to L3 for instruction fetches. 117.It Li REQ_BUS_LOCKS 118Bus lock and split lock requests. 119.It Li REQ_STRM_ST 120Streaming store requests. 121.It Li REQ_OTHER 122Any other request that crosses IDI, including I/O. 123.It Li RES_ANY 124Catch all value for any response types. 125.It Li RES_SUPPLIER_NO_SUPP 126No Supplier Information available. 127.It Li RES_SUPPLIER_LLC_HITM 128M-state initial lookup stat in L3. 129.It Li RES_SUPPLIER_LLC_HITE 130E-state. 131.It Li RES_SUPPLIER_LLC_HITS 132S-state. 133.It Li RES_SUPPLIER_LLC_HITF 134F-state. 135.It Li RES_SUPPLIER_LOCAL 136Local DRAM Controller. 137.It Li RES_SNOOP_SNP_NONE 138No details on snoop-related information. 139.It Li RES_SNOOP_SNP_NO_NEEDED 140No snoop was needed to satisfy the request. 141.It Li RES_SNOOP_SNP_MISS 142A snoop was needed and it missed all snooped caches: 143-For LLC Hit, ReslHitl was returned by all cores 144-For LLC Miss, Rspl was returned by all sockets and data was returned from 145DRAM. 146.It Li RES_SNOOP_HIT_NO_FWD 147A snoop was needed and it hits in at least one snooped cache. 148Hit denotes a cache-line was valid before snoop effect. 149This includes: 150-Snoop Hit w/ Invalidation (LLC Hit, RFO) 151-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 152-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 153In the LLC Miss case, data is returned from DRAM. 154.It Li RES_SNOOP_HIT_FWD 155A snoop was needed and data was forwarded from a remote socket. 156This includes: 157-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 158.It Li RES_SNOOP_HITM 159A snoop was needed and it HitM-ed in local or remote cache. 160HitM denotes a cache-line was in modified state before effect as a results of snoop. 161This includes: 162-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 163-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 164-Snoop MtoS (LLC Hit, IFetch/Data_RD). 165.It Li RES_NON_DRAM 166Target was non-DRAM system address. 167This includes MMIO transactions. 168.El 169.It Li cmask= Ns Ar value 170Configure the PMC to increment only if the number of configured 171events measured in a cycle is greater than or equal to 172.Ar value . 173.It Li edge 174Configure the PMC to count the number of de-asserted to asserted 175transitions of the conditions expressed by the other qualifiers. 176If specified, the counter will increment only once whenever a 177condition becomes true, irrespective of the number of clocks during 178which the condition remains true. 179.It Li inv 180Invert the sense of comparison when the 181.Dq Li cmask 182qualifier is present, making the counter increment when the number of 183events per cycle is less than the value specified by the 184.Dq Li cmask 185qualifier. 186.It Li os 187Configure the PMC to count events happening at processor privilege 188level 0. 189.It Li usr 190Configure the PMC to count events occurring at privilege levels 1, 2 191or 3. 192.El 193.Pp 194If neither of the 195.Dq Li os 196or 197.Dq Li usr 198qualifiers are specified, the default is to enable both. 199.Ss Event Specifiers (Programmable PMCs) 200Ivy Bridge programmable PMCs support the following events: 201.Bl -tag -width indent 202.It Li LD_BLOCKS.STORE_FORWARD 203.Pq Event 03H , Umask 02H 204loads blocked by overlapping with store buffer that cannot be forwarded . 205.It Li MISALIGN_MEM_REF.LOADS 206.Pq Event 05H , Umask 01H 207Speculative cache-line split load uops dispatched to L1D. 208.It Li MISALIGN_MEM_REF.STORES 209.Pq Event 05H , Umask 02H 210Speculative cache-line split Store- address uops dispatched to L1D. 211.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 212.Pq Event 07H , Umask 01H 213False dependencies in MOB due to partial compare on address. 214.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK 215.Pq Event 08H , Umask 81H 216Misses in all TLB levels that cause a page walk of any page size from demand loads. 217.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED 218.Pq Event 08H , Umask 82H 219Misses in all TLB levels that caused page walk completed of any size by demand loads. 220.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION 221.Pq Event 08H , Umask 84H 222Cycle PMH is busy with a walk due to demand loads. 223.It Li UOPS_ISSUED.ANY 224.Pq Event 0EH , Umask 01H 225Increments each cycle the # of Uops issued by the RAT to RS. 226Set Cmask = 1, Inv = 1to count stalled cycles. 227Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. 228.It Li UOPS_ISSUED.FLAGS_MERGE 229.Pq Event 0EH , Umask 10H 230Number of flags-merge uops allocated. 231Such uops adds delay. 232.It Li UOPS_ISSUED.SLOW_LEA 233.Pq Event 0EH , Umask 20H 234Number of slow LEA or similar uops allocated. 235Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. 236.It Li UOPS_ISSUED.SINGLE_MUL 237.Pq Event 0EH , Umask 40H 238Number of multiply packed/scalar single precision uops allocated. 239.It Li ARITH.FPU_DIV_ACTIVE 240.Pq Event 14H , Umask 01H 241Cycles that the divider is active, includes INT and FP. 242Set 'edge =1, cmask=1' to count the number of divides. 243.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 244.Pq Event 24H , Umask 01H 245Demand Data Read requests that hit L2 cache. 246.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 247.Pq Event 24H , Umask 03H 248Counts any demand and L1 HW prefetch data load requests to L2. 249.It Li L2_RQSTS.RFO_HITS 250.Pq Event 24H , Umask 04H 251Counts the number of store RFO requests that hit the L2 cache. 252.It Li L2_RQSTS.RFO_MISS 253.Pq Event 24H , Umask 08H 254Counts the number of store RFO requests that miss the L2 cache. 255.It Li L2_RQSTS.ALL_RFO 256.Pq Event 24H , Umask 0CH 257Counts all L2 store RFO requests. 258.It Li L2_RQSTS.CODE_RD_HIT 259.Pq Event 24H , Umask 10H 260Number of instruction fetches that hit the L2 cache. 261.It Li L2_RQSTS.CODE_RD_MISS 262.Pq Event 24H , Umask 20H 263Number of instruction fetches that missed the L2 cache. 264.It Li L2_RQSTS.ALL_CODE_RD 265.Pq Event 24H , Umask 30H 266Counts all L2 code requests. 267.It Li L2_RQSTS.PF_HIT 268.Pq Event 24H , Umask 40H 269Counts all L2 HW prefetcher requests that hit L2. 270.It Li L2_RQSTS.PF_MISS 271.Pq Event 24H , Umask 80H 272Counts all L2 HW prefetcher requests that missed L2. 273.It Li L2_RQSTS.ALL_PF 274.Pq Event 24H , Umask C0H 275Counts all L2 HW prefetcher requests. 276.It Li L2_STORE_LOCK_RQSTS.MISS 277.Pq Event 27H , Umask 01H 278RFOs that miss cache lines. 279.It Li L2_STORE_LOCK_RQSTS.HIT_M 280.Pq Event 27H , Umask 08H 281RFOs that hit cache lines in M state. 282.It Li L2_STORE_LOCK_RQSTS.ALL 283.Pq Event 27H , Umask 0FH 284RFOs that access cache lines in any state. 285.It Li L2_L1D_WB_RQSTS.MISS 286.Pq Event 28H , Umask 01H 287Not rejected writebacks that missed LLC. 288.It Li L2_L1D_WB_RQSTS.HIT_E 289.Pq Event 28H , Umask 04H 290Not rejected writebacks from L1D to L2 cache lines in E state. 291.It Li L2_L1D_WB_RQSTS.HIT_M 292.Pq Event 28H , Umask 08H 293Not rejected writebacks from L1D to L2 cache lines in M state. 294.It Li L2_L1D_WB_RQSTS.ALL 295.Pq Event 28H , Umask 0FH 296Not rejected writebacks from L1D to L2 cache lines in any state. 297.It Li LONGEST_LAT_CACHE.REFERENCE 298.Pq Event 2EH , Umask 4FH 299This event counts requests originating from the core that reference a cache 300line in the last level cache. 301.It Li LONGEST_LAT_CACHE.MISS 302.Pq Event 2EH , Umask 41H 303This event counts each cache miss condition for references to the last level 304cache. 305.It Li CPU_CLK_UNHALTED.THREAD_P 306.Pq Event 3CH , Umask 00H 307Counts the number of thread cycles while the thread is not in a halt state. 308The thread enters the halt state when it is running the HLT instruction. 309The core frequency may change from time to time due to power or thermal 310throttling. 311.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 312.Pq Event 3CH , Umask 01H 313Increments at the frequency of XCLK (100 MHz) when not halted. 314.It Li L1D_PEND_MISS.PENDING 315.Pq Event 48H , Umask 01H 316Increments the number of outstanding L1D misses every cycle. 317Set Cmaks = 1 and Edge =1 to count occurrences. 318Counter 2 only. 319Set Cmask = 1 to count cycles. 320.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 321.Pq Event 49H , Umask 01H 322Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). 323.It Li DTLB_STORE_MISSES.WALK_COMPLETED 324.Pq Event 49H , Umask 02H 325Miss in all TLB levels causes a page walk that completes of any page size 326(4K/2M/4M/1G). 327.It Li DTLB_STORE_MISSES.WALK_DURATION 328.Pq Event 49H , Umask 04H 329Cycles PMH is busy with this walk. 330.It Li DTLB_STORE_MISSES.STLB_HIT 331.Pq Event 49H , Umask 10H 332Store operations that miss the first TLB level but hit the second and do not 333cause page walks. 334.It Li LOAD_HIT_PRE.SW_PF 335.Pq Event 4CH , Umask 01H 336Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. 337.It Li LOAD_HIT_PRE.HW_PF 338.Pq Event 4CH , Umask 02H 339Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. 340.It Li L1D.REPLACEMENT 341.Pq Event 51H , Umask 01H 342Counts the number of lines brought into the L1 data cache. 343.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 344.Pq Event 58H , Umask 01H 345Number of integer Move Elimination candidate uops that were not eliminated. 346.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED 347.Pq Event 58H , Umask 02H 348Number of SIMD Move Elimination candidate uops that were not eliminated. 349.It Li MOVE_ELIMINATION.INT_ELIMINATED 350.Pq Event 58H , Umask 04H 351Number of integer Move Elimination candidate uops that were eliminated. 352.It Li MOVE_ELIMINATION.SIMD_ELIMINATED 353.Pq Event 58H , Umask 08H 354Number of SIMD Move Elimination candidate uops that were eliminated. 355.It Li CPL_CYCLES.RING0 356.Pq Event 5CH , Umask 01H 357Unhalted core cycles when the thread is in ring 0. 358Use Edge to count transition. 359.It Li CPL_CYCLES.RING123 360.Pq Event 5CH , Umask 02H 361Unhalted core cycles when the thread is not in ring 0. 362.It Li RS_EVENTS.EMPTY_CYCLES 363.Pq Event 5EH , Umask 01H 364Cycles the RS is empty for the thread. 365.It Li TLB_ACCESS.LOAD_STLB_HIT 366.Pq Event 5FH , Umask 01H 367Counts load operations that missed 1st level DTLB but hit the 2nd level. 368.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 369.Pq Event 60H , Umask 01H 370Offcore outstanding Demand Data Read transactions in SQ to uncore. 371Set Cmask=1 to count cycles. 372.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD 373.Pq Event 60H , Umask 02H 374Offcore outstanding Demand Code Read transactions in SQ to uncore. 375Set Cmask=1 to count cycles. 376.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 377.Pq Event 60H , Umask 04H 378Offcore outstanding RFO store transactions in SQ to uncore. 379Set Cmask=1 to count cycles. 380.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 381.Pq Event 60H , Umask 08H 382Offcore outstanding cacheable data read transactions in SQ to uncore. 383Set Cmask=1 to count cycles. 384.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 385.Pq Event 63H , Umask 01H 386Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 387.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 388.Pq Event 63H , Umask 02H 389Cycles in which the L1D is locked. 390.It Li IDQ.EMPTY 391.Pq Event 79H , Umask 02H 392Counts cycles the IDQ is empty. 393.It Li IDQ.MITE_UOPS 394.Pq Event 79H , Umask 04H 395Increment each cycle # of uops delivered to IDQ from MITE path. 396Can combine Umask 04H and 20H. 397Set Cmask = 1 to count cycles. 398.It Li IDQ.DSB_UOPS 399.Pq Event 79H , Umask 08H 400Increment each cycle. # of uops delivered to IDQ from DSB path. 401Can combine Umask 08H and 10H 402Set Cmask = 1 to count cycles. 403.It Li IDQ.MS_DSB_UOPS 404.Pq Event 79H , Umask 10H 405Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. 406Set Cmask = 1 to count cycles. 407Add Edge=1 to count # of delivery. 408Can combine Umask 04H, 08H. 409.It Li IDQ.MS_MITE_UOPS 410.Pq Event 79H , Umask 20H 411Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. 412Set Cmask = 1 to count cycles. 413Can combine Umask 04H, 08H. 414.It Li IDQ.MS_UOPS 415.Pq Event 79H , Umask 30H 416Increment each cycle # of uops delivered to IDQ from MS by either DSB or 417MITE. 418Set Cmask = 1 to count cycles. 419Can combine Umask 04H, 08H. 420.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 421.Pq Event 79H , Umask 18H 422Counts cycles DSB is delivered at least one uops. 423Set Cmask = 1. 424.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 425.Pq Event 79H , Umask 18H 426Counts cycles DSB is delivered four uops. 427Set Cmask = 4. 428.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 429.Pq Event 79H , Umask 24H 430Counts cycles MITE is delivered at least one uops. 431Set Cmask = 1. 432.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 433.Pq Event 79H , Umask 24H 434Counts cycles MITE is delivered four uops. 435Set Cmask = 4. 436.It Li IDQ.MITE_ALL_UOPS 437.Pq Event 79H , Umask 3CH 438# of uops delivered to IDQ from any path. 439.It Li ICACHE.MISSES 440.Pq Event 80H , Umask 02H 441Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 442Includes UC accesses. 443.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 444.Pq Event 85H , Umask 01H 445Misses in all ITLB levels that cause page walks. 446.It Li ITLB_MISSES.WALK_COMPLETED 447.Pq Event 85H , Umask 02H 448Misses in all ITLB levels that cause completed page walks. 449.It Li ITLB_MISSES.WALK_DURATION 450.Pq Event 85H , Umask 04H 451Cycle PMH is busy with a walk. 452.It Li ITLB_MISSES.STLB_HIT 453.Pq Event 85H , Umask 10H 454Number of cache load STLB hits. 455No page walk. 456.It Li ILD_STALL.LCP 457.Pq Event 87H , Umask 01H 458Stalls caused by changing prefix length of the instruction. 459.It Li ILD_STALL.IQ_FULL 460.Pq Event 87H , Umask 04H 461Stall cycles due to IQ is full. 462.It Li BR_INST_EXEC.NONTAKEN_COND 463.Pq Event 88H , Umask 41H 464Count conditional near branch instructions that were executed (but not 465necessarily retired) and not taken. 466.It Li BR_INST_EXEC.TAKEN_COND 467.Pq Event 88H , Umask 81H 468Count conditional near branch instructions that were executed (but not 469necessarily retired) and taken. 470.It Li BR_INST_EXEC.DIRECT_JMP 471.Pq Event 88H , Umask 82H 472Count all unconditional near branch instructions excluding calls and 473indirect branches. 474.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 475.Pq Event 88H , Umask 84H 476Count executed indirect near branch instructions that are not calls nor 477returns. 478.It Li BR_INST_EXEC.RETURN_NEAR 479.Pq Event 88H , Umask 88H 480Count indirect near branches that have a return mnemonic. 481.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 482.Pq Event 88H , Umask 90H 483Count unconditional near call branch instructions, excluding non call 484branch, executed. 485.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 486.Pq Event 88H , Umask A0H 487Count indirect near calls, including both register and memory indirect, 488executed. 489.It Li BR_INST_EXEC.ALL_BRANCHES 490.Pq Event 88H , Umask FFH 491Counts all near executed branches (not necessarily retired). 492.It Li BR_MISP_EXEC.NONTAKEN_COND 493.Pq Event 89H , Umask 41H 494Count conditional near branch instructions mispredicted as nontaken. 495.It Li BR_MISP_EXEC.TAKEN_COND 496.Pq Event 89H , Umask 81H 497Count conditional near branch instructions mispredicted as taken. 498.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 499.Pq Event 89H , Umask 84H 500Count mispredicted indirect near branch instructions that are not calls 501nor returns. 502.It Li BR_MISP_EXEC.RETURN_NEAR 503.Pq Event 89H , Umask 88H 504Count mispredicted indirect near branches that have a return mnemonic. 505.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 506.Pq Event 89H , Umask 90H 507Count mispredicted unconditional near call branch instructions, excluding 508non call branch, executed. 509.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 510.Pq Event 89H , Umask A0H 511Count mispredicted indirect near calls, including both register and memory 512indirect, executed. 513.It Li BR_MISP_EXEC.ALL_BRANCHES 514.Pq Event 89H , Umask FFH 515Counts all mispredicted near executed branches (not necessarily retired). 516.It Li IDQ_UOPS_NOT_DELIVERED.CORE 517.Pq Event 9CH , Umask 01H 518Count number of non-delivered uops to RAT per thread. 519Use Cmask to qualify uop b/w. 520.It Li UOPS_DISPATCHED_PORT.PORT_0 521.Pq Event A1H , Umask 01H 522Cycles which a Uop is dispatched on port 0. 523.It Li UOPS_DISPATCHED_PORT.PORT_1 524.Pq Event A1H , Umask 02H 525Cycles which a Uop is dispatched on port 1. 526.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 527.Pq Event A1H , Umask 04H 528Cycles which a load uop is dispatched on port 2. 529.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 530.Pq Event A1H , Umask 08H 531Cycles which a store address uop is dispatched on port 2. 532.It Li UOPS_DISPATCHED_PORT.PORT_2 533.Pq Event A1H , Umask 0CH 534Cycles which a Uop is dispatched on port 2. 535.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 536.Pq Event A1H , Umask 10H 537Cycles which a load uop is dispatched on port 3. 538.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 539.Pq Event A1H , Umask 20H 540Cycles which a store address uop is dispatched on port 3. 541.It Li UOPS_DISPATCHED_PORT.PORT_3 542.Pq Event A1H , Umask 30H 543Cycles which a Uop is dispatched on port 3. 544.It Li UOPS_DISPATCHED_PORT.PORT_4 545.Pq Event A1H , Umask 40H 546Cycles which a Uop is dispatched on port 4. 547.It Li UOPS_DISPATCHED_PORT.PORT_5 548.Pq Event A1H , Umask 80H 549Cycles which a Uop is dispatched on port 5. 550.It Li RESOURCE_STALLS.ANY 551.Pq Event A2H , Umask 01H 552Cycles Allocation is stalled due to Resource Related reason. 553.It Li RESOURCE_STALLS.RS 554.Pq Event A2H , Umask 04H 555Cycles stalled due to no eligible RS entry available. 556.It Li RESOURCE_STALLS.SB 557.Pq Event A2H , Umask 08H 558Cycles stalled due to no store buffers available. (not including draining 559form sync). 560.It Li RESOURCE_STALLS.ROB 561.Pq Event A2H , Umask 10H 562Cycles stalled due to re-order buffer full. 563.It Li DSB2MITE_SWITCHES.COUNT 564.Pq Event ABH , Umask 01H 565Number of DSB to MITE switches. 566.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 567.Pq Event ABH , Umask 02H 568Cycles DSB to MITE switches caused delay. 569.It Li DSB_FILL.EXCEED_DSB_LINES 570.Pq Event ACH , Umask 08H 571DSB Fill encountered > 3 DSB lines. 572.It Li ITLB.ITLB_FLUSH 573.Pq Event AEH , Umask 01H 574Counts the number of ITLB flushes, includes 4k/2M/4M pages. 575.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 576.Pq Event B0H , Umask 01H 577Demand data read requests sent to uncore. 578.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 579.Pq Event B0H , Umask 02H 580Demand code read requests sent to uncore. 581.It Li OFFCORE_REQUESTS.DEMAND_RFO 582.Pq Event B0H , Umask 04H 583Demand RFO read requests sent to uncore, including regular RFOs, locks, 584ItoM. 585.It Li OFFCORE_REQUESTS.ALL_DATA_RD 586.Pq Event B0H , Umask 08H 587Data read requests sent to uncore (demand and prefetch). 588.It Li UOPS_EXECUTED.THREAD 589.Pq Event B1H , Umask 01H 590Counts total number of uops to be executed per-thread each cycle. 591Set Cmask = 1, INV =1 to count stall cycles. 592.It Li UOPS_EXECUTED.CORE 593.Pq Event B1H , Umask 02H 594Counts total number of uops to be executed per-core each cycle. 595Do not need to set ANY. 596.It Li OFF_CORE_RESPONSE_0 597.Pq Event B7H , Umask 01H 598Off-core Response Performance Monitoring. 599PMC0 only. 600Requires programming MSR 01A6H. 601.It Li OFF_CORE_RESPONSE_1 602.Pq Event BBH , Umask 01H 603Off-core Response Performance Monitoring. 604PMC3 only. 605Requires programming MSR 01A7H. 606.It Li TLB_FLUSH.DTLB_THREAD 607.Pq Event BDH , Umask 01H 608DTLB flush attempts of the thread- specific entries. 609.It Li TLB_FLUSH.STLB_ANY 610.Pq Event BDH , Umask 20H 611Count number of STLB flush attempts. 612.It Li INST_RETIRED.ANY_P 613.Pq Event C0H , Umask 00H 614Number of instructions at retirement. 615.It Li INST_RETIRED.ALL 616.Pq Event C0H , Umask 01H 617Precise instruction retired event with HW to reduce effect of PEBS shadow in 618IP distribution. 619PMC1 only. 620Must quiesce other PMCs. 621.It Li OTHER_ASSISTS.AVX_STORE 622.Pq Event C1H , Umask 08H 623Number of assists associated with 256-bit AVX store operations. 624.It Li OTHER_ASSISTS.AVX_TO_SSE 625.Pq Event C1H , Umask 10H 626Number of transitions from AVX- 256 to legacy SSE when penalty applicable. 627.It Li OTHER_ASSISTS.SSE_TO_AVX 628.Pq Event C1H , Umask 20H 629Number of transitions from SSE to AVX-256 when penalty applicable. 630.It Li UOPS_RETIRED.ALL 631.Pq Event C2H , Umask 01H 632Counts the number of micro-ops retired, Use cmask=1 and invert to count 633active cycles or stalled cycles. 634Supports PEBS, use Any=1 for core granular. 635.It Li UOPS_RETIRED.RETIRE_SLOTS 636.Pq Event C2H , Umask 02H 637Counts the number of retirement slots used each cycle. 638.It Li MACHINE_CLEARS.MEMORY_ORDERING 639.Pq Event C3H , Umask 02H 640Counts the number of machine clears due to memory order conflicts. 641.It Li MACHINE_CLEARS.SMC 642.Pq Event C3H , Umask 04H 643Number of self-modifying-code machine clears detected. 644.It Li MACHINE_CLEARS.MASKMOV 645.Pq Event C3H , Umask 20H 646Counts the number of executed AVX masked load operations that refer to an 647illegal address range with the mask bits set to 0. 648.It Li BR_INST_RETIRED.ALL_BRANCHES 649.Pq Event C4H , Umask 00H 650Branch instructions at retirement. 651.It Li BR_INST_RETIRED.CONDITIONAL 652.Pq Event C4H , Umask 01H 653Counts the number of conditional branch instructions retired. 654Supports PEBS. 655.It Li BR_INST_RETIRED.NEAR_CALL 656.Pq Event C4H , Umask 02H 657Direct and indirect near call instructions retired. 658.It Li BR_INST_RETIRED.ALL_BRANCHES 659.Pq Event C4H , Umask 04H 660Counts the number of branch instructions retired. 661.It Li BR_INST_RETIRED.NEAR_RETURN 662.Pq Event C4H , Umask 08H 663Counts the number of near return instructions retired. 664.It Li BR_INST_RETIRED.NOT_TAKEN 665.Pq Event C4H , Umask 10H 666Counts the number of not taken branch instructions retired. 667.It Li BR_INST_RETIRED.NEAR_TAKEN 668.Pq Event C4H , Umask 20H 669Number of near taken branches retired. 670.It Li BR_INST_RETIRED.FAR_BRANCH 671.Pq Event C4H , Umask 40H 672Number of far branches retired. 673.It Li BR_MISP_RETIRED.ALL_BRANCHES 674.Pq Event C5H , Umask 00H 675Mispredicted branch instructions at retirement. 676.It Li BR_MISP_RETIRED.CONDITIONAL 677.Pq Event C5H , Umask 01H 678Mispredicted conditional branch instructions retired. 679Supports PEBS. 680.It Li BR_MISP_RETIRED.NEAR_CALL 681.Pq Event C5H , Umask 02H 682Direct and indirect mispredicted near call instructions retired. 683.It Li BR_MISP_RETIRED.ALL_BRANCHES 684.Pq Event C5H , Umask 04H 685Mispredicted macro branch instructions retired. 686.It Li BR_MISP_RETIRED.NOT_TAKEN 687.Pq Event C5H , Umask 10H 688Mispredicted not taken branch instructions retired. 689.It Li BR_MISP_RETIRED.TAKEN 690.Pq Event C5H , Umask 20H 691Mispredicted taken branch instructions retired. 692.It Li FP_ASSIST.X87_OUTPUT 693.Pq Event CAH , Umask 02H 694Number of X87 FP assists due to Output values. 695.It Li FP_ASSIST.X87_INPUT 696.Pq Event CAH , Umask 04H 697Number of X87 FP assists due to input values. 698.It Li FP_ASSIST.SIMD_OUTPUT 699.Pq Event CAH , Umask 08H 700Number of SIMD FP assists due to Output values. 701.It Li FP_ASSIST.SIMD_INPUT 702.Pq Event CAH , Umask 10H 703Number of SIMD FP assists due to input values. 704.It Li FP_ASSIST.ANY 705.Pq Event CAH , Umask 1EH 706Cycles with any input/output SSE* or FP assists. 707.It Li ROB_MISC_EVENTS.LBR_INSERTS 708.Pq Event CCH , Umask 20H 709Count cases of saving new LBR records by hardware. 710.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 711.Pq Event CDH , Umask 01H 712Sample loads with specified latency threshold. 713PMC3 only. 714Specify threshold in MSR 0x3F6. 715.It Li MEM_TRANS_RETIRED.PRECISE_STORE 716.Pq Event CDH , Umask 02H 717Sample stores and collect precise store operation via PEBS record. 718PMC3 only. 719.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS 720.Pq Event D0H , Umask 11H 721Count retired load uops that missed the STLB. 722.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES 723.Pq Event D0H , Umask 12H 724Count retired store uops that missed the STLB. 725.It Li MEM_UOPS_RETIRED.SPLIT_LOADS 726.Pq Event D0H , Umask 41H 727Count retired load uops that were split across a cache line. 728.It Li MEM_UOPS_RETIRED.SPLIT_STORES 729.Pq Event D0H , Umask 42H 730Count retired store uops that were split across a cache line. 731.It Li MEM_UOPS_RETIRED.ALL_LOADS 732.Pq Event D0H , Umask 81H 733Count all retired load uops. 734.It Li MEM_UOPS_RETIRED.ALL_STORES 735.Pq Event D0H , Umask 82H 736Count all retired store uops. 737.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 738.Pq Event D1H , Umask 01H 739Retired load uops with L1 cache hits as data sources. 740Supports PEBS. 741.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 742.Pq Event D1H , Umask 02H 743Retired load uops with L2 cache hits as data sources. 744.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 745.Pq Event D1H , Umask 04H 746Retired load uops with LLC cache hits as data sources. 747.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 748.Pq Event D1H , Umask 40H 749Retired load uops which data sources were load uops missed L1 but hit FB due 750to preceding miss to the same cache line with data not ready. 751.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 752.Pq Event D2H , Umask 01H 753Retired load uops which data sources were LLC hit and cross-core snoop 754missed in on-pkg core cache. 755Supports PEBS. 756.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 757.Pq Event D2H , Umask 02H 758Retired load uops which data sources were LLC and cross-core snoop hits in 759on-pkg core cache. 760Supports PEBS. 761.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 762.Pq Event D2H , Umask 04H 763Retired load uops which data sources were HitM responses from shared LLC. 764.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 765.Pq Event D2H , Umask 08H 766Retired load uops which data sources were hits in LLC without snoops 767required. 768.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 769.Pq Event D3H , Umask 01H 770Retired load uops which data sources missed LLC but serviced from local 771dram. 772Supports PEBS. 773.It Li L2_TRANS.DEMAND_DATA_RD 774.Pq Event F0H , Umask 01H 775Demand Data Read requests that access L2 cache. 776.It Li L2_TRANS.RFO 777.Pq Event F0H , Umask 02H 778RFO requests that access L2 cache. 779.It Li L2_TRANS.CODE_RD 780.Pq Event F0H , Umask 04H 781L2 cache accesses when fetching instructions. 782.It Li L2_TRANS.ALL_PF 783.Pq Event F0H , Umask 08H 784Any MLC or LLC HW prefetch accessing L2, including rejects. 785.It Li L2_TRANS.L1D_WB 786.Pq Event F0H , Umask 10H 787L1D writebacks that access L2 cache. 788.It Li L2_TRANS.L2_FILL 789.Pq Event F0H , Umask 20H 790L2 fill requests that access L2 cache. 791.It Li L2_TRANS.L2_WB 792.Pq Event F0H , Umask 40H 793L2 writebacks that access L2 cache. 794.It Li L2_TRANS.ALL_REQUESTS 795.Pq Event F0H , Umask 80H 796Transactions accessing L2 pipe. 797.It Li L2_LINES_IN.I 798.Pq Event F1H , Umask 01H 799L2 cache lines in I state filling L2. 800Counting does not cover rejects. 801.It Li L2_LINES_IN.S 802.Pq Event F1H , Umask 02H 803L2 cache lines in S state filling L2. 804Counting does not cover rejects. 805.It Li L2_LINES_IN.E 806.Pq Event F1H , Umask 04H 807L2 cache lines in E state filling L2. 808Counting does not cover rejects. 809.It Li L2_LINES_IN.ALL 810.Pq Event F1H , Umask 07H 811L2 cache lines filling L2. 812Counting does not cover rejects. 813.It Li L2_LINES_OUT.DEMAND_CLEAN 814.Pq Event F2H , Umask 01H 815Clean L2 cache lines evicted by demand. 816.It Li L2_LINES_OUT.DEMAND_DIRTY 817.Pq Event F2H , Umask 02H 818Dirty L2 cache lines evicted by demand. 819.It Li L2_LINES_OUT.PF_CLEAN 820.Pq Event F2H , Umask 04H 821Clean L2 cache lines evicted by the MLC prefetcher. 822.It Li L2_LINES_OUT.PF_DIRTY 823.Pq Event F2H , Umask 08H 824Dirty L2 cache lines evicted by the MLC prefetcher. 825.El 826.Sh SEE ALSO 827.Xr pmc 3 , 828.Xr pmc.atom 3 , 829.Xr pmc.core 3 , 830.Xr pmc.corei7 3 , 831.Xr pmc.corei7uc 3 , 832.Xr pmc.iaf 3 , 833.Xr pmc.ivybridgexeon 3 , 834.Xr pmc.k7 3 , 835.Xr pmc.k8 3 , 836.Xr pmc.sandybridge 3 , 837.Xr pmc.sandybridgeuc 3 , 838.Xr pmc.sandybridgexeon 3 , 839.Xr pmc.soft 3 , 840.Xr pmc.tsc 3 , 841.Xr pmc.ucf 3 , 842.Xr pmc.westmere 3 , 843.Xr pmc.westmereuc 3 , 844.Xr pmc_cpuinfo 3 , 845.Xr pmclog 3 , 846.Xr hwpmc 4 847.Sh HISTORY 848The 849.Nm pmc 850library first appeared in 851.Fx 6.0 . 852.Sh AUTHORS 853.An -nosplit 854The 855.Lb libpmc 856library was written by 857.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 858The support for the Ivy Bridge 859microarchitecture was written by 860.An Fabien Thomas Aq Mt fabient@FreeBSD.org . 861