xref: /freebsd/lib/libpmc/pmc.ivybridge.3 (revision 25ecdc7d52770caf1c9b44b5ec11f468f6b636f3)
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24.\" $FreeBSD$
25.\"
26.Dd October 19, 2012
27.Dt PMC.IVYBRIDGE 3
28.Os
29.Sh NAME
30.Nm pmc.ivybridge
31.Nd measurement events for
32.Tn Intel
33.Tn Ivy Bridge
34family CPUs
35.Sh LIBRARY
36.Lb libpmc
37.Sh SYNOPSIS
38.In pmc.h
39.Sh DESCRIPTION
40.Tn Intel
41.Tn "Ivy Bridge"
42CPUs contain PMCs conforming to version 2 of the
43.Tn Intel
44performance measurement architecture.
45These CPUs may contain up to three classes of PMCs:
46.Bl -tag -width "Li PMC_CLASS_IAP"
47.It Li PMC_CLASS_IAF
48Fixed-function counters that count only one hardware event per counter.
49.It Li PMC_CLASS_IAP
50Programmable counters that may be configured to count one of a defined
51set of hardware events.
52.El
53.Pp
54The number of PMCs available in each class and their widths need to be
55determined at run time by calling
56.Xr pmc_cpuinfo 3 .
57.Pp
58Intel Ivy Bridge PMCs are documented in
59.Rs
60.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61.%T "Volume 3B: System Programming Guide, Part 2"
62.%N "Order Number: 253669-043US"
63.%D May 2012
64.%Q "Intel Corporation"
65.Re
66.Ss IVYBRIDGE FIXED FUNCTION PMCS
67These PMCs and their supported events are documented in
68.Xr pmc.iaf 3 .
69.Ss IVYBRIDGE PROGRAMMABLE PMCS
70The programmable PMCs support the following capabilities:
71.Bl -column "PMC_CAP_INTERRUPT" "Support"
72.It Em Capability Ta Em Support
73.It PMC_CAP_CASCADE Ta \&No
74.It PMC_CAP_EDGE Ta Yes
75.It PMC_CAP_INTERRUPT Ta Yes
76.It PMC_CAP_INVERT Ta Yes
77.It PMC_CAP_READ Ta Yes
78.It PMC_CAP_PRECISE Ta \&No
79.It PMC_CAP_SYSTEM Ta Yes
80.It PMC_CAP_TAGGING Ta \&No
81.It PMC_CAP_THRESHOLD Ta Yes
82.It PMC_CAP_USER Ta Yes
83.It PMC_CAP_WRITE Ta Yes
84.El
85.Ss Event Qualifiers
86Event specifiers for these PMCs support the following common
87qualifiers:
88.Bl -tag -width indent
89.It Li rsp= Ns Ar value
90Configure the Off-core Response bits.
91.Bl -tag -width indent
92.It Li REQ_DMND_DATA_RD
93Counts the number of demand and DCU prefetch data reads of full and partial
94cachelines as well as demand data page table entry cacheline reads. Does not
95count L2 data read prefetches or instruction fetches.
96.It Li REQ_DMND_RFO
97Counts the number of demand and DCU prefetch reads for ownership (RFO)
98requests generated by a write to data cacheline. Does not count L2 RFO
99prefetches.
100.It Li REQ_DMND_IFETCH
101Counts the number of demand and DCU prefetch instruction cacheline reads.
102Does not count L2 code read prefetches.
103.It Li REQ_WB
104Counts the number of writeback (modified to exclusive) transactions.
105.It Li REQ_PF_DATA_RD
106Counts the number of data cacheline reads generated by L2 prefetchers.
107.It Li REQ_PF_RFO
108Counts the number of RFO requests generated by L2 prefetchers.
109.It Li REQ_PF_IFETCH
110Counts the number of code reads generated by L2 prefetchers.
111.It Li REQ_PF_LLC_DATA_RD
112L2 prefetcher to L3 for loads.
113.It Li REQ_PF_LLC_RFO
114RFO requests generated by L2 prefetcher
115.It Li REQ_PF_LLC_IFETCH
116L2 prefetcher to L3 for instruction fetches.
117.It Li REQ_BUS_LOCKS
118Bus lock and split lock requests.
119.It Li REQ_STRM_ST
120Streaming store requests.
121.It Li REQ_OTHER
122Any other request that crosses IDI, including I/O.
123.It Li RES_ANY
124Catch all value for any response types.
125.It Li RES_SUPPLIER_NO_SUPP
126No Supplier Information available.
127.It Li RES_SUPPLIER_LLC_HITM
128M-state initial lookup stat in L3.
129.It Li RES_SUPPLIER_LLC_HITE
130E-state.
131.It Li RES_SUPPLIER_LLC_HITS
132S-state.
133.It Li RES_SUPPLIER_LLC_HITF
134F-state.
135.It Li RES_SUPPLIER_LOCAL
136Local DRAM Controller.
137.It Li RES_SNOOP_SNP_NONE
138No details on snoop-related information.
139.It Li RES_SNOOP_SNP_NO_NEEDED
140No snoop was needed to satisfy the request.
141.It Li RES_SNOOP_SNP_MISS
142A snoop was needed and it missed all snooped caches:
143-For LLC Hit, ReslHitl was returned by all cores
144-For LLC Miss, Rspl was returned by all sockets and data was returned from
145DRAM.
146.It Li RES_SNOOP_HIT_NO_FWD
147A snoop was needed and it hits in at least one snooped cache. Hit denotes a
148cache-line was valid before snoop effect. This includes:
149-Snoop Hit w/ Invalidation (LLC Hit, RFO)
150-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
151-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
152In the LLC Miss case, data is returned from DRAM.
153.It Li RES_SNOOP_HIT_FWD
154A snoop was needed and data was forwarded from a remote socket.
155This includes:
156-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
157.It Li RES_SNOOP_HITM
158A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
159cache-line was in modified state before effect as a results of snoop. This
160includes:
161-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
162-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
163-Snoop MtoS (LLC Hit, IFetch/Data_RD).
164.It Li RES_NON_DRAM
165Target was non-DRAM system address. This includes MMIO transactions.
166.El
167.It Li cmask= Ns Ar value
168Configure the PMC to increment only if the number of configured
169events measured in a cycle is greater than or equal to
170.Ar value .
171.It Li edge
172Configure the PMC to count the number of de-asserted to asserted
173transitions of the conditions expressed by the other qualifiers.
174If specified, the counter will increment only once whenever a
175condition becomes true, irrespective of the number of clocks during
176which the condition remains true.
177.It Li inv
178Invert the sense of comparison when the
179.Dq Li cmask
180qualifier is present, making the counter increment when the number of
181events per cycle is less than the value specified by the
182.Dq Li cmask
183qualifier.
184.It Li os
185Configure the PMC to count events happening at processor privilege
186level 0.
187.It Li usr
188Configure the PMC to count events occurring at privilege levels 1, 2
189or 3.
190.El
191.Pp
192If neither of the
193.Dq Li os
194or
195.Dq Li usr
196qualifiers are specified, the default is to enable both.
197.Ss Event Specifiers (Programmable PMCs)
198Ivy Bridge programmable PMCs support the following events:
199.Bl -tag -width indent
200.It Li LD_BLOCKS.STORE_FORWARD
201.Pq Event 03H , Umask 02H
202loads blocked by overlapping with store buffer that cannot be forwarded .
203.It Li MISALIGN_MEM_REF.LOADS
204.Pq Event 05H , Umask 01H
205Speculative cache-line split load uops dispatched to L1D.
206.It Li MISALIGN_MEM_REF.STORES
207.Pq Event 05H , Umask 02H
208Speculative cache-line split Store- address uops dispatched to L1D.
209.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
210.Pq Event 07H , Umask 01H
211False dependencies in MOB due to partial compare on address.
212.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK
213.Pq Event 08H , Umask 81H
214Misses in all TLB levels that cause a page walk of any page size from demand loads.
215.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED
216.Pq Event 08H , Umask 82H
217Misses in all TLB levels that caused page walk completed of any size by demand loads.
218.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION
219.Pq Event 08H , Umask 84H
220Cycle PMH is busy with a walk due to demand loads.
221.It Li UOPS_ISSUED.ANY
222.Pq Event 0EH , Umask 01H
223Increments each cycle the # of Uops issued by the RAT to RS.
224Set Cmask = 1, Inv = 1to count stalled cycles.
225Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
226.It Li UOPS_ISSUED.FLAGS_MERGE
227.Pq Event 0EH , Umask 10H
228Number of flags-merge uops allocated. Such uops adds delay.
229.It Li UOPS_ISSUED.SLOW_LEA
230.Pq Event 0EH , Umask 20H
231Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2
232sources + immediate) regardless if as a result of LEA instruction or not.
233.It Li UOPS_ISSUED.SINGLE_MUL
234.Pq Event 0EH , Umask 40H
235Number of multiply packed/scalar single precision uops allocated.
236.It Li ARITH.FPU_DIV_ACTIVE
237.Pq Event 14H , Umask 01H
238Cycles that the divider is active, includes INT and FP. Set 'edge =1,
239cmask=1' to count the number of divides.
240.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
241.Pq Event 24H , Umask 01H
242Demand Data Read requests that hit L2 cache.
243.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
244.Pq Event 24H , Umask 03H
245Counts any demand and L1 HW prefetch data load requests to L2.
246.It Li L2_RQSTS.RFO_HITS
247.Pq Event 24H , Umask 04H
248Counts the number of store RFO requests that hit the L2 cache.
249.It Li L2_RQSTS.RFO_MISS
250.Pq Event 24H , Umask 08H
251Counts the number of store RFO requests that miss the L2 cache.
252.It Li L2_RQSTS.ALL_RFO
253.Pq Event 24H , Umask 0CH
254Counts all L2 store RFO requests.
255.It Li L2_RQSTS.CODE_RD_HIT
256.Pq Event 24H , Umask 10H
257Number of instruction fetches that hit the L2 cache.
258.It Li L2_RQSTS.CODE_RD_MISS
259.Pq Event 24H , Umask 20H
260Number of instruction fetches that missed the L2 cache.
261.It Li L2_RQSTS.ALL_CODE_RD
262.Pq Event 24H , Umask 30H
263Counts all L2 code requests.
264.It Li L2_RQSTS.PF_HIT
265.Pq Event 24H , Umask 40H
266Counts all L2 HW prefetcher requests that hit L2.
267.It Li L2_RQSTS.PF_MISS
268.Pq Event 24H , Umask 80H
269Counts all L2 HW prefetcher requests that missed L2.
270.It Li L2_RQSTS.ALL_PF
271.Pq Event 24H , Umask C0H
272Counts all L2 HW prefetcher requests.
273.It Li L2_STORE_LOCK_RQSTS.MISS
274.Pq Event 27H , Umask 01H
275RFOs that miss cache lines.
276.It Li L2_STORE_LOCK_RQSTS.HIT_M
277.Pq Event 27H , Umask 08H
278RFOs that hit cache lines in M state.
279.It Li L2_STORE_LOCK_RQSTS.ALL
280.Pq Event 27H , Umask 0FH
281RFOs that access cache lines in any state.
282.It Li L2_L1D_WB_RQSTS.MISS
283.Pq Event 28H , Umask 01H
284Not rejected writebacks that missed LLC.
285.It Li L2_L1D_WB_RQSTS.HIT_E
286.Pq Event 28H , Umask 04H
287Not rejected writebacks from L1D to L2 cache lines in E state.
288.It Li L2_L1D_WB_RQSTS.HIT_M
289.Pq Event 28H , Umask 08H
290Not rejected writebacks from L1D to L2 cache lines in M state.
291.It Li L2_L1D_WB_RQSTS.ALL
292.Pq Event 28H , Umask 0FH
293Not rejected writebacks from L1D to L2 cache lines in any state.
294.It Li LONGEST_LAT_CACHE.REFERENCE
295.Pq Event 2EH , Umask 4FH
296This event counts requests originating from the core that reference a cache
297line in the last level cache.
298.It Li LONGEST_LAT_CACHE.MISS
299.Pq Event 2EH , Umask 41H
300This event counts each cache miss condition for references to the last level
301cache.
302.It Li CPU_CLK_UNHALTED.THREAD_P
303.Pq Event 3CH , Umask 00H
304Counts the number of thread cycles while the thread is not in a halt state.
305The thread enters the halt state when it is running the HLT instruction. The
306core frequency may change from time to time due to power or thermal
307throttling.
308.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
309.Pq Event 3CH , Umask 01H
310Increments at the frequency of XCLK (100 MHz) when not halted.
311.It Li L1D_PEND_MISS.PENDING
312.Pq Event 48H , Umask 01H
313Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1
314and Edge =1 to count occurrences.
315Counter 2 only.
316Set Cmask = 1 to count cycles.
317.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
318.Pq Event 49H , Umask 01H
319Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G).
320.It Li DTLB_STORE_MISSES.WALK_COMPLETED
321.Pq Event 49H , Umask 02H
322Miss in all TLB levels causes a page walk that completes of any page size
323(4K/2M/4M/1G).
324.It Li DTLB_STORE_MISSES.WALK_DURATION
325.Pq Event 49H , Umask 04H
326Cycles PMH is busy with this walk.
327.It Li DTLB_STORE_MISSES.STLB_HIT
328.Pq Event 49H , Umask 10H
329Store operations that miss the first TLB level but hit the second and do not
330cause page walks.
331.It Li LOAD_HIT_PRE.SW_PF
332.Pq Event 4CH , Umask 01H
333Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
334.It Li LOAD_HIT_PRE.HW_PF
335.Pq Event 4CH , Umask 02H
336Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
337.It Li L1D.REPLACEMENT
338.Pq Event 51H , Umask 01H
339Counts the number of lines brought into the L1 data cache.
340.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
341.Pq Event 58H , Umask 01H
342Number of integer Move Elimination candidate uops that were not eliminated.
343.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED
344.Pq Event 58H , Umask 02H
345Number of SIMD Move Elimination candidate uops that were not eliminated.
346.It Li MOVE_ELIMINATION.INT_ELIMINATED
347.Pq Event 58H , Umask 04H
348Number of integer Move Elimination candidate uops that were eliminated.
349.It Li MOVE_ELIMINATION.SIMD_ELIMINATED
350.Pq Event 58H , Umask 08H
351Number of SIMD Move Elimination candidate uops that were eliminated.
352.It Li CPL_CYCLES.RING0
353.Pq Event 5CH , Umask 01H
354Unhalted core cycles when the thread is in ring 0.
355Use Edge to count transition.
356.It Li CPL_CYCLES.RING123
357.Pq Event 5CH , Umask 02H
358Unhalted core cycles when the thread is not in ring 0.
359.It Li RS_EVENTS.EMPTY_CYCLES
360.Pq Event 5EH , Umask 01H
361Cycles the RS is empty for the thread.
362.It Li TLB_ACCESS.LOAD_STLB_HIT
363.Pq Event 5FH , Umask 01H
364Counts load operations that missed 1st level DTLB but hit the 2nd level.
365.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
366.Pq Event 60H , Umask 01H
367Offcore outstanding Demand Data Read transactions in SQ to uncore. Set
368Cmask=1 to count cycles.
369.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
370.Pq Event 60H , Umask 02H
371Offcore outstanding Demand Code Read transactions in SQ to uncore. Set
372Cmask=1 to count cycles.
373.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
374.Pq Event 60H , Umask 04H
375Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to
376count cycles.
377.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
378.Pq Event 60H , Umask 08H
379Offcore outstanding cacheable data read transactions in SQ to uncore. Set
380Cmask=1 to count cycles.
381.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
382.Pq Event 63H , Umask 01H
383Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
384.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
385.Pq Event 63H , Umask 02H
386Cycles in which the L1D is locked.
387.It Li IDQ.EMPTY
388.Pq Event 79H , Umask 02H
389Counts cycles the IDQ is empty.
390.It Li IDQ.MITE_UOPS
391.Pq Event 79H , Umask 04H
392Increment each cycle # of uops delivered to IDQ from MITE path.
393Can combine Umask 04H and 20H.
394Set Cmask = 1 to count cycles.
395.It Li IDQ.DSB_UOPS
396.Pq Event 79H , Umask 08H
397Increment each cycle. # of uops delivered to IDQ from DSB path.
398Can combine Umask 08H and 10H
399Set Cmask = 1 to count cycles.
400.It Li IDQ.MS_DSB_UOPS
401.Pq Event 79H , Umask 10H
402Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set
403Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.
404Can combine Umask 04H, 08H.
405.It Li IDQ.MS_MITE_UOPS
406.Pq Event 79H , Umask 20H
407Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set
408Cmask = 1 to count cycles.
409Can combine Umask 04H, 08H.
410.It Li IDQ.MS_UOPS
411.Pq Event 79H , Umask 30H
412Increment each cycle # of uops delivered to IDQ from MS by either DSB or
413MITE. Set Cmask = 1 to count cycles.
414Can combine Umask 04H, 08H.
415.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
416.Pq Event 79H , Umask 18H
417Counts cycles DSB is delivered at least one uops. Set Cmask = 1.
418.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
419.Pq Event 79H , Umask 18H
420Counts cycles DSB is delivered four uops. Set Cmask = 4.
421.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
422.Pq Event 79H , Umask 24H
423Counts cycles MITE is delivered at least one uops. Set Cmask = 1.
424.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
425.Pq Event 79H , Umask 24H
426Counts cycles MITE is delivered four uops. Set Cmask = 4.
427.It Li IDQ.MITE_ALL_UOPS
428.Pq Event 79H , Umask 3CH
429# of uops delivered to IDQ from any path.
430.It Li ICACHE.MISSES
431.Pq Event 80H , Umask 02H
432Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
433Includes UC accesses.
434.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
435.Pq Event 85H , Umask 01H
436Misses in all ITLB levels that cause page walks.
437.It Li ITLB_MISSES.WALK_COMPLETED
438.Pq Event 85H , Umask 02H
439Misses in all ITLB levels that cause completed page walks.
440.It Li ITLB_MISSES.WALK_DURATION
441.Pq Event 85H , Umask 04H
442Cycle PMH is busy with a walk.
443.It Li ITLB_MISSES.STLB_HIT
444.Pq Event 85H , Umask 10H
445Number of cache load STLB hits. No page walk.
446.It Li ILD_STALL.LCP
447.Pq Event 87H , Umask 01H
448Stalls caused by changing prefix length of the instruction.
449.It Li ILD_STALL.IQ_FULL
450.Pq Event 87H , Umask 04H
451Stall cycles due to IQ is full.
452.It Li BR_INST_EXEC.NONTAKEN_COND
453.Pq Event 88H , Umask 41H
454Count conditional near branch instructions that were executed (but not
455necessarily retired) and not taken.
456.It Li BR_INST_EXEC.TAKEN_COND
457.Pq Event 88H , Umask 81H
458Count conditional near branch instructions that were executed (but not
459necessarily retired) and taken.
460.It Li BR_INST_EXEC.DIRECT_JMP
461.Pq Event 88H , Umask 82H
462Count all unconditional near branch instructions excluding calls and
463indirect branches.
464.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
465.Pq Event 88H , Umask 84H
466Count executed indirect near branch instructions that are not calls nor
467returns.
468.It Li BR_INST_EXEC.RETURN_NEAR
469.Pq Event 88H , Umask 88H
470Count indirect near branches that have a return mnemonic.
471.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
472.Pq Event 88H , Umask 90H
473Count unconditional near call branch instructions, excluding non call
474branch, executed.
475.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
476.Pq Event 88H , Umask A0H
477Count indirect near calls, including both register and memory indirect,
478executed.
479.It Li BR_INST_EXEC.ALL_BRANCHES
480.Pq Event 88H , Umask FFH
481Counts all near executed branches (not necessarily retired).
482.It Li BR_MISP_EXEC.NONTAKEN_COND
483.Pq Event 89H , Umask 41H
484Count conditional near branch instructions mispredicted as nontaken.
485.It Li BR_MISP_EXEC.TAKEN_COND
486.Pq Event 89H , Umask 81H
487Count conditional near branch instructions mispredicted as taken.
488.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
489.Pq Event 89H , Umask 84H
490Count mispredicted indirect near branch instructions that are not calls
491nor returns.
492.It Li BR_MISP_EXEC.RETURN_NEAR
493.Pq Event 89H , Umask 88H
494Count mispredicted indirect near branches that have a return mnemonic.
495.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
496.Pq Event 89H , Umask 90H
497Count mispredicted unconditional near call branch instructions, excluding
498non call branch, executed.
499.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
500.Pq Event 89H , Umask A0H
501Count mispredicted indirect near calls, including both register and memory
502indirect, executed.
503.It Li BR_MISP_EXEC.ALL_BRANCHES
504.Pq Event 89H , Umask FFH
505Counts all mispredicted near executed branches (not necessarily retired).
506.It Li IDQ_UOPS_NOT_DELIVERED.CORE
507.Pq Event 9CH , Umask 01H
508Count number of non-delivered uops to RAT per thread.
509Use Cmask to qualify uop b/w.
510.It Li UOPS_DISPATCHED_PORT.PORT_0
511.Pq Event A1H , Umask 01H
512Cycles which a Uop is dispatched on port 0.
513.It Li UOPS_DISPATCHED_PORT.PORT_1
514.Pq Event A1H , Umask 02H
515Cycles which a Uop is dispatched on port 1.
516.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
517.Pq Event A1H , Umask 04H
518Cycles which a load uop is dispatched on port 2.
519.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
520.Pq Event A1H , Umask 08H
521Cycles which a store address uop is dispatched on port 2.
522.It Li UOPS_DISPATCHED_PORT.PORT_2
523.Pq Event A1H , Umask 0CH
524Cycles which a Uop is dispatched on port 2.
525.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
526.Pq Event A1H , Umask 10H
527Cycles which a load uop is dispatched on port 3.
528.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
529.Pq Event A1H , Umask 20H
530Cycles which a store address uop is dispatched on port 3.
531.It Li UOPS_DISPATCHED_PORT.PORT_3
532.Pq Event A1H , Umask 30H
533Cycles which a Uop is dispatched on port 3.
534.It Li UOPS_DISPATCHED_PORT.PORT_4
535.Pq Event A1H , Umask 40H
536Cycles which a Uop is dispatched on port 4.
537.It Li UOPS_DISPATCHED_PORT.PORT_5
538.Pq Event A1H , Umask 80H
539Cycles which a Uop is dispatched on port 5.
540.It Li RESOURCE_STALLS.ANY
541.Pq Event A2H , Umask 01H
542Cycles Allocation is stalled due to Resource Related reason.
543.It Li RESOURCE_STALLS.RS
544.Pq Event A2H , Umask 04H
545Cycles stalled due to no eligible RS entry available.
546.It Li RESOURCE_STALLS.SB
547.Pq Event A2H , Umask 08H
548Cycles stalled due to no store buffers available. (not including draining
549form sync).
550.It Li RESOURCE_STALLS.ROB
551.Pq Event A2H , Umask 10H
552Cycles stalled due to re-order buffer full.
553.It Li DSB2MITE_SWITCHES.COUNT
554.Pq Event ABH , Umask 01H
555Number of DSB to MITE switches.
556.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
557.Pq Event ABH , Umask 02H
558Cycles DSB to MITE switches caused delay.
559.It Li DSB_FILL.EXCEED_DSB_LINES
560.Pq Event ACH , Umask 08H
561DSB Fill encountered > 3 DSB lines.
562.It Li ITLB.ITLB_FLUSH
563.Pq Event AEH , Umask 01H
564Counts the number of ITLB flushes, includes 4k/2M/4M pages.
565.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
566.Pq Event B0H , Umask 01H
567Demand data read requests sent to uncore.
568.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
569.Pq Event B0H , Umask 02H
570Demand code read requests sent to uncore.
571.It Li OFFCORE_REQUESTS.DEMAND_RFO
572.Pq Event B0H , Umask 04H
573Demand RFO read requests sent to uncore, including regular RFOs, locks,
574ItoM.
575.It Li OFFCORE_REQUESTS.ALL_DATA_RD
576.Pq Event B0H , Umask 08H
577Data read requests sent to uncore (demand and prefetch).
578.It Li UOPS_EXECUTED.THREAD
579.Pq Event B1H , Umask 01H
580Counts total number of uops to be executed per-thread each cycle. Set Cmask
581= 1, INV =1 to count stall cycles.
582.It Li UOPS_EXECUTED.CORE
583.Pq Event B1H , Umask 02H
584Counts total number of uops to be executed per-core each cycle.
585Do not need to set ANY.
586.It Li OFF_CORE_RESPONSE_0
587.Pq Event B7H , Umask 01H
588Off-core Response Performance Monitoring.
589PMC0 only.
590Requires programming MSR 01A6H.
591.It Li OFF_CORE_RESPONSE_1
592.Pq Event BBH , Umask 01H
593Off-core Response Performance Monitoring.
594PMC3 only.
595Requires programming MSR 01A7H.
596.It Li TLB_FLUSH.DTLB_THREAD
597.Pq Event BDH , Umask 01H
598DTLB flush attempts of the thread- specific entries.
599.It Li TLB_FLUSH.STLB_ANY
600.Pq Event BDH , Umask 20H
601Count number of STLB flush attempts.
602.It Li INST_RETIRED.ANY_P
603.Pq Event C0H , Umask 00H
604Number of instructions at retirement.
605.It Li INST_RETIRED.ALL
606.Pq Event C0H , Umask 01H
607Precise instruction retired event with HW to reduce effect of PEBS shadow in
608IP distribution.
609PMC1 only.
610Must quiesce other PMCs.
611.It Li OTHER_ASSISTS.AVX_STORE
612.Pq Event C1H , Umask 08H
613Number of assists associated with 256-bit AVX store operations.
614.It Li OTHER_ASSISTS.AVX_TO_SSE
615.Pq Event C1H , Umask 10H
616Number of transitions from AVX- 256 to legacy SSE when penalty applicable.
617.It Li OTHER_ASSISTS.SSE_TO_AVX
618.Pq Event C1H , Umask 20H
619Number of transitions from SSE to AVX-256 when penalty applicable.
620.It Li UOPS_RETIRED.ALL
621.Pq Event C2H , Umask 01H
622Counts the number of micro-ops retired, Use cmask=1 and invert to count
623active cycles or stalled cycles.
624Supports PEBS, use Any=1 for core granular.
625.It Li UOPS_RETIRED.RETIRE_SLOTS
626.Pq Event C2H , Umask 02H
627Counts the number of retirement slots used each cycle.
628.It Li MACHINE_CLEARS.MEMORY_ORDERING
629.Pq Event C3H , Umask 02H
630Counts the number of machine clears due to memory order conflicts.
631.It Li MACHINE_CLEARS.SMC
632.Pq Event C3H , Umask 04H
633Number of self-modifying-code machine clears detected.
634.It Li MACHINE_CLEARS.MASKMOV
635.Pq Event C3H , Umask 20H
636Counts the number of executed AVX masked load operations that refer to an
637illegal address range with the mask bits set to 0.
638.It Li BR_INST_RETIRED.ALL_BRANCHES
639.Pq Event C4H , Umask 00H
640Branch instructions at retirement.
641.It Li BR_INST_RETIRED.CONDITIONAL
642.Pq Event C4H , Umask 01H
643Counts the number of conditional branch instructions retired.
644Supports PEBS.
645.It Li BR_INST_RETIRED.NEAR_CALL
646.Pq Event C4H , Umask 02H
647Direct and indirect near call instructions retired.
648.It Li BR_INST_RETIRED.ALL_BRANCHES
649.Pq Event C4H , Umask 04H
650Counts the number of branch instructions retired.
651.It Li BR_INST_RETIRED.NEAR_RETURN
652.Pq Event C4H , Umask 08H
653Counts the number of near return instructions retired.
654.It Li BR_INST_RETIRED.NOT_TAKEN
655.Pq Event C4H , Umask 10H
656Counts the number of not taken branch instructions retired.
657.It Li BR_INST_RETIRED.NEAR_TAKEN
658.Pq Event C4H , Umask 20H
659Number of near taken branches retired.
660.It Li BR_INST_RETIRED.FAR_BRANCH
661.Pq Event C4H , Umask 40H
662Number of far branches retired.
663.It Li BR_MISP_RETIRED.ALL_BRANCHES
664.Pq Event C5H , Umask 00H
665Mispredicted branch instructions at retirement.
666.It Li BR_MISP_RETIRED.CONDITIONAL
667.Pq Event C5H , Umask 01H
668Mispredicted conditional branch instructions retired.
669Supports PEBS.
670.It Li BR_MISP_RETIRED.NEAR_CALL
671.Pq Event C5H , Umask 02H
672Direct and indirect mispredicted near call instructions retired.
673.It Li BR_MISP_RETIRED.ALL_BRANCHES
674.Pq Event C5H , Umask 04H
675Mispredicted macro branch instructions retired.
676.It Li BR_MISP_RETIRED.NOT_TAKEN
677.Pq Event C5H , Umask 10H
678Mispredicted not taken branch instructions retired.
679.It Li BR_MISP_RETIRED.TAKEN
680.Pq Event C5H , Umask 20H
681Mispredicted taken branch instructions retired.
682.It Li FP_ASSIST.X87_OUTPUT
683.Pq Event CAH , Umask 02H
684Number of X87 FP assists due to Output values.
685.It Li FP_ASSIST.X87_INPUT
686.Pq Event CAH , Umask 04H
687Number of X87 FP assists due to input values.
688.It Li FP_ASSIST.SIMD_OUTPUT
689.Pq Event CAH , Umask 08H
690Number of SIMD FP assists due to Output values.
691.It Li FP_ASSIST.SIMD_INPUT
692.Pq Event CAH , Umask 10H
693Number of SIMD FP assists due to input values.
694.It Li FP_ASSIST.ANY
695.Pq Event CAH , Umask 1EH
696Cycles with any input/output SSE* or FP assists.
697.It Li ROB_MISC_EVENTS.LBR_INSERTS
698.Pq Event CCH , Umask 20H
699Count cases of saving new LBR records by hardware.
700.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
701.Pq Event CDH , Umask 01H
702Sample loads with specified latency threshold.
703PMC3 only.
704Specify threshold in MSR 0x3F6.
705.It Li MEM_TRANS_RETIRED.PRECISE_STORE
706.Pq Event CDH , Umask 02H
707Sample stores and collect precise store operation via PEBS record.
708PMC3 only.
709.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
710.Pq Event D0H , Umask 11H
711Count retired load uops that missed the STLB.
712.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
713.Pq Event D0H , Umask 12H
714Count retired store uops that missed the STLB.
715.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
716.Pq Event D0H , Umask 41H
717Count retired load uops that were split across a cache line.
718.It Li MEM_UOPS_RETIRED.SPLIT_STORES
719.Pq Event D0H , Umask 42H
720Count retired store uops that were split across a cache line.
721.It Li MEM_UOPS_RETIRED.ALL_LOADS
722.Pq Event D0H , Umask 81H
723Count all retired load uops.
724.It Li MEM_UOPS_RETIRED.ALL_STORES
725.Pq Event D0H , Umask 82H
726Count all retired store uops.
727.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
728.Pq Event D1H , Umask 01H
729Retired load uops with L1 cache hits as data sources.
730Supports PEBS.
731.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
732.Pq Event D1H , Umask 02H
733Retired load uops with L2 cache hits as data sources.
734.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
735.Pq Event D1H , Umask 04H
736Retired load uops with LLC cache hits as data sources.
737.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
738.Pq Event D1H , Umask 40H
739Retired load uops which data sources were load uops missed L1 but hit FB due
740to preceding miss to the same cache line with data not ready.
741.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
742.Pq Event D2H , Umask 01H
743Retired load uops which data sources were LLC hit and cross-core snoop
744missed in on-pkg core cache.
745Supports PEBS.
746.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
747.Pq Event D2H , Umask 02H
748Retired load uops which data sources were LLC and cross-core snoop hits in
749on-pkg core cache.
750Supports PEBS.
751.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
752.Pq Event D2H , Umask 04H
753Retired load uops which data sources were HitM responses from shared LLC.
754.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
755.Pq Event D2H , Umask 08H
756Retired load uops which data sources were hits in LLC without snoops
757required.
758.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
759.Pq Event D3H , Umask 01H
760Retired load uops which data sources missed LLC but serviced from local
761dram.
762Supports PEBS.
763.It Li L2_TRANS.DEMAND_DATA_RD
764.Pq Event F0H , Umask 01H
765Demand Data Read requests that access L2 cache.
766.It Li L2_TRANS.RFO
767.Pq Event F0H , Umask 02H
768RFO requests that access L2 cache.
769.It Li L2_TRANS.CODE_RD
770.Pq Event F0H , Umask 04H
771L2 cache accesses when fetching instructions.
772.It Li L2_TRANS.ALL_PF
773.Pq Event F0H , Umask 08H
774Any MLC or LLC HW prefetch accessing L2, including rejects.
775.It Li L2_TRANS.L1D_WB
776.Pq Event F0H , Umask 10H
777L1D writebacks that access L2 cache.
778.It Li L2_TRANS.L2_FILL
779.Pq Event F0H , Umask 20H
780L2 fill requests that access L2 cache.
781.It Li L2_TRANS.L2_WB
782.Pq Event F0H , Umask 40H
783L2 writebacks that access L2 cache.
784.It Li L2_TRANS.ALL_REQUESTS
785.Pq Event F0H , Umask 80H
786Transactions accessing L2 pipe.
787.It Li L2_LINES_IN.I
788.Pq Event F1H , Umask 01H
789L2 cache lines in I state filling L2.
790Counting does not cover rejects.
791.It Li L2_LINES_IN.S
792.Pq Event F1H , Umask 02H
793L2 cache lines in S state filling L2.
794Counting does not cover rejects.
795.It Li L2_LINES_IN.E
796.Pq Event F1H , Umask 04H
797L2 cache lines in E state filling L2.
798Counting does not cover rejects.
799.It Li L2_LINES_IN.ALL
800.Pq Event F1H , Umask 07H
801L2 cache lines filling L2.
802Counting does not cover rejects.
803.It Li L2_LINES_OUT.DEMAND_CLEAN
804.Pq Event F2H , Umask 01H
805Clean L2 cache lines evicted by demand.
806.It Li L2_LINES_OUT.DEMAND_DIRTY
807.Pq Event F2H , Umask 02H
808Dirty L2 cache lines evicted by demand.
809.It Li L2_LINES_OUT.PF_CLEAN
810.Pq Event F2H , Umask 04H
811Clean L2 cache lines evicted by the MLC prefetcher.
812.It Li L2_LINES_OUT.PF_DIRTY
813.Pq Event F2H , Umask 08H
814Dirty L2 cache lines evicted by the MLC prefetcher.
815.El
816.Sh SEE ALSO
817.Xr pmc 3 ,
818.Xr pmc.atom 3 ,
819.Xr pmc.core 3 ,
820.Xr pmc.corei7 3 ,
821.Xr pmc.corei7uc 3 ,
822.Xr pmc.iaf 3 ,
823.Xr pmc.ivybridgexeon 3 ,
824.Xr pmc.k7 3 ,
825.Xr pmc.k8 3 ,
826.Xr pmc.p4 3 ,
827.Xr pmc.p5 3 ,
828.Xr pmc.p6 3 ,
829.Xr pmc.sandybridge 3 ,
830.Xr pmc.sandybridgeuc 3 ,
831.Xr pmc.sandybridgexeon 3 ,
832.Xr pmc.soft 3 ,
833.Xr pmc.tsc 3 ,
834.Xr pmc.ucf 3 ,
835.Xr pmc.westmere 3 ,
836.Xr pmc.westmereuc 3 ,
837.Xr pmc_cpuinfo 3 ,
838.Xr pmclog 3 ,
839.Xr hwpmc 4
840.Sh HISTORY
841The
842.Nm pmc
843library first appeared in
844.Fx 6.0 .
845.Sh AUTHORS
846.An -nosplit
847The
848.Lb libpmc
849library was written by
850.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
851The support for the Ivy Bridge
852microarchitecture was written by
853.An Fabien Thomas Aq Mt fabient@FreeBSD.org .
854