1.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd March 22, 2013 28.Dt PMC.HASWELLUC 3 29.Os 30.Sh NAME 31.Nm pmc.haswelluc 32.Nd uncore measurement events for 33.Tn Intel 34.Tn Haswell 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Haswell" 43CPUs contain PMCs conforming to version 3 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs contain two classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_UCP" 48.It Li PMC_CLASS_UCF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_UCP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.El 54.Pp 55The number of PMCs available in each class and their widths need to be 56determined at run time by calling 57.Xr pmc_cpuinfo 3 . 58.Pp 59Intel Haswell PMCs are documented in 60.Rs 61.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 62.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" 63.%N "Order Number: 325462-045US" 64.%D January 2013 65.%Q "Intel Corporation" 66.Re 67.Ss HASWELL UNCORE FIXED FUNCTION PMCS 68These PMCs and their supported events are documented in 69.Xr pmc.ucf 3 . 70Not all CPUs in this family implement fixed-function counters. 71.Ss HASWELL UNCORE PROGRAMMABLE PMCS 72The programmable PMCs support the following capabilities: 73.Bl -column "PMC_CAP_INTERRUPT" "Support" 74.It Em Capability Ta Em Support 75.It PMC_CAP_CASCADE Ta \&No 76.It PMC_CAP_EDGE Ta Yes 77.It PMC_CAP_INTERRUPT Ta \&No 78.It PMC_CAP_INVERT Ta Yes 79.It PMC_CAP_READ Ta Yes 80.It PMC_CAP_PRECISE Ta \&No 81.It PMC_CAP_SYSTEM Ta \&No 82.It PMC_CAP_TAGGING Ta \&No 83.It PMC_CAP_THRESHOLD Ta Yes 84.It PMC_CAP_USER Ta \&No 85.It PMC_CAP_WRITE Ta Yes 86.El 87.Ss Event Qualifiers 88Event specifiers for these PMCs support the following common 89qualifiers: 90.Bl -tag -width indent 91.It Li cmask= Ns Ar value 92Configure the PMC to increment only if the number of configured 93events measured in a cycle is greater than or equal to 94.Ar value . 95.It Li edge 96Configure the PMC to count the number of de-asserted to asserted 97transitions of the conditions expressed by the other qualifiers. 98If specified, the counter will increment only once whenever a 99condition becomes true, irrespective of the number of clocks during 100which the condition remains true. 101.It Li inv 102Invert the sense of comparison when the 103.Dq Li cmask 104qualifier is present, making the counter increment when the number of 105events per cycle is less than the value specified by the 106.Dq Li cmask 107qualifier. 108.El 109.Ss Event Specifiers (Programmable PMCs) 110Haswell programmable PMCs support the following events: 111.Bl -tag -width indent 112.It Li UNC_CBO_XSNP_RESPONSE.MISS 113.Pq Event 22H , Umask 01H 114A snoop misses in some processor core. 115.It Li UNC_CBO_XSNP_RESPONSE.INVAL 116.Pq Event 22H , Umask 02H 117A snoop invalidates a non-modified line in some 118processor core. 119.It Li UNC_CBO_XSNP_RESPONSE.HIT 120.Pq Event 22H , Umask 04H 121A snoop hits a non-modified line in some processor 122core. 123.It Li UNC_CBO_XSNP_RESPONSE.HITM 124.Pq Event 22H , Umask 08H 125A snoop hits a modified line in some processor core. 126.It Li UNC_CBO_XSNP_RESPONSE.INVAL_M 127.Pq Event 22H , Umask 10H 128A snoop invalidates a modified line in some processor 129core. 130.It Li UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER 131.Pq Event 22H , Umask 20H 132Filter on cross-core snoops initiated by this Cbox due 133to external snoop request. 134.It Li UNC_CBO_XSNP_RESPONSE.XCORE_FILTER 135.Pq Event 22H , Umask 40H 136Filter on cross-core snoops initiated by this Cbox due 137to processor core memory request. 138.It Li UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER 139.Pq Event 22H , Umask 80H 140Filter on cross-core snoops initiated by this Cbox due 141to LLC eviction. 142.It Li UNC_CBO_CACHE_LOOKUP.M 143.Pq Event 34H , Umask 01H 144LLC lookup request that access cache and found line in 145M-state. 146.It Li UNC_CBO_CACHE_LOOKUP.ES 147.Pq Event 34H , Umask 06H 148LLC lookup request that access cache and found line in 149E or S state. 150.It Li UNC_CBO_CACHE_LOOKUP.I 151.Pq Event 34H , Umask 08H 152LLC lookup request that access cache and found line in 153I-state. 154.It Li UNC_CBO_CACHE_LOOKUP.READ_FILTER 155.Pq Event 34H , Umask 10H 156Filter on processor core initiated cacheable read 157requests. Must combine with at least one of 01H, 02H, 15804H, 08H. 159.It Li UNC_CBO_CACHE_LOOKUP.WRITE_FILTER 160.Pq Event 34H , Umask 20H 161Filter on processor core initiated cacheable write 162requests. Must combine with at least one of 01H, 02H, 16304H, 08H. 164.It Li UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER 165.Pq Event 34H , Umask 40H 166Filter on external snoop requests. Must combine with 167at least one of 01H, 02H, 04H, 08H. 168.It Li UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER 169.Pq Event 34H , Umask 80H 170Filter on any IRQ or IPQ initiated requests including 171uncacheable, non-coherent requests. Must combine 172with at least one of 01H, 02H, 04H, 08H. 173.It Li UNC_ARB_TRK_OCCUPANCY.ALL 174.Pq Event 80H , Umask 01H 175Counts cycles weighted by the number of requests 176waiting for data returning from the memory controller. 177Accounts for coherent and non-coherent requests 178initiated by IA cores, processor graphic units, or LLC. 179.It Li UNC_ARB_TRK_REQUEST.ALL 180.Pq Event 81H , Umask 01H 181Counts the number of coherent and in-coherent 182requests initiated by IA cores, processor graphic units, 183or LLC. 184.It Li UNC_ARB_TRK_REQUEST.WRITES 185.Pq Event 81H , Umask 20H 186Counts the number of allocated write entries, include 187full, partial, and LLC evictions. 188.It Li UNC_ARB_TRK_REQUEST.EVICTIONS 189.Pq Event 81H , Umask 80H 190Counts the number of LLC evictions allocated. 191.It Li UNC_ARB_COH , Umask TRK_OCCUPANCY.ALL 192.Pq Event 83H , Umask 01H 193Cycles weighted by number of requests pending in 194Coherency Tracker. 195.It Li UNC_ARB_COH , Umask TRK_REQUEST.ALL 196.Pq Event 84H , Umask 01H 197Number of requests allocated in Coherency Tracker. 198.El 199.Sh SEE ALSO 200.Xr pmc 3 , 201.Xr pmc.atom 3 , 202.Xr pmc.core 3 , 203.Xr pmc.corei7 3 , 204.Xr pmc.corei7uc 3 , 205.Xr pmc.haswell 3 , 206.Xr pmc.iaf 3 , 207.Xr pmc.k7 3 , 208.Xr pmc.k8 3 , 209.Xr pmc.p4 3 , 210.Xr pmc.p5 3 , 211.Xr pmc.p6 3 , 212.Xr pmc.sandybridge 3 , 213.Xr pmc.sandybridgeuc 3 , 214.Xr pmc.sandybridgexeon 3 , 215.Xr pmc.soft 3 , 216.Xr pmc.tsc 3 , 217.Xr pmc.ucf 3 , 218.Xr pmc.westmere 3 , 219.Xr pmc.westmereuc 3 , 220.Xr pmc_cpuinfo 3 , 221.Xr pmclog 3 , 222.Xr hwpmc 4 223.Sh HISTORY 224The 225.Nm pmc 226library first appeared in 227.Fx 6.0 . 228.Sh AUTHORS 229.An -nosplit 230The 231.Lb libpmc 232library was written by 233.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 234The support for the Haswell 235microarchitecture was added by 236.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 237