1.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd March 22, 2013 28.Dt PMC.HASWELL 3 29.Os 30.Sh NAME 31.Nm pmc.haswell 32.Nd measurement events for 33.Tn Intel 34.Tn Haswsell 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Haswell" 43CPUs contain PMCs conforming to version 2 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs may contain up to two classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_IAP" 48.It Li PMC_CLASS_IAF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_IAP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.El 54.Pp 55The number of PMCs available in each class and their widths need to be 56determined at run time by calling 57.Xr pmc_cpuinfo 3 . 58.Pp 59Intel Haswell PMCs are documented in 60.Rs 61.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" 63.%N "Order Number: 325462-045US" 64.%D January 2013 65.%Q "Intel Corporation" 66.Re 67.Ss HASWELL FIXED FUNCTION PMCS 68These PMCs and their supported events are documented in 69.Xr pmc.iaf 3 . 70.Ss HASWELL PROGRAMMABLE PMCS 71The programmable PMCs support the following capabilities: 72.Bl -column "PMC_CAP_INTERRUPT" "Support" 73.It Em Capability Ta Em Support 74.It PMC_CAP_CASCADE Ta \&No 75.It PMC_CAP_EDGE Ta Yes 76.It PMC_CAP_INTERRUPT Ta Yes 77.It PMC_CAP_INVERT Ta Yes 78.It PMC_CAP_READ Ta Yes 79.It PMC_CAP_PRECISE Ta \&No 80.It PMC_CAP_SYSTEM Ta Yes 81.It PMC_CAP_TAGGING Ta \&No 82.It PMC_CAP_THRESHOLD Ta Yes 83.It PMC_CAP_USER Ta Yes 84.It PMC_CAP_WRITE Ta Yes 85.El 86.Ss Event Qualifiers 87Event specifiers for these PMCs support the following common 88qualifiers: 89.Bl -tag -width indent 90.It Li rsp= Ns Ar value 91Configure the Off-core Response bits. 92.Bl -tag -width indent 93.It Li DMND_DATA_RD 94Counts the number of demand and DCU prefetch data reads of full 95and partial cachelines as well as demand data page table entry 96cacheline reads. Does not count L2 data read prefetches or 97instruction fetches. 98.It Li REQ_DMND_RFO 99Counts the number of demand and DCU prefetch reads for ownership (RFO) 100requests generated by a write to data cacheline. Does not count L2 RFO 101prefetches. 102.It Li REQ_DMND_IFETCH 103Counts the number of demand and DCU prefetch instruction cacheline reads. 104Does not count L2 code read prefetches. 105.It Li REQ_WB 106Counts the number of writeback (modified to exclusive) transactions. 107.It Li REQ_PF_DATA_RD 108Counts the number of data cacheline reads generated by L2 prefetchers. 109.It Li REQ_PF_RFO 110Counts the number of RFO requests generated by L2 prefetchers. 111.It Li REQ_PF_IFETCH 112Counts the number of code reads generated by L2 prefetchers. 113.It Li REQ_PF_LLC_DATA_RD 114L2 prefetcher to L3 for loads. 115.It Li REQ_PF_LLC_RFO 116RFO requests generated by L2 prefetcher 117.It Li REQ_PF_LLC_IFETCH 118L2 prefetcher to L3 for instruction fetches. 119.It Li REQ_BUS_LOCKS 120Bus lock and split lock requests. 121.It Li REQ_STRM_ST 122Streaming store requests. 123.It Li REQ_OTHER 124Any other request that crosses IDI, including I/O. 125.It Li RES_ANY 126Catch all value for any response types. 127.It Li RES_SUPPLIER_NO_SUPP 128No Supplier Information available. 129.It Li RES_SUPPLIER_LLC_HITM 130M-state initial lookup stat in L3. 131.It Li RES_SUPPLIER_LLC_HITE 132E-state. 133.It Li RES_SUPPLIER_LLC_HITS 134S-state. 135.It Li RES_SUPPLIER_LLC_HITF 136F-state. 137.It Li RES_SUPPLIER_LOCAL 138Local DRAM Controller. 139.It Li RES_SNOOP_SNP_NONE 140No details on snoop-related information. 141.It Li RES_SNOOP_SNP_NO_NEEDED 142No snoop was needed to satisfy the request. 143.It Li RES_SNOOP_SNP_MISS 144A snoop was needed and it missed all snooped caches: 145-For LLC Hit, ReslHitl was returned by all cores 146-For LLC Miss, Rspl was returned by all sockets and data was returned from 147DRAM. 148.It Li RES_SNOOP_HIT_NO_FWD 149A snoop was needed and it hits in at least one snooped cache. Hit denotes a 150cache-line was valid before snoop effect. This includes: 151-Snoop Hit w/ Invalidation (LLC Hit, RFO) 152-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 153-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 154In the LLC Miss case, data is returned from DRAM. 155.It Li RES_SNOOP_HIT_FWD 156A snoop was needed and data was forwarded from a remote socket. 157This includes: 158-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 159.It Li RES_SNOOP_HITM 160A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a 161cache-line was in modified state before effect as a results of snoop. This 162includes: 163-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 164-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 165-Snoop MtoS (LLC Hit, IFetch/Data_RD). 166.It Li RES_NON_DRAM 167Target was non-DRAM system address. This includes MMIO transactions. 168.El 169.It Li cmask= Ns Ar value 170Configure the PMC to increment only if the number of configured 171events measured in a cycle is greater than or equal to 172.Ar value . 173.It Li edge 174Configure the PMC to count the number of de-asserted to asserted 175transitions of the conditions expressed by the other qualifiers. 176If specified, the counter will increment only once whenever a 177condition becomes true, irrespective of the number of clocks during 178which the condition remains true. 179.It Li inv 180Invert the sense of comparison when the 181.Dq Li cmask 182qualifier is present, making the counter increment when the number of 183events per cycle is less than the value specified by the 184.Dq Li cmask 185qualifier. 186.It Li os 187Configure the PMC to count events happening at processor privilege 188level 0. 189.It Li usr 190Configure the PMC to count events occurring at privilege levels 1, 2 191or 3. 192.El 193.Pp 194If neither of the 195.Dq Li os 196or 197.Dq Li usr 198qualifiers are specified, the default is to enable both. 199.Ss Event Specifiers (Programmable PMCs) 200Haswell programmable PMCs support the following events: 201.Bl -tag -width indent 202.It Li LD_BLOCKS.STORE_FORWARD 203.Pq Event 03H , Umask 02H 204Loads blocked by overlapping with store buffer that 205cannot be forwarded. 206.It Li MISALIGN_MEM_REF.LOADS 207.Pq Event 05H , Umask 01H 208Speculative cache-line split load uops dispatched to 209L1D. 210.It Li MISALIGN_MEM_REF.STORES 211.Pq Event 05H , Umask 02H 212Speculative cache-line split Store-address uops 213dispatched to L1D. 214.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 215.Pq Event 07H , Umask 01H 216False dependencies in MOB due to partial compare 217on address. 218.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK 219.Pq Event 08H , Umask 01H 220Misses in all TLB levels that cause a page walk of any 221page size. 222.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K 223.Pq Event 08H , Umask 02H 224Completed page walks due to demand load misses 225that caused 4K page walks in any TLB levels. 226.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K 227.Pq Event 08H , Umask 02H 228Completed page walks due to demand load misses 229that caused 2M/4M page walks in any TLB levels. 230.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 231.Pq Event 08H , Umask 0EH 232Completed page walks in any TLB of any page size 233due to demand load misses 234.It Li DTLB_LOAD_MISSES.WALK_DURATION 235.Pq Event 08H , Umask 10H 236Cycle PMH is busy with a walk. 237.It Li DTLB_LOAD_MISSES.STLB_HIT_4K 238.Pq Event 08H , Umask 20H 239Load misses that missed DTLB but hit STLB (4K). 240.It Li DTLB_LOAD_MISSES.STLB_HIT_2M 241.Pq Event 08H , Umask 40H 242Load misses that missed DTLB but hit STLB (2M). 243.It Li DTLB_LOAD_MISSES.STLB_HIT 244.Pq Event 08H , Umask 60H 245Number of cache load STLB hits. No page walk. 246.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS 247.Pq Event 08H , Umask 80H 248DTLB demand load misses with low part of linear-to- 249physical address translation missed 250.It Li INT_MISC.RECOVERY_CYCLES 251.Pq Event 0DH , Umask 03H 252Cycles waiting to recover after Machine Clears 253except JEClear. Set Cmask= 1. 254.It Li UOPS_ISSUED.ANY 255.Pq Event 0EH , Umask 01H 256ncrements each cycle the # of Uops issued by the 257RAT to RS. 258Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles 259of this core. 260.It Li UOPS_ISSUED.FLAGS_MERGE 261.Pq Event 0EH , Umask 10H 262Number of flags-merge uops allocated. Such uops 263adds delay. 264.It Li UOPS_ISSUED.SLOW_LEA 265.Pq Event 0EH , Umask 20H 266Number of slow LEA or similar uops allocated. Such 267uop has 3 sources (e.g. 2 sources + immediate) 268regardless if as a result of LEA instruction or not. 269.It Li UOPS_ISSUED.SiNGLE_MUL 270.Pq Event 0EH , Umask 40H 271Number of multiply packed/scalar single precision 272uops allocated. 273.It Li L2_RQSTS.DEMAND_DATA_RD_MISS 274.Pq Event 24H , Umask 21H 275Demand Data Read requests that missed L2, no 276rejects. 277.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 278.Pq Event 24H , Umask 41H 279Demand Data Read requests that hit L2 cache. 280.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 281.Pq Event 24H , Umask E1H 282Counts any demand and L1 HW prefetch data load 283requests to L2. 284.It Li L2_RQSTS.RFO_HIT 285.Pq Event 24H , Umask 42H 286Counts the number of store RFO requests that hit 287the L2 cache. 288.It Li L2_RQSTS.RFO_MISS 289.Pq Event 24H , Umask 22H 290Counts the number of store RFO requests that miss 291the L2 cache. 292.It Li L2_RQSTS.ALL_RFO 293.Pq Event 24H , Umask E2H 294Counts all L2 store RFO requests. 295.It Li L2_RQSTS.CODE_RD_HIT 296.Pq Event 24H , Umask 44H 297Number of instruction fetches that hit the L2 cache. 298.It Li L2_RQSTS.CODE_RD_MISS 299.Pq Event 24H , Umask 24H 300Number of instruction fetches that missed the L2 301cache. 302.It Li L2_RQSTS.ALL_DEMAND_MISS 303.Pq Event 24H , Umask 27H 304Demand requests that miss L2 cache. 305.It Li L2_RQSTS.ALL_DEMAND_REFERENCES 306.Pq Event 24H , Umask E7H 307Demand requests to L2 cache. 308.It Li L2_RQSTS.ALL_CODE_RD 309.Pq Event 24H , Umask E4H 310Counts all L2 code requests. 311.It Li L2_RQSTS.L2_PF_HIT 312.Pq Event 24H , Umask 50H 313Counts all L2 HW prefetcher requests that hit L2. 314.It Li L2_RQSTS.L2_PF_MISS 315.Pq Event 24H , Umask 30H 316Counts all L2 HW prefetcher requests that missed 317L2. 318.It Li L2_RQSTS.ALL_PF 319.Pq Event 24H , Umask F8H 320Counts all L2 HW prefetcher requests. 321.It Li L2_RQSTS.MISS 322.Pq Event 24H , Umask 3FH 323All requests that missed L2. 324.It Li L2_RQSTS.REFERENCES 325.Pq Event 24H , Umask FFH 326All requests to L2 cache. 327.It Li L2_DEMAND_RQSTS.WB_HIT 328.Pq Event 27H , Umask 50H 329Not rejected writebacks that hit L2 cache 330.It Li LONGEST_LAT_CACHE.REFERENCE 331.Pq Event 2EH , Umask 4FH 332This event counts requests originating from the core 333that reference a cache line in the last level cache. 334.It Li LONGEST_LAT_CACHE.MISS 335.Pq Event 2EH , Umask 41H 336This event counts each cache miss condition for 337references to the last level cache. 338.It Li CPU_CLK_UNHALTED.THREAD_P 339.Pq Event 3CH , Umask 00H 340Counts the number of thread cycles while the thread 341is not in a halt state. The thread enters the halt state 342when it is running the HLT instruction. The core 343frequency may change from time to time due to 344power or thermal throttling. 345.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 346.Pq Event 3CH , Umask 01H 347Increments at the frequency of XCLK (100 MHz) 348when not halted. 349.It Li L1D_PEND_MISS.PENDING 350.Pq Event 48H , Umask 01H 351Increments the number of outstanding L1D misses 352every cycle. Set Cmaks = 1 and Edge =1 to count 353occurrences. 354.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 355.Pq Event 49H , Umask 01H 356Miss in all TLB levels causes an page walk of any 357page size (4K/2M/4M/1G). 358.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K 359.Pq Event 49H , Umask 02H 360Completed page walks due to store misses in one or 361more TLB levels of 4K page structure. 362.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M 363.Pq Event 49H , Umask 04H 364Completed page walks due to store misses in one or 365more TLB levels of 2M/4M page structure. 366.It Li DTLB_STORE_MISSES.WALK_COMPLETED 367.Pq Event 49H , Umask 0EH 368Completed page walks due to store miss in any TLB 369levels of any page size (4K/2M/4M/1G). 370.It Li DTLB_STORE_MISSES.WALK_DURATION 371.Pq Event 49H , Umask 10H 372Cycles PMH is busy with this walk. 373.It Li DTLB_STORE_MISSES.STLB_HIT_4K 374.Pq Event 49H , Umask 20H 375Store misses that missed DTLB but hit STLB (4K). 376.It Li DTLB_STORE_MISSES.STLB_HIT_2M 377.Pq Event 49H , Umask 40H 378Store misses that missed DTLB but hit STLB (2M). 379.It Li DTLB_STORE_MISSES.STLB_HIT 380.Pq Event 49H , Umask 60H 381Store operations that miss the first TLB level but hit 382the second and do not cause page walks. 383.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS 384.Pq Event 49H , Umask 80H 385DTLB store misses with low part of linear-to-physical 386address translation missed. 387.It Li LOAD_HIT_PRE.SW_PF 388.Pq Event 4CH , Umask 01H 389Non-SW-prefetch load dispatches that hit fill buffer 390allocated for S/W prefetch. 391.It Li LOAD_HIT_PRE.HW_PF 392.Pq Event 4CH , Umask 02H 393Non-SW-prefetch load dispatches that hit fill buffer 394allocated for H/W prefetch. 395.It Li L1D.REPLACEMENT 396.Pq Event 51H , Umask 01H 397Counts the number of lines brought into the L1 data 398cache. 399.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 400.Pq Event 58H , Umask 04H 401Number of integer Move Elimination candidate uops 402that were not eliminated. 403.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED 404.Pq Event 58H , Umask 08H 405Number of SIMD Move Elimination candidate uops 406that were not eliminated. 407.It Li MOVE_ELIMINATION.INT_ELIMINATED 408.Pq Event 58H , Umask 01H 409Unhalted core cycles when the thread is in ring 0. 410.It Li MOVE_ELIMINATION.SMID_ELIMINATED 411.Pq Event 58H , Umask 02H 412Number of SIMD Move Elimination candidate uops 413that were eliminated. 414.It Li CPL_CYCLES.RING0 415.Pq Event 5CH , Umask 02H 416Unhalted core cycles when the thread is in ring 0. 417.It Li CPL_CYCLES.RING123 418.Pq Event 5CH , Umask 01H 419Unhalted core cycles when the thread is not in ring 0. 420.It Li RS_EVENTS.EMPTY_CYCLES 421.Pq Event 5EH , Umask 01H 422Cycles the RS is empty for the thread. 423.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 424.Pq Event 60H , Umask 01H 425Offcore outstanding Demand Data Read transactions 426in SQ to uncore. Set Cmask=1 to count cycles. 427.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD 428.Pq Event 60H , Umask 02H 429Offcore outstanding Demand code Read transactions 430in SQ to uncore. Set Cmask=1 to count cycles. 431.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 432.Pq Event 60H , Umask 04H 433Offcore outstanding RFO store transactions in SQ to 434uncore. Set Cmask=1 to count cycles. 435.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 436.Pq Event 60H , Umask 08H 437Offcore outstanding cacheable data read 438transactions in SQ to uncore. Set Cmask=1 to count 439cycles. 440.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 441.Pq Event 63H , Umask 01H 442Cycles in which the L1D and L2 are locked, due to a 443UC lock or split lock. 444.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 445.Pq Event 63H , Umask 02H 446Cycles in which the L1D is locked. 447.It Li IDQ.EMPTY 448.Pq Event 79H , Umask 02H 449Counts cycles the IDQ is empty. 450.It Li IDQ.MITE_UOPS 451.Pq Event 79H , Umask 04H 452Increment each cycle # of uops delivered to IDQ from 453MITE path. 454Set Cmask = 1 to count cycles. 455.It Li IDQ.DSB_UOPS 456.Pq Event 79H , Umask 08H 457Increment each cycle. # of uops delivered to IDQ 458from DSB path. 459Set Cmask = 1 to count cycles. 460.It Li IDQ.MS_DSB_UOPS 461.Pq Event 79H , Umask 10H 462Increment each cycle # of uops delivered to IDQ 463when MS_busy by DSB. Set Cmask = 1 to count 464cycles. Add Edge=1 to count # of delivery. 465.It Li IDQ.MS_MITE_UOPS 466.Pq Event 79H , Umask 20H 467ncrement each cycle # of uops delivered to IDQ 468when MS_busy by MITE. Set Cmask = 1 to count 469cycles. 470.It Li IDQ.MS_UOPS 471.Pq Event 79H , Umask 30H 472Increment each cycle # of uops delivered to IDQ from 473MS by either DSB or MITE. Set Cmask = 1 to count 474cycles. 475.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 476.Pq Event 79H , Umask 18H 477Counts cycles DSB is delivered at least one uops. Set 478Cmask = 1. 479.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 480.Pq Event 79H , Umask 18H 481Counts cycles DSB is delivered four uops. Set Cmask 482=4. 483.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 484.Pq Event 79H , Umask 24H 485Counts cycles MITE is delivered at least one uops. Set 486Cmask = 1. 487.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 488.Pq Event 79H , Umask 24H 489Counts cycles MITE is delivered four uops. Set Cmask 490=4. 491.It Li IDQ.MITE_ALL_UOPS 492.Pq Event 79H , Umask 3CH 493# of uops delivered to IDQ from any path. 494.It Li ICACHE.MISSES 495.Pq Event 80H , Umask 02H 496Number of Instruction Cache, Streaming Buffer and 497Victim Cache Misses. Includes UC accesses. 498.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 499.Pq Event 85H , Umask 01H 500Misses in ITLB that causes a page walk of any page 501size. 502.It Li ITLB_MISSES.WALK_COMPLETED_4K 503.Pq Event 85H , Umask 02H 504Completed page walks due to misses in ITLB 4K page 505entries. 506.It Li TLB_MISSES.WALK_COMPLETED_2M_4M 507.Pq Event 85H , Umask 04H 508Completed page walks due to misses in ITLB 2M/4M 509page entries. 510.It Li ITLB_MISSES.WALK_COMPLETED 511.Pq Event 85H , Umask 0EH 512Completed page walks in ITLB of any page size. 513.It Li ITLB_MISSES.WALK_DURATION 514.Pq Event 85H , Umask 10H 515Cycle PMH is busy with a walk. 516.It Li ITLB_MISSES.STLB_HIT_4K 517.Pq Event 85H , Umask 20H 518ITLB misses that hit STLB (4K). 519.It Li ITLB_MISSES.STLB_HIT_2M 520.Pq Event 85H , Umask 40H 521ITLB misses that hit STLB (2K). 522.It Li ITLB_MISSES.STLB_HIT 523.Pq Event 85H , Umask 60H 524TLB misses that hit STLB. No page walk. 525.It Li ILD_STALL.LCP 526.Pq Event 87H , Umask 01H 527Stalls caused by changing prefix length of the 528instruction. 529.It Li ILD_STALL.IQ_FULL 530.Pq Event 87H , Umask 04H 531Stall cycles due to IQ is full. 532.It Li BR_INST_EXEC.COND 533.Pq Event 88H , Umask 01H 534Qualify conditional near branch instructions 535executed, but not necessarily retired. 536.It Li BR_INST_EXEC.DIRECT_JMP 537.Pq Event 88H , Umask 02H 538Qualify all unconditional near branch instructions 539excluding calls and indirect branches. 540.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 541.Pq Event 88H , Umask 04H 542Qualify executed indirect near branch instructions 543that are not calls nor returns. 544.It Li BR_INST_EXEC.RETURN_NEAR 545.Pq Event 88H , Umask 08H 546Qualify indirect near branches that have a return 547mnemonic. 548.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 549.Pq Event 88H , Umask 10H 550Qualify unconditional near call branch instructions, 551excluding non call branch, executed. 552.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 553.Pq Event 88H , Umask 20H 554Qualify indirect near calls, including both register and 555memory indirect, executed. 556.It Li BR_INST_EXEC.NONTAKEN 557.Pq Event 88H , Umask 40H 558Qualify non-taken near branches executed. 559.It Li BR_INST_EXEC.TAKEN 560.Pq Event 88H , Umask 80H 561Qualify taken near branches executed. Must combine 562with 01H,02H, 04H, 08H, 10H, 20H. 563.It Li BR_INST_EXEC.ALL_BRANCHES 564.Pq Event 88H , Umask FFH 565Counts all near executed branches (not necessarily 566retired). 567.It Li BR_MISP_EXEC.COND 568.Pq Event 89H , Umask 01H 569Qualify conditional near branch instructions 570mispredicted. 571.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 572.Pq Event 89H , Umask 04H 573Qualify mispredicted indirect near branch 574instructions that are not calls nor returns. 575.It Li BR_MISP_EXEC.RETURN_NEAR 576.Pq Event 89H , Umask 08H 577Qualify mispredicted indirect near branches that 578have a return mnemonic. 579.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 580.Pq Event 89H , Umask 10H 581Qualify mispredicted unconditional near call branch 582instructions, excluding non call branch, executed. 583.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 584.Pq Event 89H , Umask 20H 585Qualify mispredicted indirect near calls, including 586both register and memory indirect, executed. 587.It Li BR_MISP_EXEC.NONTAKEN 588.Pq Event 89H , Umask 40H 589Qualify mispredicted non-taken near branches 590executed. 591.It Li BR_MISP_EXEC.TAKEN 592.Pq Event 89H , Umask 80H 593Qualify mispredicted taken near branches executed. 594Must combine with 01H,02H, 04H, 08H, 10H, 20H. 595.It Li BR_MISP_EXEC.ALL_BRANCHES 596.Pq Event 89H , Umask FFH 597Counts all near executed branches (not necessarily 598retired). 599.It Li IDQ_UOPS_NOT_DELIVERED.CORE 600.Pq Event 9CH , Umask 01H 601Count number of non-delivered uops to RAT per 602thread. 603.It Li UOPS_EXECUTED_PORT.PORT_0 604.Pq Event A1H , Umask 01H 605Cycles which a Uop is dispatched on port 0 in this 606thread. 607.It Li UOPS_EXECUTED_PORT.PORT_1 608.Pq Event A1H , Umask 02H 609Cycles which a Uop is dispatched on port 1 in this 610thread. 611.It Li UOPS_EXECUTED_PORT.PORT_2 612.Pq Event A1H , Umask 04H 613Cycles which a Uop is dispatched on port 2 in this 614thread. 615.It Li UOPS_EXECUTED_PORT.PORT_3 616.Pq Event A1H , Umask 08H 617Cycles which a Uop is dispatched on port 3 in this 618thread. 619.It Li UOPS_EXECUTED_PORT.PORT_4 620.Pq Event A1H , Umask 10H 621Cycles which a Uop is dispatched on port 4 in this 622thread. 623.It Li UOPS_EXECUTED_PORT.PORT_5 624.Pq Event A1H , Umask 20H 625Cycles which a Uop is dispatched on port 5 in this 626thread. 627.It Li UOPS_EXECUTED_PORT.PORT_6 628.Pq Event A1H , Umask 40H 629Cycles which a Uop is dispatched on port 6 in this 630thread. 631.It Li UOPS_EXECUTED_PORT.PORT_7 632.Pq Event A1H , Umask 80H 633Cycles which a Uop is dispatched on port 7 in this 634thread. 635.It Li RESOURCE_STALLS.ANY 636.Pq Event A2H , Umask 01H 637Cycles Allocation is stalled due to Resource Related 638reason. 639.It Li RESOURCE_STALLS.RS 640.Pq Event A2H , Umask 04H 641Cycles stalled due to no eligible RS entry available. 642.It Li RESOURCE_STALLS.SB 643.Pq Event A2H , Umask 08H 644Cycles stalled due to no store buffers available (not 645including draining form sync). 646.It Li RESOURCE_STALLS.ROB 647.Pq Event A2H , Umask 10H 648Cycles stalled due to re-order buffer full. 649.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 650.Pq Event A3H , Umask 01H 651Cycles with pending L2 miss loads. Set Cmask=2 to 652count cycle. 653.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING 654.Pq Event A3H , Umask 02H 655Cycles with pending memory loads. Set Cmask=2 to 656count cycle. 657.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING 658.Pq Event A3H , Umask 05H 659Number of loads missed L2. 660.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 661.Pq Event A3H , Umask 08H 662Cycles with pending L1 cache miss loads. Set 663Cmask=8 to count cycle. 664.It Li ITLB.ITLB_FLUSH 665.Pq Event AEH , Umask 01H 666Counts the number of ITLB flushes, includes 6674k/2M/4M pages. 668.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 669.Pq Event B0H , Umask 01H 670Demand data read requests sent to uncore. 671.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 672.Pq Event B0H , Umask 02H 673Demand code read requests sent to uncore. 674.It Li OFFCORE_REQUESTS.DEMAND_RFO 675.Pq Event B0H , Umask 04H 676Demand RFO read requests sent to uncore, including 677regular RFOs, locks, ItoM. 678.It Li OFFCORE_REQUESTS.ALL_DATA_RD 679.Pq Event B0H , Umask 08H 680Data read requests sent to uncore (demand and 681prefetch). 682.It Li UOPS_EXECUTED.CORE 683.Pq Event B1H , Umask 02H 684Counts total number of uops to be executed per-core 685each cycle. 686.It Li OFF_CORE_RESPONSE_0 687.Pq Event B7H , Umask 01H 688Requires MSR 01A6H 689.It Li OFF_CORE_RESPONSE_1 690.Pq Event BBH , Umask 01H 691Requires MSR 01A7H 692.It Li PAGE_WALKER_LOADS.DTLB_L1 693.Pq Event BCH , Umask 11H 694Number of DTLB page walker loads that hit in the 695L1+FB. 696.It Li PAGE_WALKER_LOADS.ITLB_L1 697.Pq Event BCH , Umask 21H 698Number of ITLB page walker loads that hit in the 699L1+FB. 700.It Li PAGE_WALKER_LOADS.DTLB_L2 701.Pq Event BCH , Umask 12H 702Number of DTLB page walker loads that hit in the L2. 703.It Li PAGE_WALKER_LOADS.ITLB_L2 704.Pq Event BCH , Umask 22H 705Number of ITLB page walker loads that hit in the L2. 706.It Li PAGE_WALKER_LOADS.DTLB_L3 707.Pq Event BCH , Umask 14H 708Number of DTLB page walker loads that hit in the L3. 709.It Li PAGE_WALKER_LOADS.ITLB_L3 710.Pq Event BCH , Umask 24H 711Number of ITLB page walker loads that hit in the L3. 712.It Li PAGE_WALKER_LOADS.DTLB_MEMORY 713.Pq Event BCH , Umask 18H 714Number of DTLB page walker loads from memory. 715.It Li PAGE_WALKER_LOADS.ITLB_MEMORY 716.Pq Event BCH , Umask 28H 717Number of ITLB page walker loads from memory. 718.It Li TLB_FLUSH.DTLB_THREAD 719.Pq Event BDH , Umask 01H 720DTLB flush attempts of the thread-specific entries. 721.It Li TLB_FLUSH.STLB_ANY 722.Pq Event BDH , Umask 20H 723Count number of STLB flush attempts. 724.It Li INST_RETIRED.ANY_P 725.Pq Event C0H , Umask 00H 726Number of instructions at retirement. 727.It Li INST_RETIRED.ALL 728.Pq Event C0H , Umask 01H 729Precise instruction retired event with HW to reduce 730effect of PEBS shadow in IP distribution. 731.It Li OTHER_ASSISTS.AVX_TO_SSE 732.Pq Event C1H , Umask 08H 733Number of transitions from AVX-256 to legacy SSE 734when penalty applicable. 735.It Li OTHER_ASSISTS.SSE_TO_AVX 736.Pq Event C1H , Umask 10H 737Number of transitions from SSE to AVX-256 when 738penalty applicable. 739.It Li OTHER_ASSISTS.ANY_WB_ASSIST 740.Pq Event C1H , Umask 40H 741Number of microcode assists invoked by HW upon 742uop writeback. 743.It Li UOPS_RETIRED.ALL 744.Pq Event C2H , Umask 01H 745Counts the number of micro-ops retired, Use 746cmask=1 and invert to count active cycles or stalled 747cycles. 748.It Li UOPS_RETIRED.RETIRE_SLOTS 749.Pq Event C2H , Umask 02H 750Counts the number of retirement slots used each 751cycle. 752.It Li MACHINE_CLEARS.MEMORY_ORDERING 753.Pq Event C3H , Umask 02H 754Counts the number of machine clears due to memory 755order conflicts. 756.It Li MACHINE_CLEARS.SMC 757.Pq Event C3H , Umask 04H 758Number of self-modifying-code machine clears 759detected. 760.It Li MACHINE_CLEARS.MASKMOV 761.Pq Event C3H , Umask 20H 762Counts the number of executed AVX masked load 763operations that refer to an illegal address range with 764the mask bits set to 0. 765.It Li BR_INST_RETIRED.ALL_BRANCHES 766.Pq Event C4H , Umask 00H 767Branch instructions at retirement. 768.It Li BR_INST_RETIRED.CONDITIONAL 769.Pq Event C4H , Umask 01H 770Counts the number of conditional branch instructions Supports PEBS 771retired. 772.It Li BR_INST_RETIRED.NEAR_CALL 773.Pq Event C4H , Umask 02H 774Direct and indirect near call instructions retired. 775.It Li BR_INST_RETIRED.ALL_BRANCHES 776.Pq Event C4H , Umask 04H 777Counts the number of branch instructions retired. 778.It Li BR_INST_RETIRED.NEAR_RETURN 779.Pq Event C4H , Umask 08H 780Counts the number of near return instructions 781retired. 782.It Li BR_INST_RETIRED.NOT_TAKEN 783.Pq Event C4H , Umask 10H 784Counts the number of not taken branch instructions 785retired. 786 It Li BR_INST_RETIRED.NEAR_TAKEN 787.Pq Event C4H , Umask 20H 788Number of near taken branches retired. 789.It Li BR_INST_RETIRED.FAR_BRANCH 790.Pq Event C4H , Umask 40H 791Number of far branches retired. 792.It Li BR_MISP_RETIRED.ALL_BRANCHES 793.Pq Event C5H , Umask 00H 794Mispredicted branch instructions at retirement 795.It Li BR_MISP_RETIRED.CONDITIONAL 796.Pq Event C5H , Umask 01H 797Mispredicted conditional branch instructions retired. 798.It Li BR_MISP_RETIRED.CONDITIONAL 799.Pq Event C5H , Umask 04H 800Mispredicted macro branch instructions retired. 801.It Li FP_ASSIST.X87_OUTPUT 802.Pq Event CAH , Umask 02H 803Number of X87 FP assists due to Output values. 804.It Li FP_ASSIST.X87_INPUT 805.Pq Event CAH , Umask 04H 806Number of X87 FP assists due to input values. 807.It Li FP_ASSIST.SIMD_OUTPUT 808.Pq Event CAH , Umask 08H 809Number of SIMD FP assists due to Output values. 810.It Li FP_ASSIST.SIMD_INPUT 811.Pq Event CAH , Umask 10H 812Number of SIMD FP assists due to input values. 813.It Li FP_ASSIST.ANY 814.Pq Event CAH , Umask 1EH 815Cycles with any input/output SSE* or FP assists. 816.It Li ROB_MISC_EVENTS.LBR_INSERTS 817.Pq Event CCH , Umask 20H 818Count cases of saving new LBR records by hardware. 819.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 820.Pq Event CDH , Umask 01H 821Randomly sampled loads whose latency is above a 822user defined threshold. A small fraction of the overall 823loads are sampled due to randomization. 824.It Li MEM_UOP_RETIRED.LOADS 825.Pq Event D0H , Umask 01H 826Qualify retired memory uops that are loads. Combine Supports PEBS and 827with umask 10H, 20H, 40H, 80H. 828.It Li MEM_UOP_RETIRED.STORES 829.Pq Event D0H , Umask 02H 830Qualify retired memory uops that are stores. 831Combine with umask 10H, 20H, 40H, 80H. 832.It Li MEM_UOP_RETIRED.STLB_MISS 833.Pq Event D0H , Umask 10H 834Qualify retired memory uops with STLB miss. Must 835combine with umask 01H, 02H, to produce counts. 836.It Li MEM_UOP_RETIRED.LOCK 837.Pq Event D0H , Umask 20H 838Qualify retired memory uops with lock. Must combine Supports PEBS and 839with umask 01H, 02H, to produce counts. 840.It Li MEM_UOP_RETIRED.SPLIT 841.Pq Event D0H , Umask 40H 842Qualify retired memory uops with line split. Must 843combine with umask 01H, 02H, to produce counts. 844.It Li MEM_UOP_RETIRED.ALL 845.Pq Event D0H , Umask 80H 846Qualify any retired memory uops. Must combine with Supports PEBS and 847umask 01H, 02H, to produce counts. 848.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 849.Pq Event D1H , Umask 01H 850Retired load uops with L1 cache hits as data sources. 851.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 852.Pq Event D1H , Umask 02H 853Retired load uops with L2 cache hits as data sources. 854.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 855.Pq Event D1H , Umask 04H 856Retired load uops with LLC cache hits as data 857sources. 858.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS 859.Pq Event D1H , Umask 10H 860Retired load uops missed L2. Unknown data source 861excluded. 862.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 863.Pq Event D1H , Umask 40H 864Retired load uops which data sources were load uops 865missed L1 but hit FB due to preceding miss to the 866same cache line with data not ready. 867.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 868.Pq Event D2H , Umask 01H 869Retired load uops which data sources were LLC hit 870and cross-core snoop missed in on-pkg core cache. 871.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 872.Pq Event D2H , Umask 02H 873Retired load uops which data sources were LLC and 874cross-core snoop hits in on-pkg core cache. 875.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 876.Pq Event D2H , Umask 04H 877Retired load uops which data sources were HitM 878responses from shared LLC. 879.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 880.Pq Event D2H , Umask 08H 881Retired load uops which data sources were hits in 882LLC without snoops required. 883.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 884.Pq Event D3H , Umask 01H 885Retired load uops which data sources missed LLC but 886serviced from local dram. 887.It Li BACLEARS.ANY 888.Pq Event E6H , Umask 1FH 889Number of front end re-steers due to BPU 890misprediction. 891.It Li L2_TRANS.DEMAND_DATA_RD 892.Pq Event F0H , Umask 01H 893Demand Data Read requests that access L2 cache. 894.It Li L2_TRANS.RFO 895.Pq Event F0H , Umask 02H 896RFO requests that access L2 cache. 897.It Li L2_TRANS.CODE_RD 898.Pq Event F0H , Umask 04H 899L2 cache accesses when fetching instructions. 900.It Li L2_TRANS.ALL_PF 901.Pq Event F0H , Umask 08H 902Any MLC or LLC HW prefetch accessing L2, including 903rejects. 904.It Li L2_TRANS.L1D_WB 905.Pq Event F0H , Umask 10H 906L1D writebacks that access L2 cache. 907.It Li L2_TRANS.L2_FILL 908.Pq Event F0H , Umask 20H 909L2 fill requests that access L2 cache. 910.It Li L2_TRANS.L2_WB 911.Pq Event F0H , Umask 40H 912L2 writebacks that access L2 cache. 913.It Li L2_TRANS.ALL_REQUESTS 914.Pq Event F0H , Umask 80H 915Transactions accessing L2 pipe. 916.It Li L2_LINES_IN.I 917.Pq Event F1H , Umask 01H 918L2 cache lines in I state filling L2. 919.It Li L2_LINES_IN.S 920.Pq Event F1H , Umask 02H 921L2 cache lines in S state filling L2. 922.It Li L2_LINES_IN.E 923.Pq Event F1H , Umask 04H 924L2 cache lines in E state filling L2. 925.It Li L2_LINES_IN.ALL 926.Pq Event F1H , Umask 07H 927L2 cache lines filling L2. 928.It Li L2_LINES_OUT.DEMAND_CLEAN 929.Pq Event F2H , Umask 05H 930Clean L2 cache lines evicted by demand. 931.It Li L2_LINES_OUT.DEMAND_DIRTY 932.Pq Event F2H , Umask 06H 933Dirty L2 cache lines evicted by demand. 934.El 935.Sh SEE ALSO 936.Xr pmc 3 , 937.Xr pmc.atom 3 , 938.Xr pmc.core 3 , 939.Xr pmc.iaf 3 , 940.Xr pmc.ucf 3 , 941.Xr pmc.k7 3 , 942.Xr pmc.k8 3 , 943.Xr pmc.p4 3 , 944.Xr pmc.p5 3 , 945.Xr pmc.p6 3 , 946.Xr pmc.corei7 3 , 947.Xr pmc.corei7uc 3 , 948.Xr pmc.haswelluc 3 , 949.Xr pmc.ivybridge 3 , 950.Xr pmc.ivybridgexeon 3 , 951.Xr pmc.sandybridge 3 , 952.Xr pmc.sandybridgeuc 3 , 953.Xr pmc.sandybridgexeon 3 , 954.Xr pmc.westmere 3 , 955.Xr pmc.westmereuc 3 , 956.Xr pmc.soft 3 , 957.Xr pmc.tsc 3 , 958.Xr pmc_cpuinfo 3 , 959.Xr pmclog 3 , 960.Xr hwpmc 4 961.Sh HISTORY 962The 963.Nm pmc 964library first appeared in 965.Fx 6.0 . 966.Sh AUTHORS 967.An -nosplit 968The 969.Lb libpmc 970library was written by 971.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 972The support for the Haswell 973microarchitecture was written by 974.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 975