1.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd March 22, 2013 28.Dt PMC.HASWELL 3 29.Os 30.Sh NAME 31.Nm pmc.haswell 32.Nd measurement events for 33.Tn Intel 34.Tn Haswell 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Haswell" 43CPUs contain PMCs conforming to version 2 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs may contain up to two classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_IAP" 48.It Li PMC_CLASS_IAF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_IAP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.El 54.Pp 55The number of PMCs available in each class and their widths need to be 56determined at run time by calling 57.Xr pmc_cpuinfo 3 . 58.Pp 59Intel Haswell PMCs are documented in 60.Rs 61.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" 63.%N "Order Number: 325462-045US" 64.%D January 2013 65.%Q "Intel Corporation" 66.Re 67.Ss HASWELL FIXED FUNCTION PMCS 68These PMCs and their supported events are documented in 69.Xr pmc.iaf 3 . 70.Ss HASWELL PROGRAMMABLE PMCS 71The programmable PMCs support the following capabilities: 72.Bl -column "PMC_CAP_INTERRUPT" "Support" 73.It Em Capability Ta Em Support 74.It PMC_CAP_CASCADE Ta \&No 75.It PMC_CAP_EDGE Ta Yes 76.It PMC_CAP_INTERRUPT Ta Yes 77.It PMC_CAP_INVERT Ta Yes 78.It PMC_CAP_READ Ta Yes 79.It PMC_CAP_PRECISE Ta \&No 80.It PMC_CAP_SYSTEM Ta Yes 81.It PMC_CAP_TAGGING Ta \&No 82.It PMC_CAP_THRESHOLD Ta Yes 83.It PMC_CAP_USER Ta Yes 84.It PMC_CAP_WRITE Ta Yes 85.El 86.Ss Event Qualifiers 87Event specifiers for these PMCs support the following common 88qualifiers: 89.Bl -tag -width indent 90.It Li rsp= Ns Ar value 91Configure the Off-core Response bits. 92.Bl -tag -width indent 93.It Li DMND_DATA_RD 94Counts the number of demand and DCU prefetch data reads of full 95and partial cachelines as well as demand data page table entry 96cacheline reads. 97Does not count L2 data read prefetches or instruction fetches. 98.It Li REQ_DMND_RFO 99Counts the number of demand and DCU prefetch reads for ownership (RFO) 100requests generated by a write to data cacheline. 101Does not count L2 RFO prefetches. 102.It Li REQ_DMND_IFETCH 103Counts the number of demand and DCU prefetch instruction cacheline reads. 104Does not count L2 code read prefetches. 105.It Li REQ_WB 106Counts the number of writeback (modified to exclusive) transactions. 107.It Li REQ_PF_DATA_RD 108Counts the number of data cacheline reads generated by L2 prefetchers. 109.It Li REQ_PF_RFO 110Counts the number of RFO requests generated by L2 prefetchers. 111.It Li REQ_PF_IFETCH 112Counts the number of code reads generated by L2 prefetchers. 113.It Li REQ_PF_LLC_DATA_RD 114L2 prefetcher to L3 for loads. 115.It Li REQ_PF_LLC_RFO 116RFO requests generated by L2 prefetcher 117.It Li REQ_PF_LLC_IFETCH 118L2 prefetcher to L3 for instruction fetches. 119.It Li REQ_BUS_LOCKS 120Bus lock and split lock requests. 121.It Li REQ_STRM_ST 122Streaming store requests. 123.It Li REQ_OTHER 124Any other request that crosses IDI, including I/O. 125.It Li RES_ANY 126Catch all value for any response types. 127.It Li RES_SUPPLIER_NO_SUPP 128No Supplier Information available. 129.It Li RES_SUPPLIER_LLC_HITM 130M-state initial lookup stat in L3. 131.It Li RES_SUPPLIER_LLC_HITE 132E-state. 133.It Li RES_SUPPLIER_LLC_HITS 134S-state. 135.It Li RES_SUPPLIER_LLC_HITF 136F-state. 137.It Li RES_SUPPLIER_LOCAL 138Local DRAM Controller. 139.It Li RES_SNOOP_SNP_NONE 140No details on snoop-related information. 141.It Li RES_SNOOP_SNP_NO_NEEDED 142No snoop was needed to satisfy the request. 143.It Li RES_SNOOP_SNP_MISS 144A snoop was needed and it missed all snooped caches: 145-For LLC Hit, ReslHitl was returned by all cores 146-For LLC Miss, Rspl was returned by all sockets and data was returned from 147DRAM. 148.It Li RES_SNOOP_HIT_NO_FWD 149A snoop was needed and it hits in at least one snooped cache. 150Hit denotes a cache-line was valid before snoop effect. 151This includes: 152-Snoop Hit w/ Invalidation (LLC Hit, RFO) 153-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 154-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 155In the LLC Miss case, data is returned from DRAM. 156.It Li RES_SNOOP_HIT_FWD 157A snoop was needed and data was forwarded from a remote socket. 158This includes: 159-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 160.It Li RES_SNOOP_HITM 161A snoop was needed and it HitM-ed in local or remote cache. 162HitM denotes a cache-line was in modified state before effect as a results of snoop. 163This includes: 164-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 165-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 166-Snoop MtoS (LLC Hit, IFetch/Data_RD). 167.It Li RES_NON_DRAM 168Target was non-DRAM system address. 169This includes MMIO transactions. 170.El 171.It Li cmask= Ns Ar value 172Configure the PMC to increment only if the number of configured 173events measured in a cycle is greater than or equal to 174.Ar value . 175.It Li edge 176Configure the PMC to count the number of de-asserted to asserted 177transitions of the conditions expressed by the other qualifiers. 178If specified, the counter will increment only once whenever a 179condition becomes true, irrespective of the number of clocks during 180which the condition remains true. 181.It Li inv 182Invert the sense of comparison when the 183.Dq Li cmask 184qualifier is present, making the counter increment when the number of 185events per cycle is less than the value specified by the 186.Dq Li cmask 187qualifier. 188.It Li os 189Configure the PMC to count events happening at processor privilege 190level 0. 191.It Li usr 192Configure the PMC to count events occurring at privilege levels 1, 2 193or 3. 194.El 195.Pp 196If neither of the 197.Dq Li os 198or 199.Dq Li usr 200qualifiers are specified, the default is to enable both. 201.Ss Event Specifiers (Programmable PMCs) 202Haswell programmable PMCs support the following events: 203.Bl -tag -width indent 204.It Li LD_BLOCKS.STORE_FORWARD 205.Pq Event 03H , Umask 02H 206Loads blocked by overlapping with store buffer that 207cannot be forwarded. 208.It Li MISALIGN_MEM_REF.LOADS 209.Pq Event 05H , Umask 01H 210Speculative cache-line split load uops dispatched to 211L1D. 212.It Li MISALIGN_MEM_REF.STORES 213.Pq Event 05H , Umask 02H 214Speculative cache-line split Store-address uops 215dispatched to L1D. 216.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 217.Pq Event 07H , Umask 01H 218False dependencies in MOB due to partial compare 219on address. 220.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK 221.Pq Event 08H , Umask 01H 222Misses in all TLB levels that cause a page walk of any 223page size. 224.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K 225.Pq Event 08H , Umask 02H 226Completed page walks due to demand load misses 227that caused 4K page walks in any TLB levels. 228.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K 229.Pq Event 08H , Umask 02H 230Completed page walks due to demand load misses 231that caused 2M/4M page walks in any TLB levels. 232.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 233.Pq Event 08H , Umask 0EH 234Completed page walks in any TLB of any page size 235due to demand load misses 236.It Li DTLB_LOAD_MISSES.WALK_DURATION 237.Pq Event 08H , Umask 10H 238Cycle PMH is busy with a walk. 239.It Li DTLB_LOAD_MISSES.STLB_HIT_4K 240.Pq Event 08H , Umask 20H 241Load misses that missed DTLB but hit STLB (4K). 242.It Li DTLB_LOAD_MISSES.STLB_HIT_2M 243.Pq Event 08H , Umask 40H 244Load misses that missed DTLB but hit STLB (2M). 245.It Li DTLB_LOAD_MISSES.STLB_HIT 246.Pq Event 08H , Umask 60H 247Number of cache load STLB hits. 248No page walk. 249.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS 250.Pq Event 08H , Umask 80H 251DTLB demand load misses with low part of linear-to- 252physical address translation missed 253.It Li INT_MISC.RECOVERY_CYCLES 254.Pq Event 0DH , Umask 03H 255Cycles waiting to recover after Machine Clears 256except JEClear. 257Set Cmask= 1. 258.It Li UOPS_ISSUED.ANY 259.Pq Event 0EH , Umask 01H 260ncrements each cycle the # of Uops issued by the 261RAT to RS. 262Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles 263of this core. 264.It Li UOPS_ISSUED.FLAGS_MERGE 265.Pq Event 0EH , Umask 10H 266Number of flags-merge uops allocated. 267Such uops adds delay. 268.It Li UOPS_ISSUED.SLOW_LEA 269.Pq Event 0EH , Umask 20H 270Number of slow LEA or similar uops allocated. 271Such uop has 3 sources (e.g. 2 sources + immediate) 272regardless if as a result of LEA instruction or not. 273.It Li UOPS_ISSUED.SiNGLE_MUL 274.Pq Event 0EH , Umask 40H 275Number of multiply packed/scalar single precision 276uops allocated. 277.It Li L2_RQSTS.DEMAND_DATA_RD_MISS 278.Pq Event 24H , Umask 21H 279Demand Data Read requests that missed L2, no 280rejects. 281.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 282.Pq Event 24H , Umask 41H 283Demand Data Read requests that hit L2 cache. 284.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 285.Pq Event 24H , Umask E1H 286Counts any demand and L1 HW prefetch data load 287requests to L2. 288.It Li L2_RQSTS.RFO_HIT 289.Pq Event 24H , Umask 42H 290Counts the number of store RFO requests that hit 291the L2 cache. 292.It Li L2_RQSTS.RFO_MISS 293.Pq Event 24H , Umask 22H 294Counts the number of store RFO requests that miss 295the L2 cache. 296.It Li L2_RQSTS.ALL_RFO 297.Pq Event 24H , Umask E2H 298Counts all L2 store RFO requests. 299.It Li L2_RQSTS.CODE_RD_HIT 300.Pq Event 24H , Umask 44H 301Number of instruction fetches that hit the L2 cache. 302.It Li L2_RQSTS.CODE_RD_MISS 303.Pq Event 24H , Umask 24H 304Number of instruction fetches that missed the L2 305cache. 306.It Li L2_RQSTS.ALL_DEMAND_MISS 307.Pq Event 24H , Umask 27H 308Demand requests that miss L2 cache. 309.It Li L2_RQSTS.ALL_DEMAND_REFERENCES 310.Pq Event 24H , Umask E7H 311Demand requests to L2 cache. 312.It Li L2_RQSTS.ALL_CODE_RD 313.Pq Event 24H , Umask E4H 314Counts all L2 code requests. 315.It Li L2_RQSTS.L2_PF_HIT 316.Pq Event 24H , Umask 50H 317Counts all L2 HW prefetcher requests that hit L2. 318.It Li L2_RQSTS.L2_PF_MISS 319.Pq Event 24H , Umask 30H 320Counts all L2 HW prefetcher requests that missed 321L2. 322.It Li L2_RQSTS.ALL_PF 323.Pq Event 24H , Umask F8H 324Counts all L2 HW prefetcher requests. 325.It Li L2_RQSTS.MISS 326.Pq Event 24H , Umask 3FH 327All requests that missed L2. 328.It Li L2_RQSTS.REFERENCES 329.Pq Event 24H , Umask FFH 330All requests to L2 cache. 331.It Li L2_DEMAND_RQSTS.WB_HIT 332.Pq Event 27H , Umask 50H 333Not rejected writebacks that hit L2 cache 334.It Li LONGEST_LAT_CACHE.REFERENCE 335.Pq Event 2EH , Umask 4FH 336This event counts requests originating from the core 337that reference a cache line in the last level cache. 338.It Li LONGEST_LAT_CACHE.MISS 339.Pq Event 2EH , Umask 41H 340This event counts each cache miss condition for 341references to the last level cache. 342.It Li CPU_CLK_UNHALTED.THREAD_P 343.Pq Event 3CH , Umask 00H 344Counts the number of thread cycles while the thread is not in a halt state. 345The thread enters the halt state when it is running the HLT instruction. 346The core frequency may change from time to time due to power or thermal throttling. 347.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 348.Pq Event 3CH , Umask 01H 349Increments at the frequency of XCLK (100 MHz) 350when not halted. 351.It Li L1D_PEND_MISS.PENDING 352.Pq Event 48H , Umask 01H 353Increments the number of outstanding L1D misses every cycle. 354Set Cmaks = 1 and Edge =1 to count occurrences. 355.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 356.Pq Event 49H , Umask 01H 357Miss in all TLB levels causes an page walk of any 358page size (4K/2M/4M/1G). 359.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K 360.Pq Event 49H , Umask 02H 361Completed page walks due to store misses in one or 362more TLB levels of 4K page structure. 363.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M 364.Pq Event 49H , Umask 04H 365Completed page walks due to store misses in one or 366more TLB levels of 2M/4M page structure. 367.It Li DTLB_STORE_MISSES.WALK_COMPLETED 368.Pq Event 49H , Umask 0EH 369Completed page walks due to store miss in any TLB 370levels of any page size (4K/2M/4M/1G). 371.It Li DTLB_STORE_MISSES.WALK_DURATION 372.Pq Event 49H , Umask 10H 373Cycles PMH is busy with this walk. 374.It Li DTLB_STORE_MISSES.STLB_HIT_4K 375.Pq Event 49H , Umask 20H 376Store misses that missed DTLB but hit STLB (4K). 377.It Li DTLB_STORE_MISSES.STLB_HIT_2M 378.Pq Event 49H , Umask 40H 379Store misses that missed DTLB but hit STLB (2M). 380.It Li DTLB_STORE_MISSES.STLB_HIT 381.Pq Event 49H , Umask 60H 382Store operations that miss the first TLB level but hit 383the second and do not cause page walks. 384.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS 385.Pq Event 49H , Umask 80H 386DTLB store misses with low part of linear-to-physical 387address translation missed. 388.It Li LOAD_HIT_PRE.SW_PF 389.Pq Event 4CH , Umask 01H 390Non-SW-prefetch load dispatches that hit fill buffer 391allocated for S/W prefetch. 392.It Li LOAD_HIT_PRE.HW_PF 393.Pq Event 4CH , Umask 02H 394Non-SW-prefetch load dispatches that hit fill buffer 395allocated for H/W prefetch. 396.It Li L1D.REPLACEMENT 397.Pq Event 51H , Umask 01H 398Counts the number of lines brought into the L1 data 399cache. 400.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 401.Pq Event 58H , Umask 04H 402Number of integer Move Elimination candidate uops 403that were not eliminated. 404.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED 405.Pq Event 58H , Umask 08H 406Number of SIMD Move Elimination candidate uops 407that were not eliminated. 408.It Li MOVE_ELIMINATION.INT_ELIMINATED 409.Pq Event 58H , Umask 01H 410Unhalted core cycles when the thread is in ring 0. 411.It Li MOVE_ELIMINATION.SMID_ELIMINATED 412.Pq Event 58H , Umask 02H 413Number of SIMD Move Elimination candidate uops 414that were eliminated. 415.It Li CPL_CYCLES.RING0 416.Pq Event 5CH , Umask 02H 417Unhalted core cycles when the thread is in ring 0. 418.It Li CPL_CYCLES.RING123 419.Pq Event 5CH , Umask 01H 420Unhalted core cycles when the thread is not in ring 0. 421.It Li RS_EVENTS.EMPTY_CYCLES 422.Pq Event 5EH , Umask 01H 423Cycles the RS is empty for the thread. 424.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 425.Pq Event 60H , Umask 01H 426Offcore outstanding Demand Data Read transactions in SQ to uncore. 427Set Cmask=1 to count cycles. 428.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD 429.Pq Event 60H , Umask 02H 430Offcore outstanding Demand code Read transactions in SQ to uncore. 431Set Cmask=1 to count cycles. 432.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 433.Pq Event 60H , Umask 04H 434Offcore outstanding RFO store transactions in SQ to uncore. 435Set Cmask=1 to count cycles. 436.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 437.Pq Event 60H , Umask 08H 438Offcore outstanding cacheable data read transactions in SQ to uncore. 439Set Cmask=1 to count cycles. 440.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 441.Pq Event 63H , Umask 01H 442Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 443.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 444.Pq Event 63H , Umask 02H 445Cycles in which the L1D is locked. 446.It Li IDQ.EMPTY 447.Pq Event 79H , Umask 02H 448Counts cycles the IDQ is empty. 449.It Li IDQ.MITE_UOPS 450.Pq Event 79H , Umask 04H 451Increment each cycle # of uops delivered to IDQ from MITE path. 452Set Cmask = 1 to count cycles. 453.It Li IDQ.DSB_UOPS 454.Pq Event 79H , Umask 08H 455Increment each cycle. # of uops delivered to IDQ 456from DSB path. 457Set Cmask = 1 to count cycles. 458.It Li IDQ.MS_DSB_UOPS 459.Pq Event 79H , Umask 10H 460Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. 461Set Cmask = 1 to count cycles. 462Add Edge=1 to count # of delivery. 463.It Li IDQ.MS_MITE_UOPS 464.Pq Event 79H , Umask 20H 465ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. 466Set Cmask = 1 to count cycles. 467.It Li IDQ.MS_UOPS 468.Pq Event 79H , Umask 30H 469Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. 470Set Cmask = 1 to count cycles. 471.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 472.Pq Event 79H , Umask 18H 473Counts cycles DSB is delivered at least one uops. 474Set Cmask = 1. 475.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 476.Pq Event 79H , Umask 18H 477Counts cycles DSB is delivered four uops. 478Set Cmask=4. 479.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 480.Pq Event 79H , Umask 24H 481Counts cycles MITE is delivered at least one uops. 482Set Cmask = 1. 483.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 484.Pq Event 79H , Umask 24H 485Counts cycles MITE is delivered four uops. 486Set Cmask =4. 487.It Li IDQ.MITE_ALL_UOPS 488.Pq Event 79H , Umask 3CH 489# of uops delivered to IDQ from any path. 490.It Li ICACHE.MISSES 491.Pq Event 80H , Umask 02H 492Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 493Includes UC accesses. 494.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 495.Pq Event 85H , Umask 01H 496Misses in ITLB that causes a page walk of any page 497size. 498.It Li ITLB_MISSES.WALK_COMPLETED_4K 499.Pq Event 85H , Umask 02H 500Completed page walks due to misses in ITLB 4K page 501entries. 502.It Li TLB_MISSES.WALK_COMPLETED_2M_4M 503.Pq Event 85H , Umask 04H 504Completed page walks due to misses in ITLB 2M/4M 505page entries. 506.It Li ITLB_MISSES.WALK_COMPLETED 507.Pq Event 85H , Umask 0EH 508Completed page walks in ITLB of any page size. 509.It Li ITLB_MISSES.WALK_DURATION 510.Pq Event 85H , Umask 10H 511Cycle PMH is busy with a walk. 512.It Li ITLB_MISSES.STLB_HIT_4K 513.Pq Event 85H , Umask 20H 514ITLB misses that hit STLB (4K). 515.It Li ITLB_MISSES.STLB_HIT_2M 516.Pq Event 85H , Umask 40H 517ITLB misses that hit STLB (2K). 518.It Li ITLB_MISSES.STLB_HIT 519.Pq Event 85H , Umask 60H 520TLB misses that hit STLB. 521No page walk. 522.It Li ILD_STALL.LCP 523.Pq Event 87H , Umask 01H 524Stalls caused by changing prefix length of the 525instruction. 526.It Li ILD_STALL.IQ_FULL 527.Pq Event 87H , Umask 04H 528Stall cycles due to IQ is full. 529.It Li BR_INST_EXEC.NONTAKEN_COND 530.Pq Event 88H , Umask 41H 531Count conditional near branch instructions that were executed (but not 532necessarily retired) and not taken. 533.It Li BR_INST_EXEC.TAKEN_COND 534.Pq Event 88H , Umask 81H 535Count conditional near branch instructions that were executed (but not 536necessarily retired) and taken. 537.It Li BR_INST_EXEC.DIRECT_JMP 538.Pq Event 88H , Umask 82H 539Count all unconditional near branch instructions excluding calls and 540indirect branches. 541.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 542.Pq Event 88H , Umask 84H 543Count executed indirect near branch instructions that are not calls nor 544returns. 545.It Li BR_INST_EXEC.RETURN_NEAR 546.Pq Event 88H , Umask 88H 547Count indirect near branches that have a return mnemonic. 548.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 549.Pq Event 88H , Umask 90H 550Count unconditional near call branch instructions, excluding non call 551branch, executed. 552.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 553.Pq Event 88H , Umask A0H 554Count indirect near calls, including both register and memory indirect, 555executed. 556.It Li BR_INST_EXEC.ALL_BRANCHES 557.Pq Event 88H , Umask FFH 558Counts all near executed branches (not necessarily retired). 559.It Li BR_MISP_EXEC.NONTAKEN_COND 560.Pq Event 89H , Umask 41H 561Count conditional near branch instructions mispredicted as nontaken. 562.It Li BR_MISP_EXEC.TAKEN_COND 563.Pq Event 89H , Umask 81H 564Count conditional near branch instructions mispredicted as taken. 565.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 566.Pq Event 89H , Umask 84H 567Count mispredicted indirect near branch instructions that are not calls 568nor returns. 569.It Li BR_MISP_EXEC.RETURN_NEAR 570.Pq Event 89H , Umask 88H 571Count mispredicted indirect near branches that have a return mnemonic. 572.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 573.Pq Event 89H , Umask 90H 574Count mispredicted unconditional near call branch instructions, excluding 575non call branch, executed. 576.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 577.Pq Event 89H , Umask A0H 578Count mispredicted indirect near calls, including both register and memory 579indirect, executed. 580.It Li BR_MISP_EXEC.ALL_BRANCHES 581.Pq Event 89H , Umask FFH 582Counts all mispredicted near executed branches (not necessarily retired). 583.It Li IDQ_UOPS_NOT_DELIVERED.CORE 584.Pq Event 9CH , Umask 01H 585Count number of non-delivered uops to RAT per 586thread. 587.It Li UOPS_EXECUTED_PORT.PORT_0 588.Pq Event A1H , Umask 01H 589Cycles which a Uop is dispatched on port 0 in this 590thread. 591.It Li UOPS_EXECUTED_PORT.PORT_1 592.Pq Event A1H , Umask 02H 593Cycles which a Uop is dispatched on port 1 in this 594thread. 595.It Li UOPS_EXECUTED_PORT.PORT_2 596.Pq Event A1H , Umask 04H 597Cycles which a Uop is dispatched on port 2 in this 598thread. 599.It Li UOPS_EXECUTED_PORT.PORT_3 600.Pq Event A1H , Umask 08H 601Cycles which a Uop is dispatched on port 3 in this 602thread. 603.It Li UOPS_EXECUTED_PORT.PORT_4 604.Pq Event A1H , Umask 10H 605Cycles which a Uop is dispatched on port 4 in this 606thread. 607.It Li UOPS_EXECUTED_PORT.PORT_5 608.Pq Event A1H , Umask 20H 609Cycles which a Uop is dispatched on port 5 in this 610thread. 611.It Li UOPS_EXECUTED_PORT.PORT_6 612.Pq Event A1H , Umask 40H 613Cycles which a Uop is dispatched on port 6 in this 614thread. 615.It Li UOPS_EXECUTED_PORT.PORT_7 616.Pq Event A1H , Umask 80H 617Cycles which a Uop is dispatched on port 7 in this 618thread. 619.It Li RESOURCE_STALLS.ANY 620.Pq Event A2H , Umask 01H 621Cycles Allocation is stalled due to Resource Related 622reason. 623.It Li RESOURCE_STALLS.RS 624.Pq Event A2H , Umask 04H 625Cycles stalled due to no eligible RS entry available. 626.It Li RESOURCE_STALLS.SB 627.Pq Event A2H , Umask 08H 628Cycles stalled due to no store buffers available (not 629including draining form sync). 630.It Li RESOURCE_STALLS.ROB 631.Pq Event A2H , Umask 10H 632Cycles stalled due to re-order buffer full. 633.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 634.Pq Event A3H , Umask 01H 635Cycles with pending L2 miss loads. 636Set Cmask=2 to count cycle. 637.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING 638.Pq Event A3H , Umask 02H 639Cycles with pending memory loads. 640Set Cmask=2 to count cycle. 641.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING 642.Pq Event A3H , Umask 05H 643Number of loads missed L2. 644.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 645.Pq Event A3H , Umask 08H 646Cycles with pending L1 cache miss loads. 647Set Cmask=8 to count cycle. 648.It Li ITLB.ITLB_FLUSH 649.Pq Event AEH , Umask 01H 650Counts the number of ITLB flushes, includes 6514k/2M/4M pages. 652.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 653.Pq Event B0H , Umask 01H 654Demand data read requests sent to uncore. 655.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 656.Pq Event B0H , Umask 02H 657Demand code read requests sent to uncore. 658.It Li OFFCORE_REQUESTS.DEMAND_RFO 659.Pq Event B0H , Umask 04H 660Demand RFO read requests sent to uncore, including 661regular RFOs, locks, ItoM. 662.It Li OFFCORE_REQUESTS.ALL_DATA_RD 663.Pq Event B0H , Umask 08H 664Data read requests sent to uncore (demand and 665prefetch). 666.It Li UOPS_EXECUTED.CORE 667.Pq Event B1H , Umask 02H 668Counts total number of uops to be executed per-core 669each cycle. 670.It Li OFF_CORE_RESPONSE_0 671.Pq Event B7H , Umask 01H 672Requires MSR 01A6H 673.It Li OFF_CORE_RESPONSE_1 674.Pq Event BBH , Umask 01H 675Requires MSR 01A7H 676.It Li PAGE_WALKER_LOADS.DTLB_L1 677.Pq Event BCH , Umask 11H 678Number of DTLB page walker loads that hit in the 679L1+FB. 680.It Li PAGE_WALKER_LOADS.ITLB_L1 681.Pq Event BCH , Umask 21H 682Number of ITLB page walker loads that hit in the 683L1+FB. 684.It Li PAGE_WALKER_LOADS.DTLB_L2 685.Pq Event BCH , Umask 12H 686Number of DTLB page walker loads that hit in the L2. 687.It Li PAGE_WALKER_LOADS.ITLB_L2 688.Pq Event BCH , Umask 22H 689Number of ITLB page walker loads that hit in the L2. 690.It Li PAGE_WALKER_LOADS.DTLB_L3 691.Pq Event BCH , Umask 14H 692Number of DTLB page walker loads that hit in the L3. 693.It Li PAGE_WALKER_LOADS.ITLB_L3 694.Pq Event BCH , Umask 24H 695Number of ITLB page walker loads that hit in the L3. 696.It Li PAGE_WALKER_LOADS.DTLB_MEMORY 697.Pq Event BCH , Umask 18H 698Number of DTLB page walker loads from memory. 699.It Li PAGE_WALKER_LOADS.ITLB_MEMORY 700.Pq Event BCH , Umask 28H 701Number of ITLB page walker loads from memory. 702.It Li TLB_FLUSH.DTLB_THREAD 703.Pq Event BDH , Umask 01H 704DTLB flush attempts of the thread-specific entries. 705.It Li TLB_FLUSH.STLB_ANY 706.Pq Event BDH , Umask 20H 707Count number of STLB flush attempts. 708.It Li INST_RETIRED.ANY_P 709.Pq Event C0H , Umask 00H 710Number of instructions at retirement. 711.It Li INST_RETIRED.ALL 712.Pq Event C0H , Umask 01H 713Precise instruction retired event with HW to reduce 714effect of PEBS shadow in IP distribution. 715.It Li OTHER_ASSISTS.AVX_TO_SSE 716.Pq Event C1H , Umask 08H 717Number of transitions from AVX-256 to legacy SSE 718when penalty applicable. 719.It Li OTHER_ASSISTS.SSE_TO_AVX 720.Pq Event C1H , Umask 10H 721Number of transitions from SSE to AVX-256 when 722penalty applicable. 723.It Li OTHER_ASSISTS.ANY_WB_ASSIST 724.Pq Event C1H , Umask 40H 725Number of microcode assists invoked by HW upon 726uop writeback. 727.It Li UOPS_RETIRED.ALL 728.Pq Event C2H , Umask 01H 729Counts the number of micro-ops retired, Use 730cmask=1 and invert to count active cycles or stalled 731cycles. 732.It Li UOPS_RETIRED.RETIRE_SLOTS 733.Pq Event C2H , Umask 02H 734Counts the number of retirement slots used each 735cycle. 736.It Li MACHINE_CLEARS.MEMORY_ORDERING 737.Pq Event C3H , Umask 02H 738Counts the number of machine clears due to memory 739order conflicts. 740.It Li MACHINE_CLEARS.SMC 741.Pq Event C3H , Umask 04H 742Number of self-modifying-code machine clears 743detected. 744.It Li MACHINE_CLEARS.MASKMOV 745.Pq Event C3H , Umask 20H 746Counts the number of executed AVX masked load 747operations that refer to an illegal address range with 748the mask bits set to 0. 749.It Li BR_INST_RETIRED.ALL_BRANCHES 750.Pq Event C4H , Umask 00H 751Branch instructions at retirement. 752.It Li BR_INST_RETIRED.CONDITIONAL 753.Pq Event C4H , Umask 01H 754Counts the number of conditional branch instructions Supports PEBS 755retired. 756.It Li BR_INST_RETIRED.NEAR_CALL 757.Pq Event C4H , Umask 02H 758Direct and indirect near call instructions retired. 759.It Li BR_INST_RETIRED.ALL_BRANCHES 760.Pq Event C4H , Umask 04H 761Counts the number of branch instructions retired. 762.It Li BR_INST_RETIRED.NEAR_RETURN 763.Pq Event C4H , Umask 08H 764Counts the number of near return instructions 765retired. 766.It Li BR_INST_RETIRED.NOT_TAKEN 767.Pq Event C4H , Umask 10H 768Counts the number of not taken branch instructions 769retired. 770 It Li BR_INST_RETIRED.NEAR_TAKEN 771.Pq Event C4H , Umask 20H 772Number of near taken branches retired. 773.It Li BR_INST_RETIRED.FAR_BRANCH 774.Pq Event C4H , Umask 40H 775Number of far branches retired. 776.It Li BR_MISP_RETIRED.ALL_BRANCHES 777.Pq Event C5H , Umask 00H 778Mispredicted branch instructions at retirement 779.It Li BR_MISP_RETIRED.CONDITIONAL 780.Pq Event C5H , Umask 01H 781Mispredicted conditional branch instructions retired. 782.It Li BR_MISP_RETIRED.CONDITIONAL 783.Pq Event C5H , Umask 04H 784Mispredicted macro branch instructions retired. 785.It Li FP_ASSIST.X87_OUTPUT 786.Pq Event CAH , Umask 02H 787Number of X87 FP assists due to Output values. 788.It Li FP_ASSIST.X87_INPUT 789.Pq Event CAH , Umask 04H 790Number of X87 FP assists due to input values. 791.It Li FP_ASSIST.SIMD_OUTPUT 792.Pq Event CAH , Umask 08H 793Number of SIMD FP assists due to Output values. 794.It Li FP_ASSIST.SIMD_INPUT 795.Pq Event CAH , Umask 10H 796Number of SIMD FP assists due to input values. 797.It Li FP_ASSIST.ANY 798.Pq Event CAH , Umask 1EH 799Cycles with any input/output SSE* or FP assists. 800.It Li ROB_MISC_EVENTS.LBR_INSERTS 801.Pq Event CCH , Umask 20H 802Count cases of saving new LBR records by hardware. 803.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 804.Pq Event CDH , Umask 01H 805Randomly sampled loads whose latency is above a user defined threshold. 806A small fraction of the overall loads are sampled due to randomization. 807.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS 808.Pq Event D0H , Umask 11H 809Count retired load uops that missed the STLB. 810.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES 811.Pq Event D0H , Umask 12H 812Count retired store uops that missed the STLB. 813.It Li MEM_UOPS_RETIRED.SPLIT_LOADS 814.Pq Event D0H , Umask 41H 815Count retired load uops that were split across a cache line. 816.It Li MEM_UOPS_RETIRED.SPLIT_STORES 817.Pq Event D0H , Umask 42H 818Count retired store uops that were split across a cache line. 819.It Li MEM_UOPS_RETIRED.ALL_LOADS 820.Pq Event D0H , Umask 81H 821Count all retired load uops. 822.It Li MEM_UOPS_RETIRED.ALL_STORES 823.Pq Event D0H , Umask 82H 824Count all retired store uops. 825.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 826.Pq Event D1H , Umask 01H 827Retired load uops with L1 cache hits as data sources. 828.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 829.Pq Event D1H , Umask 02H 830Retired load uops with L2 cache hits as data sources. 831.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 832.Pq Event D1H , Umask 04H 833Retired load uops with LLC cache hits as data 834sources. 835.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS 836.Pq Event D1H , Umask 10H 837Retired load uops missed L2. 838Unknown data source excluded. 839.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 840.Pq Event D1H , Umask 40H 841Retired load uops which data sources were load uops 842missed L1 but hit FB due to preceding miss to the 843same cache line with data not ready. 844.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 845.Pq Event D2H , Umask 01H 846Retired load uops which data sources were LLC hit 847and cross-core snoop missed in on-pkg core cache. 848.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 849.Pq Event D2H , Umask 02H 850Retired load uops which data sources were LLC and 851cross-core snoop hits in on-pkg core cache. 852.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 853.Pq Event D2H , Umask 04H 854Retired load uops which data sources were HitM 855responses from shared LLC. 856.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 857.Pq Event D2H , Umask 08H 858Retired load uops which data sources were hits in 859LLC without snoops required. 860.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 861.Pq Event D3H , Umask 01H 862Retired load uops which data sources missed LLC but 863serviced from local dram. 864.It Li BACLEARS.ANY 865.Pq Event E6H , Umask 1FH 866Number of front end re-steers due to BPU 867misprediction. 868.It Li L2_TRANS.DEMAND_DATA_RD 869.Pq Event F0H , Umask 01H 870Demand Data Read requests that access L2 cache. 871.It Li L2_TRANS.RFO 872.Pq Event F0H , Umask 02H 873RFO requests that access L2 cache. 874.It Li L2_TRANS.CODE_RD 875.Pq Event F0H , Umask 04H 876L2 cache accesses when fetching instructions. 877.It Li L2_TRANS.ALL_PF 878.Pq Event F0H , Umask 08H 879Any MLC or LLC HW prefetch accessing L2, including 880rejects. 881.It Li L2_TRANS.L1D_WB 882.Pq Event F0H , Umask 10H 883L1D writebacks that access L2 cache. 884.It Li L2_TRANS.L2_FILL 885.Pq Event F0H , Umask 20H 886L2 fill requests that access L2 cache. 887.It Li L2_TRANS.L2_WB 888.Pq Event F0H , Umask 40H 889L2 writebacks that access L2 cache. 890.It Li L2_TRANS.ALL_REQUESTS 891.Pq Event F0H , Umask 80H 892Transactions accessing L2 pipe. 893.It Li L2_LINES_IN.I 894.Pq Event F1H , Umask 01H 895L2 cache lines in I state filling L2. 896.It Li L2_LINES_IN.S 897.Pq Event F1H , Umask 02H 898L2 cache lines in S state filling L2. 899.It Li L2_LINES_IN.E 900.Pq Event F1H , Umask 04H 901L2 cache lines in E state filling L2. 902.It Li L2_LINES_IN.ALL 903.Pq Event F1H , Umask 07H 904L2 cache lines filling L2. 905.It Li L2_LINES_OUT.DEMAND_CLEAN 906.Pq Event F2H , Umask 05H 907Clean L2 cache lines evicted by demand. 908.It Li L2_LINES_OUT.DEMAND_DIRTY 909.Pq Event F2H , Umask 06H 910Dirty L2 cache lines evicted by demand. 911.El 912.Sh SEE ALSO 913.Xr pmc 3 , 914.Xr pmc.atom 3 , 915.Xr pmc.core 3 , 916.Xr pmc.corei7 3 , 917.Xr pmc.corei7uc 3 , 918.Xr pmc.haswelluc 3 , 919.Xr pmc.iaf 3 , 920.Xr pmc.ivybridge 3 , 921.Xr pmc.ivybridgexeon 3 , 922.Xr pmc.k7 3 , 923.Xr pmc.k8 3 , 924.Xr pmc.p4 3 , 925.Xr pmc.p5 3 , 926.Xr pmc.p6 3 , 927.Xr pmc.sandybridge 3 , 928.Xr pmc.sandybridgeuc 3 , 929.Xr pmc.sandybridgexeon 3 , 930.Xr pmc.soft 3 , 931.Xr pmc.tsc 3 , 932.Xr pmc.ucf 3 , 933.Xr pmc.westmere 3 , 934.Xr pmc.westmereuc 3 , 935.Xr pmc_cpuinfo 3 , 936.Xr pmclog 3 , 937.Xr hwpmc 4 938.Sh HISTORY 939The 940.Nm pmc 941library first appeared in 942.Fx 6.0 . 943.Sh AUTHORS 944.An -nosplit 945The 946.Lb libpmc 947library was written by 948.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 949The support for the Haswell 950microarchitecture was written by 951.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 952