1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 24, 2010 27.Dt PMC.COREI7UC 3 28.Os 29.Sh NAME 30.Nm pmc.corei7uc 31.Nd uncore measurement events for 32.Tn Intel 33.Tn Core i7 and Xeon 5500 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core i7" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs contain 2 classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_UCP" 47.It Li PMC_CLASS_UCF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_UCP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Core i7 and Xeon 5500 PMCs are documented in 59.Rs 60.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 61.%T "Volume 3B: System Programming Guide, Part 2" 62.%N "Order Number: 253669-033US" 63.%D December 2009 64.%Q "Intel Corporation" 65.Re 66.Ss COREI7 AND XEON 5500 UNCORE FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.ucf 3 . 69.Ss COREI7 AND XEON 5500 UNCORE PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta \&No 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta \&No 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta \&No 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li cmask= Ns Ar value 90Configure the PMC to increment only if the number of configured 91events measured in a cycle is greater than or equal to 92.Ar value . 93.It Li edge 94Configure the PMC to count the number of de-asserted to asserted 95transitions of the conditions expressed by the other qualifiers. 96If specified, the counter will increment only once whenever a 97condition becomes true, irrespective of the number of clocks during 98which the condition remains true. 99.It Li inv 100Invert the sense of comparison when the 101.Dq Li cmask 102qualifier is present, making the counter increment when the number of 103events per cycle is less than the value specified by the 104.Dq Li cmask 105qualifier. 106.El 107.Ss Event Specifiers (Programmable PMCs) 108Core i7 and Xeon 5500 uncore programmable PMCs support the following events: 109.Bl -tag -width indent 110.It Li GQ_CYCLES_FULL.READ_TRACKER 111.Pq Event 00H , Umask 01H 112Uncore cycles Global Queue read tracker is full. 113.It Li GQ_CYCLES_FULL.WRITE_TRACKER 114.Pq Event 00H , Umask 02H 115Uncore cycles Global Queue write tracker is full. 116.It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER 117.Pq Event 00H , Umask 04H 118Uncore cycles Global Queue peer probe tracker is full. The peer probe 119tracker queue tracks snoops from the IOH and remote sockets. 120.It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER 121.Pq Event 01H , Umask 01H 122Uncore cycles were Global Queue read tracker has at least one valid entry. 123.It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER 124.Pq Event 01H , Umask 02H 125Uncore cycles were Global Queue write tracker has at least one valid entry. 126.It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER 127.Pq Event 01H , Umask 04H 128Uncore cycles were Global Queue peer probe tracker has at least one valid 129entry. The peer probe tracker queue tracks IOH and remote socket snoops. 130.It Li GQ_ALLOC.READ_TRACKER 131.Pq Event 03H , Umask 01H 132Counts the number of tread tracker allocate to deallocate entries. The GQ 133read tracker allocate to deallocate occupancy count is divided by the count 134to obtain the average read tracker latency. 135.It Li GQ_ALLOC.RT_L3_MISS 136.Pq Event 03H , Umask 02H 137Counts the number GQ read tracker entries for which a full cache line read 138has missed the L3. The GQ read tracker L3 miss to fill occupancy count is 139divided by this count to obtain the average cache line read L3 miss latency. 140The latency represents the time after which the L3 has determined that the 141cache line has missed. The time between a GQ read tracker allocation and the 142L3 determining that the cache line has missed is the average L3 hit latency. 143The total L3 cache line read miss latency is the hit latency + L3 miss 144latency. 145.It Li GQ_ALLOC.RT_TO_L3_RESP 146.Pq Event 03H , Umask 04H 147Counts the number of GQ read tracker entries that are allocated in the read 148tracker queue that hit or miss the L3. The GQ read tracker L3 hit occupancy 149count is divided by this count to obtain the average L3 hit latency. 150.It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED 151.Pq Event 03H , Umask 08H 152Counts the number of GQ read tracker entries that are allocated in the read 153tracker, have missed in the L3 and have not acquired a Request Transaction 154ID. The GQ read tracker L3 miss to RTID acquired occupancy count is 155divided by this count to obtain the average latency for a read L3 miss to 156acquire an RTID. 157.It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED 158.Pq Event 03H , Umask 10H 159Counts the number of GQ write tracker entries that are allocated in the 160write tracker, have missed in the L3 and have not acquired a Request 161Transaction ID. The GQ write tracker L3 miss to RTID occupancy count is 162divided by this count to obtain the average latency for a write L3 miss to 163acquire an RTID. 164.It Li GQ_ALLOC.WRITE_TRACKER 165.Pq Event 03H , Umask 20H 166Counts the number of GQ write tracker entries that are allocated in the 167write tracker queue that miss the L3. The GQ write tracker occupancy count 168is divided by the this count to obtain the average L3 write miss latency. 169.It Li GQ_ALLOC.PEER_PROBE_TRACKER 170.Pq Event 03H , Umask 40H 171Counts the number of GQ peer probe tracker (snoop) entries that are 172allocated in the peer probe tracker queue that miss the L3. The GQ peer 173probe occupancy count is divided by this count to obtain the average L3 peer 174probe miss latency. 175.It Li GQ_DATA.FROM_QPI 176.Pq Event 04H , Umask 01H 177Cycles Global Queue Quickpath Interface input data port is busy importing 178data from the Quickpath Interface. Each cycle the input port can transfer 8 179or 16 bytes of data. 180.It Li GQ_DATA.FROM_QMC 181.Pq Event 04H , Umask 02H 182Cycles Global Queue Quickpath Memory Interface input data port is busy 183importing data from the Quickpath Memory Interface. Each cycle the input 184port can transfer 8 or 16 bytes of data. 185.It Li GQ_DATA.FROM_L3 186.Pq Event 04H , Umask 04H 187Cycles GQ L3 input data port is busy importing data from the Last Level 188Cache. Each cycle the input port can transfer 32 bytes of data. 189.It Li GQ_DATA.FROM_CORES_02 190.Pq Event 04H , Umask 08H 191Cycles GQ Core 0 and 2 input data port is busy importing data from processor 192cores 0 and 2. Each cycle the input port can transfer 32 bytes of data. 193.It Li GQ_DATA.FROM_CORES_13 194.Pq Event 04H , Umask 10H 195Cycles GQ Core 1 and 3 input data port is busy importing data from processor 196cores 1 and 3. Each cycle the input port can transfer 32 bytes of data. 197.It Li GQ_DATA.TO_QPI_QMC 198.Pq Event 05H , Umask 01H 199Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath 200Interface or Quickpath Memory Interface. Each cycle the output port can 201transfer 32 bytes of data. 202.It Li GQ_DATA.TO_L3 203.Pq Event 05H , Umask 02H 204Cycles GQ L3 output data port is busy sending data to the Last Level Cache. 205Each cycle the output port can transfer 32 bytes of data. 206.It Li GQ_DATA.TO_CORES 207.Pq Event 05H , Umask 04H 208Cycles GQ Core output data port is busy sending data to the Cores. Each 209cycle the output port can transfer 32 bytes of data. 210.It Li SNP_RESP_TO_LOCAL_HOME.I_STATE 211.Pq Event 06H , Umask 01H 212Number of snoop responses to the local home that L3 does not have the 213referenced cache line. 214.It Li SNP_RESP_TO_LOCAL_HOME.S_STATE 215.Pq Event 06H , Umask 02H 216Number of snoop responses to the local home that L3 has the referenced line 217cached in the S state. 218.It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE 219.Pq Event 06H , Umask 04H 220Number of responses to code or data read snoops to the local home that the 221L3 has the referenced cache line in the E state. The L3 cache line state is 222changed to the S state and the line is forwarded to the local home in the S 223state. 224.It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE 225.Pq Event 06H , Umask 08H 226Number of responses to read invalidate snoops to the local home that the L3 227has the referenced cache line in the M state. The L3 cache line state is 228invalidated and the line is forwarded to the local home in the M state. 229.It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT 230.Pq Event 06H , Umask 10H 231Number of conflict snoop responses sent to the local home. 232.It Li SNP_RESP_TO_LOCAL_HOME.WB 233.Pq Event 06H , Umask 20H 234Number of responses to code or data read snoops to the local home that the 235L3 has the referenced line cached in the M state. 236.It Li SNP_RESP_TO_REMOTE_HOME.I_STATE 237.Pq Event 07H , Umask 01H 238Number of snoop responses to a remote home that L3 does not have the 239referenced cache line. 240.It Li SNP_RESP_TO_REMOTE_HOME.S_STATE 241.Pq Event 07H , Umask 02H 242Number of snoop responses to a remote home that L3 has the referenced line 243cached in the S state. 244.It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE 245.Pq Event 07H , Umask 04H 246Number of responses to code or data read snoops to a remote home that the L3 247has the referenced cache line in the E state. The L3 cache line state is 248changed to the S state and the line is forwarded to the remote home in the S 249state. 250.It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE 251.Pq Event 07H , Umask 08H 252Number of responses to read invalidate snoops to a remote home that the L3 253has the referenced cache line in the M state. The L3 cache line state is 254invalidated and the line is forwarded to the remote home in the M state. 255.It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT 256.Pq Event 07H , Umask 10H 257Number of conflict snoop responses sent to the local home. 258.It Li SNP_RESP_TO_REMOTE_HOME.WB 259.Pq Event 07H , Umask 20H 260Number of responses to code or data read snoops to a remote home that the L3 261has the referenced line cached in the M state. 262.It Li SNP_RESP_TO_REMOTE_HOME.HITM 263.Pq Event 07H , Umask 24H 264Number of HITM snoop responses to a remote home 265.It Li L3_HITS.READ 266.Pq Event 08H , Umask 01H 267Number of code read, data read and RFO requests that hit in the L3 268.It Li L3_HITS.WRITE 269.Pq Event 08H , Umask 02H 270Number of writeback requests that hit in the L3. Writebacks from the cores 271will always result in L3 hits due to the inclusive property of the L3. 272.It Li L3_HITS.PROBE 273.Pq Event 08H , Umask 04H 274Number of snoops from IOH or remote sockets that hit in the L3. 275.It Li L3_HITS.ANY 276.Pq Event 08H , Umask 03H 277Number of reads and writes that hit the L3. 278.It Li L3_MISS.READ 279.Pq Event 09H , Umask 01H 280Number of code read, data read and RFO requests that miss the L3. 281.It Li L3_MISS.WRITE 282.Pq Event 09H , Umask 02H 283Number of writeback requests that miss the L3. Should always be zero as 284writebacks from the cores will always result in L3 hits due to the inclusive 285property of the L3. 286.It Li L3_MISS.PROBE 287.Pq Event 09H , Umask 04H 288Number of snoops from IOH or remote sockets that miss the L3. 289.It Li L3_MISS.ANY 290.Pq Event 09H , Umask 03H 291Number of reads and writes that miss the L3. 292.It Li L3_LINES_IN.M_STATE 293.Pq Event 0AH , Umask 01H 294Counts the number of L3 lines allocated in M state. The only time a cache 295line is allocated in the M state is when the line was forwarded in M state 296is forwarded due to a Snoop Read Invalidate Own request. 297.It Li L3_LINES_IN.E_STATE 298.Pq Event 0AH , Umask 02H 299Counts the number of L3 lines allocated in E state. 300.It Li L3_LINES_IN.S_STATE 301.Pq Event 0AH , Umask 04H 302Counts the number of L3 lines allocated in S state. 303.It Li L3_LINES_IN.F_STATE 304.Pq Event 0AH , Umask 08H 305Counts the number of L3 lines allocated in F state. 306.It Li L3_LINES_IN.ANY 307.Pq Event 0AH , Umask 0FH 308Counts the number of L3 lines allocated in any state. 309.It Li L3_LINES_OUT.M_STATE 310.Pq Event 0BH , Umask 01H 311Counts the number of L3 lines victimized that were in the M state. When the 312victim cache line is in M state, the line is written to its home cache agent 313which can be either local or remote. 314.It Li L3_LINES_OUT.E_STATE 315.Pq Event 0BH , Umask 02H 316Counts the number of L3 lines victimized that were in the E state. 317.It Li L3_LINES_OUT.S_STATE 318.Pq Event 0BH , Umask 04H 319Counts the number of L3 lines victimized that were in the S state. 320.It Li L3_LINES_OUT.I_STATE 321.Pq Event 0BH , Umask 08H 322Counts the number of L3 lines victimized that were in the I state. 323.It Li L3_LINES_OUT.F_STATE 324.Pq Event 0BH , Umask 10H 325Counts the number of L3 lines victimized that were in the F state. 326.It Li L3_LINES_OUT.ANY 327.Pq Event 0BH , Umask 1FH 328Counts the number of L3 lines victimized in any state. 329.It Li QHL_REQUESTS.IOH_READS 330.Pq Event 20H , Umask 01H 331Counts number of Quickpath Home Logic read requests from the IOH. 332.It Li QHL_REQUESTS.IOH_WRITES 333.Pq Event 20H , Umask 02H 334Counts number of Quickpath Home Logic write requests from the IOH. 335.It Li QHL_REQUESTS.REMOTE_READS 336.Pq Event 20H , Umask 04H 337Counts number of Quickpath Home Logic read requests from a remote socket. 338.It Li QHL_REQUESTS.REMOTE_WRITES 339.Pq Event 20H , Umask 08H 340Counts number of Quickpath Home Logic write requests from a remote socket. 341.It Li QHL_REQUESTS.LOCAL_READS 342.Pq Event 20H , Umask 10H 343Counts number of Quickpath Home Logic read requests from the local socket. 344.It Li QHL_REQUESTS.LOCAL_WRITES 345.Pq Event 20H , Umask 20H 346Counts number of Quickpath Home Logic write requests from the local socket. 347.It Li QHL_CYCLES_FULL.IOH 348.Pq Event 21H , Umask 01H 349Counts uclk cycles all entries in the Quickpath Home Logic IOH are full. 350.It Li QHL_CYCLES_FULL.REMOTE 351.Pq Event 21H , Umask 02H 352Counts uclk cycles all entries in the Quickpath Home Logic remote tracker 353are full. 354.It Li QHL_CYCLES_FULL.LOCAL 355.Pq Event 21H , Umask 04H 356Counts uclk cycles all entries in the Quickpath Home Logic local tracker are 357full. 358.It Li QHL_CYCLES_NOT_EMPTY.IOH 359.Pq Event 22H , Umask 01H 360Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy. 361.It Li QHL_CYCLES_NOT_EMPTY.REMOTE 362.Pq Event 22H , Umask 02H 363Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is 364busy. 365.It Li QHL_CYCLES_NOT_EMPTY.LOCAL 366.Pq Event 22H , Umask 04H 367Counts uclk cycles all entries in the Quickpath Home Logic local tracker is 368busy. 369.It Li QHL_OCCUPANCY.IOH 370.Pq Event 23H , Umask 01H 371QHL IOH tracker allocate to deallocate read occupancy. 372.It Li QHL_OCCUPANCY.REMOTE 373.Pq Event 23H , Umask 02H 374QHL remote tracker allocate to deallocate read occupancy. 375.It Li QHL_OCCUPANCY.LOCAL 376.Pq Event 23H , Umask 04H 377QHL local tracker allocate to deallocate read occupancy. 378.It Li QHL_ADDRESS_CONFLICTS.2WAY 379.Pq Event 24H , Umask 02H 380Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 381conflicts. The AAT is a structure that tracks requests that are in conflict. 382The requests themselves are in the home tracker entries. The count is 383reported when an AAT entry deallocates. 384.It Li QHL_ADDRESS_CONFLICTS.3WAY 385.Pq Event 24H , Umask 04H 386Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 387conflicts. The AAT is a structure that tracks requests that are in conflict. 388The requests themselves are in the home tracker entries. The count is 389reported when an AAT entry deallocates. 390.It Li QHL_CONFLICT_CYCLES.IOH 391.Pq Event 25H , Umask 01H 392Counts cycles the Quickpath Home Logic IOH Tracker contains two or more 393requests with an address conflict. A max of 3 requests can be in conflict. 394.It Li QHL_CONFLICT_CYCLES.REMOTE 395.Pq Event 25H , Umask 02H 396Counts cycles the Quickpath Home Logic Remote Tracker contains two or more 397requests with an address conflict. A max of 3 requests can be in conflict. 398.It Li QHL_CONFLICT_CYCLES.LOCAL 399.Pq Event 25H , Umask 04H 400Counts cycles the Quickpath Home Logic Local Tracker contains two or more 401requests with an address conflict. A max of 3 requests can be in conflict. 402.It Li QHL_TO_QMC_BYPASS 403.Pq Event 26H , Umask 01H 404Counts number or requests to the Quickpath Memory Controller that bypass the 405Quickpath Home Logic. All local accesses can be bypassed. For remote 406requests, only read requests can be bypassed. 407.It Li QMC_NORMAL_FULL.READ.CH0 408.Pq Event 27H , Umask 01H 409Uncore cycles all the entries in the DRAM channel 0 medium or low priority 410queue are occupied with read requests. 411.It Li QMC_NORMAL_FULL.READ.CH1 412.Pq Event 27H , Umask 02H 413Uncore cycles all the entries in the DRAM channel 1 medium or low priority 414queue are occupied with read requests. 415.It Li QMC_NORMAL_FULL.READ.CH2 416.Pq Event 27H , Umask 04H 417Uncore cycles all the entries in the DRAM channel 2 medium or low priority 418queue are occupied with read requests. 419.It Li QMC_NORMAL_FULL.WRITE.CH0 420.Pq Event 27H , Umask 08H 421Uncore cycles all the entries in the DRAM channel 0 medium or low priority 422queue are occupied with write requests. 423.It Li QMC_NORMAL_FULL.WRITE.CH1 424.Pq Event 27H , Umask 10H 425Counts cycles all the entries in the DRAM channel 1 medium or low priority 426queue are occupied with write requests. 427.It Li QMC_NORMAL_FULL.WRITE.CH2 428.Pq Event 27H , Umask 20H 429Uncore cycles all the entries in the DRAM channel 2 medium or low priority 430queue are occupied with write requests. 431.It Li QMC_ISOC_FULL.READ.CH0 432.Pq Event 28H , Umask 01H 433Counts cycles all the entries in the DRAM channel 0 high priority queue are 434occupied with isochronous read requests. 435.It Li QMC_ISOC_FULL.READ.CH1 436.Pq Event 28H , Umask 02H 437Counts cycles all the entries in the DRAM channel 1 high priority queue are 438occupied with isochronous read requests. 439.It Li QMC_ISOC_FULL.READ.CH2 440.Pq Event 28H , Umask 04H 441Counts cycles all the entries in the DRAM channel 2 high priority queue are 442occupied with isochronous read requests. 443.It Li QMC_ISOC_FULL.WRITE.CH0 444.Pq Event 28H , Umask 08H 445Counts cycles all the entries in the DRAM channel 0 high priority queue are 446occupied with isochronous write requests. 447.It Li QMC_ISOC_FULL.WRITE.CH1 448.Pq Event 28H , Umask 10H 449Counts cycles all the entries in the DRAM channel 1 high priority queue are 450occupied with isochronous write requests. 451.It Li QMC_ISOC_FULL.WRITE.CH2 452.Pq Event 28H , Umask 20H 453Counts cycles all the entries in the DRAM channel 2 high priority queue are 454occupied with isochronous write requests. 455.It Li QMC_BUSY.READ.CH0 456.Pq Event 29H , Umask 01H 457Counts cycles where Quickpath Memory Controller has at least 1 outstanding 458read request to DRAM channel 0. 459.It Li QMC_BUSY.READ.CH1 460.Pq Event 29H , Umask 02H 461Counts cycles where Quickpath Memory Controller has at least 1 outstanding 462read request to DRAM channel 1. 463.It Li QMC_BUSY.READ.CH2 464.Pq Event 29H , Umask 04H 465Counts cycles where Quickpath Memory Controller has at least 1 outstanding 466read request to DRAM channel 2. 467.It Li QMC_BUSY.WRITE.CH0 468.Pq Event 29H , Umask 08H 469Counts cycles where Quickpath Memory Controller has at least 1 outstanding 470write request to DRAM channel 0. 471.It Li QMC_BUSY.WRITE.CH1 472.Pq Event 29H , Umask 10H 473Counts cycles where Quickpath Memory Controller has at least 1 outstanding 474write request to DRAM channel 1. 475.It Li QMC_BUSY.WRITE.CH2 476.Pq Event 29H , Umask 20H 477Counts cycles where Quickpath Memory Controller has at least 1 outstanding 478write request to DRAM channel 2. 479.It Li QMC_OCCUPANCY.CH0 480.Pq Event 2AH , Umask 01H 481IMC channel 0 normal read request occupancy. 482.It Li QMC_OCCUPANCY.CH1 483.Pq Event 2AH , Umask 02H 484IMC channel 1 normal read request occupancy. 485.It Li QMC_OCCUPANCY.CH2 486.Pq Event 2AH , Umask 04H 487IMC channel 2 normal read request occupancy. 488.It Li QMC_ISSOC_OCCUPANCY.CH0 489.Pq Event 2BH , Umask 01H 490IMC channel 0 issoc read request occupancy. 491.It Li QMC_ISSOC_OCCUPANCY.CH1 492.Pq Event 2BH , Umask 02H 493IMC channel 1 issoc read request occupancy. 494.It Li QMC_ISSOC_OCCUPANCY.CH2 495.Pq Event 2BH , Umask 04H 496IMC channel 2 issoc read request occupancy. 497.It Li QMC_ISSOC_READS.ANY 498.Pq Event 2BH , Umask 07H 499IMC issoc read request occupancy. 500.It Li QMC_NORMAL_READS.CH0 501.Pq Event 2CH , Umask 01H 502Counts the number of Quickpath Memory Controller channel 0 medium and low 503priority read requests. The QMC channel 0 normal read occupancy divided by 504this count provides the average QMC channel 0 read latency. 505.It Li QMC_NORMAL_READS.CH1 506.Pq Event 2CH , Umask 02H 507Counts the number of Quickpath Memory Controller channel 1 medium and low 508priority read requests. The QMC channel 1 normal read occupancy divided by 509this count provides the average QMC channel 1 read latency. 510.It Li QMC_NORMAL_READS.CH2 511.Pq Event 2CH , Umask 04H 512Counts the number of Quickpath Memory Controller channel 2 medium and low 513priority read requests. The QMC channel 2 normal read occupancy divided by 514this count provides the average QMC channel 2 read latency. 515.It Li QMC_NORMAL_READS.ANY 516.Pq Event 2CH , Umask 07H 517Counts the number of Quickpath Memory Controller medium and low priority 518read requests. The QMC normal read occupancy divided by this count provides 519the average QMC read latency. 520.It Li QMC_HIGH_PRIORITY_READS.CH0 521.Pq Event 2DH , Umask 01H 522Counts the number of Quickpath Memory Controller channel 0 high priority 523isochronous read requests. 524.It Li QMC_HIGH_PRIORITY_READS.CH1 525.Pq Event 2DH , Umask 02H 526Counts the number of Quickpath Memory Controller channel 1 high priority 527isochronous read requests. 528.It Li QMC_HIGH_PRIORITY_READS.CH2 529.Pq Event 2DH , Umask 04H 530Counts the number of Quickpath Memory Controller channel 2 high priority 531isochronous read requests. 532.It Li QMC_HIGH_PRIORITY_READS.ANY 533.Pq Event 2DH , Umask 07H 534Counts the number of Quickpath Memory Controller high priority isochronous 535read requests. 536.It Li QMC_CRITICAL_PRIORITY_READS.CH0 537.Pq Event 2EH , Umask 01H 538Counts the number of Quickpath Memory Controller channel 0 critical priority 539isochronous read requests. 540.It Li QMC_CRITICAL_PRIORITY_READS.CH1 541.Pq Event 2EH , Umask 02H 542Counts the number of Quickpath Memory Controller channel 1 critical priority 543isochronous read requests. 544.It Li QMC_CRITICAL_PRIORITY_READS.CH2 545.Pq Event 2EH , Umask 04H 546Counts the number of Quickpath Memory Controller channel 2 critical priority 547isochronous read requests. 548.It Li QMC_CRITICAL_PRIORITY_READS.ANY 549.Pq Event 2EH , Umask 07H 550Counts the number of Quickpath Memory Controller critical priority 551isochronous read requests. 552.It Li QMC_WRITES.FULL.CH0 553.Pq Event 2FH , Umask 01H 554Counts number of full cache line writes to DRAM channel 0. 555.It Li QMC_WRITES.FULL.CH1 556.Pq Event 2FH , Umask 02H 557Counts number of full cache line writes to DRAM channel 1. 558.It Li QMC_WRITES.FULL.CH2 559.Pq Event 2FH , Umask 04H 560Counts number of full cache line writes to DRAM channel 2. 561.It Li QMC_WRITES.FULL.ANY 562.Pq Event 2FH , Umask 07H 563Counts number of full cache line writes to DRAM. 564.It Li QMC_WRITES.PARTIAL.CH0 565.Pq Event 2FH , Umask 08H 566Counts number of partial cache line writes to DRAM channel 0. 567.It Li QMC_WRITES.PARTIAL.CH1 568.Pq Event 2FH , Umask 10H 569Counts number of partial cache line writes to DRAM channel 1. 570.It Li QMC_WRITES.PARTIAL.CH2 571.Pq Event 2FH , Umask 20H 572Counts number of partial cache line writes to DRAM channel 2. 573.It Li QMC_WRITES.PARTIAL.ANY 574.Pq Event 2FH , Umask 38H 575Counts number of partial cache line writes to DRAM. 576.It Li QMC_CANCEL.CH0 577.Pq Event 30H , Umask 01H 578Counts number of DRAM channel 0 cancel requests. 579.It Li QMC_CANCEL.CH1 580.Pq Event 30H , Umask 02H 581Counts number of DRAM channel 1 cancel requests. 582.It Li QMC_CANCEL.CH2 583.Pq Event 30H , Umask 04H 584Counts number of DRAM channel 2 cancel requests. 585.It Li QMC_CANCEL.ANY 586.Pq Event 30H , Umask 07H 587Counts number of DRAM cancel requests. 588.It Li QMC_PRIORITY_UPDATES.CH0 589.Pq Event 31H , Umask 01H 590Counts number of DRAM channel 0 priority updates. A priority update occurs 591when an ISOC high or critical request is received by the QHL and there is a 592matching request with normal priority that has already been issued to the 593QMC. In this instance, the QHL will send a priority update to QMC to 594expedite the request. 595.It Li QMC_PRIORITY_UPDATES.CH1 596.Pq Event 31H , Umask 02H 597Counts number of DRAM channel 1 priority updates. A priority update occurs 598when an ISOC high or critical request is received by the QHL and there is a 599matching request with normal priority that has already been issued to the 600QMC. In this instance, the QHL will send a priority update to QMC to 601expedite the request. 602.It Li QMC_PRIORITY_UPDATES.CH2 603.Pq Event 31H , Umask 04H 604Counts number of DRAM channel 2 priority updates. A priority update occurs 605when an ISOC high or critical request is received by the QHL and there is a 606matching request with normal priority that has already been issued to the 607QMC. In this instance, the QHL will send a priority update to QMC to 608expedite the request. 609.It Li QMC_PRIORITY_UPDATES.ANY 610.Pq Event 31H , Umask 07H 611Counts number of DRAM priority updates. A priority update occurs when an 612ISOC high or critical request is received by the QHL and there is a matching 613request with normal priority that has already been issued to the QMC. In 614this instance, the QHL will send a priority update to QMC to expedite the 615request. 616.It Li QHL_FRC_ACK_CNFLTS.LOCAL 617.Pq Event 33H , Umask 04H 618Counts number of Force Acknowledge Conflict messages sent by the Quickpath 619Home Logic to the local home. 620.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 621.Pq Event 40H , Umask 01H 622Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled 623due to lack of a VNA and VN0 credit. Note that this event does not filter 624out when a flit would not have been selected for arbitration because another 625virtual channel is getting arbitrated. 626.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 627.Pq Event 40H , Umask 02H 628Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled 629due to lack of a VNA and VN0 credit. Note that this event does not filter 630out when a flit would not have been selected for arbitration because another 631virtual channel is getting arbitrated. 632.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 633.Pq Event 40H , Umask 04H 634Counts cycles the Quickpath outbound link 0 non-data response virtual 635channel is stalled due to lack of a VNA and VN0 credit. Note that this event 636does not filter out when a flit would not have been selected for arbitration 637because another virtual channel is getting arbitrated. 638.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 639.Pq Event 40H , Umask 08H 640Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled 641due to lack of a VNA and VN0 credit. Note that this event does not filter 642out when a flit would not have been selected for arbitration because another 643virtual channel is getting arbitrated. 644.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 645.Pq Event 40H , Umask 10H 646Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled 647due to lack of a VNA and VN0 credit. Note that this event does not filter 648out when a flit would not have been selected for arbitration because another 649virtual channel is getting arbitrated. 650.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 651.Pq Event 40H , Umask 20H 652Counts cycles the Quickpath outbound link 1 non-data response virtual 653channel is stalled due to lack of a VNA and VN0 credit. Note that this event 654does not filter out when a flit would not have been selected for arbitration 655because another virtual channel is getting arbitrated. 656.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 657.Pq Event 40H , Umask 07H 658Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 659to lack of a VNA and VN0 credit. Note that this event does not filter out 660when a flit would not have been selected for arbitration because another 661virtual channel is getting arbitrated. 662.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 663.Pq Event 40H , Umask 38H 664Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 665to lack of a VNA and VN0 credit. Note that this event does not filter out 666when a flit would not have been selected for arbitration because another 667virtual channel is getting arbitrated. 668.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 669.Pq Event 41H , Umask 01H 670Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is 671stalled due to lack of VNA and VN0 credits. Note that this event does not 672filter out when a flit would not have been selected for arbitration because 673another virtual channel is getting arbitrated. 674.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 675.Pq Event 41H , Umask 02H 676Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual 677channel is stalled due to lack of VNA and VN0 credits. Note that this event 678does not filter out when a flit would not have been selected for arbitration 679because another virtual channel is getting arbitrated. 680.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 681.Pq Event 41H , Umask 04H 682Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual 683channel is stalled due to lack of VNA and VN0 credits. Note that this event 684does not filter out when a flit would not have been selected for arbitration 685because another virtual channel is getting arbitrated. 686.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 687.Pq Event 41H , Umask 08H 688Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is 689stalled due to lack of VNA and VN0 credits. Note that this event does not 690filter out when a flit would not have been selected for arbitration because 691another virtual channel is getting arbitrated. 692.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 693.Pq Event 41H , Umask 10H 694Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual 695channel is stalled due to lack of VNA and VN0 credits. Note that this event 696does not filter out when a flit would not have been selected for arbitration 697because another virtual channel is getting arbitrated. 698.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 699.Pq Event 41H , Umask 20H 700Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual 701channel is stalled due to lack of VNA and VN0 credits. Note that this event 702does not filter out when a flit would not have been selected for arbitration 703because another virtual channel is getting arbitrated. 704.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 705.Pq Event 41H , Umask 07H 706Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 707to lack of VNA and VN0 credits. Note that this event does not filter out 708when a flit would not have been selected for arbitration because another 709virtual channel is getting arbitrated. 710.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 711.Pq Event 41H , Umask 38H 712Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 713to lack of VNA and VN0 credits. Note that this event does not filter out 714when a flit would not have been selected for arbitration because another 715virtual channel is getting arbitrated. 716.It Li QPI_TX_HEADER.BUSY.LINK_0 717.Pq Event 42H , Umask 02H 718Number of cycles that the header buffer in the Quickpath Interface outbound 719link 0 is busy. 720.It Li QPI_TX_HEADER.BUSY.LINK_1 721.Pq Event 42H , Umask 08H 722Number of cycles that the header buffer in the Quickpath Interface outbound 723link 1 is busy. 724.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 725.Pq Event 43H , Umask 01H 726Number of cycles that snoop packets incoming to the Quickpath Interface link 7270 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 728does not have any available entries. 729.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 730.Pq Event 43H , Umask 02H 731Number of cycles that snoop packets incoming to the Quickpath Interface link 7321 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 733does not have any available entries. 734.It Li DRAM_OPEN.CH0 735.Pq Event 60H , Umask 01H 736Counts number of DRAM Channel 0 open commands issued either for read or 737write. To read or write data, the referenced DRAM page must first be opened. 738.It Li DRAM_OPEN.CH1 739.Pq Event 60H , Umask 02H 740Counts number of DRAM Channel 1 open commands issued either for read or 741write. To read or write data, the referenced DRAM page must first be opened. 742.It Li DRAM_OPEN.CH2 743.Pq Event 60H , Umask 04H 744Counts number of DRAM Channel 2 open commands issued either for read or 745write. To read or write data, the referenced DRAM page must first be opened. 746.It Li DRAM_PAGE_CLOSE.CH0 747.Pq Event 61H , Umask 01H 748DRAM channel 0 command issued to CLOSE a page due to page idle timer 749expiration. Closing a page is done by issuing a precharge. 750.It Li DRAM_PAGE_CLOSE.CH1 751.Pq Event 61H , Umask 02H 752DRAM channel 1 command issued to CLOSE a page due to page idle timer 753expiration. Closing a page is done by issuing a precharge. 754.It Li DRAM_PAGE_CLOSE.CH2 755.Pq Event 61H , Umask 04H 756DRAM channel 2 command issued to CLOSE a page due to page idle timer 757expiration. Closing a page is done by issuing a precharge. 758.It Li DRAM_PAGE_MISS.CH0 759.Pq Event 62H , Umask 01H 760Counts the number of precharges (PRE) that were issued to DRAM channel 0 761because there was a page miss. A page miss refers to a situation in which a 762page is currently open and another page from the same bank needs to be 763opened. The new page experiences a page miss. Closing of the old page is 764done by issuing a precharge. 765.It Li DRAM_PAGE_MISS.CH1 766.Pq Event 62H , Umask 02H 767Counts the number of precharges (PRE) that were issued to DRAM channel 1 768because there was a page miss. A page miss refers to a situation in which a 769page is currently open and another page from the same bank needs to be 770opened. The new page experiences a page miss. Closing of the old page is 771done by issuing a precharge. 772.It Li DRAM_PAGE_MISS.CH2 773.Pq Event 62H , Umask 04H 774Counts the number of precharges (PRE) that were issued to DRAM channel 2 775because there was a page miss. A page miss refers to a situation in which a 776page is currently open and another page from the same bank needs to be 777opened. The new page experiences a page miss. Closing of the old page is 778done by issuing a precharge. 779.It Li DRAM_READ_CAS.CH0 780.Pq Event 63H , Umask 01H 781Counts the number of times a read CAS command was issued on DRAM channel 0. 782.It Li DRAM_READ_CAS.AUTOPRE_CH0 783.Pq Event 63H , Umask 02H 784Counts the number of times a read CAS command was issued on DRAM channel 0 785where the command issued used the auto-precharge (auto page close) mode. 786.It Li DRAM_READ_CAS.CH1 787.Pq Event 63H , Umask 04H 788Counts the number of times a read CAS command was issued on DRAM channel 1. 789.It Li DRAM_READ_CAS.AUTOPRE_CH1 790.Pq Event 63H , Umask 08H 791Counts the number of times a read CAS command was issued on DRAM channel 1 792where the command issued used the auto-precharge (auto page close) mode. 793.It Li DRAM_READ_CAS.CH2 794.Pq Event 63H , Umask 10H 795Counts the number of times a read CAS command was issued on DRAM channel 2. 796.It Li DRAM_READ_CAS.AUTOPRE_CH2 797.Pq Event 63H , Umask 20H 798Counts the number of times a read CAS command was issued on DRAM channel 2 799where the command issued used the auto-precharge (auto page close) mode. 800.It Li DRAM_WRITE_CAS.CH0 801.Pq Event 64H , Umask 01H 802Counts the number of times a write CAS command was issued on DRAM channel 0. 803.It Li DRAM_WRITE_CAS.AUTOPRE_CH0 804.Pq Event 64H , Umask 02H 805Counts the number of times a write CAS command was issued on DRAM channel 0 806where the command issued used the auto-precharge (auto page close) mode. 807.It Li DRAM_WRITE_CAS.CH1 808.Pq Event 64H , Umask 04H 809Counts the number of times a write CAS command was issued on DRAM channel 1. 810.It Li DRAM_WRITE_CAS.AUTOPRE_CH1 811.Pq Event 64H , Umask 08H 812Counts the number of times a write CAS command was issued on DRAM channel 1 813where the command issued used the auto-precharge (auto page close) mode. 814.It Li DRAM_WRITE_CAS.CH2 815.Pq Event 64H , Umask 10H 816Counts the number of times a write CAS command was issued on DRAM channel 2. 817.It Li DRAM_WRITE_CAS.AUTOPRE_CH2 818.Pq Event 64H , Umask 20H 819Counts the number of times a write CAS command was issued on DRAM channel 2 820where the command issued used the auto-precharge (auto page close) mode. 821.It Li DRAM_REFRESH.CH0 822.Pq Event 65H , Umask 01H 823Counts number of DRAM channel 0 refresh commands. DRAM loses data content 824over time. In order to keep correct data content, the data values have to be 825refreshed periodically. 826.It Li DRAM_REFRESH.CH1 827.Pq Event 65H , Umask 02H 828Counts number of DRAM channel 1 refresh commands. DRAM loses data content 829over time. In order to keep correct data content, the data values have to be 830refreshed periodically. 831.It Li DRAM_REFRESH.CH2 832.Pq Event 65H , Umask 04H 833Counts number of DRAM channel 2 refresh commands. DRAM loses data content 834over time. In order to keep correct data content, the data values have to be 835refreshed periodically. 836.It Li DRAM_PRE_ALL.CH0 837.Pq Event 66H , Umask 01H 838Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close 839all open pages in a rank. PREALL is issued when the DRAM needs to be 840refreshed or needs to go into a power down mode. 841.It Li DRAM_PRE_ALL.CH1 842.Pq Event 66H , Umask 02H 843Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close 844all open pages in a rank. PREALL is issued when the DRAM needs to be 845refreshed or needs to go into a power down mode. 846.It Li DRAM_PRE_ALL.CH2 847.Pq Event 66H , Umask 04H 848Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close 849all open pages in a rank. PREALL is issued when the DRAM needs to be 850refreshed or needs to go into a power down mode. 851.El 852.Sh SEE ALSO 853.Xr pmc 3 , 854.Xr pmc.atom 3 , 855.Xr pmc.core 3 , 856.Xr pmc.corei7 3 , 857.Xr pmc.iaf 3 , 858.Xr pmc.k7 3 , 859.Xr pmc.k8 3 , 860.Xr pmc.p4 3 , 861.Xr pmc.p5 3 , 862.Xr pmc.p6 3 , 863.Xr pmc.soft 3 , 864.Xr pmc.tsc 3 , 865.Xr pmc.ucf 3 , 866.Xr pmc.westmere 3 , 867.Xr pmc.westmereuc 3 , 868.Xr pmc_cpuinfo 3 , 869.Xr pmclog 3 , 870.Xr hwpmc 4 871.Sh HISTORY 872The 873.Nm pmc 874library first appeared in 875.Fx 6.0 . 876.Sh AUTHORS 877The 878.Lb libpmc 879library was written by 880.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 881