1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 24, 2010 27.Dt PMC.COREI7UC 3 28.Os 29.Sh NAME 30.Nm pmc.corei7uc 31.Nd uncore measurement events for 32.Tn Intel 33.Tn Core i7 and Xeon 5500 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core i7" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs contain 2 classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_UCP" 47.It Li PMC_CLASS_UCF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_UCP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Core i7 and Xeon 5500 PMCs are documented in 59.Rs 60.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 61.%T "Volume 3B: System Programming Guide, Part 2" 62.%N "Order Number: 253669-033US" 63.%D December 2009 64.%Q "Intel Corporation" 65.Re 66.Ss COREI7 AND XEON 5500 UNCORE FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.ucf 3 . 69.Ss COREI7 AND XEON 5500 UNCORE PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta \&No 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta \&No 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta \&No 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li cmask= Ns Ar value 90Configure the PMC to increment only if the number of configured 91events measured in a cycle is greater than or equal to 92.Ar value . 93.It Li edge 94Configure the PMC to count the number of de-asserted to asserted 95transitions of the conditions expressed by the other qualifiers. 96If specified, the counter will increment only once whenever a 97condition becomes true, irrespective of the number of clocks during 98which the condition remains true. 99.It Li inv 100Invert the sense of comparison when the 101.Dq Li cmask 102qualifier is present, making the counter increment when the number of 103events per cycle is less than the value specified by the 104.Dq Li cmask 105qualifier. 106.El 107.Ss Event Specifiers (Programmable PMCs) 108Core i7 and Xeon 5500 uncore programmable PMCs support the following events: 109.Bl -tag -width indent 110.It Li GQ_CYCLES_FULL.READ_TRACKER 111.Pq Event 00H , Umask 01H 112Uncore cycles Global Queue read tracker is full. 113.It Li GQ_CYCLES_FULL.WRITE_TRACKER 114.Pq Event 00H , Umask 02H 115Uncore cycles Global Queue write tracker is full. 116.It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER 117.Pq Event 00H , Umask 04H 118Uncore cycles Global Queue peer probe tracker is full. 119The peer probe tracker queue tracks snoops from the IOH and remote sockets. 120.It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER 121.Pq Event 01H , Umask 01H 122Uncore cycles were Global Queue read tracker has at least one valid entry. 123.It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER 124.Pq Event 01H , Umask 02H 125Uncore cycles were Global Queue write tracker has at least one valid entry. 126.It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER 127.Pq Event 01H , Umask 04H 128Uncore cycles were Global Queue peer probe tracker has at least one valid entry. 129The peer probe tracker queue tracks IOH and remote socket snoops. 130.It Li GQ_ALLOC.READ_TRACKER 131.Pq Event 03H , Umask 01H 132Counts the number of tread tracker allocate to deallocate entries. 133The GQ read tracker allocate to deallocate occupancy count is divided 134by the count to obtain the average read tracker latency. 135.It Li GQ_ALLOC.RT_L3_MISS 136.Pq Event 03H , Umask 02H 137Counts the number GQ read tracker entries for which a full cache line read 138has missed the L3. 139The GQ read tracker L3 miss to fill occupancy count is divided by this count 140to obtain the average cache line read L3 miss latency. 141The latency represents the time after which the L3 has determined that the 142cache line has missed. 143The time between a GQ read tracker allocation and the L3 determining that the 144cache line has missed is the average L3 hit latency. 145The total L3 cache line read miss latency is the hit latency + L3 miss 146latency. 147.It Li GQ_ALLOC.RT_TO_L3_RESP 148.Pq Event 03H , Umask 04H 149Counts the number of GQ read tracker entries that are allocated in the read 150tracker queue that hit or miss the L3. 151The GQ read tracker L3 hit occupancy count is divided by this count to obtain 152the average L3 hit latency. 153.It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED 154.Pq Event 03H , Umask 08H 155Counts the number of GQ read tracker entries that are allocated in the read 156tracker, have missed in the L3 and have not acquired a Request Transaction ID. 157The GQ read tracker L3 miss to RTID acquired occupancy count is 158divided by this count to obtain the average latency for a read L3 miss to 159acquire an RTID. 160.It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED 161.Pq Event 03H , Umask 10H 162Counts the number of GQ write tracker entries that are allocated in the 163write tracker, have missed in the L3 and have not acquired a Request 164Transaction ID. 165The GQ write tracker L3 miss to RTID occupancy count is divided by this count 166to obtain the average latency for a write L3 miss to acquire an RTID. 167.It Li GQ_ALLOC.WRITE_TRACKER 168.Pq Event 03H , Umask 20H 169Counts the number of GQ write tracker entries that are allocated in the 170write tracker queue that miss the L3. 171The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write miss latency. 172.It Li GQ_ALLOC.PEER_PROBE_TRACKER 173.Pq Event 03H , Umask 40H 174Counts the number of GQ peer probe tracker (snoop) entries that are 175allocated in the peer probe tracker queue that miss the L3. 176The GQ peer probe occupancy count is divided by this count to obtain the average L3 peer 177probe miss latency. 178.It Li GQ_DATA.FROM_QPI 179.Pq Event 04H , Umask 01H 180Cycles Global Queue Quickpath Interface input data port is busy importing 181data from the Quickpath Interface. 182Each cycle the input port can transfer 8 or 16 bytes of data. 183.It Li GQ_DATA.FROM_QMC 184.Pq Event 04H , Umask 02H 185Cycles Global Queue Quickpath Memory Interface input data port is busy 186importing data from the Quickpath Memory Interface. 187Each cycle the input port can transfer 8 or 16 bytes of data. 188.It Li GQ_DATA.FROM_L3 189.Pq Event 04H , Umask 04H 190Cycles GQ L3 input data port is busy importing data from the Last Level Cache. 191Each cycle the input port can transfer 32 bytes of data. 192.It Li GQ_DATA.FROM_CORES_02 193.Pq Event 04H , Umask 08H 194Cycles GQ Core 0 and 2 input data port is busy importing data from processor 195cores 0 and 2. 196Each cycle the input port can transfer 32 bytes of data. 197.It Li GQ_DATA.FROM_CORES_13 198.Pq Event 04H , Umask 10H 199Cycles GQ Core 1 and 3 input data port is busy importing data from processor 200cores 1 and 3. 201Each cycle the input port can transfer 32 bytes of data. 202.It Li GQ_DATA.TO_QPI_QMC 203.Pq Event 05H , Umask 01H 204Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath 205Interface or Quickpath Memory Interface. 206Each cycle the output port can transfer 32 bytes of data. 207.It Li GQ_DATA.TO_L3 208.Pq Event 05H , Umask 02H 209Cycles GQ L3 output data port is busy sending data to the Last Level Cache. 210Each cycle the output port can transfer 32 bytes of data. 211.It Li GQ_DATA.TO_CORES 212.Pq Event 05H , Umask 04H 213Cycles GQ Core output data port is busy sending data to the Cores. 214Each cycle the output port can transfer 32 bytes of data. 215.It Li SNP_RESP_TO_LOCAL_HOME.I_STATE 216.Pq Event 06H , Umask 01H 217Number of snoop responses to the local home that L3 does not have the 218referenced cache line. 219.It Li SNP_RESP_TO_LOCAL_HOME.S_STATE 220.Pq Event 06H , Umask 02H 221Number of snoop responses to the local home that L3 has the referenced line 222cached in the S state. 223.It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE 224.Pq Event 06H , Umask 04H 225Number of responses to code or data read snoops to the local home that the 226L3 has the referenced cache line in the E state. 227The L3 cache line state is changed to the S state and the line is 228forwarded to the local home in the S state. 229.It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE 230.Pq Event 06H , Umask 08H 231Number of responses to read invalidate snoops to the local home that the L3 232has the referenced cache line in the M state. 233The L3 cache line state is invalidated and the line is forwarded to the 234local home in the M state. 235.It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT 236.Pq Event 06H , Umask 10H 237Number of conflict snoop responses sent to the local home. 238.It Li SNP_RESP_TO_LOCAL_HOME.WB 239.Pq Event 06H , Umask 20H 240Number of responses to code or data read snoops to the local home that the 241L3 has the referenced line cached in the M state. 242.It Li SNP_RESP_TO_REMOTE_HOME.I_STATE 243.Pq Event 07H , Umask 01H 244Number of snoop responses to a remote home that L3 does not have the 245referenced cache line. 246.It Li SNP_RESP_TO_REMOTE_HOME.S_STATE 247.Pq Event 07H , Umask 02H 248Number of snoop responses to a remote home that L3 has the referenced line 249cached in the S state. 250.It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE 251.Pq Event 07H , Umask 04H 252Number of responses to code or data read snoops to a remote home that the L3 253has the referenced cache line in the E state. 254The L3 cache line state is changed to the S state and the line is forwarded to 255the remote home in the S state. 256.It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE 257.Pq Event 07H , Umask 08H 258Number of responses to read invalidate snoops to a remote home that the L3 259has the referenced cache line in the M state. 260The L3 cache line state is invalidated and the line is forwarded to the 261remote home in the M state. 262.It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT 263.Pq Event 07H , Umask 10H 264Number of conflict snoop responses sent to the local home. 265.It Li SNP_RESP_TO_REMOTE_HOME.WB 266.Pq Event 07H , Umask 20H 267Number of responses to code or data read snoops to a remote home that the L3 268has the referenced line cached in the M state. 269.It Li SNP_RESP_TO_REMOTE_HOME.HITM 270.Pq Event 07H , Umask 24H 271Number of HITM snoop responses to a remote home 272.It Li L3_HITS.READ 273.Pq Event 08H , Umask 01H 274Number of code read, data read and RFO requests that hit in the L3 275.It Li L3_HITS.WRITE 276.Pq Event 08H , Umask 02H 277Number of writeback requests that hit in the L3. 278Writebacks from the cores will always result in L3 hits due to the inclusive property of the L3. 279.It Li L3_HITS.PROBE 280.Pq Event 08H , Umask 04H 281Number of snoops from IOH or remote sockets that hit in the L3. 282.It Li L3_HITS.ANY 283.Pq Event 08H , Umask 03H 284Number of reads and writes that hit the L3. 285.It Li L3_MISS.READ 286.Pq Event 09H , Umask 01H 287Number of code read, data read and RFO requests that miss the L3. 288.It Li L3_MISS.WRITE 289.Pq Event 09H , Umask 02H 290Number of writeback requests that miss the L3. 291Should always be zero as writebacks from the cores will always result in 292L3 hits due to the inclusive property of the L3. 293.It Li L3_MISS.PROBE 294.Pq Event 09H , Umask 04H 295Number of snoops from IOH or remote sockets that miss the L3. 296.It Li L3_MISS.ANY 297.Pq Event 09H , Umask 03H 298Number of reads and writes that miss the L3. 299.It Li L3_LINES_IN.M_STATE 300.Pq Event 0AH , Umask 01H 301Counts the number of L3 lines allocated in M state. 302The only time a cache line is allocated in the M state is when the line 303was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request. 304.It Li L3_LINES_IN.E_STATE 305.Pq Event 0AH , Umask 02H 306Counts the number of L3 lines allocated in E state. 307.It Li L3_LINES_IN.S_STATE 308.Pq Event 0AH , Umask 04H 309Counts the number of L3 lines allocated in S state. 310.It Li L3_LINES_IN.F_STATE 311.Pq Event 0AH , Umask 08H 312Counts the number of L3 lines allocated in F state. 313.It Li L3_LINES_IN.ANY 314.Pq Event 0AH , Umask 0FH 315Counts the number of L3 lines allocated in any state. 316.It Li L3_LINES_OUT.M_STATE 317.Pq Event 0BH , Umask 01H 318Counts the number of L3 lines victimized that were in the M state. 319When the victim cache line is in M state, the line is written to its home cache agent 320which can be either local or remote. 321.It Li L3_LINES_OUT.E_STATE 322.Pq Event 0BH , Umask 02H 323Counts the number of L3 lines victimized that were in the E state. 324.It Li L3_LINES_OUT.S_STATE 325.Pq Event 0BH , Umask 04H 326Counts the number of L3 lines victimized that were in the S state. 327.It Li L3_LINES_OUT.I_STATE 328.Pq Event 0BH , Umask 08H 329Counts the number of L3 lines victimized that were in the I state. 330.It Li L3_LINES_OUT.F_STATE 331.Pq Event 0BH , Umask 10H 332Counts the number of L3 lines victimized that were in the F state. 333.It Li L3_LINES_OUT.ANY 334.Pq Event 0BH , Umask 1FH 335Counts the number of L3 lines victimized in any state. 336.It Li QHL_REQUESTS.IOH_READS 337.Pq Event 20H , Umask 01H 338Counts number of Quickpath Home Logic read requests from the IOH. 339.It Li QHL_REQUESTS.IOH_WRITES 340.Pq Event 20H , Umask 02H 341Counts number of Quickpath Home Logic write requests from the IOH. 342.It Li QHL_REQUESTS.REMOTE_READS 343.Pq Event 20H , Umask 04H 344Counts number of Quickpath Home Logic read requests from a remote socket. 345.It Li QHL_REQUESTS.REMOTE_WRITES 346.Pq Event 20H , Umask 08H 347Counts number of Quickpath Home Logic write requests from a remote socket. 348.It Li QHL_REQUESTS.LOCAL_READS 349.Pq Event 20H , Umask 10H 350Counts number of Quickpath Home Logic read requests from the local socket. 351.It Li QHL_REQUESTS.LOCAL_WRITES 352.Pq Event 20H , Umask 20H 353Counts number of Quickpath Home Logic write requests from the local socket. 354.It Li QHL_CYCLES_FULL.IOH 355.Pq Event 21H , Umask 01H 356Counts uclk cycles all entries in the Quickpath Home Logic IOH are full. 357.It Li QHL_CYCLES_FULL.REMOTE 358.Pq Event 21H , Umask 02H 359Counts uclk cycles all entries in the Quickpath Home Logic remote tracker 360are full. 361.It Li QHL_CYCLES_FULL.LOCAL 362.Pq Event 21H , Umask 04H 363Counts uclk cycles all entries in the Quickpath Home Logic local tracker are 364full. 365.It Li QHL_CYCLES_NOT_EMPTY.IOH 366.Pq Event 22H , Umask 01H 367Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy. 368.It Li QHL_CYCLES_NOT_EMPTY.REMOTE 369.Pq Event 22H , Umask 02H 370Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is 371busy. 372.It Li QHL_CYCLES_NOT_EMPTY.LOCAL 373.Pq Event 22H , Umask 04H 374Counts uclk cycles all entries in the Quickpath Home Logic local tracker is 375busy. 376.It Li QHL_OCCUPANCY.IOH 377.Pq Event 23H , Umask 01H 378QHL IOH tracker allocate to deallocate read occupancy. 379.It Li QHL_OCCUPANCY.REMOTE 380.Pq Event 23H , Umask 02H 381QHL remote tracker allocate to deallocate read occupancy. 382.It Li QHL_OCCUPANCY.LOCAL 383.Pq Event 23H , Umask 04H 384QHL local tracker allocate to deallocate read occupancy. 385.It Li QHL_ADDRESS_CONFLICTS.2WAY 386.Pq Event 24H , Umask 02H 387Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 388conflicts. 389The AAT is a structure that tracks requests that are in conflict. 390The requests themselves are in the home tracker entries. 391The count is reported when an AAT entry deallocates. 392.It Li QHL_ADDRESS_CONFLICTS.3WAY 393.Pq Event 24H , Umask 04H 394Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 395conflicts. 396The AAT is a structure that tracks requests that are in conflict. 397The requests themselves are in the home tracker entries. 398The count is reported when an AAT entry deallocates. 399.It Li QHL_CONFLICT_CYCLES.IOH 400.Pq Event 25H , Umask 01H 401Counts cycles the Quickpath Home Logic IOH Tracker contains two or more 402requests with an address conflict. 403A max of 3 requests can be in conflict. 404.It Li QHL_CONFLICT_CYCLES.REMOTE 405.Pq Event 25H , Umask 02H 406Counts cycles the Quickpath Home Logic Remote Tracker contains two or more 407requests with an address conflict. 408A max of 3 requests can be in conflict. 409.It Li QHL_CONFLICT_CYCLES.LOCAL 410.Pq Event 25H , Umask 04H 411Counts cycles the Quickpath Home Logic Local Tracker contains two or more 412requests with an address conflict. 413A max of 3 requests can be in conflict. 414.It Li QHL_TO_QMC_BYPASS 415.Pq Event 26H , Umask 01H 416Counts number or requests to the Quickpath Memory Controller that bypass the 417Quickpath Home Logic. 418All local accesses can be bypassed. 419For remote requests, only read requests can be bypassed. 420.It Li QMC_NORMAL_FULL.READ.CH0 421.Pq Event 27H , Umask 01H 422Uncore cycles all the entries in the DRAM channel 0 medium or low priority 423queue are occupied with read requests. 424.It Li QMC_NORMAL_FULL.READ.CH1 425.Pq Event 27H , Umask 02H 426Uncore cycles all the entries in the DRAM channel 1 medium or low priority 427queue are occupied with read requests. 428.It Li QMC_NORMAL_FULL.READ.CH2 429.Pq Event 27H , Umask 04H 430Uncore cycles all the entries in the DRAM channel 2 medium or low priority 431queue are occupied with read requests. 432.It Li QMC_NORMAL_FULL.WRITE.CH0 433.Pq Event 27H , Umask 08H 434Uncore cycles all the entries in the DRAM channel 0 medium or low priority 435queue are occupied with write requests. 436.It Li QMC_NORMAL_FULL.WRITE.CH1 437.Pq Event 27H , Umask 10H 438Counts cycles all the entries in the DRAM channel 1 medium or low priority 439queue are occupied with write requests. 440.It Li QMC_NORMAL_FULL.WRITE.CH2 441.Pq Event 27H , Umask 20H 442Uncore cycles all the entries in the DRAM channel 2 medium or low priority 443queue are occupied with write requests. 444.It Li QMC_ISOC_FULL.READ.CH0 445.Pq Event 28H , Umask 01H 446Counts cycles all the entries in the DRAM channel 0 high priority queue are 447occupied with isochronous read requests. 448.It Li QMC_ISOC_FULL.READ.CH1 449.Pq Event 28H , Umask 02H 450Counts cycles all the entries in the DRAM channel 1 high priority queue are 451occupied with isochronous read requests. 452.It Li QMC_ISOC_FULL.READ.CH2 453.Pq Event 28H , Umask 04H 454Counts cycles all the entries in the DRAM channel 2 high priority queue are 455occupied with isochronous read requests. 456.It Li QMC_ISOC_FULL.WRITE.CH0 457.Pq Event 28H , Umask 08H 458Counts cycles all the entries in the DRAM channel 0 high priority queue are 459occupied with isochronous write requests. 460.It Li QMC_ISOC_FULL.WRITE.CH1 461.Pq Event 28H , Umask 10H 462Counts cycles all the entries in the DRAM channel 1 high priority queue are 463occupied with isochronous write requests. 464.It Li QMC_ISOC_FULL.WRITE.CH2 465.Pq Event 28H , Umask 20H 466Counts cycles all the entries in the DRAM channel 2 high priority queue are 467occupied with isochronous write requests. 468.It Li QMC_BUSY.READ.CH0 469.Pq Event 29H , Umask 01H 470Counts cycles where Quickpath Memory Controller has at least 1 outstanding 471read request to DRAM channel 0. 472.It Li QMC_BUSY.READ.CH1 473.Pq Event 29H , Umask 02H 474Counts cycles where Quickpath Memory Controller has at least 1 outstanding 475read request to DRAM channel 1. 476.It Li QMC_BUSY.READ.CH2 477.Pq Event 29H , Umask 04H 478Counts cycles where Quickpath Memory Controller has at least 1 outstanding 479read request to DRAM channel 2. 480.It Li QMC_BUSY.WRITE.CH0 481.Pq Event 29H , Umask 08H 482Counts cycles where Quickpath Memory Controller has at least 1 outstanding 483write request to DRAM channel 0. 484.It Li QMC_BUSY.WRITE.CH1 485.Pq Event 29H , Umask 10H 486Counts cycles where Quickpath Memory Controller has at least 1 outstanding 487write request to DRAM channel 1. 488.It Li QMC_BUSY.WRITE.CH2 489.Pq Event 29H , Umask 20H 490Counts cycles where Quickpath Memory Controller has at least 1 outstanding 491write request to DRAM channel 2. 492.It Li QMC_OCCUPANCY.CH0 493.Pq Event 2AH , Umask 01H 494IMC channel 0 normal read request occupancy. 495.It Li QMC_OCCUPANCY.CH1 496.Pq Event 2AH , Umask 02H 497IMC channel 1 normal read request occupancy. 498.It Li QMC_OCCUPANCY.CH2 499.Pq Event 2AH , Umask 04H 500IMC channel 2 normal read request occupancy. 501.It Li QMC_ISSOC_OCCUPANCY.CH0 502.Pq Event 2BH , Umask 01H 503IMC channel 0 issoc read request occupancy. 504.It Li QMC_ISSOC_OCCUPANCY.CH1 505.Pq Event 2BH , Umask 02H 506IMC channel 1 issoc read request occupancy. 507.It Li QMC_ISSOC_OCCUPANCY.CH2 508.Pq Event 2BH , Umask 04H 509IMC channel 2 issoc read request occupancy. 510.It Li QMC_ISSOC_READS.ANY 511.Pq Event 2BH , Umask 07H 512IMC issoc read request occupancy. 513.It Li QMC_NORMAL_READS.CH0 514.Pq Event 2CH , Umask 01H 515Counts the number of Quickpath Memory Controller channel 0 medium and low 516priority read requests. 517The QMC channel 0 normal read occupancy divided by this count provides the 518average QMC channel 0 read latency. 519.It Li QMC_NORMAL_READS.CH1 520.Pq Event 2CH , Umask 02H 521Counts the number of Quickpath Memory Controller channel 1 medium and low 522priority read requests. 523The QMC channel 1 normal read occupancy divided by this count provides the 524average QMC channel 1 read latency. 525.It Li QMC_NORMAL_READS.CH2 526.Pq Event 2CH , Umask 04H 527Counts the number of Quickpath Memory Controller channel 2 medium and low 528priority read requests. 529The QMC channel 2 normal read occupancy divided by this count provides the 530average QMC channel 2 read latency. 531.It Li QMC_NORMAL_READS.ANY 532.Pq Event 2CH , Umask 07H 533Counts the number of Quickpath Memory Controller medium and low priority 534read requests. 535The QMC normal read occupancy divided by this count provides the average 536QMC read latency. 537.It Li QMC_HIGH_PRIORITY_READS.CH0 538.Pq Event 2DH , Umask 01H 539Counts the number of Quickpath Memory Controller channel 0 high priority 540isochronous read requests. 541.It Li QMC_HIGH_PRIORITY_READS.CH1 542.Pq Event 2DH , Umask 02H 543Counts the number of Quickpath Memory Controller channel 1 high priority 544isochronous read requests. 545.It Li QMC_HIGH_PRIORITY_READS.CH2 546.Pq Event 2DH , Umask 04H 547Counts the number of Quickpath Memory Controller channel 2 high priority 548isochronous read requests. 549.It Li QMC_HIGH_PRIORITY_READS.ANY 550.Pq Event 2DH , Umask 07H 551Counts the number of Quickpath Memory Controller high priority isochronous 552read requests. 553.It Li QMC_CRITICAL_PRIORITY_READS.CH0 554.Pq Event 2EH , Umask 01H 555Counts the number of Quickpath Memory Controller channel 0 critical priority 556isochronous read requests. 557.It Li QMC_CRITICAL_PRIORITY_READS.CH1 558.Pq Event 2EH , Umask 02H 559Counts the number of Quickpath Memory Controller channel 1 critical priority 560isochronous read requests. 561.It Li QMC_CRITICAL_PRIORITY_READS.CH2 562.Pq Event 2EH , Umask 04H 563Counts the number of Quickpath Memory Controller channel 2 critical priority 564isochronous read requests. 565.It Li QMC_CRITICAL_PRIORITY_READS.ANY 566.Pq Event 2EH , Umask 07H 567Counts the number of Quickpath Memory Controller critical priority 568isochronous read requests. 569.It Li QMC_WRITES.FULL.CH0 570.Pq Event 2FH , Umask 01H 571Counts number of full cache line writes to DRAM channel 0. 572.It Li QMC_WRITES.FULL.CH1 573.Pq Event 2FH , Umask 02H 574Counts number of full cache line writes to DRAM channel 1. 575.It Li QMC_WRITES.FULL.CH2 576.Pq Event 2FH , Umask 04H 577Counts number of full cache line writes to DRAM channel 2. 578.It Li QMC_WRITES.FULL.ANY 579.Pq Event 2FH , Umask 07H 580Counts number of full cache line writes to DRAM. 581.It Li QMC_WRITES.PARTIAL.CH0 582.Pq Event 2FH , Umask 08H 583Counts number of partial cache line writes to DRAM channel 0. 584.It Li QMC_WRITES.PARTIAL.CH1 585.Pq Event 2FH , Umask 10H 586Counts number of partial cache line writes to DRAM channel 1. 587.It Li QMC_WRITES.PARTIAL.CH2 588.Pq Event 2FH , Umask 20H 589Counts number of partial cache line writes to DRAM channel 2. 590.It Li QMC_WRITES.PARTIAL.ANY 591.Pq Event 2FH , Umask 38H 592Counts number of partial cache line writes to DRAM. 593.It Li QMC_CANCEL.CH0 594.Pq Event 30H , Umask 01H 595Counts number of DRAM channel 0 cancel requests. 596.It Li QMC_CANCEL.CH1 597.Pq Event 30H , Umask 02H 598Counts number of DRAM channel 1 cancel requests. 599.It Li QMC_CANCEL.CH2 600.Pq Event 30H , Umask 04H 601Counts number of DRAM channel 2 cancel requests. 602.It Li QMC_CANCEL.ANY 603.Pq Event 30H , Umask 07H 604Counts number of DRAM cancel requests. 605.It Li QMC_PRIORITY_UPDATES.CH0 606.Pq Event 31H , Umask 01H 607Counts number of DRAM channel 0 priority updates. 608A priority update occurs when an ISOC high or critical request 609is received by the QHL and there is a matching request with normal priority 610that has already been issued to the QMC. 611In this instance, the QHL will send a priority update to QMC to expedite the request. 612.It Li QMC_PRIORITY_UPDATES.CH1 613.Pq Event 31H , Umask 02H 614Counts number of DRAM channel 1 priority updates. 615A priority update occurs when an ISOC high or critical request is received by 616the QHL and there is a matching request with normal priority that has 617already been issued to the QMC. 618In this instance, the QHL will send a priority update to QMC to expedite the request. 619.It Li QMC_PRIORITY_UPDATES.CH2 620.Pq Event 31H , Umask 04H 621Counts number of DRAM channel 2 priority updates. 622A priority update occurs when an ISOC high or critical request is received by 623the QHL and there is a matching request with normal priority that has 624already been issued to the QMC. 625In this instance, the QHL will send a priority update to QMC to expedite the request. 626.It Li QMC_PRIORITY_UPDATES.ANY 627.Pq Event 31H , Umask 07H 628Counts number of DRAM priority updates. 629A priority update occurs when an ISOC high or critical request is received by 630the QHL and there is a matching request with normal priority that has 631already been issued to the QMC. 632In this instance, the QHL will send a priority update to QMC to expedite the request. 633.It Li QHL_FRC_ACK_CNFLTS.LOCAL 634.Pq Event 33H , Umask 04H 635Counts number of Force Acknowledge Conflict messages sent by the Quickpath 636Home Logic to the local home. 637.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 638.Pq Event 40H , Umask 01H 639Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled 640due to lack of a VNA and VN0 credit. 641Note that this event does not filter out when a flit would not have been 642selected for arbitration because another virtual channel is getting arbitrated. 643.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 644.Pq Event 40H , Umask 02H 645Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled 646due to lack of a VNA and VN0 credit. 647Note that this event does not filter out when a flit would not have been 648selected for arbitration because another virtual channel is getting arbitrated. 649.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 650.Pq Event 40H , Umask 04H 651Counts cycles the Quickpath outbound link 0 non-data response virtual 652channel is stalled due to lack of a VNA and VN0 credit. 653Note that this event does not filter out when a flit would not have been 654selected for arbitration because another virtual channel is getting arbitrated. 655.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 656.Pq Event 40H , Umask 08H 657Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled 658due to lack of a VNA and VN0 credit. 659Note that this event does not filter out when a flit would not have been 660selected for arbitration because another virtual channel is getting arbitrated. 661.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 662.Pq Event 40H , Umask 10H 663Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled 664due to lack of a VNA and VN0 credit. 665Note that this event does not filter out when a flit would not have been 666selected for arbitration because another virtual channel is getting arbitrated. 667.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 668.Pq Event 40H , Umask 20H 669Counts cycles the Quickpath outbound link 1 non-data response virtual 670channel is stalled due to lack of a VNA and VN0 credit. 671Note that this event does not filter out when a flit would not have been 672selected for arbitration because another virtual channel is getting arbitrated. 673.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 674.Pq Event 40H , Umask 07H 675Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 676to lack of a VNA and VN0 credit. 677Note that this event does not filter out when a flit would not have been 678selected for arbitration because another virtual channel is getting arbitrated. 679.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 680.Pq Event 40H , Umask 38H 681Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 682to lack of a VNA and VN0 credit. 683Note that this event does not filter out when a flit would not have been 684selected for arbitration because another virtual channel is getting arbitrated. 685.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 686.Pq Event 41H , Umask 01H 687Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is 688stalled due to lack of VNA and VN0 credits. 689Note that this event does not filter out when a flit would not have been 690selected for arbitration because another virtual channel is getting arbitrated. 691.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 692.Pq Event 41H , Umask 02H 693Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual 694channel is stalled due to lack of VNA and VN0 credits. 695Note that this event does not filter out when a flit would not have been 696selected for arbitration because another virtual channel is getting arbitrated. 697.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 698.Pq Event 41H , Umask 04H 699Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual 700channel is stalled due to lack of VNA and VN0 credits. 701Note that this event does not filter out when a flit would not have been 702selected for arbitration because another virtual channel is getting arbitrated. 703.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 704.Pq Event 41H , Umask 08H 705Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is 706stalled due to lack of VNA and VN0 credits. 707Note that this event does not filter out when a flit would not have been 708selected for arbitration because another virtual channel is getting arbitrated. 709.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 710.Pq Event 41H , Umask 10H 711Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual 712channel is stalled due to lack of VNA and VN0 credits. 713Note that this event does not filter out when a flit would not have been 714selected for arbitration because another virtual channel is getting arbitrated. 715.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 716.Pq Event 41H , Umask 20H 717Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual 718channel is stalled due to lack of VNA and VN0 credits. 719Note that this event does not filter out when a flit would not have been 720selected for arbitration because another virtual channel is getting arbitrated. 721.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 722.Pq Event 41H , Umask 07H 723Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 724to lack of VNA and VN0 credits. 725Note that this event does not filter out when a flit would not have been 726selected for arbitration because another virtual channel is getting arbitrated. 727.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 728.Pq Event 41H , Umask 38H 729Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 730to lack of VNA and VN0 credits. 731Note that this event does not filter out when a flit would not have been 732selected for arbitration because another virtual channel is getting arbitrated. 733.It Li QPI_TX_HEADER.BUSY.LINK_0 734.Pq Event 42H , Umask 02H 735Number of cycles that the header buffer in the Quickpath Interface outbound 736link 0 is busy. 737.It Li QPI_TX_HEADER.BUSY.LINK_1 738.Pq Event 42H , Umask 08H 739Number of cycles that the header buffer in the Quickpath Interface outbound 740link 1 is busy. 741.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 742.Pq Event 43H , Umask 01H 743Number of cycles that snoop packets incoming to the Quickpath Interface link 7440 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 745does not have any available entries. 746.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 747.Pq Event 43H , Umask 02H 748Number of cycles that snoop packets incoming to the Quickpath Interface link 7491 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 750does not have any available entries. 751.It Li DRAM_OPEN.CH0 752.Pq Event 60H , Umask 01H 753Counts number of DRAM Channel 0 open commands issued either for read or write. 754To read or write data, the referenced DRAM page must first be opened. 755.It Li DRAM_OPEN.CH1 756.Pq Event 60H , Umask 02H 757Counts number of DRAM Channel 1 open commands issued either for read or write. 758To read or write data, the referenced DRAM page must first be opened. 759.It Li DRAM_OPEN.CH2 760.Pq Event 60H , Umask 04H 761Counts number of DRAM Channel 2 open commands issued either for read or write. 762To read or write data, the referenced DRAM page must first be opened. 763.It Li DRAM_PAGE_CLOSE.CH0 764.Pq Event 61H , Umask 01H 765DRAM channel 0 command issued to CLOSE a page due to page idle timer 766expiration. 767Closing a page is done by issuing a precharge. 768.It Li DRAM_PAGE_CLOSE.CH1 769.Pq Event 61H , Umask 02H 770DRAM channel 1 command issued to CLOSE a page due to page idle timer 771expiration. 772Closing a page is done by issuing a precharge. 773.It Li DRAM_PAGE_CLOSE.CH2 774.Pq Event 61H , Umask 04H 775DRAM channel 2 command issued to CLOSE a page due to page idle timer 776expiration. 777Closing a page is done by issuing a precharge. 778.It Li DRAM_PAGE_MISS.CH0 779.Pq Event 62H , Umask 01H 780Counts the number of precharges (PRE) that were issued to DRAM channel 0 781because there was a page miss. 782A page miss refers to a situation in which a page is currently open and 783another page from the same bank needs to be opened. 784The new page experiences a page miss. 785Closing of the old page is done by issuing a precharge. 786.It Li DRAM_PAGE_MISS.CH1 787.Pq Event 62H , Umask 02H 788Counts the number of precharges (PRE) that were issued to DRAM channel 1 789because there was a page miss. 790A page miss refers to a situation in which a page is currently open and 791another page from the same bank needs to be opened. 792The new page experiences a page miss. 793Closing of the old page is done by issuing a precharge. 794.It Li DRAM_PAGE_MISS.CH2 795.Pq Event 62H , Umask 04H 796Counts the number of precharges (PRE) that were issued to DRAM channel 2 797because there was a page miss. 798A page miss refers to a situation in which a page is currently open and 799another page from the same bank needs to be opened. 800The new page experiences a page miss. 801Closing of the old page is done by issuing a precharge. 802.It Li DRAM_READ_CAS.CH0 803.Pq Event 63H , Umask 01H 804Counts the number of times a read CAS command was issued on DRAM channel 0. 805.It Li DRAM_READ_CAS.AUTOPRE_CH0 806.Pq Event 63H , Umask 02H 807Counts the number of times a read CAS command was issued on DRAM channel 0 808where the command issued used the auto-precharge (auto page close) mode. 809.It Li DRAM_READ_CAS.CH1 810.Pq Event 63H , Umask 04H 811Counts the number of times a read CAS command was issued on DRAM channel 1. 812.It Li DRAM_READ_CAS.AUTOPRE_CH1 813.Pq Event 63H , Umask 08H 814Counts the number of times a read CAS command was issued on DRAM channel 1 815where the command issued used the auto-precharge (auto page close) mode. 816.It Li DRAM_READ_CAS.CH2 817.Pq Event 63H , Umask 10H 818Counts the number of times a read CAS command was issued on DRAM channel 2. 819.It Li DRAM_READ_CAS.AUTOPRE_CH2 820.Pq Event 63H , Umask 20H 821Counts the number of times a read CAS command was issued on DRAM channel 2 822where the command issued used the auto-precharge (auto page close) mode. 823.It Li DRAM_WRITE_CAS.CH0 824.Pq Event 64H , Umask 01H 825Counts the number of times a write CAS command was issued on DRAM channel 0. 826.It Li DRAM_WRITE_CAS.AUTOPRE_CH0 827.Pq Event 64H , Umask 02H 828Counts the number of times a write CAS command was issued on DRAM channel 0 829where the command issued used the auto-precharge (auto page close) mode. 830.It Li DRAM_WRITE_CAS.CH1 831.Pq Event 64H , Umask 04H 832Counts the number of times a write CAS command was issued on DRAM channel 1. 833.It Li DRAM_WRITE_CAS.AUTOPRE_CH1 834.Pq Event 64H , Umask 08H 835Counts the number of times a write CAS command was issued on DRAM channel 1 836where the command issued used the auto-precharge (auto page close) mode. 837.It Li DRAM_WRITE_CAS.CH2 838.Pq Event 64H , Umask 10H 839Counts the number of times a write CAS command was issued on DRAM channel 2. 840.It Li DRAM_WRITE_CAS.AUTOPRE_CH2 841.Pq Event 64H , Umask 20H 842Counts the number of times a write CAS command was issued on DRAM channel 2 843where the command issued used the auto-precharge (auto page close) mode. 844.It Li DRAM_REFRESH.CH0 845.Pq Event 65H , Umask 01H 846Counts number of DRAM channel 0 refresh commands. 847DRAM loses data content over time. 848In order to keep correct data content, the data values have to be 849refreshed periodically. 850.It Li DRAM_REFRESH.CH1 851.Pq Event 65H , Umask 02H 852Counts number of DRAM channel 1 refresh commands. 853DRAM loses data content over time. 854In order to keep correct data content, the data values have to be 855refreshed periodically. 856.It Li DRAM_REFRESH.CH2 857.Pq Event 65H , Umask 04H 858Counts number of DRAM channel 2 refresh commands. 859DRAM loses data content over time. 860In order to keep correct data content, the data values have to be 861refreshed periodically. 862.It Li DRAM_PRE_ALL.CH0 863.Pq Event 66H , Umask 01H 864Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close 865all open pages in a rank. 866PREALL is issued when the DRAM needs to be refreshed or needs to go 867into a power down mode. 868.It Li DRAM_PRE_ALL.CH1 869.Pq Event 66H , Umask 02H 870Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close 871all open pages in a rank. 872PREALL is issued when the DRAM needs to be refreshed or needs to go 873into a power down mode. 874.It Li DRAM_PRE_ALL.CH2 875.Pq Event 66H , Umask 04H 876Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close 877all open pages in a rank. 878PREALL is issued when the DRAM needs to be refreshed or needs to go 879into a power down mode. 880.El 881.Sh SEE ALSO 882.Xr pmc 3 , 883.Xr pmc.atom 3 , 884.Xr pmc.core 3 , 885.Xr pmc.corei7 3 , 886.Xr pmc.iaf 3 , 887.Xr pmc.k7 3 , 888.Xr pmc.k8 3 , 889.Xr pmc.soft 3 , 890.Xr pmc.tsc 3 , 891.Xr pmc.ucf 3 , 892.Xr pmc.westmere 3 , 893.Xr pmc.westmereuc 3 , 894.Xr pmc_cpuinfo 3 , 895.Xr pmclog 3 , 896.Xr hwpmc 4 897.Sh HISTORY 898The 899.Nm pmc 900library first appeared in 901.Fx 6.0 . 902.Sh AUTHORS 903The 904.Lb libpmc 905library was written by 906.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 907