1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd March 24, 2010 25.Dt PMC.COREI7UC 3 26.Os 27.Sh NAME 28.Nm pmc.corei7uc 29.Nd uncore measurement events for 30.Tn Intel 31.Tn Core i7 and Xeon 5500 32family CPUs 33.Sh LIBRARY 34.Lb libpmc 35.Sh SYNOPSIS 36.In pmc.h 37.Sh DESCRIPTION 38.Tn Intel 39.Tn "Core i7" 40CPUs contain PMCs conforming to version 2 of the 41.Tn Intel 42performance measurement architecture. 43These CPUs contain 2 classes of PMCs: 44.Bl -tag -width "Li PMC_CLASS_UCP" 45.It Li PMC_CLASS_UCF 46Fixed-function counters that count only one hardware event per counter. 47.It Li PMC_CLASS_UCP 48Programmable counters that may be configured to count one of a defined 49set of hardware events. 50.El 51.Pp 52The number of PMCs available in each class and their widths need to be 53determined at run time by calling 54.Xr pmc_cpuinfo 3 . 55.Pp 56Intel Core i7 and Xeon 5500 PMCs are documented in 57.Rs 58.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 59.%T "Volume 3B: System Programming Guide, Part 2" 60.%N "Order Number: 253669-033US" 61.%D December 2009 62.%Q "Intel Corporation" 63.Re 64.Ss COREI7 AND XEON 5500 UNCORE FIXED FUNCTION PMCS 65These PMCs and their supported events are documented in 66.Xr pmc.ucf 3 . 67.Ss COREI7 AND XEON 5500 UNCORE PROGRAMMABLE PMCS 68The programmable PMCs support the following capabilities: 69.Bl -column "PMC_CAP_INTERRUPT" "Support" 70.It Em Capability Ta Em Support 71.It PMC_CAP_CASCADE Ta \&No 72.It PMC_CAP_EDGE Ta Yes 73.It PMC_CAP_INTERRUPT Ta \&No 74.It PMC_CAP_INVERT Ta Yes 75.It PMC_CAP_READ Ta Yes 76.It PMC_CAP_PRECISE Ta \&No 77.It PMC_CAP_SYSTEM Ta \&No 78.It PMC_CAP_TAGGING Ta \&No 79.It PMC_CAP_THRESHOLD Ta Yes 80.It PMC_CAP_USER Ta \&No 81.It PMC_CAP_WRITE Ta Yes 82.El 83.Ss Event Qualifiers 84Event specifiers for these PMCs support the following common 85qualifiers: 86.Bl -tag -width indent 87.It Li cmask= Ns Ar value 88Configure the PMC to increment only if the number of configured 89events measured in a cycle is greater than or equal to 90.Ar value . 91.It Li edge 92Configure the PMC to count the number of de-asserted to asserted 93transitions of the conditions expressed by the other qualifiers. 94If specified, the counter will increment only once whenever a 95condition becomes true, irrespective of the number of clocks during 96which the condition remains true. 97.It Li inv 98Invert the sense of comparison when the 99.Dq Li cmask 100qualifier is present, making the counter increment when the number of 101events per cycle is less than the value specified by the 102.Dq Li cmask 103qualifier. 104.El 105.Ss Event Specifiers (Programmable PMCs) 106Core i7 and Xeon 5500 uncore programmable PMCs support the following events: 107.Bl -tag -width indent 108.It Li GQ_CYCLES_FULL.READ_TRACKER 109.Pq Event 00H , Umask 01H 110Uncore cycles Global Queue read tracker is full. 111.It Li GQ_CYCLES_FULL.WRITE_TRACKER 112.Pq Event 00H , Umask 02H 113Uncore cycles Global Queue write tracker is full. 114.It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER 115.Pq Event 00H , Umask 04H 116Uncore cycles Global Queue peer probe tracker is full. 117The peer probe tracker queue tracks snoops from the IOH and remote sockets. 118.It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER 119.Pq Event 01H , Umask 01H 120Uncore cycles were Global Queue read tracker has at least one valid entry. 121.It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER 122.Pq Event 01H , Umask 02H 123Uncore cycles were Global Queue write tracker has at least one valid entry. 124.It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER 125.Pq Event 01H , Umask 04H 126Uncore cycles were Global Queue peer probe tracker has at least one valid entry. 127The peer probe tracker queue tracks IOH and remote socket snoops. 128.It Li GQ_ALLOC.READ_TRACKER 129.Pq Event 03H , Umask 01H 130Counts the number of tread tracker allocate to deallocate entries. 131The GQ read tracker allocate to deallocate occupancy count is divided 132by the count to obtain the average read tracker latency. 133.It Li GQ_ALLOC.RT_L3_MISS 134.Pq Event 03H , Umask 02H 135Counts the number GQ read tracker entries for which a full cache line read 136has missed the L3. 137The GQ read tracker L3 miss to fill occupancy count is divided by this count 138to obtain the average cache line read L3 miss latency. 139The latency represents the time after which the L3 has determined that the 140cache line has missed. 141The time between a GQ read tracker allocation and the L3 determining that the 142cache line has missed is the average L3 hit latency. 143The total L3 cache line read miss latency is the hit latency + L3 miss 144latency. 145.It Li GQ_ALLOC.RT_TO_L3_RESP 146.Pq Event 03H , Umask 04H 147Counts the number of GQ read tracker entries that are allocated in the read 148tracker queue that hit or miss the L3. 149The GQ read tracker L3 hit occupancy count is divided by this count to obtain 150the average L3 hit latency. 151.It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED 152.Pq Event 03H , Umask 08H 153Counts the number of GQ read tracker entries that are allocated in the read 154tracker, have missed in the L3 and have not acquired a Request Transaction ID. 155The GQ read tracker L3 miss to RTID acquired occupancy count is 156divided by this count to obtain the average latency for a read L3 miss to 157acquire an RTID. 158.It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED 159.Pq Event 03H , Umask 10H 160Counts the number of GQ write tracker entries that are allocated in the 161write tracker, have missed in the L3 and have not acquired a Request 162Transaction ID. 163The GQ write tracker L3 miss to RTID occupancy count is divided by this count 164to obtain the average latency for a write L3 miss to acquire an RTID. 165.It Li GQ_ALLOC.WRITE_TRACKER 166.Pq Event 03H , Umask 20H 167Counts the number of GQ write tracker entries that are allocated in the 168write tracker queue that miss the L3. 169The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write miss latency. 170.It Li GQ_ALLOC.PEER_PROBE_TRACKER 171.Pq Event 03H , Umask 40H 172Counts the number of GQ peer probe tracker (snoop) entries that are 173allocated in the peer probe tracker queue that miss the L3. 174The GQ peer probe occupancy count is divided by this count to obtain the average L3 peer 175probe miss latency. 176.It Li GQ_DATA.FROM_QPI 177.Pq Event 04H , Umask 01H 178Cycles Global Queue Quickpath Interface input data port is busy importing 179data from the Quickpath Interface. 180Each cycle the input port can transfer 8 or 16 bytes of data. 181.It Li GQ_DATA.FROM_QMC 182.Pq Event 04H , Umask 02H 183Cycles Global Queue Quickpath Memory Interface input data port is busy 184importing data from the Quickpath Memory Interface. 185Each cycle the input port can transfer 8 or 16 bytes of data. 186.It Li GQ_DATA.FROM_L3 187.Pq Event 04H , Umask 04H 188Cycles GQ L3 input data port is busy importing data from the Last Level Cache. 189Each cycle the input port can transfer 32 bytes of data. 190.It Li GQ_DATA.FROM_CORES_02 191.Pq Event 04H , Umask 08H 192Cycles GQ Core 0 and 2 input data port is busy importing data from processor 193cores 0 and 2. 194Each cycle the input port can transfer 32 bytes of data. 195.It Li GQ_DATA.FROM_CORES_13 196.Pq Event 04H , Umask 10H 197Cycles GQ Core 1 and 3 input data port is busy importing data from processor 198cores 1 and 3. 199Each cycle the input port can transfer 32 bytes of data. 200.It Li GQ_DATA.TO_QPI_QMC 201.Pq Event 05H , Umask 01H 202Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath 203Interface or Quickpath Memory Interface. 204Each cycle the output port can transfer 32 bytes of data. 205.It Li GQ_DATA.TO_L3 206.Pq Event 05H , Umask 02H 207Cycles GQ L3 output data port is busy sending data to the Last Level Cache. 208Each cycle the output port can transfer 32 bytes of data. 209.It Li GQ_DATA.TO_CORES 210.Pq Event 05H , Umask 04H 211Cycles GQ Core output data port is busy sending data to the Cores. 212Each cycle the output port can transfer 32 bytes of data. 213.It Li SNP_RESP_TO_LOCAL_HOME.I_STATE 214.Pq Event 06H , Umask 01H 215Number of snoop responses to the local home that L3 does not have the 216referenced cache line. 217.It Li SNP_RESP_TO_LOCAL_HOME.S_STATE 218.Pq Event 06H , Umask 02H 219Number of snoop responses to the local home that L3 has the referenced line 220cached in the S state. 221.It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE 222.Pq Event 06H , Umask 04H 223Number of responses to code or data read snoops to the local home that the 224L3 has the referenced cache line in the E state. 225The L3 cache line state is changed to the S state and the line is 226forwarded to the local home in the S state. 227.It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE 228.Pq Event 06H , Umask 08H 229Number of responses to read invalidate snoops to the local home that the L3 230has the referenced cache line in the M state. 231The L3 cache line state is invalidated and the line is forwarded to the 232local home in the M state. 233.It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT 234.Pq Event 06H , Umask 10H 235Number of conflict snoop responses sent to the local home. 236.It Li SNP_RESP_TO_LOCAL_HOME.WB 237.Pq Event 06H , Umask 20H 238Number of responses to code or data read snoops to the local home that the 239L3 has the referenced line cached in the M state. 240.It Li SNP_RESP_TO_REMOTE_HOME.I_STATE 241.Pq Event 07H , Umask 01H 242Number of snoop responses to a remote home that L3 does not have the 243referenced cache line. 244.It Li SNP_RESP_TO_REMOTE_HOME.S_STATE 245.Pq Event 07H , Umask 02H 246Number of snoop responses to a remote home that L3 has the referenced line 247cached in the S state. 248.It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE 249.Pq Event 07H , Umask 04H 250Number of responses to code or data read snoops to a remote home that the L3 251has the referenced cache line in the E state. 252The L3 cache line state is changed to the S state and the line is forwarded to 253the remote home in the S state. 254.It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE 255.Pq Event 07H , Umask 08H 256Number of responses to read invalidate snoops to a remote home that the L3 257has the referenced cache line in the M state. 258The L3 cache line state is invalidated and the line is forwarded to the 259remote home in the M state. 260.It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT 261.Pq Event 07H , Umask 10H 262Number of conflict snoop responses sent to the local home. 263.It Li SNP_RESP_TO_REMOTE_HOME.WB 264.Pq Event 07H , Umask 20H 265Number of responses to code or data read snoops to a remote home that the L3 266has the referenced line cached in the M state. 267.It Li SNP_RESP_TO_REMOTE_HOME.HITM 268.Pq Event 07H , Umask 24H 269Number of HITM snoop responses to a remote home 270.It Li L3_HITS.READ 271.Pq Event 08H , Umask 01H 272Number of code read, data read and RFO requests that hit in the L3 273.It Li L3_HITS.WRITE 274.Pq Event 08H , Umask 02H 275Number of writeback requests that hit in the L3. 276Writebacks from the cores will always result in L3 hits due to the inclusive property of the L3. 277.It Li L3_HITS.PROBE 278.Pq Event 08H , Umask 04H 279Number of snoops from IOH or remote sockets that hit in the L3. 280.It Li L3_HITS.ANY 281.Pq Event 08H , Umask 03H 282Number of reads and writes that hit the L3. 283.It Li L3_MISS.READ 284.Pq Event 09H , Umask 01H 285Number of code read, data read and RFO requests that miss the L3. 286.It Li L3_MISS.WRITE 287.Pq Event 09H , Umask 02H 288Number of writeback requests that miss the L3. 289Should always be zero as writebacks from the cores will always result in 290L3 hits due to the inclusive property of the L3. 291.It Li L3_MISS.PROBE 292.Pq Event 09H , Umask 04H 293Number of snoops from IOH or remote sockets that miss the L3. 294.It Li L3_MISS.ANY 295.Pq Event 09H , Umask 03H 296Number of reads and writes that miss the L3. 297.It Li L3_LINES_IN.M_STATE 298.Pq Event 0AH , Umask 01H 299Counts the number of L3 lines allocated in M state. 300The only time a cache line is allocated in the M state is when the line 301was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request. 302.It Li L3_LINES_IN.E_STATE 303.Pq Event 0AH , Umask 02H 304Counts the number of L3 lines allocated in E state. 305.It Li L3_LINES_IN.S_STATE 306.Pq Event 0AH , Umask 04H 307Counts the number of L3 lines allocated in S state. 308.It Li L3_LINES_IN.F_STATE 309.Pq Event 0AH , Umask 08H 310Counts the number of L3 lines allocated in F state. 311.It Li L3_LINES_IN.ANY 312.Pq Event 0AH , Umask 0FH 313Counts the number of L3 lines allocated in any state. 314.It Li L3_LINES_OUT.M_STATE 315.Pq Event 0BH , Umask 01H 316Counts the number of L3 lines victimized that were in the M state. 317When the victim cache line is in M state, the line is written to its home cache agent 318which can be either local or remote. 319.It Li L3_LINES_OUT.E_STATE 320.Pq Event 0BH , Umask 02H 321Counts the number of L3 lines victimized that were in the E state. 322.It Li L3_LINES_OUT.S_STATE 323.Pq Event 0BH , Umask 04H 324Counts the number of L3 lines victimized that were in the S state. 325.It Li L3_LINES_OUT.I_STATE 326.Pq Event 0BH , Umask 08H 327Counts the number of L3 lines victimized that were in the I state. 328.It Li L3_LINES_OUT.F_STATE 329.Pq Event 0BH , Umask 10H 330Counts the number of L3 lines victimized that were in the F state. 331.It Li L3_LINES_OUT.ANY 332.Pq Event 0BH , Umask 1FH 333Counts the number of L3 lines victimized in any state. 334.It Li QHL_REQUESTS.IOH_READS 335.Pq Event 20H , Umask 01H 336Counts number of Quickpath Home Logic read requests from the IOH. 337.It Li QHL_REQUESTS.IOH_WRITES 338.Pq Event 20H , Umask 02H 339Counts number of Quickpath Home Logic write requests from the IOH. 340.It Li QHL_REQUESTS.REMOTE_READS 341.Pq Event 20H , Umask 04H 342Counts number of Quickpath Home Logic read requests from a remote socket. 343.It Li QHL_REQUESTS.REMOTE_WRITES 344.Pq Event 20H , Umask 08H 345Counts number of Quickpath Home Logic write requests from a remote socket. 346.It Li QHL_REQUESTS.LOCAL_READS 347.Pq Event 20H , Umask 10H 348Counts number of Quickpath Home Logic read requests from the local socket. 349.It Li QHL_REQUESTS.LOCAL_WRITES 350.Pq Event 20H , Umask 20H 351Counts number of Quickpath Home Logic write requests from the local socket. 352.It Li QHL_CYCLES_FULL.IOH 353.Pq Event 21H , Umask 01H 354Counts uclk cycles all entries in the Quickpath Home Logic IOH are full. 355.It Li QHL_CYCLES_FULL.REMOTE 356.Pq Event 21H , Umask 02H 357Counts uclk cycles all entries in the Quickpath Home Logic remote tracker 358are full. 359.It Li QHL_CYCLES_FULL.LOCAL 360.Pq Event 21H , Umask 04H 361Counts uclk cycles all entries in the Quickpath Home Logic local tracker are 362full. 363.It Li QHL_CYCLES_NOT_EMPTY.IOH 364.Pq Event 22H , Umask 01H 365Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy. 366.It Li QHL_CYCLES_NOT_EMPTY.REMOTE 367.Pq Event 22H , Umask 02H 368Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is 369busy. 370.It Li QHL_CYCLES_NOT_EMPTY.LOCAL 371.Pq Event 22H , Umask 04H 372Counts uclk cycles all entries in the Quickpath Home Logic local tracker is 373busy. 374.It Li QHL_OCCUPANCY.IOH 375.Pq Event 23H , Umask 01H 376QHL IOH tracker allocate to deallocate read occupancy. 377.It Li QHL_OCCUPANCY.REMOTE 378.Pq Event 23H , Umask 02H 379QHL remote tracker allocate to deallocate read occupancy. 380.It Li QHL_OCCUPANCY.LOCAL 381.Pq Event 23H , Umask 04H 382QHL local tracker allocate to deallocate read occupancy. 383.It Li QHL_ADDRESS_CONFLICTS.2WAY 384.Pq Event 24H , Umask 02H 385Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 386conflicts. 387The AAT is a structure that tracks requests that are in conflict. 388The requests themselves are in the home tracker entries. 389The count is reported when an AAT entry deallocates. 390.It Li QHL_ADDRESS_CONFLICTS.3WAY 391.Pq Event 24H , Umask 04H 392Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 393conflicts. 394The AAT is a structure that tracks requests that are in conflict. 395The requests themselves are in the home tracker entries. 396The count is reported when an AAT entry deallocates. 397.It Li QHL_CONFLICT_CYCLES.IOH 398.Pq Event 25H , Umask 01H 399Counts cycles the Quickpath Home Logic IOH Tracker contains two or more 400requests with an address conflict. 401A max of 3 requests can be in conflict. 402.It Li QHL_CONFLICT_CYCLES.REMOTE 403.Pq Event 25H , Umask 02H 404Counts cycles the Quickpath Home Logic Remote Tracker contains two or more 405requests with an address conflict. 406A max of 3 requests can be in conflict. 407.It Li QHL_CONFLICT_CYCLES.LOCAL 408.Pq Event 25H , Umask 04H 409Counts cycles the Quickpath Home Logic Local Tracker contains two or more 410requests with an address conflict. 411A max of 3 requests can be in conflict. 412.It Li QHL_TO_QMC_BYPASS 413.Pq Event 26H , Umask 01H 414Counts number or requests to the Quickpath Memory Controller that bypass the 415Quickpath Home Logic. 416All local accesses can be bypassed. 417For remote requests, only read requests can be bypassed. 418.It Li QMC_NORMAL_FULL.READ.CH0 419.Pq Event 27H , Umask 01H 420Uncore cycles all the entries in the DRAM channel 0 medium or low priority 421queue are occupied with read requests. 422.It Li QMC_NORMAL_FULL.READ.CH1 423.Pq Event 27H , Umask 02H 424Uncore cycles all the entries in the DRAM channel 1 medium or low priority 425queue are occupied with read requests. 426.It Li QMC_NORMAL_FULL.READ.CH2 427.Pq Event 27H , Umask 04H 428Uncore cycles all the entries in the DRAM channel 2 medium or low priority 429queue are occupied with read requests. 430.It Li QMC_NORMAL_FULL.WRITE.CH0 431.Pq Event 27H , Umask 08H 432Uncore cycles all the entries in the DRAM channel 0 medium or low priority 433queue are occupied with write requests. 434.It Li QMC_NORMAL_FULL.WRITE.CH1 435.Pq Event 27H , Umask 10H 436Counts cycles all the entries in the DRAM channel 1 medium or low priority 437queue are occupied with write requests. 438.It Li QMC_NORMAL_FULL.WRITE.CH2 439.Pq Event 27H , Umask 20H 440Uncore cycles all the entries in the DRAM channel 2 medium or low priority 441queue are occupied with write requests. 442.It Li QMC_ISOC_FULL.READ.CH0 443.Pq Event 28H , Umask 01H 444Counts cycles all the entries in the DRAM channel 0 high priority queue are 445occupied with isochronous read requests. 446.It Li QMC_ISOC_FULL.READ.CH1 447.Pq Event 28H , Umask 02H 448Counts cycles all the entries in the DRAM channel 1 high priority queue are 449occupied with isochronous read requests. 450.It Li QMC_ISOC_FULL.READ.CH2 451.Pq Event 28H , Umask 04H 452Counts cycles all the entries in the DRAM channel 2 high priority queue are 453occupied with isochronous read requests. 454.It Li QMC_ISOC_FULL.WRITE.CH0 455.Pq Event 28H , Umask 08H 456Counts cycles all the entries in the DRAM channel 0 high priority queue are 457occupied with isochronous write requests. 458.It Li QMC_ISOC_FULL.WRITE.CH1 459.Pq Event 28H , Umask 10H 460Counts cycles all the entries in the DRAM channel 1 high priority queue are 461occupied with isochronous write requests. 462.It Li QMC_ISOC_FULL.WRITE.CH2 463.Pq Event 28H , Umask 20H 464Counts cycles all the entries in the DRAM channel 2 high priority queue are 465occupied with isochronous write requests. 466.It Li QMC_BUSY.READ.CH0 467.Pq Event 29H , Umask 01H 468Counts cycles where Quickpath Memory Controller has at least 1 outstanding 469read request to DRAM channel 0. 470.It Li QMC_BUSY.READ.CH1 471.Pq Event 29H , Umask 02H 472Counts cycles where Quickpath Memory Controller has at least 1 outstanding 473read request to DRAM channel 1. 474.It Li QMC_BUSY.READ.CH2 475.Pq Event 29H , Umask 04H 476Counts cycles where Quickpath Memory Controller has at least 1 outstanding 477read request to DRAM channel 2. 478.It Li QMC_BUSY.WRITE.CH0 479.Pq Event 29H , Umask 08H 480Counts cycles where Quickpath Memory Controller has at least 1 outstanding 481write request to DRAM channel 0. 482.It Li QMC_BUSY.WRITE.CH1 483.Pq Event 29H , Umask 10H 484Counts cycles where Quickpath Memory Controller has at least 1 outstanding 485write request to DRAM channel 1. 486.It Li QMC_BUSY.WRITE.CH2 487.Pq Event 29H , Umask 20H 488Counts cycles where Quickpath Memory Controller has at least 1 outstanding 489write request to DRAM channel 2. 490.It Li QMC_OCCUPANCY.CH0 491.Pq Event 2AH , Umask 01H 492IMC channel 0 normal read request occupancy. 493.It Li QMC_OCCUPANCY.CH1 494.Pq Event 2AH , Umask 02H 495IMC channel 1 normal read request occupancy. 496.It Li QMC_OCCUPANCY.CH2 497.Pq Event 2AH , Umask 04H 498IMC channel 2 normal read request occupancy. 499.It Li QMC_ISSOC_OCCUPANCY.CH0 500.Pq Event 2BH , Umask 01H 501IMC channel 0 issoc read request occupancy. 502.It Li QMC_ISSOC_OCCUPANCY.CH1 503.Pq Event 2BH , Umask 02H 504IMC channel 1 issoc read request occupancy. 505.It Li QMC_ISSOC_OCCUPANCY.CH2 506.Pq Event 2BH , Umask 04H 507IMC channel 2 issoc read request occupancy. 508.It Li QMC_ISSOC_READS.ANY 509.Pq Event 2BH , Umask 07H 510IMC issoc read request occupancy. 511.It Li QMC_NORMAL_READS.CH0 512.Pq Event 2CH , Umask 01H 513Counts the number of Quickpath Memory Controller channel 0 medium and low 514priority read requests. 515The QMC channel 0 normal read occupancy divided by this count provides the 516average QMC channel 0 read latency. 517.It Li QMC_NORMAL_READS.CH1 518.Pq Event 2CH , Umask 02H 519Counts the number of Quickpath Memory Controller channel 1 medium and low 520priority read requests. 521The QMC channel 1 normal read occupancy divided by this count provides the 522average QMC channel 1 read latency. 523.It Li QMC_NORMAL_READS.CH2 524.Pq Event 2CH , Umask 04H 525Counts the number of Quickpath Memory Controller channel 2 medium and low 526priority read requests. 527The QMC channel 2 normal read occupancy divided by this count provides the 528average QMC channel 2 read latency. 529.It Li QMC_NORMAL_READS.ANY 530.Pq Event 2CH , Umask 07H 531Counts the number of Quickpath Memory Controller medium and low priority 532read requests. 533The QMC normal read occupancy divided by this count provides the average 534QMC read latency. 535.It Li QMC_HIGH_PRIORITY_READS.CH0 536.Pq Event 2DH , Umask 01H 537Counts the number of Quickpath Memory Controller channel 0 high priority 538isochronous read requests. 539.It Li QMC_HIGH_PRIORITY_READS.CH1 540.Pq Event 2DH , Umask 02H 541Counts the number of Quickpath Memory Controller channel 1 high priority 542isochronous read requests. 543.It Li QMC_HIGH_PRIORITY_READS.CH2 544.Pq Event 2DH , Umask 04H 545Counts the number of Quickpath Memory Controller channel 2 high priority 546isochronous read requests. 547.It Li QMC_HIGH_PRIORITY_READS.ANY 548.Pq Event 2DH , Umask 07H 549Counts the number of Quickpath Memory Controller high priority isochronous 550read requests. 551.It Li QMC_CRITICAL_PRIORITY_READS.CH0 552.Pq Event 2EH , Umask 01H 553Counts the number of Quickpath Memory Controller channel 0 critical priority 554isochronous read requests. 555.It Li QMC_CRITICAL_PRIORITY_READS.CH1 556.Pq Event 2EH , Umask 02H 557Counts the number of Quickpath Memory Controller channel 1 critical priority 558isochronous read requests. 559.It Li QMC_CRITICAL_PRIORITY_READS.CH2 560.Pq Event 2EH , Umask 04H 561Counts the number of Quickpath Memory Controller channel 2 critical priority 562isochronous read requests. 563.It Li QMC_CRITICAL_PRIORITY_READS.ANY 564.Pq Event 2EH , Umask 07H 565Counts the number of Quickpath Memory Controller critical priority 566isochronous read requests. 567.It Li QMC_WRITES.FULL.CH0 568.Pq Event 2FH , Umask 01H 569Counts number of full cache line writes to DRAM channel 0. 570.It Li QMC_WRITES.FULL.CH1 571.Pq Event 2FH , Umask 02H 572Counts number of full cache line writes to DRAM channel 1. 573.It Li QMC_WRITES.FULL.CH2 574.Pq Event 2FH , Umask 04H 575Counts number of full cache line writes to DRAM channel 2. 576.It Li QMC_WRITES.FULL.ANY 577.Pq Event 2FH , Umask 07H 578Counts number of full cache line writes to DRAM. 579.It Li QMC_WRITES.PARTIAL.CH0 580.Pq Event 2FH , Umask 08H 581Counts number of partial cache line writes to DRAM channel 0. 582.It Li QMC_WRITES.PARTIAL.CH1 583.Pq Event 2FH , Umask 10H 584Counts number of partial cache line writes to DRAM channel 1. 585.It Li QMC_WRITES.PARTIAL.CH2 586.Pq Event 2FH , Umask 20H 587Counts number of partial cache line writes to DRAM channel 2. 588.It Li QMC_WRITES.PARTIAL.ANY 589.Pq Event 2FH , Umask 38H 590Counts number of partial cache line writes to DRAM. 591.It Li QMC_CANCEL.CH0 592.Pq Event 30H , Umask 01H 593Counts number of DRAM channel 0 cancel requests. 594.It Li QMC_CANCEL.CH1 595.Pq Event 30H , Umask 02H 596Counts number of DRAM channel 1 cancel requests. 597.It Li QMC_CANCEL.CH2 598.Pq Event 30H , Umask 04H 599Counts number of DRAM channel 2 cancel requests. 600.It Li QMC_CANCEL.ANY 601.Pq Event 30H , Umask 07H 602Counts number of DRAM cancel requests. 603.It Li QMC_PRIORITY_UPDATES.CH0 604.Pq Event 31H , Umask 01H 605Counts number of DRAM channel 0 priority updates. 606A priority update occurs when an ISOC high or critical request 607is received by the QHL and there is a matching request with normal priority 608that has already been issued to the QMC. 609In this instance, the QHL will send a priority update to QMC to expedite the request. 610.It Li QMC_PRIORITY_UPDATES.CH1 611.Pq Event 31H , Umask 02H 612Counts number of DRAM channel 1 priority updates. 613A priority update occurs when an ISOC high or critical request is received by 614the QHL and there is a matching request with normal priority that has 615already been issued to the QMC. 616In this instance, the QHL will send a priority update to QMC to expedite the request. 617.It Li QMC_PRIORITY_UPDATES.CH2 618.Pq Event 31H , Umask 04H 619Counts number of DRAM channel 2 priority updates. 620A priority update occurs when an ISOC high or critical request is received by 621the QHL and there is a matching request with normal priority that has 622already been issued to the QMC. 623In this instance, the QHL will send a priority update to QMC to expedite the request. 624.It Li QMC_PRIORITY_UPDATES.ANY 625.Pq Event 31H , Umask 07H 626Counts number of DRAM priority updates. 627A priority update occurs when an ISOC high or critical request is received by 628the QHL and there is a matching request with normal priority that has 629already been issued to the QMC. 630In this instance, the QHL will send a priority update to QMC to expedite the request. 631.It Li QHL_FRC_ACK_CNFLTS.LOCAL 632.Pq Event 33H , Umask 04H 633Counts number of Force Acknowledge Conflict messages sent by the Quickpath 634Home Logic to the local home. 635.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 636.Pq Event 40H , Umask 01H 637Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled 638due to lack of a VNA and VN0 credit. 639Note that this event does not filter out when a flit would not have been 640selected for arbitration because another virtual channel is getting arbitrated. 641.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 642.Pq Event 40H , Umask 02H 643Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled 644due to lack of a VNA and VN0 credit. 645Note that this event does not filter out when a flit would not have been 646selected for arbitration because another virtual channel is getting arbitrated. 647.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 648.Pq Event 40H , Umask 04H 649Counts cycles the Quickpath outbound link 0 non-data response virtual 650channel is stalled due to lack of a VNA and VN0 credit. 651Note that this event does not filter out when a flit would not have been 652selected for arbitration because another virtual channel is getting arbitrated. 653.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 654.Pq Event 40H , Umask 08H 655Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled 656due to lack of a VNA and VN0 credit. 657Note that this event does not filter out when a flit would not have been 658selected for arbitration because another virtual channel is getting arbitrated. 659.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 660.Pq Event 40H , Umask 10H 661Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled 662due to lack of a VNA and VN0 credit. 663Note that this event does not filter out when a flit would not have been 664selected for arbitration because another virtual channel is getting arbitrated. 665.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 666.Pq Event 40H , Umask 20H 667Counts cycles the Quickpath outbound link 1 non-data response virtual 668channel is stalled due to lack of a VNA and VN0 credit. 669Note that this event does not filter out when a flit would not have been 670selected for arbitration because another virtual channel is getting arbitrated. 671.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 672.Pq Event 40H , Umask 07H 673Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 674to lack of a VNA and VN0 credit. 675Note that this event does not filter out when a flit would not have been 676selected for arbitration because another virtual channel is getting arbitrated. 677.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 678.Pq Event 40H , Umask 38H 679Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 680to lack of a VNA and VN0 credit. 681Note that this event does not filter out when a flit would not have been 682selected for arbitration because another virtual channel is getting arbitrated. 683.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 684.Pq Event 41H , Umask 01H 685Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is 686stalled due to lack of VNA and VN0 credits. 687Note that this event does not filter out when a flit would not have been 688selected for arbitration because another virtual channel is getting arbitrated. 689.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 690.Pq Event 41H , Umask 02H 691Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual 692channel is stalled due to lack of VNA and VN0 credits. 693Note that this event does not filter out when a flit would not have been 694selected for arbitration because another virtual channel is getting arbitrated. 695.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 696.Pq Event 41H , Umask 04H 697Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual 698channel is stalled due to lack of VNA and VN0 credits. 699Note that this event does not filter out when a flit would not have been 700selected for arbitration because another virtual channel is getting arbitrated. 701.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 702.Pq Event 41H , Umask 08H 703Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is 704stalled due to lack of VNA and VN0 credits. 705Note that this event does not filter out when a flit would not have been 706selected for arbitration because another virtual channel is getting arbitrated. 707.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 708.Pq Event 41H , Umask 10H 709Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual 710channel is stalled due to lack of VNA and VN0 credits. 711Note that this event does not filter out when a flit would not have been 712selected for arbitration because another virtual channel is getting arbitrated. 713.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 714.Pq Event 41H , Umask 20H 715Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual 716channel is stalled due to lack of VNA and VN0 credits. 717Note that this event does not filter out when a flit would not have been 718selected for arbitration because another virtual channel is getting arbitrated. 719.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 720.Pq Event 41H , Umask 07H 721Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 722to lack of VNA and VN0 credits. 723Note that this event does not filter out when a flit would not have been 724selected for arbitration because another virtual channel is getting arbitrated. 725.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 726.Pq Event 41H , Umask 38H 727Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 728to lack of VNA and VN0 credits. 729Note that this event does not filter out when a flit would not have been 730selected for arbitration because another virtual channel is getting arbitrated. 731.It Li QPI_TX_HEADER.BUSY.LINK_0 732.Pq Event 42H , Umask 02H 733Number of cycles that the header buffer in the Quickpath Interface outbound 734link 0 is busy. 735.It Li QPI_TX_HEADER.BUSY.LINK_1 736.Pq Event 42H , Umask 08H 737Number of cycles that the header buffer in the Quickpath Interface outbound 738link 1 is busy. 739.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 740.Pq Event 43H , Umask 01H 741Number of cycles that snoop packets incoming to the Quickpath Interface link 7420 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 743does not have any available entries. 744.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 745.Pq Event 43H , Umask 02H 746Number of cycles that snoop packets incoming to the Quickpath Interface link 7471 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 748does not have any available entries. 749.It Li DRAM_OPEN.CH0 750.Pq Event 60H , Umask 01H 751Counts number of DRAM Channel 0 open commands issued either for read or write. 752To read or write data, the referenced DRAM page must first be opened. 753.It Li DRAM_OPEN.CH1 754.Pq Event 60H , Umask 02H 755Counts number of DRAM Channel 1 open commands issued either for read or write. 756To read or write data, the referenced DRAM page must first be opened. 757.It Li DRAM_OPEN.CH2 758.Pq Event 60H , Umask 04H 759Counts number of DRAM Channel 2 open commands issued either for read or write. 760To read or write data, the referenced DRAM page must first be opened. 761.It Li DRAM_PAGE_CLOSE.CH0 762.Pq Event 61H , Umask 01H 763DRAM channel 0 command issued to CLOSE a page due to page idle timer 764expiration. 765Closing a page is done by issuing a precharge. 766.It Li DRAM_PAGE_CLOSE.CH1 767.Pq Event 61H , Umask 02H 768DRAM channel 1 command issued to CLOSE a page due to page idle timer 769expiration. 770Closing a page is done by issuing a precharge. 771.It Li DRAM_PAGE_CLOSE.CH2 772.Pq Event 61H , Umask 04H 773DRAM channel 2 command issued to CLOSE a page due to page idle timer 774expiration. 775Closing a page is done by issuing a precharge. 776.It Li DRAM_PAGE_MISS.CH0 777.Pq Event 62H , Umask 01H 778Counts the number of precharges (PRE) that were issued to DRAM channel 0 779because there was a page miss. 780A page miss refers to a situation in which a page is currently open and 781another page from the same bank needs to be opened. 782The new page experiences a page miss. 783Closing of the old page is done by issuing a precharge. 784.It Li DRAM_PAGE_MISS.CH1 785.Pq Event 62H , Umask 02H 786Counts the number of precharges (PRE) that were issued to DRAM channel 1 787because there was a page miss. 788A page miss refers to a situation in which a page is currently open and 789another page from the same bank needs to be opened. 790The new page experiences a page miss. 791Closing of the old page is done by issuing a precharge. 792.It Li DRAM_PAGE_MISS.CH2 793.Pq Event 62H , Umask 04H 794Counts the number of precharges (PRE) that were issued to DRAM channel 2 795because there was a page miss. 796A page miss refers to a situation in which a page is currently open and 797another page from the same bank needs to be opened. 798The new page experiences a page miss. 799Closing of the old page is done by issuing a precharge. 800.It Li DRAM_READ_CAS.CH0 801.Pq Event 63H , Umask 01H 802Counts the number of times a read CAS command was issued on DRAM channel 0. 803.It Li DRAM_READ_CAS.AUTOPRE_CH0 804.Pq Event 63H , Umask 02H 805Counts the number of times a read CAS command was issued on DRAM channel 0 806where the command issued used the auto-precharge (auto page close) mode. 807.It Li DRAM_READ_CAS.CH1 808.Pq Event 63H , Umask 04H 809Counts the number of times a read CAS command was issued on DRAM channel 1. 810.It Li DRAM_READ_CAS.AUTOPRE_CH1 811.Pq Event 63H , Umask 08H 812Counts the number of times a read CAS command was issued on DRAM channel 1 813where the command issued used the auto-precharge (auto page close) mode. 814.It Li DRAM_READ_CAS.CH2 815.Pq Event 63H , Umask 10H 816Counts the number of times a read CAS command was issued on DRAM channel 2. 817.It Li DRAM_READ_CAS.AUTOPRE_CH2 818.Pq Event 63H , Umask 20H 819Counts the number of times a read CAS command was issued on DRAM channel 2 820where the command issued used the auto-precharge (auto page close) mode. 821.It Li DRAM_WRITE_CAS.CH0 822.Pq Event 64H , Umask 01H 823Counts the number of times a write CAS command was issued on DRAM channel 0. 824.It Li DRAM_WRITE_CAS.AUTOPRE_CH0 825.Pq Event 64H , Umask 02H 826Counts the number of times a write CAS command was issued on DRAM channel 0 827where the command issued used the auto-precharge (auto page close) mode. 828.It Li DRAM_WRITE_CAS.CH1 829.Pq Event 64H , Umask 04H 830Counts the number of times a write CAS command was issued on DRAM channel 1. 831.It Li DRAM_WRITE_CAS.AUTOPRE_CH1 832.Pq Event 64H , Umask 08H 833Counts the number of times a write CAS command was issued on DRAM channel 1 834where the command issued used the auto-precharge (auto page close) mode. 835.It Li DRAM_WRITE_CAS.CH2 836.Pq Event 64H , Umask 10H 837Counts the number of times a write CAS command was issued on DRAM channel 2. 838.It Li DRAM_WRITE_CAS.AUTOPRE_CH2 839.Pq Event 64H , Umask 20H 840Counts the number of times a write CAS command was issued on DRAM channel 2 841where the command issued used the auto-precharge (auto page close) mode. 842.It Li DRAM_REFRESH.CH0 843.Pq Event 65H , Umask 01H 844Counts number of DRAM channel 0 refresh commands. 845DRAM loses data content over time. 846In order to keep correct data content, the data values have to be 847refreshed periodically. 848.It Li DRAM_REFRESH.CH1 849.Pq Event 65H , Umask 02H 850Counts number of DRAM channel 1 refresh commands. 851DRAM loses data content over time. 852In order to keep correct data content, the data values have to be 853refreshed periodically. 854.It Li DRAM_REFRESH.CH2 855.Pq Event 65H , Umask 04H 856Counts number of DRAM channel 2 refresh commands. 857DRAM loses data content over time. 858In order to keep correct data content, the data values have to be 859refreshed periodically. 860.It Li DRAM_PRE_ALL.CH0 861.Pq Event 66H , Umask 01H 862Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close 863all open pages in a rank. 864PREALL is issued when the DRAM needs to be refreshed or needs to go 865into a power down mode. 866.It Li DRAM_PRE_ALL.CH1 867.Pq Event 66H , Umask 02H 868Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close 869all open pages in a rank. 870PREALL is issued when the DRAM needs to be refreshed or needs to go 871into a power down mode. 872.It Li DRAM_PRE_ALL.CH2 873.Pq Event 66H , Umask 04H 874Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close 875all open pages in a rank. 876PREALL is issued when the DRAM needs to be refreshed or needs to go 877into a power down mode. 878.El 879.Sh SEE ALSO 880.Xr pmc 3 , 881.Xr pmc.amd 3 , 882.Xr pmc.atom 3 , 883.Xr pmc.core 3 , 884.Xr pmc.corei7 3 , 885.Xr pmc.iaf 3 , 886.Xr pmc.soft 3 , 887.Xr pmc.tsc 3 , 888.Xr pmc.ucf 3 , 889.Xr pmc.westmere 3 , 890.Xr pmc.westmereuc 3 , 891.Xr pmc_cpuinfo 3 , 892.Xr pmclog 3 , 893.Xr hwpmc 4 894.Sh HISTORY 895The 896.Nm pmc 897library first appeared in 898.Fx 6.0 . 899.Sh AUTHORS 900The 901.Lb libpmc 902library was written by 903.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 904