1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 24, 2010 27.Dt PMC.COREI7 3 28.Os 29.Sh NAME 30.Nm pmc.corei7 31.Nd measurement events for 32.Tn Intel 33.Tn Core i7 and Xeon 5500 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core i7" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs may contain up to three classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Core i7 and Xeon 5500 PMCs are documented in 59.Rs 60.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 61.%T "Volume 3B: System Programming Guide, Part 2" 62.%N "Order Number: 253669-033US" 63.%D December 2009 64.%Q "Intel Corporation" 65.Re 66.Ss COREI7 AND XEON 5500 FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69Not all CPUs in this family implement fixed-function counters. 70.Ss COREI7 AND XEON 5500 PROGRAMMABLE PMCS 71The programmable PMCs support the following capabilities: 72.Bl -column "PMC_CAP_INTERRUPT" "Support" 73.It Em Capability Ta Em Support 74.It PMC_CAP_CASCADE Ta \&No 75.It PMC_CAP_EDGE Ta Yes 76.It PMC_CAP_INTERRUPT Ta Yes 77.It PMC_CAP_INVERT Ta Yes 78.It PMC_CAP_READ Ta Yes 79.It PMC_CAP_PRECISE Ta \&No 80.It PMC_CAP_SYSTEM Ta Yes 81.It PMC_CAP_TAGGING Ta \&No 82.It PMC_CAP_THRESHOLD Ta Yes 83.It PMC_CAP_USER Ta Yes 84.It PMC_CAP_WRITE Ta Yes 85.El 86.Ss Event Qualifiers 87Event specifiers for these PMCs support the following common 88qualifiers: 89.Bl -tag -width indent 90.It Li rsp= Ns Ar value 91Configure the Off-core Response bits. 92.Bl -tag -width indent 93.It Li DMND_DATA_RD 94Counts the number of demand and DCU prefetch data reads of full 95and partial cachelines as well as demand data page table entry 96cacheline reads. 97Does not count L2 data read prefetches or instruction fetches. 98.It Li DMND_RFO 99Counts the number of demand and DCU prefetch reads for ownership 100(RFO) requests generated by a write to data cacheline. 101Does not count L2 RFO. 102.It Li DMND_IFETCH 103Counts the number of demand and DCU prefetch instruction cacheline 104reads. 105Does not count L2 code read prefetches. 106WB Counts the number of writeback (modified to exclusive) transactions. 107.It Li PF_DATA_RD 108Counts the number of data cacheline reads generated by L2 prefetchers. 109.It Li PF_RFO 110Counts the number of RFO requests generated by L2 prefetchers. 111.It Li PF_IFETCH 112Counts the number of code reads generated by L2 prefetchers. 113.It Li OTHER 114Counts one of the following transaction types, including L3 invalidate, 115I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, 116lock, unlock, split lock. 117.It Li UNCORE_HIT 118L3 Hit: local or remote home requests that hit L3 cache in the uncore 119with no coherency actions required (snooping). 120.It Li OTHER_CORE_HIT_SNP 121L3 Hit: local or remote home requests that hit L3 cache in the uncore 122and was serviced by another core with a cross core snoop where no modified 123copies were found (clean). 124.It Li OTHER_CORE_HITM 125L3 Hit: local or remote home requests that hit L3 cache in the uncore 126and was serviced by another core with a cross core snoop where modified 127copies were found (HITM). 128.It Li REMOTE_CACHE_FWD 129L3 Miss: local homed requests that missed the L3 cache and was serviced 130by forwarded data following a cross package snoop where no modified 131copies found. (Remote home requests are not counted) 132.It Li REMOTE_DRAM 133L3 Miss: remote home requests that missed the L3 cache and were serviced 134by remote DRAM. 135.It Li LOCAL_DRAM 136L3 Miss: local home requests that missed the L3 cache and were serviced 137by local DRAM. 138.It Li NON_DRAM 139Non-DRAM requests that were serviced by IOH. 140.El 141.It Li cmask= Ns Ar value 142Configure the PMC to increment only if the number of configured 143events measured in a cycle is greater than or equal to 144.Ar value . 145.It Li edge 146Configure the PMC to count the number of de-asserted to asserted 147transitions of the conditions expressed by the other qualifiers. 148If specified, the counter will increment only once whenever a 149condition becomes true, irrespective of the number of clocks during 150which the condition remains true. 151.It Li inv 152Invert the sense of comparison when the 153.Dq Li cmask 154qualifier is present, making the counter increment when the number of 155events per cycle is less than the value specified by the 156.Dq Li cmask 157qualifier. 158.It Li os 159Configure the PMC to count events happening at processor privilege 160level 0. 161.It Li usr 162Configure the PMC to count events occurring at privilege levels 1, 2 163or 3. 164.El 165.Pp 166If neither of the 167.Dq Li os 168or 169.Dq Li usr 170qualifiers are specified, the default is to enable both. 171.Ss Event Specifiers (Programmable PMCs) 172Core i7 and Xeon 5500 programmable PMCs support the following events: 173.Bl -tag -width indent 174.It Li SB_DRAIN.ANY 175.Pq Event 04H , Umask 07H 176Counts the number of store buffer drains. 177.It Li STORE_BLOCKS.AT_RET 178.Pq Event 06H , Umask 04H 179Counts number of loads delayed with at-Retirement block code. 180The following loads need to be executed at retirement and wait for all 181senior stores on the same thread to be drained: load splitting across 1824K boundary (page split), load accessing uncacheable 183(UC or USWC) memory, load lock, and load with page table in UC or USWC memory region. 184.It Li STORE_BLOCKS.L1D_BLOCK 185.Pq Event 06H , Umask 08H 186Cacheable loads delayed with L1D block code 187.It Li PARTIAL_ADDRESS_ALIAS 188.Pq Event 07H , Umask 01H 189Counts false dependency due to partial address aliasing 190.It Li DTLB_LOAD_MISSES.ANY 191.Pq Event 08H , Umask 01H 192Counts all load misses that cause a page walk 193.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 194.Pq Event 08H , Umask 02H 195Counts number of completed page walks due to load miss in the STLB. 196.It Li DTLB_LOAD_MISSES.STLB_HIT 197.Pq Event 08H , Umask 10H 198Number of cache load STLB hits 199.It Li DTLB_LOAD_MISSES.PDE_MISS 200.Pq Event 08H , Umask 20H 201Number of DTLB cache load misses where the low part of the linear to 202physical address translation was missed. 203.It Li DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED 204.Pq Event 08H , Umask 80H 205Counts number of completed large page walks due to load miss in the STLB. 206.It Li MEM_INST_RETIRED.LOADS 207.Pq Event 0BH , Umask 01H 208Counts the number of instructions with an architecturally-visible store 209retired on the architected path. 210In conjunction with ld_lat facility 211.It Li MEM_INST_RETIRED.STORES 212.Pq Event 0BH , Umask 02H 213Counts the number of instructions with an architecturally-visible store 214retired on the architected path. 215In conjunction with ld_lat facility 216.It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD 217.Pq Event 0BH , Umask 10H 218Counts the number of instructions exceeding the latency specified with 219ld_lat facility. 220In conjunction with ld_lat facility 221.It Li MEM_STORE_RETIRED.DTLB_MISS 222.Pq Event 0CH , Umask 01H 223The event counts the number of retired stores that missed the DTLB. 224The DTLB miss is not counted if the store operation causes a fault. 225Does not counter prefetches. 226Counts both primary and secondary misses to the TLB 227.It Li UOPS_ISSUED.ANY 228.Pq Event 0EH , Umask 01H 229Counts the number of Uops issued by the Register Allocation Table to the 230Reservation Station, i.e. the UOPs issued from the front end to the back 231end. 232.It Li UOPS_ISSUED.STALLED_CYCLES 233.Pq Event 0EH , Umask 01H 234Counts the number of cycles no Uops issued by the Register Allocation Table 235to the Reservation Station, i.e. the UOPs issued from the front end to the 236back end. 237set invert=1, cmask = 1 238.It Li UOPS_ISSUED.FUSED 239.Pq Event 0EH , Umask 02H 240Counts the number of fused Uops that were issued from the Register 241Allocation Table to the Reservation Station. 242.It Li MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN 243.Pq Event 0FH , Umask 01H 244Counts number of memory load instructions retired where the memory reference 245missed L3 and data source is unknown. 246Available only for CPUID signature 06_2EH 247.It Li MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM 248.Pq Event 0FH , Umask 02H 249Counts number of memory load instructions retired where the memory reference 250hit modified data in a sibling core residing on the same socket. 251.It Li MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT 252.Pq Event 0FH , Umask 08H 253Counts number of memory load instructions retired where the memory reference 254missed the L1, L2 and L3 caches and HIT in a remote socket's cache. 255Only counts locally homed lines. 256.It Li MEM_UNCORE_RETIRED.REMOTE_DRAM 257.Pq Event 0FH , Umask 10H 258Counts number of memory load instructions retired where the memory reference 259missed the L1, L2 and L3 caches and was remotely homed. 260This includes both DRAM access and HITM in a remote socket's cache 261for remotely homed lines. 262.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM 263.Pq Event 0FH , Umask 20H 264Counts number of memory load instructions retired where the memory reference 265missed the L1, L2 and L3 caches and required a local socket memory 266reference. 267This includes locally homed cachelines that were in a modified 268state in another socket. 269.It Li MEM_UNCORE_RETIRED.UNCACHEABLE 270.Pq Event 0FH , Umask 80H 271Counts number of memory load instructions retired where the memory reference 272missed the L1, L2 and L3 caches and to perform I/O. 273Available only for CPUID signature 06_2EH 274.It Li FP_COMP_OPS_EXE.X87 275.Pq Event 10H , Umask 01H 276Counts the number of FP Computational Uops Executed. 277The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer 278DIVs, and IDIVs. 279This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction. 280.It Li FP_COMP_OPS_EXE.MMX 281.Pq Event 10H , Umask 02H 282Counts number of MMX Uops executed. 283.It Li FP_COMP_OPS_EXE.SSE_FP 284.Pq Event 10H , Umask 04H 285Counts number of SSE and SSE2 FP uops executed. 286.It Li FP_COMP_OPS_EXE.SSE2_INTEGER 287.Pq Event 10H , Umask 08H 288Counts number of SSE2 integer uops executed. 289.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED 290.Pq Event 10H , Umask 10H 291Counts number of SSE FP packed uops executed. 292.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR 293.Pq Event 10H , Umask 20H 294Counts number of SSE FP scalar uops executed. 295.It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION 296.Pq Event 10H , Umask 40H 297Counts number of SSE* FP single precision uops executed. 298.It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION 299.Pq Event 10H , Umask 80H 300Counts number of SSE* FP double precision uops executed. 301.It Li SIMD_INT_128.PACKED_MPY 302.Pq Event 12H , Umask 01H 303Counts number of 128 bit SIMD integer multiply operations. 304.It Li SIMD_INT_128.PACKED_SHIFT 305.Pq Event 12H , Umask 02H 306Counts number of 128 bit SIMD integer shift operations. 307.It Li SIMD_INT_128.PACK 308.Pq Event 12H , Umask 04H 309Counts number of 128 bit SIMD integer pack operations. 310.It Li SIMD_INT_128.UNPACK 311.Pq Event 12H , Umask 08H 312Counts number of 128 bit SIMD integer unpack operations. 313.It Li SIMD_INT_128.PACKED_LOGICAL 314.Pq Event 12H , Umask 10H 315Counts number of 128 bit SIMD integer logical operations. 316.It Li SIMD_INT_128.PACKED_ARITH 317.Pq Event 12H , Umask 20H 318Counts number of 128 bit SIMD integer arithmetic operations. 319.It Li SIMD_INT_128.SHUFFLE_MOVE 320.Pq Event 12H , Umask 40H 321Counts number of 128 bit SIMD integer shuffle and move operations. 322.It Li LOAD_DISPATCH.RS 323.Pq Event 13H , Umask 01H 324Counts number of loads dispatched from the Reservation Station that bypass 325the Memory Order Buffer. 326.It Li LOAD_DISPATCH.RS_DELAYED 327.Pq Event 13H , Umask 02H 328Counts the number of delayed RS dispatches at the stage latch. 329If an RS dispatch can not bypass to LB, it has another chance to dispatch from the 330one-cycle delayed staging latch before it is written into the LB. 331.It Li LOAD_DISPATCH.MOB 332.Pq Event 13H , Umask 04H 333Counts the number of loads dispatched from the Reservation Station to the 334Memory Order Buffer. 335.It Li LOAD_DISPATCH.ANY 336.Pq Event 13H , Umask 07H 337Counts all loads dispatched from the Reservation Station. 338.It Li ARITH.CYCLES_DIV_BUSY 339.Pq Event 14H , Umask 01H 340Counts the number of cycles the divider is busy executing divide or square 341root operations. 342The divide can be integer, X87 or Streaming SIMD Extensions (SSE). 343The square root operation can be either X87 or SSE. 344Set 'edge =1, invert=1, cmask=1' to count the number of divides. 345Count may be incorrect When SMT is on. 346.It Li ARITH.MUL 347.Pq Event 14H , Umask 02H 348Counts the number of multiply operations executed. 349This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. 350Count may be incorrect When SMT is on 351.It Li INST_QUEUE_WRITES 352.Pq Event 17H , Umask 01H 353Counts the number of instructions written into the instruction queue every 354cycle. 355.It Li INST_DECODED.DEC0 356.Pq Event 18H , Umask 01H 357Counts number of instructions that require decoder 0 to be decoded. 358Usually, this means that the instruction maps to more than 1 uop 359.It Li TWO_UOP_INSTS_DECODED 360.Pq Event 19H , Umask 01H 361An instruction that generates two uops was decoded 362.It Li INST_QUEUE_WRITE_CYCLES 363.Pq Event 1EH , Umask 01H 364This event counts the number of cycles during which instructions are written 365to the instruction queue. 366Dividing this counter by the number of instructions written to the 367instruction queue (INST_QUEUE_WRITES) yields the average number of 368instructions decoded each cycle. 369If this number is less than four and the pipe stalls, this indicates that the decoder is failing to 370decode enough instructions per cycle to sustain the 4-wide pipeline. 371If SSE* instructions that are 6 bytes or longer arrive one after another, 372then front end throughput may limit execution speed. 373In such case, 374.It Li LSD_OVERFLOW 375.Pq Event 20H , Umask 01H 376Counts number of loops that cant stream from the instruction queue. 377.It Li L2_RQSTS.LD_HIT 378.Pq Event 24H , Umask 01H 379Counts number of loads that hit the L2 cache. 380L2 loads include both L1D demand misses as well as L1D prefetches. 381L2 loads can be rejected for various reasons. 382Only non rejected loads are counted. 383.It Li L2_RQSTS.LD_MISS 384.Pq Event 24H , Umask 02H 385Counts the number of loads that miss the L2 cache. 386L2 loads include both L1D demand misses as well as L1D prefetches. 387.It Li L2_RQSTS.LOADS 388.Pq Event 24H , Umask 03H 389Counts all L2 load requests. 390L2 loads include both L1D demand misses as well as L1D prefetches. 391.It Li L2_RQSTS.RFO_HIT 392.Pq Event 24H , Umask 04H 393Counts the number of store RFO requests that hit the L2 cache. 394L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. 395Count includes WC memory requests, where the data is not fetched but the 396permission to write the line is required. 397.It Li L2_RQSTS.RFO_MISS 398.Pq Event 24H , Umask 08H 399Counts the number of store RFO requests that miss the L2 cache. 400L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. 401.It Li L2_RQSTS.RFOS 402.Pq Event 24H , Umask 0CH 403Counts all L2 store RFO requests. 404L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. 405.It Li L2_RQSTS.IFETCH_HIT 406.Pq Event 24H , Umask 10H 407Counts number of instruction fetches that hit the L2 cache. 408L2 instruction fetches include both L1I demand misses as well as L1I instruction 409prefetches. 410.It Li L2_RQSTS.IFETCH_MISS 411.Pq Event 24H , Umask 20H 412Counts number of instruction fetches that miss the L2 cache. 413L2 instruction fetches include both L1I demand misses as well as L1I instruction 414prefetches. 415.It Li L2_RQSTS.IFETCHES 416.Pq Event 24H , Umask 30H 417Counts all instruction fetches. 418L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. 419.It Li L2_RQSTS.PREFETCH_HIT 420.Pq Event 24H , Umask 40H 421Counts L2 prefetch hits for both code and data. 422.It Li L2_RQSTS.PREFETCH_MISS 423.Pq Event 24H , Umask 80H 424Counts L2 prefetch misses for both code and data. 425.It Li L2_RQSTS.PREFETCHES 426.Pq Event 24H , Umask C0H 427Counts all L2 prefetches for both code and data. 428.It Li L2_RQSTS.MISS 429.Pq Event 24H , Umask AAH 430Counts all L2 misses for both code and data. 431.It Li L2_RQSTS.REFERENCES 432.Pq Event 24H , Umask FFH 433Counts all L2 requests for both code and data. 434.It Li L2_DATA_RQSTS.DEMAND.I_STATE 435.Pq Event 26H , Umask 01H 436Counts number of L2 data demand loads where the cache line to be loaded is 437in the I (invalid) state, i.e. a cache miss. 438L2 demand loads are both L1D demand misses and L1D prefetches. 439.It Li L2_DATA_RQSTS.DEMAND.S_STATE 440.Pq Event 26H , Umask 02H 441Counts number of L2 data demand loads where the cache line to be loaded is 442in the S (shared) state. 443L2 demand loads are both L1D demand misses and L1D prefetches. 444.It Li L2_DATA_RQSTS.DEMAND.E_STATE 445.Pq Event 26H , Umask 04H 446Counts number of L2 data demand loads where the cache line to be loaded is 447in the E (exclusive) state. 448L2 demand loads are both L1D demand misses and L1D prefetches. 449.It Li L2_DATA_RQSTS.DEMAND.M_STATE 450.Pq Event 26H , Umask 08H 451Counts number of L2 data demand loads where the cache line to be loaded is 452in the M (modified) state. 453L2 demand loads are both L1D demand misses and L1D prefetches. 454.It Li L2_DATA_RQSTS.DEMAND.MESI 455.Pq Event 26H , Umask 0FH 456Counts all L2 data demand requests. 457L2 demand loads are both L1D demand misses and L1D prefetches. 458.It Li L2_DATA_RQSTS.PREFETCH.I_STATE 459.Pq Event 26H , Umask 10H 460Counts number of L2 prefetch data loads where the cache line to be loaded is 461in the I (invalid) state, i.e. a cache miss. 462.It Li L2_DATA_RQSTS.PREFETCH.S_STATE 463.Pq Event 26H , Umask 20H 464Counts number of L2 prefetch data loads where the cache line to be loaded is 465in the S (shared) state. 466A prefetch RFO will miss on an S state line, while a prefetch read will 467hit on an S state line. 468.It Li L2_DATA_RQSTS.PREFETCH.E_STATE 469.Pq Event 26H , Umask 40H 470Counts number of L2 prefetch data loads where the cache line to be loaded is 471in the E (exclusive) state. 472.It Li L2_DATA_RQSTS.PREFETCH.M_STATE 473.Pq Event 26H , Umask 80H 474Counts number of L2 prefetch data loads where the cache line to be loaded is 475in the M (modified) state. 476.It Li L2_DATA_RQSTS.PREFETCH.MESI 477.Pq Event 26H , Umask F0H 478Counts all L2 prefetch requests. 479.It Li L2_DATA_RQSTS.ANY 480.Pq Event 26H , Umask FFH 481Counts all L2 data requests. 482.It Li L2_WRITE.RFO.I_STATE 483.Pq Event 27H , Umask 01H 484Counts number of L2 demand store RFO requests where the cache line to be 485loaded is in the I (invalid) state, i.e, a cache miss. 486The L1D prefetcher does not issue a RFO prefetch. 487This is a demand RFO request 488.It Li L2_WRITE.RFO.S_STATE 489.Pq Event 27H , Umask 02H 490Counts number of L2 store RFO requests where the cache line to be loaded is 491in the S (shared) state. 492The L1D prefetcher does not issue a RFO prefetch. 493This is a demand RFO request 494.It Li L2_WRITE.RFO.M_STATE 495.Pq Event 27H , Umask 08H 496Counts number of L2 store RFO requests where the cache line to be loaded is 497in the M (modified) state. 498The L1D prefetcher does not issue a RFO prefetch. 499This is a demand RFO request 500.It Li L2_WRITE.RFO.HIT 501.Pq Event 27H , Umask 0EH 502Counts number of L2 store RFO requests where the cache line to be loaded is 503in either the S, E or M states. 504The L1D prefetcher does not issue a RFO prefetch. 505This is a demand RFO request 506.It Li L2_WRITE.RFO.MESI 507.Pq Event 27H , Umask 0FH 508Counts all L2 store RFO requests. 509The L1D prefetcher does not issue a RFO prefetch. 510This is a demand RFO request 511.It Li L2_WRITE.LOCK.I_STATE 512.Pq Event 27H , Umask 10H 513Counts number of L2 demand lock RFO requests where the cache line to be 514loaded is in the I (invalid) state, i.e. a cache miss. 515.It Li L2_WRITE.LOCK.S_STATE 516.Pq Event 27H , Umask 20H 517Counts number of L2 lock RFO requests where the cache line to be loaded is 518in the S (shared) state. 519.It Li L2_WRITE.LOCK.E_STATE 520.Pq Event 27H , Umask 40H 521Counts number of L2 demand lock RFO requests where the cache line to be 522loaded is in the E (exclusive) state. 523.It Li L2_WRITE.LOCK.M_STATE 524.Pq Event 27H , Umask 80H 525Counts number of L2 demand lock RFO requests where the cache line to be 526loaded is in the M (modified) state. 527.It Li L2_WRITE.LOCK.HIT 528.Pq Event 27H , Umask E0H 529Counts number of L2 demand lock RFO requests where the cache line to be 530loaded is in either the S, E, or M state. 531.It Li L2_WRITE.LOCK.MESI 532.Pq Event 27H , Umask F0H 533Counts all L2 demand lock RFO requests. 534.It Li L1D_WB_L2.I_STATE 535.Pq Event 28H , Umask 01H 536Counts number of L1 writebacks to the L2 where the cache line to be written 537is in the I (invalid) state, i.e. a cache miss. 538.It Li L1D_WB_L2.S_STATE 539.Pq Event 28H , Umask 02H 540Counts number of L1 writebacks to the L2 where the cache line to be written 541is in the S state. 542.It Li L1D_WB_L2.E_STATE 543.Pq Event 28H , Umask 04H 544Counts number of L1 writebacks to the L2 where the cache line to be written 545is in the E (exclusive) state. 546.It Li L1D_WB_L2.M_STATE 547.Pq Event 28H , Umask 08H 548Counts number of L1 writebacks to the L2 where the cache line to be written 549is in the M (modified) state. 550.It Li L1D_WB_L2.MESI 551.Pq Event 28H , Umask 0FH 552Counts all L1 writebacks to the L2. 553.It Li L3_LAT_CACHE.REFERENCE 554.Pq Event 2EH , Umask 4FH 555This event counts requests originating from the core that reference a cache 556line in the last level cache. 557The event count includes speculative traffic but excludes cache line fills 558due to a L2 hardware-prefetch. 559Because cache hierarchy, cache sizes and other implementation-specific 560characteristics; value comparison to estimate performance differences is not recommended. 561see Table A-1 562.It Li L3_LAT_CACHE.MISS 563.Pq Event 2EH , Umask 41H 564This event counts each cache miss condition for references to the last level 565cache. 566The event count may include speculative traffic but excludes cache 567line fills due to L2 hardware-prefetches. 568Because cache hierarchy, cache sizes and other implementation-specific 569characteristics; value comparison to estimate performance differences is not recommended. 570see Table A-1 571.It Li CPU_CLK_UNHALTED.THREAD_P 572.Pq Event 3CH , Umask 00H 573Counts the number of thread cycles while the thread is not in a halt state. 574The thread enters the halt state when it is running the HLT instruction. 575The core frequency may change from time to time due to power or thermal throttling. 576see Table A-1 577.It Li CPU_CLK_UNHALTED.REF_P 578.Pq Event 3CH , Umask 01H 579Increments at the frequency of TSC when not halted. 580see Table A-1 581.It Li L1D_CACHE_LD.I_STATE 582.Pq Event 40H , Umask 01H 583Counts L1 data cache read requests where the cache line to be loaded is in 584the I (invalid) state, i.e. the read request missed the cache. 585Counter 0, 1 only 586.It Li L1D_CACHE_LD.S_STATE 587.Pq Event 40H , Umask 02H 588Counts L1 data cache read requests where the cache line to be loaded is in 589the S (shared) state. 590Counter 0, 1 only 591.It Li L1D_CACHE_LD.E_STATE 592.Pq Event 40H , Umask 04H 593Counts L1 data cache read requests where the cache line to be loaded is in 594the E (exclusive) state. 595Counter 0, 1 only 596.It Li L1D_CACHE_LD.M_STATE 597.Pq Event 40H , Umask 08H 598Counts L1 data cache read requests where the cache line to be loaded is in 599the M (modified) state. 600Counter 0, 1 only 601.It Li L1D_CACHE_LD.MESI 602.Pq Event 40H , Umask 0FH 603Counts L1 data cache read requests. 604Counter 0, 1 only 605.It Li L1D_CACHE_ST.S_STATE 606.Pq Event 41H , Umask 02H 607Counts L1 data cache store RFO requests where the cache line to be loaded is 608in the S (shared) state. 609Counter 0, 1 only 610.It Li L1D_CACHE_ST.E_STATE 611.Pq Event 41H , Umask 04H 612Counts L1 data cache store RFO requests where the cache line to be loaded is 613in the E (exclusive) state. 614Counter 0, 1 only 615.It Li L1D_CACHE_ST.M_STATE 616.Pq Event 41H , Umask 08H 617Counts L1 data cache store RFO requests where cache line to be loaded is in 618the M (modified) state. 619Counter 0, 1 only 620.It Li L1D_CACHE_LOCK.HIT 621.Pq Event 42H , Umask 01H 622Counts retired load locks that hit in the L1 data cache or hit in an already 623allocated fill buffer. 624The lock portion of the load lock transaction must hit in the L1D. 625The initial load will pull the lock into the L1 data cache. 626Counter 0, 1 only 627.It Li L1D_CACHE_LOCK.S_STATE 628.Pq Event 42H , Umask 02H 629Counts L1 data cache retired load locks that hit the target cache line in 630the shared state. 631Counter 0, 1 only 632.It Li L1D_CACHE_LOCK.E_STATE 633.Pq Event 42H , Umask 04H 634Counts L1 data cache retired load locks that hit the target cache line in 635the exclusive state. 636Counter 0, 1 only 637.It Li L1D_CACHE_LOCK.M_STATE 638.Pq Event 42H , Umask 08H 639Counts L1 data cache retired load locks that hit the target cache line in 640the modified state. 641Counter 0, 1 only 642.It Li L1D_ALL_REF.ANY 643.Pq Event 43H , Umask 01H 644Counts all references (uncached, speculated and retired) to the L1 data 645cache, including all loads and stores with any memory types. 646The event counts memory accesses only when they are actually performed. 647For example, a load blocked by unknown store address and later performed 648is only counted once. 649The event does not include non- memory accesses, such as I/O accesses. 650Counter 0, 1 only 651.It Li L1D_ALL_REF.CACHEABLE 652.Pq Event 43H , Umask 02H 653Counts all data reads and writes (speculated and retired) from cacheable 654memory, including locked operations. 655Counter 0, 1 only 656.It Li DTLB_MISSES.ANY 657.Pq Event 49H , Umask 01H 658Counts the number of misses in the STLB which causes a page walk. 659.It Li DTLB_MISSES.WALK_COMPLETED 660.Pq Event 49H , Umask 02H 661Counts number of misses in the STLB which resulted in a completed page walk. 662.It Li DTLB_MISSES.STLB_HIT 663.Pq Event 49H , Umask 10H 664Counts the number of DTLB first level misses that hit in the second level TLB. 665This event is only relevant if the core contains multiple DTLB levels. 666.It Li DTLB_MISSES.PDE_MISS 667.Pq Event 49H , Umask 20H 668Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pages do not use the PDE. 669.It Li DTLB_MISSES.LARGE_WALK_COMPLETED 670.Pq Event 49H , Umask 80H 671Counts number of misses in the STLB which resulted in a completed page walk for large pages. 672.It Li LOAD_HIT_PRE 673.Pq Event 4CH , Umask 01H 674Counts load operations sent to the L1 data cache while a previous SSE 675prefetch instruction to the same cache line has started prefetching but has 676not yet finished. 677.It Li L1D_PREFETCH.REQUESTS 678.Pq Event 4EH , Umask 01H 679Counts number of hardware prefetch requests dispatched out of the prefetch 680FIFO. 681.It Li L1D_PREFETCH.MISS 682.Pq Event 4EH , Umask 02H 683Counts number of hardware prefetch requests that miss the L1D. 684There are two prefetchers in the L1D. 685A streamer, which predicts lines sequentially after this one should be fetched, 686and the IP prefetcher that remembers access patterns for the current instruction. 687The streamer prefetcher stops on an L1D hit, while the IP prefetcher does not. 688.It Li L1D_PREFETCH.TRIGGERS 689.Pq Event 4EH , Umask 04H 690Counts number of prefetch requests triggered by the Finite State Machine and 691pushed into the prefetch FIFO. 692Some of the prefetch requests are dropped due to overwrites or competition between 693the IP index prefetcher and streamer prefetcher. 694The prefetch FIFO contains 4 entries. 695.It Li L1D.REPL 696.Pq Event 51H , Umask 01H 697Counts the number of lines brought into the L1 data cache. 698Counter 0, 1 only 699.It Li L1D.M_REPL 700.Pq Event 51H , Umask 02H 701Counts the number of modified lines brought into the L1 data cache. 702Counter 0, 1 only 703.It Li L1D.M_EVICT 704.Pq Event 51H , Umask 04H 705Counts the number of modified lines evicted from the L1 data cache due to 706replacement. 707Counter 0, 1 only 708.It Li L1D.M_SNOOP_EVICT 709.Pq Event 51H , Umask 08H 710Counts the number of modified lines evicted from the L1 data cache due to 711snoop HITM intervention. 712Counter 0, 1 only 713.It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT 714.Pq Event 52H , Umask 01H 715Counts the number of cacheable load lock speculated instructions accepted 716into the fill buffer. 717.It Li L1D_CACHE_LOCK_FB_HIT 718.Pq Event 53H , Umask 01H 719Counts the number of cacheable load lock speculated or retired instructions 720accepted into the fill buffer. 721.It Li CACHE_LOCK_CYCLES.L1D_L2 722.Pq Event 63H , Umask 01H 723Cycle count during which the L1D and L2 are locked. 724A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked 725operation that spans two cache lines, or a page walk from an uncacheable 726page table. 727Counter 0, 1 only. 728L1D and L2 locks have a very high performance penalty and it is highly recommended to 729avoid such accesses. 730.It Li CACHE_LOCK_CYCLES.L1D 731.Pq Event 63H , Umask 02H 732Counts the number of cycles that cacheline in the L1 data cache unit is 733locked. 734Counter 0, 1 only. 735.It Li IO_TRANSACTIONS 736.Pq Event 6CH , Umask 01H 737Counts the number of completed I/O transactions. 738.It Li L1I.HITS 739.Pq Event 80H , Umask 01H 740Counts all instruction fetches that hit the L1 instruction cache. 741.It Li L1I.MISSES 742.Pq Event 80H , Umask 02H 743Counts all instruction fetches that miss the L1I cache. 744This includes instruction cache misses, streaming buffer misses, victim cache misses and 745uncacheable fetches. 746An instruction fetch miss is counted only once and not once for every cycle 747it is outstanding. 748.It Li L1I.READS 749.Pq Event 80H , Umask 03H 750Counts all instruction fetches, including uncacheable fetches that bypass 751the L1I. 752.It Li L1I.CYCLES_STALLED 753.Pq Event 80H , Umask 04H 754Cycle counts for which an instruction fetch stalls due to a L1I cache miss, 755ITLB miss or ITLB fault. 756.It Li LARGE_ITLB.HIT 757.Pq Event 82H , Umask 01H 758Counts number of large ITLB hits. 759.It Li ITLB_MISSES.ANY 760.Pq Event 85H , Umask 01H 761Counts the number of misses in all levels of the ITLB which causes a page 762walk. 763.It Li ITLB_MISSES.WALK_COMPLETED 764.Pq Event 85H , Umask 02H 765Counts number of misses in all levels of the ITLB which resulted in a 766completed page walk. 767.It Li ILD_STALL.LCP 768.Pq Event 87H , Umask 01H 769Cycles Instruction Length Decoder stalls due to length changing prefixes: 77066, 67 or REX.W (for EM64T) instructions which change the length of the 771decoded instruction. 772.It Li ILD_STALL.MRU 773.Pq Event 87H , Umask 02H 774Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) 775Most Recently Used (MRU) bypass. 776.It Li ILD_STALL.IQ_FULL 777.Pq Event 87H , Umask 04H 778Stall cycles due to a full instruction queue. 779.It Li ILD_STALL.REGEN 780.Pq Event 87H , Umask 08H 781Counts the number of regen stalls. 782.It Li ILD_STALL.ANY 783.Pq Event 87H , Umask 0FH 784Counts any cycles the Instruction Length Decoder is stalled. 785.It Li BR_INST_EXEC.COND 786.Pq Event 88H , Umask 01H 787Counts the number of conditional near branch instructions executed, but not 788necessarily retired. 789.It Li BR_INST_EXEC.DIRECT 790.Pq Event 88H , Umask 02H 791Counts all unconditional near branch instructions excluding calls and 792indirect branches. 793.It Li BR_INST_EXEC.INDIRECT_NON_CALL 794.Pq Event 88H , Umask 04H 795Counts the number of executed indirect near branch instructions that are not 796calls. 797.It Li BR_INST_EXEC.NON_CALLS 798.Pq Event 88H , Umask 07H 799Counts all non call near branch instructions executed, but not necessarily 800retired. 801.It Li BR_INST_EXEC.RETURN_NEAR 802.Pq Event 88H , Umask 08H 803Counts indirect near branches that have a return mnemonic. 804.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 805.Pq Event 88H , Umask 10H 806Counts unconditional near call branch instructions, excluding non call 807branch, executed. 808.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 809.Pq Event 88H , Umask 20H 810Counts indirect near calls, including both register and memory indirect, 811executed. 812.It Li BR_INST_EXEC.NEAR_CALLS 813.Pq Event 88H , Umask 30H 814Counts all near call branches executed, but not necessarily retired. 815.It Li BR_INST_EXEC.TAKEN 816.Pq Event 88H , Umask 40H 817Counts taken near branches executed, but not necessarily retired. 818.It Li BR_INST_EXEC.ANY 819.Pq Event 88H , Umask 7FH 820Counts all near executed branches (not necessarily retired). 821This includes only instructions and not micro-op branches. 822Frequent branching is not necessarily a major performance issue. 823However frequent branch mispredictions may be a problem. 824.It Li BR_MISP_EXEC.COND 825.Pq Event 89H , Umask 01H 826Counts the number of mispredicted conditional near branch instructions 827executed, but not necessarily retired. 828.It Li BR_MISP_EXEC.DIRECT 829.Pq Event 89H , Umask 02H 830Counts mispredicted macro unconditional near branch instructions, excluding 831calls and indirect branches (should always be 0). 832.It Li BR_MISP_EXEC.INDIRECT_NON_CALL 833.Pq Event 89H , Umask 04H 834Counts the number of executed mispredicted indirect near branch instructions 835that are not calls. 836.It Li BR_MISP_EXEC.NON_CALLS 837.Pq Event 89H , Umask 07H 838Counts mispredicted non call near branches executed, but not necessarily 839retired. 840.It Li BR_MISP_EXEC.RETURN_NEAR 841.Pq Event 89H , Umask 08H 842Counts mispredicted indirect branches that have a rear return mnemonic. 843.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 844.Pq Event 89H , Umask 10H 845Counts mispredicted non-indirect near calls executed, (should always be 0). 846.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 847.Pq Event 89H , Umask 20H 848Counts mispredicted indirect near calls executed, including both register 849and memory indirect. 850.It Li BR_MISP_EXEC.NEAR_CALLS 851.Pq Event 89H , Umask 30H 852Counts all mispredicted near call branches executed, but not necessarily 853retired. 854.It Li BR_MISP_EXEC.TAKEN 855.Pq Event 89H , Umask 40H 856Counts executed mispredicted near branches that are taken, but not 857necessarily retired. 858.It Li BR_MISP_EXEC.ANY 859.Pq Event 89H , Umask 7FH 860Counts the number of mispredicted near branch instructions that were 861executed, but not necessarily retired. 862.It Li RESOURCE_STALLS.ANY 863.Pq Event A2H , Umask 01H 864Counts the number of Allocator resource related stalls. 865Includes register renaming buffer entries, memory buffer entries. 866In addition to resource related stalls, this event counts some other events. 867Includes stalls arising during branch misprediction recovery, such as if retirement of the 868mispredicted branch is delayed and stalls arising while store buffer is 869draining from synchronizing operations. 870Does not include stalls due to SuperQ (off core) queue full, too many cache 871misses, etc. 872.It Li RESOURCE_STALLS.LOAD 873.Pq Event A2H , Umask 02H 874Counts the cycles of stall due to lack of load buffer for load operation. 875.It Li RESOURCE_STALLS.RS_FULL 876.Pq Event A2H , Umask 04H 877This event counts the number of cycles when the number of instructions in 878the pipeline waiting for execution reaches the limit the processor can handle. 879A high count of this event indicates that there are long latency 880operations in the pipe (possibly load and store operations that miss the L2 881cache, or instructions dependent upon instructions further down the pipeline 882that have yet to retire. 883When RS is full, new instructions can not enter the reservation station and 884start execution. 885.It Li RESOURCE_STALLS.STORE 886.Pq Event A2H , Umask 08H 887This event counts the number of cycles that a resource related stall will 888occur due to the number of store instructions reaching the limit of the 889pipeline, (i.e. all store buffers are used). 890The stall ends when a store instruction commits its data to the cache or memory. 891.It Li RESOURCE_STALLS.ROB_FULL 892.Pq Event A2H , Umask 10H 893Counts the cycles of stall due to re- order buffer full. 894.It Li RESOURCE_STALLS.FPCW 895.Pq Event A2H , Umask 20H 896Counts the number of cycles while execution was stalled due to writing the 897floating-point unit (FPU) control word. 898.It Li RESOURCE_STALLS.MXCSR 899.Pq Event A2H , Umask 40H 900Stalls due to the MXCSR register rename occurring to close to a previous 901MXCSR rename. 902The MXCSR provides control and status for the MMX registers. 903.It Li RESOURCE_STALLS.OTHER 904.Pq Event A2H , Umask 80H 905Counts the number of cycles while execution was stalled due to other 906resource issues. 907.It Li MACRO_INSTS.FUSIONS_DECODED 908.Pq Event A6H , Umask 01H 909Counts the number of instructions decoded that are macro-fused but not 910necessarily executed or retired. 911.It Li BACLEAR_FORCE_IQ 912.Pq Event A7H , Umask 01H 913Counts number of times a BACLEAR was forced by the Instruction Queue. 914The IQ is also responsible for providing conditional branch prediction direction 915based on a static scheme and dynamic data provided by the L2 Branch 916Prediction Unit. 917If the conditional branch target is not found in the Target Array and the IQ 918predicts that the branch is taken, then the IQ will force 919the Branch Address Calculator to issue a BACLEAR. 920Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble 921in the instruction fetch pipeline. 922.It Li LSD.UOPS 923.Pq Event A8H , Umask 01H 924Counts the number of micro-ops delivered by loop stream detector 925Use cmask=1 and invert to count cycles 926.It Li ITLB_FLUSH 927.Pq Event AEH , Umask 01H 928Counts the number of ITLB flushes 929.It Li OFFCORE_REQUESTS.L1D_WRITEBACK 930.Pq Event B0H , Umask 40H 931Counts number of L1D writebacks to the uncore. 932.It Li UOPS_EXECUTED.PORT0 933.Pq Event B1H , Umask 01H 934Counts number of Uops executed that were issued on port 0. 935Port 0 handles integer arithmetic, SIMD and FP add Uops. 936.It Li UOPS_EXECUTED.PORT1 937.Pq Event B1H , Umask 02H 938Counts number of Uops executed that were issued on port 1. 939Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. 940.It Li UOPS_EXECUTED.PORT2_CORE 941.Pq Event B1H , Umask 04H 942Counts number of Uops executed that were issued on port 2. 943Port 2 handles the load Uops. 944This is a core count only and can not be collected per thread. 945.It Li UOPS_EXECUTED.PORT3_CORE 946.Pq Event B1H , Umask 08H 947Counts number of Uops executed that were issued on port 3. 948Port 3 handles store Uops. 949This is a core count only and can not be collected per thread. 950.It Li UOPS_EXECUTED.PORT4_CORE 951.Pq Event B1H , Umask 10H 952Counts number of Uops executed that where issued on port 4. 953Port 4 handles the value to be stored for the store Uops issued on port 3. 954This is a core count only and can not be collected per thread. 955.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 956.Pq Event B1H , Umask 1FH 957Counts cycles when the Uops executed were issued from any ports except port 9585. 959Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, 960Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count 961P0-4 stalls. 962.It Li UOPS_EXECUTED.PORT5 963.Pq Event B1H , Umask 20H 964Counts number of Uops executed that where issued on port 5. 965.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES 966.Pq Event B1H , Umask 3FH 967Counts cycles when the Uops are executing. 968Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled 969cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. 970.It Li UOPS_EXECUTED.PORT015 971.Pq Event B1H , Umask 40H 972Counts number of Uops executed that where issued on port 0, 1, or 5. 973use cmask=1, invert=1 to count stall cycles 974.It Li UOPS_EXECUTED.PORT234 975.Pq Event B1H , Umask 80H 976Counts number of Uops executed that where issued on port 2, 3, or 4. 977.It Li OFFCORE_REQUESTS_SQ_FULL 978.Pq Event B2H , Umask 01H 979Counts number of cycles the SQ is full to handle off-core requests. 980.It Li OFF_CORE_RESPONSE_0 981.Pq Event B7H , Umask 01H 982see Section 30.6.1.3, Off-core Response Performance Monitoring in the 983Processor Core 984Requires programming MSR 01A6H 985.It Li SNOOP_RESPONSE.HIT 986.Pq Event B8H , Umask 01H 987Counts HIT snoop response sent by this thread in response to a snoop 988request. 989.It Li SNOOP_RESPONSE.HITE 990.Pq Event B8H , Umask 02H 991Counts HIT E snoop response sent by this thread in response to a snoop 992request. 993.It Li SNOOP_RESPONSE.HITM 994.Pq Event B8H , Umask 04H 995Counts HIT M snoop response sent by this thread in response to a snoop 996request. 997.It Li OFF_CORE_RESPONSE_1 998.Pq Event BBH , Umask 01H 999see Section 30.6.1.3, Off-core Response Performance Monitoring in the 1000Processor Core 1001Requires programming MSR 01A7H 1002.It Li INST_RETIRED.ANY_P 1003.Pq Event C0H , Umask 01H 1004See Table A-1 1005Notes: INST_RETIRED.ANY is counted by a designated fixed counter. 1006INST_RETIRED.ANY_P is counted by a programmable counter and is an 1007architectural performance event. 1008Event is supported if CPUID.A.EBX[1] = 0. 1009Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not 1010count as retired instructions. 1011.It Li INST_RETIRED.X87 1012.Pq Event C0H , Umask 02H 1013Counts the number of MMX instructions retired. 1014.It Li INST_RETIRED.MMX 1015.Pq Event C0H , Umask 04H 1016Counts the number of floating point computational operations retired: 1017floating point computational operations executed by the assist handler and 1018sub-operations of complex floating point instructions like transcendental 1019instructions. 1020.It Li UOPS_RETIRED.ANY 1021.Pq Event C2H , Umask 01H 1022Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, 1023others=1; maximum count of 8 per cycle). 1024Most instructions are composed of one or two micro-ops. 1025Some instructions are decoded into longer sequences such as repeat instructions, 1026floating point transcendental instructions, and assists. 1027Use cmask=1 and invert to count active cycles or stalled cycles 1028.It Li UOPS_RETIRED.RETIRE_SLOTS 1029.Pq Event C2H , Umask 02H 1030Counts the number of retirement slots used each cycle 1031.It Li UOPS_RETIRED.MACRO_FUSED 1032.Pq Event C2H , Umask 04H 1033Counts number of macro-fused uops retired. 1034.It Li MACHINE_CLEARS.CYCLES 1035.Pq Event C3H , Umask 01H 1036Counts the cycles machine clear is asserted. 1037.It Li MACHINE_CLEARS.MEM_ORDER 1038.Pq Event C3H , Umask 02H 1039Counts the number of machine clears due to memory order conflicts. 1040.It Li MACHINE_CLEARS.SMC 1041.Pq Event C3H , Umask 04H 1042Counts the number of times that a program writes to a code section. 1043Self-modifying code causes a sever penalty in all Intel 64 and IA-32 1044processors. 1045The modified cache line is written back to the L2 and L3caches. 1046.It Li BR_INST_RETIRED.ALL_BRANCHES 1047.Pq Event C4H , Umask 00H 1048See Table A-1 1049.It Li BR_INST_RETIRED.CONDITIONAL 1050.Pq Event C4H , Umask 01H 1051Counts the number of conditional branch instructions retired. 1052.It Li BR_INST_RETIRED.NEAR_CALL 1053.Pq Event C4H , Umask 02H 1054Counts the number of direct & indirect near unconditional calls retired 1055.It Li BR_INST_RETIRED.ALL_BRANCHES 1056.Pq Event C4H , Umask 04H 1057Counts the number of branch instructions retired 1058.It Li BR_MISP_RETIRED.ALL_BRANCHES 1059.Pq Event C5H , Umask 00H 1060See Table A-1 1061.It Li BR_MISP_RETIRED.NEAR_CALL 1062.Pq Event C5H , Umask 02H 1063Counts mispredicted direct & indirect near unconditional retired calls. 1064.It Li SSEX_UOPS_RETIRED.PACKED_SINGLE 1065.Pq Event C7H , Umask 01H 1066Counts SIMD packed single-precision floating point Uops retired. 1067.It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE 1068.Pq Event C7H , Umask 02H 1069Counts SIMD calar single-precision floating point Uops retired. 1070.It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE 1071.Pq Event C7H , Umask 04H 1072Counts SIMD packed double- precision floating point Uops retired. 1073.It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE 1074.Pq Event C7H , Umask 08H 1075Counts SIMD scalar double-precision floating point Uops retired. 1076.It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER 1077.Pq Event C7H , Umask 10H 1078Counts 128-bit SIMD vector integer Uops retired. 1079.It Li ITLB_MISS_RETIRED 1080.Pq Event C8H , Umask 20H 1081Counts the number of retired instructions that missed the ITLB when the 1082instruction was fetched. 1083.It Li MEM_LOAD_RETIRED.L1D_HIT 1084.Pq Event CBH , Umask 01H 1085Counts number of retired loads that hit the L1 data cache. 1086.It Li MEM_LOAD_RETIRED.L2_HIT 1087.Pq Event CBH , Umask 02H 1088Counts number of retired loads that hit the L2 data cache. 1089.It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT 1090.Pq Event CBH , Umask 04H 1091Counts number of retired loads that hit their own, unshared lines in the L3 1092cache. 1093.It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM 1094.Pq Event CBH , Umask 08H 1095Counts number of retired loads that hit in a sibling core's L2 (on die core). 1096Since the L3 is inclusive of all cores on the package, this is an L3 hit. 1097This counts both clean or modified hits. 1098.It Li MEM_LOAD_RETIRED.L3_MISS 1099.Pq Event CBH , Umask 10H 1100Counts number of retired loads that miss the L3 cache. 1101The load was satisfied by a remote socket, local memory or an IOH. 1102.It Li MEM_LOAD_RETIRED.HIT_LFB 1103.Pq Event CBH , Umask 40H 1104Counts number of retired loads that miss the L1D and the address is located 1105in an allocated line fill buffer and will soon be committed to cache. 1106This is counting secondary L1D misses. 1107.It Li MEM_LOAD_RETIRED.DTLB_MISS 1108.Pq Event CBH , Umask 80H 1109Counts the number of retired loads that missed the DTLB. 1110The DTLB miss is not counted if the load operation causes a fault. 1111This event counts loads from cacheable memory only. 1112The event does not count loads by software prefetches. 1113Counts both primary and secondary misses to the TLB. 1114.It Li FP_MMX_TRANS.TO_FP 1115.Pq Event CCH , Umask 01H 1116Counts the first floating-point instruction following any MMX instruction. 1117You can use this event to estimate the penalties for the transitions between 1118floating-point and MMX technology states. 1119.It Li FP_MMX_TRANS.TO_MMX 1120.Pq Event CCH , Umask 02H 1121Counts the first MMX instruction following a floating-point instruction. 1122You can use this event to estimate the penalties for the transitions between 1123floating-point and MMX technology states. 1124.It Li FP_MMX_TRANS.ANY 1125.Pq Event CCH , Umask 03H 1126Counts all transitions from floating point to MMX instructions and from MMX 1127instructions to floating point instructions. 1128You can use this event to estimate the penalties for the transitions between 1129floating-point and MMX technology states. 1130.It Li MACRO_INSTS.DECODED 1131.Pq Event D0H , Umask 01H 1132Counts the number of instructions decoded, (but not necessarily executed or 1133retired). 1134.It Li UOPS_DECODED.MS 1135.Pq Event D1H , Umask 02H 1136Counts the number of Uops decoded by the Microcode Sequencer, MS. 1137The MS delivers uops when the instruction is more than 4 uops long or a microcode 1138assist is occurring. 1139.It Li UOPS_DECODED.ESP_FOLDING 1140.Pq Event D1H , Umask 04H 1141Counts number of stack pointer (ESP) instructions decoded: push , pop , call 1142, ret, etc. 1143ESP instructions do not generate a Uop to increment or decrement ESP. 1144Instead, they update an ESP_Offset register that keeps track of the 1145delta to the current value of the ESP register. 1146.It Li UOPS_DECODED.ESP_SYNC 1147.Pq Event D1H , Umask 08H 1148Counts number of stack pointer (ESP) sync operations where an ESP 1149instruction is corrected by adding the ESP offset register to the current 1150value of the ESP register. 1151.It Li RAT_STALLS.FLAGS 1152.Pq Event D2H , Umask 01H 1153Counts the number of cycles during which execution stalled due to several 1154reasons, one of which is a partial flag register stall. 1155A partial register stall may occur when two conditions are met: 1) an instruction modifies 1156some, but not all, of the flags in the flag register and 2) the next 1157instruction, which depends on flags, depends on flags that were not modified 1158by this instruction. 1159.It Li RAT_STALLS.REGISTERS 1160.Pq Event D2H , Umask 02H 1161This event counts the number of cycles instruction execution latency became 1162longer than the defined latency because the instruction used a register that 1163was partially written by previous instruction. 1164.It Li RAT_STALLS.ROB_READ_PORT 1165.Pq Event D2H , Umask 04H 1166Counts the number of cycles when ROB read port stalls occurred, which did 1167not allow new micro-ops to enter the out-of-order pipeline. 1168Note that, at this stage in the pipeline, additional stalls may occur at 1169the same cycle and prevent the stalled micro-ops from entering the pipe. 1170In such a case, micro-ops retry entering the execution pipe in the next 1171cycle and the ROB-read port stall is counted again. 1172.It Li RAT_STALLS.SCOREBOARD 1173.Pq Event D2H , Umask 08H 1174Counts the cycles where we stall due to microarchitecturally required 1175serialization. 1176Microcode scoreboarding stalls. 1177.It Li RAT_STALLS.ANY 1178.Pq Event D2H , Umask 0FH 1179Counts all Register Allocation Table stall cycles due to: Cycles when ROB 1180read port stalls occurred, which did not allow new micro-ops to enter the 1181execution pipe. 1182Cycles when partial register stalls occurred Cycles when flag stalls occurred 1183Cycles floating-point unit (FPU) status word stalls occurred. 1184To count each of these conditions separately use the events: 1185RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and 1186RAT_STALLS.FPSW. 1187.It Li SEG_RENAME_STALLS 1188.Pq Event D4H , Umask 01H 1189Counts the number of stall cycles due to the lack of renaming resources for 1190the ES, DS, FS, and GS segment registers. 1191If a segment is renamed but not retired and a second update to the same 1192segment occurs, a stall occurs in the front-end of the pipeline until the 1193renamed segment retires. 1194.It Li ES_REG_RENAMES 1195.Pq Event D5H , Umask 01H 1196Counts the number of times the ES segment register is renamed. 1197.It Li UOP_UNFUSION 1198.Pq Event DBH , Umask 01H 1199Counts unfusion events due to floating point exception to a fused uop. 1200.It Li BR_INST_DECODED 1201.Pq Event E0H , Umask 01H 1202Counts the number of branch instructions decoded. 1203.It Li BPU_MISSED_CALL_RET 1204.Pq Event E5H , Umask 01H 1205Counts number of times the Branch Prediction Unit missed predicting a call 1206or return branch. 1207.It Li BACLEAR.CLEAR 1208.Pq Event E6H , Umask 01H 1209Counts the number of times the front end is resteered, mainly when the 1210Branch Prediction Unit cannot provide a correct prediction and this is 1211corrected by the Branch Address Calculator at the front end. 1212This can occur if the code has many branches such that they cannot be 1213consumed by the BPU. 1214Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble 1215in the instruction fetch pipeline. 1216The effect on total execution time depends on the surrounding code. 1217.It Li BACLEAR.BAD_TARGET 1218.Pq Event E6H , Umask 02H 1219Counts number of Branch Address Calculator clears (BACLEAR) asserted due to 1220conditional branch instructions in which there was a target hit but the 1221direction was wrong. 1222Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in 1223the instruction fetch pipeline. 1224.It Li BPU_CLEARS.EARLY 1225.Pq Event E8H , Umask 01H 1226Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken 1227branch after incorrectly assuming that it was not taken. 1228The BPU clear leads to 2 cycle bubble in the Front End. 1229.It Li BPU_CLEARS.LATE 1230.Pq Event E8H , Umask 02H 1231Counts late Branch Prediction Unit clears due to Most Recently Used conflicts. 1232The PBU clear leads to a 3 cycle bubble in the Front End. 1233.It Li L2_TRANSACTIONS.LOAD 1234.Pq Event F0H , Umask 01H 1235Counts L2 load operations due to HW prefetch or demand loads. 1236.It Li L2_TRANSACTIONS.RFO 1237.Pq Event F0H , Umask 02H 1238Counts L2 RFO operations due to HW prefetch or demand RFOs. 1239.It Li L2_TRANSACTIONS.IFETCH 1240.Pq Event F0H , Umask 04H 1241Counts L2 instruction fetch operations due to HW prefetch or demand ifetch. 1242.It Li L2_TRANSACTIONS.PREFETCH 1243.Pq Event F0H , Umask 08H 1244Counts L2 prefetch operations. 1245.It Li L2_TRANSACTIONS.L1D_WB 1246.Pq Event F0H , Umask 10H 1247Counts L1D writeback operations to the L2. 1248.It Li L2_TRANSACTIONS.FILL 1249.Pq Event F0H , Umask 20H 1250Counts L2 cache line fill operations due to load, RFO, L1D writeback or 1251prefetch. 1252.It Li L2_TRANSACTIONS.WB 1253.Pq Event F0H , Umask 40H 1254Counts L2 writeback operations to the L3. 1255.It Li L2_TRANSACTIONS.ANY 1256.Pq Event F0H , Umask 80H 1257Counts all L2 cache operations. 1258.It Li L2_LINES_IN.S_STATE 1259.Pq Event F1H , Umask 02H 1260Counts the number of cache lines allocated in the L2 cache in the S (shared) 1261state. 1262.It Li L2_LINES_IN.E_STATE 1263.Pq Event F1H , Umask 04H 1264Counts the number of cache lines allocated in the L2 cache in the E 1265(exclusive) state. 1266.It Li L2_LINES_IN.ANY 1267.Pq Event F1H , Umask 07H 1268Counts the number of cache lines allocated in the L2 cache. 1269.It Li L2_LINES_OUT.DEMAND_CLEAN 1270.Pq Event F2H , Umask 01H 1271Counts L2 clean cache lines evicted by a demand request. 1272.It Li L2_LINES_OUT.DEMAND_DIRTY 1273.Pq Event F2H , Umask 02H 1274Counts L2 dirty (modified) cache lines evicted by a demand request. 1275.It Li L2_LINES_OUT.PREFETCH_CLEAN 1276.Pq Event F2H , Umask 04H 1277Counts L2 clean cache line evicted by a prefetch request. 1278.It Li L2_LINES_OUT.PREFETCH_DIRTY 1279.Pq Event F2H , Umask 08H 1280Counts L2 modified cache line evicted by a prefetch request. 1281.It Li L2_LINES_OUT.ANY 1282.Pq Event F2H , Umask 0FH 1283Counts all L2 cache lines evicted for any reason. 1284.It Li SQ_MISC.SPLIT_LOCK 1285.Pq Event F4H , Umask 10H 1286Counts the number of SQ lock splits across a cache line. 1287.It Li SQ_FULL_STALL_CYCLES 1288.Pq Event F6H , Umask 01H 1289Counts cycles the Super Queue is full. 1290Neither of the threads on this core will be able to access the uncore. 1291.It Li FP_ASSIST.ALL 1292.Pq Event F7H , Umask 01H 1293Counts the number of floating point operations executed that required 1294micro-code assist intervention. 1295Assists are required in the following cases: 1296SSE instructions, (Denormal input when the DAZ flag is off or Underflow 1297result when the FTZ flag is off): x87 instructions, (NaN or denormal are 1298loaded to a register or used as input from memory, Division by 0 or 1299Underflow output). 1300.It Li FP_ASSIST.OUTPUT 1301.Pq Event F7H , Umask 02H 1302Counts number of floating point micro-code assist when the output value 1303(destination register) is invalid. 1304.It Li FP_ASSIST.INPUT 1305.Pq Event F7H , Umask 04H 1306Counts number of floating point micro-code assist when the input value (one 1307of the source operands to an FP instruction) is invalid. 1308.It Li SIMD_INT_64.PACKED_MPY 1309.Pq Event FDH , Umask 01H 1310Counts number of SID integer 64 bit packed multiply operations. 1311.It Li SIMD_INT_64.PACKED_SHIFT 1312.Pq Event FDH , Umask 02H 1313Counts number of SID integer 64 bit packed shift operations. 1314.It Li SIMD_INT_64.PACK 1315.Pq Event FDH , Umask 04H 1316Counts number of SID integer 64 bit pack operations. 1317.It Li SIMD_INT_64.UNPACK 1318.Pq Event FDH , Umask 08H 1319Counts number of SID integer 64 bit unpack operations. 1320.It Li SIMD_INT_64.PACKED_LOGICAL 1321.Pq Event FDH , Umask 10H 1322Counts number of SID integer 64 bit logical operations. 1323.It Li SIMD_INT_64.PACKED_ARITH 1324.Pq Event FDH , Umask 20H 1325Counts number of SID integer 64 bit arithmetic operations. 1326.It Li SIMD_INT_64.SHUFFLE_MOVE 1327.Pq Event FDH , Umask 40H 1328Counts number of SID integer 64 bit shift or move operations. 1329.El 1330.Ss Event Specifiers (Programmable PMCs) 1331Core i7 and Xeon 5500 programmable PMCs support the following events as 1332June 2009 document (removed in December 2009): 1333.Bl -tag -width indent 1334.It Li SB_FORWARD.ANY 1335.Pq Event 02H , Umask 01H 1336Counts the number of store forwards. 1337.It Li LOAD_BLOCK.STD 1338.Pq Event 03H , Umask 01H 1339Counts the number of loads blocked by a preceding store with unknown data. 1340.It Li LOAD_BLOCK.ADDRESS_OFFSET 1341.Pq Event 03H , Umask 04H 1342Counts the number of loads blocked by a preceding store address. 1343.It Li LOAD_BLOCK.ADDRESS_OFFSET 1344.Pq Event 01H , Umask 04H 1345Counts the cycles of store buffer drains. 1346.It Li MISALIGN_MEM_REF.LOAD 1347.Pq Event 05H , Umask 01H 1348Counts the number of misaligned load references 1349.It Li MISALIGN_MEM_REF.STORE 1350.Pq Event 05H , Umask 02H 1351Counts the number of misaligned store references 1352.It Li MISALIGN_MEM_REF.ANY 1353.Pq Event 05H , Umask 03H 1354Counts the number of misaligned memory references 1355.It Li STORE_BLOCKS.NOT_STA 1356.Pq Event 06H , Umask 01H 1357This event counts the number of load operations delayed caused by preceding 1358stores whose addresses are known but whose data is unknown, and preceding 1359stores that conflict with the load but which incompletely overlap the load. 1360.It Li STORE_BLOCKS.STA 1361.Pq Event 06H , Umask 02H 1362This event counts load operations delayed caused by preceding stores whose 1363addresses are unknown (STA block). 1364.It Li STORE_BLOCKS.ANY 1365.Pq Event 06H , Umask 0FH 1366All loads delayed due to store blocks 1367.It Li MEMORY_DISAMBIGURATION.RESET 1368.Pq Event 09H , Umask 01H 1369Counts memory disambiguration reset cycles 1370.It Li MEMORY_DISAMBIGURATION.SUCCESS 1371.Pq Event 09H , Umask 02H 1372Counts the number of loads that memory disambiguration succeeded 1373.It Li MEMORY_DISAMBIGURATION.WATCHDOG 1374.Pq Event 09H , Umask 04H 1375Counts the number of times the memory disambiguration watchdog kicked in. 1376.It Li MEMORY_DISAMBIGURATION.WATCH_CYCLES 1377.Pq Event 09H , Umask 08H 1378Counts the cycles that the memory disambiguration watchdog is active. 1379set invert=1, cmask = 1 1380.It Li HW_INT.RCV 1381.Pq Event 1DH , Umask 01H 1382Number of interrupt received 1383.It Li HW_INT.CYCLES_MASKED 1384.Pq Event 1DH , Umask 02H 1385Number of cycles interrupt are masked 1386.It Li HW_INT.CYCLES_PENDING_AND_MASKED 1387.Pq Event 1DH , Umask 04H 1388Number of cycles interrupts are pending and masked 1389.It Li HW_INT.CYCLES_PENDING_AND_MASKED 1390.Pq Event 04H , Umask 04H 1391Counts number of L2 store RFO requests where the cache line to be loaded is 1392in the E (exclusive) state. 1393The L1D prefetcher does not issue a RFO prefetch. 1394This is a demand RFO request 1395.It Li HW_INT.CYCLES_PENDING_AND_MASKED 1396.Pq Event 27H , Umask 04H 1397LONGEST_LAT_CACH E.MISS 1398.It Li UOPS_DECODED.DEC0 1399.Pq Event 3DH , Umask 01H 1400Counts micro-ops decoded by decoder 0. 1401.It Li UOPS_DECODED.DEC0 1402.Pq Event 01H , Umask 01H 1403Counts L1 data cache store RFO requests where the cache line to be loaded is 1404in the I state. 1405Counter 0, 1 only 1406.It Li 0FH 1407.Pq Event 41H , Umask 41H 1408L1D_CACHE_ST.MESI 1409Counts L1 data cache store RFO requests. 1410Counter 0, 1 only 1411.It Li DTLB_MISSES.PDE_MISS 1412.Pq Event 49H , Umask 20H 1413Number of DTLB cache misses where the low part of the linear to physical 1414address translation was missed. 1415.It Li DTLB_MISSES.PDP_MISS 1416.Pq Event 49H , Umask 40H 1417Number of DTLB misses where the high part of the linear to physical address 1418translation was missed. 1419.It Li DTLB_MISSES.LARGE_WALK_COMPLETED 1420.Pq Event 49H , Umask 80H 1421Counts number of completed large page walks due to misses in the STLB. 1422.It Li SSE_MEM_EXEC.NTA 1423.Pq Event 4BH , Umask 01H 1424Counts number of SSE NTA prefetch/weakly-ordered instructions which missed 1425the L1 data cache. 1426.It Li SSE_MEM_EXEC.STREAMING_STORES 1427.Pq Event 4BH , Umask 08H 1428Counts number of SSE non temporal stores 1429.It Li SFENCE_CYCLES 1430.Pq Event 4DH , Umask 01H 1431Counts store fence cycles 1432.It Li EPT.EPDE_MISS 1433.Pq Event 4FH , Umask 02H 1434Counts Extended Page Directory Entry misses. 1435The Extended Page Directory cache is used by Virtual Machine operating 1436systems while the guest operating systems use the standard TLB caches. 1437.It Li EPT.EPDPE_HIT 1438.Pq Event 4FH , Umask 04H 1439Counts Extended Page Directory Pointer Entry hits. 1440.It Li EPT.EPDPE_MISS 1441.Pq Event 4FH , Umask 08H 1442Counts Extended Page Directory Pointer Entry misses. 1443.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA 1444.Pq Event 60H , Umask 01H 1445Counts weighted cycles of offcore demand data read requests. 1446Does not include L2 prefetch requests. 1447counter 0 1448.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE 1449.Pq Event 60H , Umask 02H 1450Counts weighted cycles of offcore demand code read requests. 1451Does not include L2 prefetch requests. 1452counter 0 1453.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO 1454.Pq Event 60H , Umask 04H 1455Counts weighted cycles of offcore demand RFO requests. 1456Does not include L2 prefetch requests. 1457counter 0 1458.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ 1459.Pq Event 60H , Umask 08H 1460Counts weighted cycles of offcore read requests of any kind. 1461Include L2 prefetch requests. 1462counter 0 1463.It Li IFU_IVC.FULL 1464.Pq Event 81H , Umask 01H 1465Instruction Fetche unit victim cache full. 1466.It Li IFU_IVC.L1I_EVICTION 1467.Pq Event 81H , Umask 02H 1468L1 Instruction cache evictions. 1469.It Li L1I_OPPORTUNISTIC_HITS 1470.Pq Event 83H , Umask 01H 1471Opportunistic hits in streaming. 1472.It Li ITLB_MISSES.WALK_CYCLES 1473.Pq Event 85H , Umask 04H 1474Counts ITLB miss page walk cycles. 1475.It Li ITLB_MISSES.PMH_BUSY_CYCLES 1476.Pq Event 85H , Umask 04H 1477Counts PMH busy cycles. 1478.It Li ITLB_MISSES.STLB_HIT 1479.Pq Event 85H , Umask 10H 1480Counts the number of ITLB misses that hit in the second level TLB. 1481.It Li ITLB_MISSES.PDE_MISS 1482.Pq Event 85H , Umask 20H 1483Number of ITLB misses where the low part of the linear to physical address 1484translation was missed. 1485.It Li ITLB_MISSES.PDP_MISS 1486.Pq Event 85H , Umask 40H 1487Number of ITLB misses where the high part of the linear to physical address 1488translation was missed. 1489.It Li ITLB_MISSES.LARGE_WALK_COMPLETED 1490.Pq Event 85H , Umask 80H 1491Counts number of completed large page walks due to misses in the STLB. 1492.It Li ITLB_MISSES.LARGE_WALK_COMPLETED 1493.Pq Event 01H , Umask 80H 1494Counts number of offcore demand data read requests. 1495Does not count L2 prefetch requests. 1496.It Li OFFCORE_REQUESTS.DEMAND.READ_CODE 1497.Pq Event B0H , Umask 02H 1498Counts number of offcore demand code read requests. 1499Does not count L2 prefetch requests. 1500.It Li OFFCORE_REQUESTS.DEMAND.RFO 1501.Pq Event B0H , Umask 04H 1502Counts number of offcore demand RFO requests. 1503Does not count L2 prefetch requests. 1504.It Li OFFCORE_REQUESTS.ANY.READ 1505.Pq Event B0H , Umask 08H 1506Counts number of offcore read requests. 1507Includes L2 prefetch requests. 1508.It Li OFFCORE_REQUESTS.ANY.RFO 1509.Pq Event B0H , Umask 10H 1510Counts number of offcore RFO requests. 1511Includes L2 prefetch requests. 1512.It Li OFFCORE_REQUESTS.UNCACHED_MEM 1513.Pq Event B0H , Umask 20H 1514Counts number of offcore uncached memory requests. 1515.It Li OFFCORE_REQUESTS.ANY 1516.Pq Event B0H , Umask 80H 1517Counts all offcore requests. 1518.It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA 1519.Pq Event B3H , Umask 01H 1520Counts weighted cycles of snoopq requests for data. 1521Counter 0 only Use cmask=1 to count cycles not empty. 1522.It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE 1523.Pq Event B3H , Umask 02H 1524Counts weighted cycles of snoopq invalidate requests. 1525Counter 0 only Use cmask=1 to count cycles not empty. 1526.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE 1527.Pq Event B3H , Umask 04H 1528Counts weighted cycles of snoopq requests for code. 1529Counter 0 only Use cmask=1 to count cycles not empty. 1530.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE 1531.Pq Event BAH , Umask 04H 1532Counts number of TPR reads 1533.It Li PIC_ACCESSES.TPR_WRITES 1534.Pq Event BAH , Umask 02H 1535Counts number of TPR writes one or two micro-ops. 1536Some instructions are decoded into longer sequences 1537.It Li MACHINE_CLEARS.FUSION_ASSIST 1538.Pq Event C3H , Umask 10H 1539Counts the number of macro-fusion assists 1540Counts SIMD packed single- precision floating point Uops retired. 1541.It Li BOGUS_BR 1542.Pq Event E4H , Umask 01H 1543Counts the number of bogus branches. 1544.It Li L2_HW_PREFETCH.HIT 1545.Pq Event F3H , Umask 01H 1546Count L2 HW prefetcher detector hits 1547.It Li L2_HW_PREFETCH.ALLOC 1548.Pq Event F3H , Umask 02H 1549Count L2 HW prefetcher allocations 1550.It Li L2_HW_PREFETCH.DATA_TRIGGER 1551.Pq Event F3H , Umask 04H 1552Count L2 HW data prefetcher triggered 1553.It Li L2_HW_PREFETCH.CODE_TRIGGER 1554.Pq Event F3H , Umask 08H 1555Count L2 HW code prefetcher triggered 1556.It Li L2_HW_PREFETCH.DCA_TRIGGER 1557.Pq Event F3H , Umask 10H 1558Count L2 HW DCA prefetcher triggered 1559.It Li L2_HW_PREFETCH.KICK_START 1560.Pq Event F3H , Umask 20H 1561Count L2 HW prefetcher kick started 1562.It Li SQ_MISC.PROMOTION 1563.Pq Event F4H , Umask 01H 1564Counts the number of L2 secondary misses that hit the Super Queue. 1565.It Li SQ_MISC.PROMOTION_POST_GO 1566.Pq Event F4H , Umask 02H 1567Counts the number of L2 secondary misses during the Super Queue filling L2. 1568.It Li SQ_MISC.LRU_HINTS 1569.Pq Event F4H , Umask 04H 1570Counts number of Super Queue LRU hints sent to L3. 1571.It Li SQ_MISC.FILL_DROPPED 1572.Pq Event F4H , Umask 08H 1573Counts the number of SQ L2 fills dropped due to L2 busy. 1574.It Li SEGMENT_REG_LOADS 1575.Pq Event F8H , Umask 01H 1576Counts number of segment register loads. 1577.El 1578.Sh SEE ALSO 1579.Xr pmc 3 , 1580.Xr pmc.atom 3 , 1581.Xr pmc.core 3 , 1582.Xr pmc.corei7uc 3 , 1583.Xr pmc.iaf 3 , 1584.Xr pmc.k7 3 , 1585.Xr pmc.k8 3 , 1586.Xr pmc.soft 3 , 1587.Xr pmc.tsc 3 , 1588.Xr pmc.ucf 3 , 1589.Xr pmc.westmere 3 , 1590.Xr pmc.westmereuc 3 , 1591.Xr pmc_cpuinfo 3 , 1592.Xr pmclog 3 , 1593.Xr hwpmc 4 1594.Sh HISTORY 1595The 1596.Nm pmc 1597library first appeared in 1598.Fx 6.0 . 1599.Sh AUTHORS 1600The 1601.Lb libpmc 1602library was written by 1603.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1604