1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" This software is provided by Joseph Koshy ``as is'' and 13.\" any express or implied warranties, including, but not limited to, the 14.\" implied warranties of merchantability and fitness for a particular purpose 15.\" are disclaimed. in no event shall Joseph Koshy be liable 16.\" for any direct, indirect, incidental, special, exemplary, or consequential 17.\" damages (including, but not limited to, procurement of substitute goods 18.\" or services; loss of use, data, or profits; or business interruption) 19.\" however caused and on any theory of liability, whether in contract, strict 20.\" liability, or tort (including negligence or otherwise) arising in any way 21.\" out of the use of this software, even if advised of the possibility of 22.\" such damage. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 24, 2010 27.Dt PMC.COREI7 3 28.Os 29.Sh NAME 30.Nm pmc.corei7 31.Nd measurement events for 32.Tn Intel 33.Tn Core i7 and Xeon 5500 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core i7" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs may contain up to three classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Core i7 and Xeon 5500 PMCs are documented in 59.Rs 60.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 61.%T "Volume 3B: System Programming Guide, Part 2" 62.%N "Order Number: 253669-033US" 63.%D December 2009 64.%Q "Intel Corporation" 65.Re 66.Ss COREI7 AND XEON 5500 FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69Not all CPUs in this family implement fixed-function counters. 70.Ss COREI7 AND XEON 5500 PROGRAMMABLE PMCS 71The programmable PMCs support the following capabilities: 72.Bl -column "PMC_CAP_INTERRUPT" "Support" 73.It Em Capability Ta Em Support 74.It PMC_CAP_CASCADE Ta \&No 75.It PMC_CAP_EDGE Ta Yes 76.It PMC_CAP_INTERRUPT Ta Yes 77.It PMC_CAP_INVERT Ta Yes 78.It PMC_CAP_READ Ta Yes 79.It PMC_CAP_PRECISE Ta \&No 80.It PMC_CAP_SYSTEM Ta Yes 81.It PMC_CAP_TAGGING Ta \&No 82.It PMC_CAP_THRESHOLD Ta Yes 83.It PMC_CAP_USER Ta Yes 84.It PMC_CAP_WRITE Ta Yes 85.El 86.Ss Event Qualifiers 87Event specifiers for these PMCs support the following common 88qualifiers: 89.Bl -tag -width indent 90.It Li rsp= Ns Ar value 91Configure the Off-core Response bits. 92.Bl -tag -width indent 93.It Li DMND_DATA_RD 94Counts the number of demand and DCU prefetch data reads of full 95and partial cachelines as well as demand data page table entry 96cacheline reads. Does not count L2 data read prefetches or 97instruction fetches. 98.It Li DMND_RFO 99Counts the number of demand and DCU prefetch reads for ownership 100(RFO) requests generated by a write to data cacheline. Does not 101count L2 RFO. 102.It Li DMND_IFETCH 103Counts the number of demand and DCU prefetch instruction cacheline 104reads. Does not count L2 code read prefetches. 105WB 106Counts the number of writeback (modified to exclusive) transactions. 107.It Li PF_DATA_RD 108Counts the number of data cacheline reads generated by L2 prefetchers. 109.It Li PF_RFO 110Counts the number of RFO requests generated by L2 prefetchers. 111.It Li PF_IFETCH 112Counts the number of code reads generated by L2 prefetchers. 113.It Li OTHER 114Counts one of the following transaction types, including L3 invalidate, 115I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, 116lock, unlock, split lock. 117.It Li UNCORE_HIT 118L3 Hit: local or remote home requests that hit L3 cache in the uncore 119with no coherency actions required (snooping). 120.It Li OTHER_CORE_HIT_SNP 121L3 Hit: local or remote home requests that hit L3 cache in the uncore 122and was serviced by another core with a cross core snoop where no modified 123copies were found (clean). 124.It Li OTHER_CORE_HITM 125L3 Hit: local or remote home requests that hit L3 cache in the uncore 126and was serviced by another core with a cross core snoop where modified 127copies were found (HITM). 128.It Li REMOTE_CACHE_FWD 129L3 Miss: local homed requests that missed the L3 cache and was serviced 130by forwarded data following a cross package snoop where no modified 131copies found. (Remote home requests are not counted) 132.It Li REMOTE_DRAM 133L3 Miss: remote home requests that missed the L3 cache and were serviced 134by remote DRAM. 135.It Li LOCAL_DRAM 136L3 Miss: local home requests that missed the L3 cache and were serviced 137by local DRAM. 138.It Li NON_DRAM 139Non-DRAM requests that were serviced by IOH. 140.El 141.It Li cmask= Ns Ar value 142Configure the PMC to increment only if the number of configured 143events measured in a cycle is greater than or equal to 144.Ar value . 145.It Li edge 146Configure the PMC to count the number of de-asserted to asserted 147transitions of the conditions expressed by the other qualifiers. 148If specified, the counter will increment only once whenever a 149condition becomes true, irrespective of the number of clocks during 150which the condition remains true. 151.It Li inv 152Invert the sense of comparison when the 153.Dq Li cmask 154qualifier is present, making the counter increment when the number of 155events per cycle is less than the value specified by the 156.Dq Li cmask 157qualifier. 158.It Li os 159Configure the PMC to count events happening at processor privilege 160level 0. 161.It Li usr 162Configure the PMC to count events occurring at privilege levels 1, 2 163or 3. 164.El 165.Pp 166If neither of the 167.Dq Li os 168or 169.Dq Li usr 170qualifiers are specified, the default is to enable both. 171.Ss Event Specifiers (Programmable PMCs) 172Core i7 and Xeon 5500 programmable PMCs support the following events: 173.Bl -tag -width indent 174.It Li SB_DRAIN.ANY 175.Pq Event 04H , Umask 07H 176Counts the number of store buffer drains. 177.It Li STORE_BLOCKS.AT_RET 178.Pq Event 06H , Umask 04H 179Counts number of loads delayed with at-Retirement block code. The following 180loads need to be executed at retirement and wait for all senior stores on 181the same thread to be drained: load splitting across 4K boundary (page 182split), load accessing uncacheable (UC or USWC) memory, load lock, and load 183with page table in UC or USWC memory region. 184.It Li STORE_BLOCKS.L1D_BLOCK 185.Pq Event 06H , Umask 08H 186Cacheable loads delayed with L1D block code 187.It Li PARTIAL_ADDRESS_ALIAS 188.Pq Event 07H , Umask 01H 189Counts false dependency due to partial address aliasing 190.It Li DTLB_LOAD_MISSES.ANY 191.Pq Event 08H , Umask 01H 192Counts all load misses that cause a page walk 193.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 194.Pq Event 08H , Umask 02H 195Counts number of completed page walks due to load miss in the STLB. 196.It Li DTLB_LOAD_MISSES.STLB_HIT 197.Pq Event 08H , Umask 10H 198Number of cache load STLB hits 199.It Li DTLB_LOAD_MISSES.PDE_MISS 200.Pq Event 08H , Umask 20H 201Number of DTLB cache load misses where the low part of the linear to 202physical address translation was missed. 203.It Li DTLB_LOAD_MISSES.PDP_MISS 204.Pq Event 08H , Umask 40H 205Number of DTLB cache load misses where the high part of the linear to 206physical address translation was missed. 207.It Li DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED 208.Pq Event 08H , Umask 80H 209Counts number of completed large page walks due to load miss in the STLB. 210.It Li MEM_INST_RETIRED.LOADS 211.Pq Event 0BH , Umask 01H 212Counts the number of instructions with an architecturally-visible store 213retired on the architected path. 214In conjunction with ld_lat facility 215.It Li MEM_INST_RETIRED.STORES 216.Pq Event 0BH , Umask 02H 217Counts the number of instructions with an architecturally-visible store 218retired on the architected path. 219In conjunction with ld_lat facility 220.It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD 221.Pq Event 0BH , Umask 10H 222Counts the number of instructions exceeding the latency specified with 223ld_lat facility. 224In conjunction with ld_lat facility 225.It Li MEM_STORE_RETIRED.DTLB_MISS 226.Pq Event 0CH , Umask 01H 227The event counts the number of retired stores that missed the DTLB. The DTLB 228miss is not counted if the store operation causes a fault. Does not counter 229prefetches. Counts both primary and secondary misses to the TLB 230.It Li UOPS_ISSUED.ANY 231.Pq Event 0EH , Umask 01H 232Counts the number of Uops issued by the Register Allocation Table to the 233Reservation Station, i.e. the UOPs issued from the front end to the back 234end. 235.It Li UOPS_ISSUED.STALLED_CYCLES 236.Pq Event 0EH , Umask 01H 237Counts the number of cycles no Uops issued by the Register Allocation Table 238to the Reservation Station, i.e. the UOPs issued from the front end to the 239back end. 240set invert=1, cmask = 1 241.It Li UOPS_ISSUED.FUSED 242.Pq Event 0EH , Umask 02H 243Counts the number of fused Uops that were issued from the Register 244Allocation Table to the Reservation Station. 245.It Li MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN 246.Pq Event 0FH , Umask 01H 247Counts number of memory load instructions retired where the memory reference 248missed L3 and data source is unknown. 249Available only for CPUID signature 06_2EH 250.It Li MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM 251.Pq Event 0FH , Umask 02H 252Counts number of memory load instructions retired where the memory reference 253hit modified data in a sibling core residing on the same socket. 254.It Li MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT 255.Pq Event 0FH , Umask 08H 256Counts number of memory load instructions retired where the memory reference 257missed the L1, L2 and L3 caches and HIT in a remote socket's cache. Only 258counts locally homed lines. 259.It Li MEM_UNCORE_RETIRED.REMOTE_DRAM 260.Pq Event 0FH , Umask 10H 261Counts number of memory load instructions retired where the memory reference 262missed the L1, L2 and L3 caches and was remotely homed. This includes both 263DRAM access and HITM in a remote socket's cache for remotely homed lines. 264.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM 265.Pq Event 0FH , Umask 20H 266Counts number of memory load instructions retired where the memory reference 267missed the L1, L2 and L3 caches and required a local socket memory 268reference. This includes locally homed cachelines that were in a modified 269state in another socket. 270.It Li MEM_UNCORE_RETIRED.UNCACHEABLE 271.Pq Event 0FH , Umask 80H 272Counts number of memory load instructions retired where the memory reference 273missed the L1, L2 and L3 caches and to perform I/O. 274Available only for CPUID signature 06_2EH 275.It Li FP_COMP_OPS_EXE.X87 276.Pq Event 10H , Umask 01H 277Counts the number of FP Computational Uops Executed. The number of FADD, 278FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer 279DIVs, and IDIVs. This event does not distinguish an FADD used in the middle 280of a transcendental flow from a separate FADD instruction. 281.It Li FP_COMP_OPS_EXE.MMX 282.Pq Event 10H , Umask 02H 283Counts number of MMX Uops executed. 284.It Li FP_COMP_OPS_EXE.SSE_FP 285.Pq Event 10H , Umask 04H 286Counts number of SSE and SSE2 FP uops executed. 287.It Li FP_COMP_OPS_EXE.SSE2_INTEGER 288.Pq Event 10H , Umask 08H 289Counts number of SSE2 integer uops executed. 290.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED 291.Pq Event 10H , Umask 10H 292Counts number of SSE FP packed uops executed. 293.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR 294.Pq Event 10H , Umask 20H 295Counts number of SSE FP scalar uops executed. 296.It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION 297.Pq Event 10H , Umask 40H 298Counts number of SSE* FP single precision uops executed. 299.It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION 300.Pq Event 10H , Umask 80H 301Counts number of SSE* FP double precision uops executed. 302.It Li SIMD_INT_128.PACKED_MPY 303.Pq Event 12H , Umask 01H 304Counts number of 128 bit SIMD integer multiply operations. 305.It Li SIMD_INT_128.PACKED_SHIFT 306.Pq Event 12H , Umask 02H 307Counts number of 128 bit SIMD integer shift operations. 308.It Li SIMD_INT_128.PACK 309.Pq Event 12H , Umask 04H 310Counts number of 128 bit SIMD integer pack operations. 311.It Li SIMD_INT_128.UNPACK 312.Pq Event 12H , Umask 08H 313Counts number of 128 bit SIMD integer unpack operations. 314.It Li SIMD_INT_128.PACKED_LOGICAL 315.Pq Event 12H , Umask 10H 316Counts number of 128 bit SIMD integer logical operations. 317.It Li SIMD_INT_128.PACKED_ARITH 318.Pq Event 12H , Umask 20H 319Counts number of 128 bit SIMD integer arithmetic operations. 320.It Li SIMD_INT_128.SHUFFLE_MOVE 321.Pq Event 12H , Umask 40H 322Counts number of 128 bit SIMD integer shuffle and move operations. 323.It Li LOAD_DISPATCH.RS 324.Pq Event 13H , Umask 01H 325Counts number of loads dispatched from the Reservation Station that bypass 326the Memory Order Buffer. 327.It Li LOAD_DISPATCH.RS_DELAYED 328.Pq Event 13H , Umask 02H 329Counts the number of delayed RS dispatches at the stage latch. If an RS 330dispatch can not bypass to LB, it has another chance to dispatch from the 331one-cycle delayed staging latch before it is written into the LB. 332.It Li LOAD_DISPATCH.MOB 333.Pq Event 13H , Umask 04H 334Counts the number of loads dispatched from the Reservation Station to the 335Memory Order Buffer. 336.It Li LOAD_DISPATCH.ANY 337.Pq Event 13H , Umask 07H 338Counts all loads dispatched from the Reservation Station. 339.It Li ARITH.CYCLES_DIV_BUSY 340.Pq Event 14H , Umask 01H 341Counts the number of cycles the divider is busy executing divide or square 342root operations. The divide can be integer, X87 or Streaming SIMD Extensions 343(SSE). The square root operation can be either X87 or SSE. 344Set 'edge =1, invert=1, cmask=1' to count the number of divides. 345Count may be incorrect When SMT is on. 346.It Li ARITH.MUL 347.Pq Event 14H , Umask 02H 348Counts the number of multiply operations executed. This includes integer as 349well as floating point multiply operations but excludes DPPS mul and MPSAD. 350Count may be incorrect When SMT is on 351.It Li INST_QUEUE_WRITES 352.Pq Event 17H , Umask 01H 353Counts the number of instructions written into the instruction queue every 354cycle. 355.It Li INST_DECODED.DEC0 356.Pq Event 18H , Umask 01H 357Counts number of instructions that require decoder 0 to be decoded. Usually, 358this means that the instruction maps to more than 1 uop 359.It Li TWO_UOP_INSTS_DECODED 360.Pq Event 19H , Umask 01H 361An instruction that generates two uops was decoded 362.It Li INST_QUEUE_WRITE_CYCLES 363.Pq Event 1EH , Umask 01H 364This event counts the number of cycles during which instructions are written 365to the instruction queue. Dividing this counter by the number of 366instructions written to the instruction queue (INST_QUEUE_WRITES) yields the 367average number of instructions decoded each cycle. If this number is less 368than four and the pipe stalls, this indicates that the decoder is failing to 369decode enough instructions per cycle to sustain the 4-wide pipeline. 370If SSE* instructions that are 6 bytes or longer arrive one after another, 371then front end throughput may limit execution speed. In such case, 372.It Li LSD_OVERFLOW 373.Pq Event 20H , Umask 01H 374Counts number of loops that cant stream from the instruction queue. 375.It Li L2_RQSTS.LD_HIT 376.Pq Event 24H , Umask 01H 377Counts number of loads that hit the L2 cache. L2 loads include both L1D 378demand misses as well as L1D prefetches. L2 loads can be rejected for 379various reasons. Only non rejected loads are counted. 380.It Li L2_RQSTS.LD_MISS 381.Pq Event 24H , Umask 02H 382Counts the number of loads that miss the L2 cache. L2 loads include both L1D 383demand misses as well as L1D prefetches. 384.It Li L2_RQSTS.LOADS 385.Pq Event 24H , Umask 03H 386Counts all L2 load requests. L2 loads include both L1D demand misses as well 387as L1D prefetches. 388.It Li L2_RQSTS.RFO_HIT 389.Pq Event 24H , Umask 04H 390Counts the number of store RFO requests that hit the L2 cache. L2 RFO 391requests include both L1D demand RFO misses as well as L1D RFO prefetches. 392Count includes WC memory requests, where the data is not fetched but the 393permission to write the line is required. 394.It Li L2_RQSTS.RFO_MISS 395.Pq Event 24H , Umask 08H 396Counts the number of store RFO requests that miss the L2 cache. L2 RFO 397requests include both L1D demand RFO misses as well as L1D RFO prefetches. 398.It Li L2_RQSTS.RFOS 399.Pq Event 24H , Umask 0CH 400Counts all L2 store RFO requests. L2 RFO requests include both L1D demand 401RFO misses as well as L1D RFO prefetches. 402.It Li L2_RQSTS.IFETCH_HIT 403.Pq Event 24H , Umask 10H 404Counts number of instruction fetches that hit the L2 cache. L2 instruction 405fetches include both L1I demand misses as well as L1I instruction 406prefetches. 407.It Li L2_RQSTS.IFETCH_MISS 408.Pq Event 24H , Umask 20H 409Counts number of instruction fetches that miss the L2 cache. L2 instruction 410fetches include both L1I demand misses as well as L1I instruction 411prefetches. 412.It Li L2_RQSTS.IFETCHES 413.Pq Event 24H , Umask 30H 414Counts all instruction fetches. L2 instruction fetches include both L1I 415demand misses as well as L1I instruction prefetches. 416.It Li L2_RQSTS.PREFETCH_HIT 417.Pq Event 24H , Umask 40H 418Counts L2 prefetch hits for both code and data. 419.It Li L2_RQSTS.PREFETCH_MISS 420.Pq Event 24H , Umask 80H 421Counts L2 prefetch misses for both code and data. 422.It Li L2_RQSTS.PREFETCHES 423.Pq Event 24H , Umask C0H 424Counts all L2 prefetches for both code and data. 425.It Li L2_RQSTS.MISS 426.Pq Event 24H , Umask AAH 427Counts all L2 misses for both code and data. 428.It Li L2_RQSTS.REFERENCES 429.Pq Event 24H , Umask FFH 430Counts all L2 requests for both code and data. 431.It Li L2_DATA_RQSTS.DEMAND.I_STATE 432.Pq Event 26H , Umask 01H 433Counts number of L2 data demand loads where the cache line to be loaded is 434in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D 435demand misses and L1D prefetches. 436.It Li L2_DATA_RQSTS.DEMAND.S_STATE 437.Pq Event 26H , Umask 02H 438Counts number of L2 data demand loads where the cache line to be loaded is 439in the S (shared) state. L2 demand loads are both L1D demand misses and L1D 440prefetches. 441.It Li L2_DATA_RQSTS.DEMAND.E_STATE 442.Pq Event 26H , Umask 04H 443Counts number of L2 data demand loads where the cache line to be loaded is 444in the E (exclusive) state. L2 demand loads are both L1D demand misses and 445L1D prefetches. 446.It Li L2_DATA_RQSTS.DEMAND.M_STATE 447.Pq Event 26H , Umask 08H 448Counts number of L2 data demand loads where the cache line to be loaded is 449in the M (modified) state. L2 demand loads are both L1D demand misses and 450L1D prefetches. 451.It Li L2_DATA_RQSTS.DEMAND.MESI 452.Pq Event 26H , Umask 0FH 453Counts all L2 data demand requests. L2 demand loads are both L1D demand 454misses and L1D prefetches. 455.It Li L2_DATA_RQSTS.PREFETCH.I_STATE 456.Pq Event 26H , Umask 10H 457Counts number of L2 prefetch data loads where the cache line to be loaded is 458in the I (invalid) state, i.e. a cache miss. 459.It Li L2_DATA_RQSTS.PREFETCH.S_STATE 460.Pq Event 26H , Umask 20H 461Counts number of L2 prefetch data loads where the cache line to be loaded is 462in the S (shared) state. A prefetch RFO will miss on an S state line, while 463a prefetch read will hit on an S state line. 464.It Li L2_DATA_RQSTS.PREFETCH.E_STATE 465.Pq Event 26H , Umask 40H 466Counts number of L2 prefetch data loads where the cache line to be loaded is 467in the E (exclusive) state. 468.It Li L2_DATA_RQSTS.PREFETCH.M_STATE 469.Pq Event 26H , Umask 80H 470Counts number of L2 prefetch data loads where the cache line to be loaded is 471in the M (modified) state. 472.It Li L2_DATA_RQSTS.PREFETCH.MESI 473.Pq Event 26H , Umask F0H 474Counts all L2 prefetch requests. 475.It Li L2_DATA_RQSTS.ANY 476.Pq Event 26H , Umask FFH 477Counts all L2 data requests. 478.It Li L2_WRITE.RFO.I_STATE 479.Pq Event 27H , Umask 01H 480Counts number of L2 demand store RFO requests where the cache line to be 481loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher 482does not issue a RFO prefetch. 483This is a demand RFO request 484.It Li L2_WRITE.RFO.S_STATE 485.Pq Event 27H , Umask 02H 486Counts number of L2 store RFO requests where the cache line to be loaded is 487in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch,. 488This is a demand RFO request 489.It Li L2_WRITE.RFO.M_STATE 490.Pq Event 27H , Umask 08H 491Counts number of L2 store RFO requests where the cache line to be loaded is 492in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch. 493This is a demand RFO request 494.It Li L2_WRITE.RFO.HIT 495.Pq Event 27H , Umask 0EH 496Counts number of L2 store RFO requests where the cache line to be loaded is 497in either the S, E or M states. The L1D prefetcher does not issue a RFO 498prefetch. 499This is a demand RFO request 500.It Li L2_WRITE.RFO.MESI 501.Pq Event 27H , Umask 0FH 502Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO 503prefetch. 504This is a demand RFO request 505.It Li L2_WRITE.LOCK.I_STATE 506.Pq Event 27H , Umask 10H 507Counts number of L2 demand lock RFO requests where the cache line to be 508loaded is in the I (invalid) state, i.e. a cache miss. 509.It Li L2_WRITE.LOCK.S_STATE 510.Pq Event 27H , Umask 20H 511Counts number of L2 lock RFO requests where the cache line to be loaded is 512in the S (shared) state. 513.It Li L2_WRITE.LOCK.E_STATE 514.Pq Event 27H , Umask 40H 515Counts number of L2 demand lock RFO requests where the cache line to be 516loaded is in the E (exclusive) state. 517.It Li L2_WRITE.LOCK.M_STATE 518.Pq Event 27H , Umask 80H 519Counts number of L2 demand lock RFO requests where the cache line to be 520loaded is in the M (modified) state. 521.It Li L2_WRITE.LOCK.HIT 522.Pq Event 27H , Umask E0H 523Counts number of L2 demand lock RFO requests where the cache line to be 524loaded is in either the S, E, or M state. 525.It Li L2_WRITE.LOCK.MESI 526.Pq Event 27H , Umask F0H 527Counts all L2 demand lock RFO requests. 528.It Li L1D_WB_L2.I_STATE 529.Pq Event 28H , Umask 01H 530Counts number of L1 writebacks to the L2 where the cache line to be written 531is in the I (invalid) state, i.e. a cache miss. 532.It Li L1D_WB_L2.S_STATE 533.Pq Event 28H , Umask 02H 534Counts number of L1 writebacks to the L2 where the cache line to be written 535is in the S state. 536.It Li L1D_WB_L2.E_STATE 537.Pq Event 28H , Umask 04H 538Counts number of L1 writebacks to the L2 where the cache line to be written 539is in the E (exclusive) state. 540.It Li L1D_WB_L2.M_STATE 541.Pq Event 28H , Umask 08H 542Counts number of L1 writebacks to the L2 where the cache line to be written 543is in the M (modified) state. 544.It Li L1D_WB_L2.MESI 545.Pq Event 28H , Umask 0FH 546Counts all L1 writebacks to the L2. 547.It Li L3_LAT_CACHE.REFERENCE 548.Pq Event 2EH , Umask 4FH 549This event counts requests originating from the core that reference a cache 550line in the last level cache. The event count includes speculative traffic 551but excludes cache line fills due to a L2 hardware-prefetch. Because cache 552hierarchy, cache sizes and other implementation-specific characteristics; 553value comparison to estimate performance differences is not recommended. 554see Table A-1 555.It Li L3_LAT_CACHE.MISS 556.Pq Event 2EH , Umask 41H 557This event counts each cache miss condition for references to the last level 558cache. The event count may include speculative traffic but excludes cache 559line fills due to L2 hardware-prefetches. Because cache hierarchy, cache 560sizes and other implementation-specific characteristics; value comparison to 561estimate performance differences is not recommended. 562see Table A-1 563.It Li CPU_CLK_UNHALTED.THREAD_P 564.Pq Event 3CH , Umask 00H 565Counts the number of thread cycles while the thread is not in a halt state. 566The thread enters the halt state when it is running the HLT instruction. The 567core frequency may change from time to time due to power or thermal 568throttling. 569see Table A-1 570.It Li CPU_CLK_UNHALTED.REF_P 571.Pq Event 3CH , Umask 01H 572Increments at the frequency of TSC when not halted. 573see Table A-1 574.It Li L1D_CACHE_LD.I_STATE 575.Pq Event 40H , Umask 01H 576Counts L1 data cache read requests where the cache line to be loaded is in 577the I (invalid) state, i.e. the read request missed the cache. 578Counter 0, 1 only 579.It Li L1D_CACHE_LD.S_STATE 580.Pq Event 40H , Umask 02H 581Counts L1 data cache read requests where the cache line to be loaded is in 582the S (shared) state. 583Counter 0, 1 only 584.It Li L1D_CACHE_LD.E_STATE 585.Pq Event 40H , Umask 04H 586Counts L1 data cache read requests where the cache line to be loaded is in 587the E (exclusive) state. 588Counter 0, 1 only 589.It Li L1D_CACHE_LD.M_STATE 590.Pq Event 40H , Umask 08H 591Counts L1 data cache read requests where the cache line to be loaded is in 592the M (modified) state. 593Counter 0, 1 only 594.It Li L1D_CACHE_LD.MESI 595.Pq Event 40H , Umask 0FH 596Counts L1 data cache read requests. 597Counter 0, 1 only 598.It Li L1D_CACHE_ST.S_STATE 599.Pq Event 41H , Umask 02H 600Counts L1 data cache store RFO requests where the cache line to be loaded is 601in the S (shared) state. 602Counter 0, 1 only 603.It Li L1D_CACHE_ST.E_STATE 604.Pq Event 41H , Umask 04H 605Counts L1 data cache store RFO requests where the cache line to be loaded is 606in the E (exclusive) state. 607Counter 0, 1 only 608.It Li L1D_CACHE_ST.M_STATE 609.Pq Event 41H , Umask 08H 610Counts L1 data cache store RFO requests where cache line to be loaded is in 611the M (modified) state. 612Counter 0, 1 only 613.It Li L1D_CACHE_LOCK.HIT 614.Pq Event 42H , Umask 01H 615Counts retired load locks that hit in the L1 data cache or hit in an already 616allocated fill buffer. The lock portion of the load lock transaction must 617hit in the L1D. 618The initial load will pull the lock into the L1 data cache. Counter 0, 1 619only 620.It Li L1D_CACHE_LOCK.S_STATE 621.Pq Event 42H , Umask 02H 622Counts L1 data cache retired load locks that hit the target cache line in 623the shared state. 624Counter 0, 1 only 625.It Li L1D_CACHE_LOCK.E_STATE 626.Pq Event 42H , Umask 04H 627Counts L1 data cache retired load locks that hit the target cache line in 628the exclusive state. 629Counter 0, 1 only 630.It Li L1D_CACHE_LOCK.M_STATE 631.Pq Event 42H , Umask 08H 632Counts L1 data cache retired load locks that hit the target cache line in 633the modified state. 634Counter 0, 1 only 635.It Li L1D_ALL_REF.ANY 636.Pq Event 43H , Umask 01H 637Counts all references (uncached, speculated and retired) to the L1 data 638cache, including all loads and stores with any memory types. The event 639counts memory accesses only when they are actually performed. For example, a 640load blocked by unknown store address and later performed is only counted 641once. 642The event does not include non- memory accesses, such as I/O accesses. 643Counter 0, 1 only 644.It Li L1D_ALL_REF.CACHEABLE 645.Pq Event 43H , Umask 02H 646Counts all data reads and writes (speculated and retired) from cacheable 647memory, including locked operations. 648Counter 0, 1 only 649.It Li L1D_PEND_MISS.LOAD_BUFFERS_FULL 650.Pq Event 48H , Umask 02H 651Counts cycles of L1 data cache load fill buffers full. 652Counter 0, 1 only 653.It Li DTLB_MISSES.ANY 654.Pq Event 49H , Umask 01H 655Counts the number of misses in the STLB which causes a page walk. 656.It Li DTLB_MISSES.WALK_COMPLETED 657.Pq Event 49H , Umask 02H 658Counts number of misses in the STLB which resulted in a completed page walk. 659.It Li DTLB_MISSES.STLB_HIT 660.Pq Event 49H , Umask 10H 661Counts the number of DTLB first level misses that hit in the second level 662TLB. This event is only relevant if the core contains multiple DTLB levels. 663.It Li LOAD_HIT_PRE 664.Pq Event 4CH , Umask 01H 665Counts load operations sent to the L1 data cache while a previous SSE 666prefetch instruction to the same cache line has started prefetching but has 667not yet finished. 668.It Li L1D_PREFETCH.REQUESTS 669.Pq Event 4EH , Umask 01H 670Counts number of hardware prefetch requests dispatched out of the prefetch 671FIFO. 672.It Li L1D_PREFETCH.MISS 673.Pq Event 4EH , Umask 02H 674Counts number of hardware prefetch requests that miss the L1D. There are two 675prefetchers in the L1D. A streamer, which predicts lines sequentially after 676this one should be fetched, and the IP prefetcher that remembers access 677patterns for the current instruction. The streamer prefetcher stops on an 678L1D hit, while the IP prefetcher does not. 679.It Li L1D_PREFETCH.TRIGGERS 680.Pq Event 4EH , Umask 04H 681Counts number of prefetch requests triggered by the Finite State Machine and 682pushed into the prefetch FIFO. Some of the prefetch requests are dropped due 683to overwrites or competition between the IP index prefetcher and streamer 684prefetcher. The prefetch FIFO contains 4 entries. 685.It Li L1D.REPL 686.Pq Event 51H , Umask 01H 687Counts the number of lines brought into the L1 data cache. 688Counter 0, 1 only 689.It Li L1D.M_REPL 690.Pq Event 51H , Umask 02H 691Counts the number of modified lines brought into the L1 data cache. 692Counter 0, 1 only 693.It Li L1D.M_EVICT 694.Pq Event 51H , Umask 04H 695Counts the number of modified lines evicted from the L1 data cache due to 696replacement. 697Counter 0, 1 only 698.It Li L1D.M_SNOOP_EVICT 699.Pq Event 51H , Umask 08H 700Counts the number of modified lines evicted from the L1 data cache due to 701snoop HITM intervention. 702Counter 0, 1 only 703.It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT 704.Pq Event 52H , Umask 01H 705Counts the number of cacheable load lock speculated instructions accepted 706into the fill buffer. 707.It Li L1D_CACHE_LOCK_FB_HIT 708.Pq Event 53H , Umask 01H 709Counts the number of cacheable load lock speculated or retired instructions 710accepted into the fill buffer. 711.It Li CACHE_LOCK_CYCLES.L1D_L2 712.Pq Event 63H , Umask 01H 713Cycle count during which the L1D and L2 are locked. A lock is asserted when 714there is a locked memory access, due to uncacheable memory, a locked 715operation that spans two cache lines, or a page walk from an uncacheable 716page table. 717Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and 718it is highly recommended to avoid such accesses. 719.It Li CACHE_LOCK_CYCLES.L1D 720.Pq Event 63H , Umask 02H 721Counts the number of cycles that cacheline in the L1 data cache unit is 722locked. 723Counter 0, 1 only. 724.It Li IO_TRANSACTIONS 725.Pq Event 6CH , Umask 01H 726Counts the number of completed I/O transactions. 727.It Li L1I.HITS 728.Pq Event 80H , Umask 01H 729Counts all instruction fetches that hit the L1 instruction cache. 730.It Li L1I.MISSES 731.Pq Event 80H , Umask 02H 732Counts all instruction fetches that miss the L1I cache. This includes 733instruction cache misses, streaming buffer misses, victim cache misses and 734uncacheable fetches. An instruction fetch miss is counted only once and not 735once for every cycle it is outstanding. 736.It Li L1I.READS 737.Pq Event 80H , Umask 03H 738Counts all instruction fetches, including uncacheable fetches that bypass 739the L1I. 740.It Li L1I.CYCLES_STALLED 741.Pq Event 80H , Umask 04H 742Cycle counts for which an instruction fetch stalls due to a L1I cache miss, 743ITLB miss or ITLB fault. 744.It Li LARGE_ITLB.HIT 745.Pq Event 82H , Umask 01H 746Counts number of large ITLB hits. 747.It Li ITLB_MISSES.ANY 748.Pq Event 85H , Umask 01H 749Counts the number of misses in all levels of the ITLB which causes a page 750walk. 751.It Li ITLB_MISSES.WALK_COMPLETED 752.Pq Event 85H , Umask 02H 753Counts number of misses in all levels of the ITLB which resulted in a 754completed page walk. 755.It Li ILD_STALL.LCP 756.Pq Event 87H , Umask 01H 757Cycles Instruction Length Decoder stalls due to length changing prefixes: 75866, 67 or REX.W (for EM64T) instructions which change the length of the 759decoded instruction. 760.It Li ILD_STALL.MRU 761.Pq Event 87H , Umask 02H 762Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) 763Most Recently Used (MRU) bypass. 764.It Li ILD_STALL.IQ_FULL 765.Pq Event 87H , Umask 04H 766Stall cycles due to a full instruction queue. 767.It Li ILD_STALL.REGEN 768.Pq Event 87H , Umask 08H 769Counts the number of regen stalls. 770.It Li ILD_STALL.ANY 771.Pq Event 87H , Umask 0FH 772Counts any cycles the Instruction Length Decoder is stalled. 773.It Li BR_INST_EXEC.COND 774.Pq Event 88H , Umask 01H 775Counts the number of conditional near branch instructions executed, but not 776necessarily retired. 777.It Li BR_INST_EXEC.DIRECT 778.Pq Event 88H , Umask 02H 779Counts all unconditional near branch instructions excluding calls and 780indirect branches. 781.It Li BR_INST_EXEC.INDIRECT_NON_CALL 782.Pq Event 88H , Umask 04H 783Counts the number of executed indirect near branch instructions that are not 784calls. 785.It Li BR_INST_EXEC.NON_CALLS 786.Pq Event 88H , Umask 07H 787Counts all non call near branch instructions executed, but not necessarily 788retired. 789.It Li BR_INST_EXEC.RETURN_NEAR 790.Pq Event 88H , Umask 08H 791Counts indirect near branches that have a return mnemonic. 792.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 793.Pq Event 88H , Umask 10H 794Counts unconditional near call branch instructions, excluding non call 795branch, executed. 796.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 797.Pq Event 88H , Umask 20H 798Counts indirect near calls, including both register and memory indirect, 799executed. 800.It Li BR_INST_EXEC.NEAR_CALLS 801.Pq Event 88H , Umask 30H 802Counts all near call branches executed, but not necessarily retired. 803.It Li BR_INST_EXEC.TAKEN 804.Pq Event 88H , Umask 40H 805Counts taken near branches executed, but not necessarily retired. 806.It Li BR_INST_EXEC.ANY 807.Pq Event 88H , Umask 7FH 808Counts all near executed branches (not necessarily retired). This includes 809only instructions and not micro-op branches. Frequent branching is not 810necessarily a major performance issue. However frequent branch 811mispredictions may be a problem. 812.It Li BR_MISP_EXEC.COND 813.Pq Event 89H , Umask 01H 814Counts the number of mispredicted conditional near branch instructions 815executed, but not necessarily retired. 816.It Li BR_MISP_EXEC.DIRECT 817.Pq Event 89H , Umask 02H 818Counts mispredicted macro unconditional near branch instructions, excluding 819calls and indirect branches (should always be 0). 820.It Li BR_MISP_EXEC.INDIRECT_NON_CALL 821.Pq Event 89H , Umask 04H 822Counts the number of executed mispredicted indirect near branch instructions 823that are not calls. 824.It Li BR_MISP_EXEC.NON_CALLS 825.Pq Event 89H , Umask 07H 826Counts mispredicted non call near branches executed, but not necessarily 827retired. 828.It Li BR_MISP_EXEC.RETURN_NEAR 829.Pq Event 89H , Umask 08H 830Counts mispredicted indirect branches that have a rear return mnemonic. 831.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 832.Pq Event 89H , Umask 10H 833Counts mispredicted non-indirect near calls executed, (should always be 0). 834.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 835.Pq Event 89H , Umask 20H 836Counts mispredicted indirect near calls exeucted, including both register 837and memory indirect. 838.It Li BR_MISP_EXEC.NEAR_CALLS 839.Pq Event 89H , Umask 30H 840Counts all mispredicted near call branches executed, but not necessarily 841retired. 842.It Li BR_MISP_EXEC.TAKEN 843.Pq Event 89H , Umask 40H 844Counts executed mispredicted near branches that are taken, but not 845necessarily retired. 846.It Li BR_MISP_EXEC.ANY 847.Pq Event 89H , Umask 7FH 848Counts the number of mispredicted near branch instructions that were 849executed, but not necessarily retired. 850.It Li RESOURCE_STALLS.ANY 851.Pq Event A2H , Umask 01H 852Counts the number of Allocator resource related stalls. Includes register 853renaming buffer entries, memory buffer entries. In addition to resource 854related stalls, this event counts some other events. Includes stalls arising 855during branch misprediction recovery, such as if retirement of the 856mispredicted branch is delayed and stalls arising while store buffer is 857draining from synchronizing operations. 858Does not include stalls due to SuperQ (off core) queue full, too many cache 859misses, etc. 860.It Li RESOURCE_STALLS.LOAD 861.Pq Event A2H , Umask 02H 862Counts the cycles of stall due to lack of load buffer for load operation. 863.It Li RESOURCE_STALLS.RS_FULL 864.Pq Event A2H , Umask 04H 865This event counts the number of cycles when the number of instructions in 866the pipeline waiting for execution reaches the limit the processor can 867handle. A high count of this event indicates that there are long latency 868operations in the pipe (possibly load and store operations that miss the L2 869cache, or instructions dependent upon instructions further down the pipeline 870that have yet to retire. 871When RS is full, new instructions can not enter the reservation station and 872start execution. 873.It Li RESOURCE_STALLS.STORE 874.Pq Event A2H , Umask 08H 875This event counts the number of cycles that a resource related stall will 876occur due to the number of store instructions reaching the limit of the 877pipeline, (i.e. all store buffers are used). The stall ends when a store 878instruction commits its data to the cache or memory. 879.It Li RESOURCE_STALLS.ROB_FULL 880.Pq Event A2H , Umask 10H 881Counts the cycles of stall due to re- order buffer full. 882.It Li RESOURCE_STALLS.FPCW 883.Pq Event A2H , Umask 20H 884Counts the number of cycles while execution was stalled due to writing the 885floating-point unit (FPU) control word. 886.It Li RESOURCE_STALLS.MXCSR 887.Pq Event A2H , Umask 40H 888Stalls due to the MXCSR register rename occurring to close to a previous 889MXCSR rename. The MXCSR provides control and status for the MMX registers. 890.It Li RESOURCE_STALLS.OTHER 891.Pq Event A2H , Umask 80H 892Counts the number of cycles while execution was stalled due to other 893resource issues. 894.It Li MACRO_INSTS.FUSIONS_DECODED 895.Pq Event A6H , Umask 01H 896Counts the number of instructions decoded that are macro-fused but not 897necessarily executed or retired. 898.It Li BACLEAR_FORCE_IQ 899.Pq Event A7H , Umask 01H 900Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ 901is also responsible for providing conditional branch prediction direction 902based on a static scheme and dynamic data provided by the L2 Branch 903Prediction Unit. If the conditional branch target is not found in the Target 904Array and the IQ predicts that the branch is taken, then the IQ will force 905the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by 906the BAC generates approximately an 8 cycle bubble in the instruction fetch 907pipeline. 908.It Li LSD.UOPS 909.Pq Event A8H , Umask 01H 910Counts the number of micro-ops delivered by loop stream detector 911Use cmask=1 and invert to count cycles 912.It Li ITLB_FLUSH 913.Pq Event AEH , Umask 01H 914Counts the number of ITLB flushes 915.It Li OFFCORE_REQUESTS.L1D_WRITEBACK 916.Pq Event B0H , Umask 40H 917Counts number of L1D writebacks to the uncore. 918.It Li UOPS_EXECUTED.PORT0 919.Pq Event B1H , Umask 01H 920Counts number of Uops executed that were issued on port 0. Port 0 handles 921integer arithmetic, SIMD and FP add Uops. 922.It Li UOPS_EXECUTED.PORT1 923.Pq Event B1H , Umask 02H 924Counts number of Uops executed that were issued on port 1. Port 1 handles 925integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. 926.It Li UOPS_EXECUTED.PORT2_CORE 927.Pq Event B1H , Umask 04H 928Counts number of Uops executed that were issued on port 2. Port 2 handles 929the load Uops. This is a core count only and can not be collected per 930thread. 931.It Li UOPS_EXECUTED.PORT3_CORE 932.Pq Event B1H , Umask 08H 933Counts number of Uops executed that were issued on port 3. Port 3 handles 934store Uops. This is a core count only and can not be collected per thread. 935.It Li UOPS_EXECUTED.PORT4_CORE 936.Pq Event B1H , Umask 10H 937Counts number of Uops executed that where issued on port 4. Port 4 handles 938the value to be stored for the store Uops issued on port 3. This is a core 939count only and can not be collected per thread. 940.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 941.Pq Event B1H , Umask 1FH 942Counts cycles when the Uops executed were issued from any ports except port 9435. Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, 944Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count 945P0-4 stalls. 946.It Li UOPS_EXECUTED.PORT5 947.Pq Event B1H , Umask 20H 948Counts number of Uops executed that where issued on port 5. 949.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES 950.Pq Event B1H , Umask 3FH 951Counts cycles when the Uops are executing. Use Cmask=1 for active cycles; 952Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled 953cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. 954.It Li UOPS_EXECUTED.PORT015 955.Pq Event B1H , Umask 40H 956Counts number of Uops executed that where issued on port 0, 1, or 5. 957use cmask=1, invert=1 to count stall cycles 958.It Li UOPS_EXECUTED.PORT234 959.Pq Event B1H , Umask 80H 960Counts number of Uops executed that where issued on port 2, 3, or 4. 961.It Li OFFCORE_REQUESTS_SQ_FULL 962.Pq Event B2H , Umask 01H 963Counts number of cycles the SQ is full to handle off-core requests. 964.It Li OFF_CORE_RESPONSE_0 965.Pq Event B7H , Umask 01H 966see Section 30.6.1.3, Off-core Response Performance Monitoring in the 967Processor Core 968Requires programming MSR 01A6H 969.It Li SNOOP_RESPONSE.HIT 970.Pq Event B8H , Umask 01H 971Counts HIT snoop response sent by this thread in response to a snoop 972request. 973.It Li SNOOP_RESPONSE.HITE 974.Pq Event B8H , Umask 02H 975Counts HIT E snoop response sent by this thread in response to a snoop 976request. 977.It Li SNOOP_RESPONSE.HITM 978.Pq Event B8H , Umask 04H 979Counts HIT M snoop response sent by this thread in response to a snoop 980request. 981.It Li OFF_CORE_RESPONSE_1 982.Pq Event BBH , Umask 01H 983see Section 30.6.1.3, Off-core Response Performance Monitoring in the 984Processor Core 985Requires programming MSR 01A7H 986.It Li INST_RETIRED.ANY_P 987.Pq Event C0H , Umask 01H 988See Table A-1 989Notes: INST_RETIRED.ANY is counted by a designated fixed counter. 990INST_RETIRED.ANY_P is counted by a programmable counter and is an 991architectural performance event. Event is supported if CPUID.A.EBX[1] = 0. 992Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not 993count as retired instructions. 994.It Li INST_RETIRED.X87 995.Pq Event C0H , Umask 02H 996Counts the number of MMX instructions retired:. 997.It Li INST_RETIRED.MMX 998.Pq Event C0H , Umask 04H 999Counts the number of floating point computational operations retired: 1000floating point computational operations executed by the assist handler and 1001sub-operations of complex floating point instructions like transcendental 1002instructions. 1003.It Li UOPS_RETIRED.ANY 1004.Pq Event C2H , Umask 01H 1005Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, 1006others=1; maximum count of 8 per cycle). Most instructions are composed of 1007one or two micro-ops. Some instructions are decoded into longer sequences 1008such as repeat instructions, floating point transcendental instructions, and 1009assists. 1010Use cmask=1 and invert to count active cycles or stalled cycles 1011.It Li UOPS_RETIRED.RETIRE_SLOTS 1012.Pq Event C2H , Umask 02H 1013Counts the number of retirement slots used each cycle 1014.It Li UOPS_RETIRED.MACRO_FUSED 1015.Pq Event C2H , Umask 04H 1016Counts number of macro-fused uops retired. 1017.It Li MACHINE_CLEARS.CYCLES 1018.Pq Event C3H , Umask 01H 1019Counts the cycles machine clear is asserted. 1020.It Li MACHINE_CLEARS.MEM_ORDER 1021.Pq Event C3H , Umask 02H 1022Counts the number of machine clears due to memory order conflicts. 1023.It Li MACHINE_CLEARS.SMC 1024.Pq Event C3H , Umask 04H 1025Counts the number of times that a program writes to a code section. 1026Self-modifying code causes a sever penalty in all Intel 64 and IA-32 1027processors. The modified cache line is written back to the L2 and L3caches. 1028.It Li BR_INST_RETIRED.ALL_BRANCHES 1029.Pq Event C4H , Umask 00H 1030See Table A-1 1031.It Li BR_INST_RETIRED.CONDITIONAL 1032.Pq Event C4H , Umask 01H 1033Counts the number of conditional branch instructions retired. 1034.It Li BR_INST_RETIRED.NEAR_CALL 1035.Pq Event C4H , Umask 02H 1036Counts the number of direct & indirect near unconditional calls retired 1037.It Li BR_INST_RETIRED.ALL_BRANCHES 1038.Pq Event C4H , Umask 04H 1039Counts the number of branch instructions retired 1040.It Li BR_MISP_RETIRED.ALL_BRANCHES 1041.Pq Event C5H , Umask 00H 1042See Table A-1 1043.It Li BR_MISP_RETIRED.NEAR_CALL 1044.Pq Event C5H , Umask 02H 1045Counts mispredicted direct & indirect near unconditional retired calls. 1046.It Li SSEX_UOPS_RETIRED.PACKED_SINGLE 1047.Pq Event C7H , Umask 01H 1048Counts SIMD packed single-precision floating point Uops retired. 1049.It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE 1050.Pq Event C7H , Umask 02H 1051Counts SIMD calar single-precision floating point Uops retired. 1052.It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE 1053.Pq Event C7H , Umask 04H 1054Counts SIMD packed double- precision floating point Uops retired. 1055.It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE 1056.Pq Event C7H , Umask 08H 1057Counts SIMD scalar double-precision floating point Uops retired. 1058.It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER 1059.Pq Event C7H , Umask 10H 1060Counts 128-bit SIMD vector integer Uops retired. 1061.It Li ITLB_MISS_RETIRED 1062.Pq Event C8H , Umask 20H 1063Counts the number of retired instructions that missed the ITLB when the 1064instruction was fetched. 1065.It Li MEM_LOAD_RETIRED.L1D_HIT 1066.Pq Event CBH , Umask 01H 1067Counts number of retired loads that hit the L1 data cache. 1068.It Li MEM_LOAD_RETIRED.L2_HIT 1069.Pq Event CBH , Umask 02H 1070Counts number of retired loads that hit the L2 data cache. 1071.It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT 1072.Pq Event CBH , Umask 04H 1073Counts number of retired loads that hit their own, unshared lines in the L3 1074cache. 1075.It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM 1076.Pq Event CBH , Umask 08H 1077Counts number of retired loads that hit in a sibling core's L2 (on die 1078core). Since the L3 is inclusive of all cores on the package, this is an L3 1079hit. This counts both clean or modified hits. 1080.It Li MEM_LOAD_RETIRED.L3_MISS 1081.Pq Event CBH , Umask 10H 1082Counts number of retired loads that miss the L3 cache. The load was 1083satisfied by a remote socket, local memory or an IOH. 1084.It Li MEM_LOAD_RETIRED.HIT_LFB 1085.Pq Event CBH , Umask 40H 1086Counts number of retired loads that miss the L1D and the address is located 1087in an allocated line fill buffer and will soon be committed to cache. This 1088is counting secondary L1D misses. 1089.It Li MEM_LOAD_RETIRED.DTLB_MISS 1090.Pq Event CBH , Umask 80H 1091Counts the number of retired loads that missed the DTLB. The DTLB miss is 1092not counted if the load operation causes a fault. This event counts loads 1093from cacheable memory only. The event does not count loads by software 1094prefetches. Counts both primary and secondary misses to the TLB. 1095.It Li FP_MMX_TRANS.TO_FP 1096.Pq Event CCH , Umask 01H 1097Counts the first floating-point instruction following any MMX instruction. 1098You can use this event to estimate the penalties for the transitions between 1099floating-point and MMX technology states. 1100.It Li FP_MMX_TRANS.TO_MMX 1101.Pq Event CCH , Umask 02H 1102Counts the first MMX instruction following a floating-point instruction. You 1103can use this event to estimate the penalties for the transitions between 1104floating-point and MMX technology states. 1105.It Li FP_MMX_TRANS.ANY 1106.Pq Event CCH , Umask 03H 1107Counts all transitions from floating point to MMX instructions and from MMX 1108instructions to floating point instructions. You can use this event to 1109estimate the penalties for the transitions between floating-point and MMX 1110technology states. 1111.It Li MACRO_INSTS.DECODED 1112.Pq Event D0H , Umask 01H 1113Counts the number of instructions decoded, (but not necessarily executed or 1114retired). 1115.It Li UOPS_DECODED.MS 1116.Pq Event D1H , Umask 02H 1117Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS 1118delivers uops when the instruction is more than 4 uops long or a microcode 1119assist is occurring. 1120.It Li UOPS_DECODED.ESP_FOLDING 1121.Pq Event D1H , Umask 04H 1122Counts number of stack pointer (ESP) instructions decoded: push , pop , call 1123, ret, etc. ESP instructions do not generate a Uop to increment or decrement 1124ESP. Instead, they update an ESP_Offset register that keeps track of the 1125delta to the current value of the ESP register. 1126.It Li UOPS_DECODED.ESP_SYNC 1127.Pq Event D1H , Umask 08H 1128Counts number of stack pointer (ESP) sync operations where an ESP 1129instruction is corrected by adding the ESP offset register to the current 1130value of the ESP register. 1131.It Li RAT_STALLS.FLAGS 1132.Pq Event D2H , Umask 01H 1133Counts the number of cycles during which execution stalled due to several 1134reasons, one of which is a partial flag register stall. A partial register 1135stall may occur when two conditions are met: 1) an instruction modifies 1136some, but not all, of the flags in the flag register and 2) the next 1137instruction, which depends on flags, depends on flags that were not modified 1138by this instruction. 1139.It Li RAT_STALLS.REGISTERS 1140.Pq Event D2H , Umask 02H 1141This event counts the number of cycles instruction execution latency became 1142longer than the defined latency because the instruction used a register that 1143was partially written by previous instruction. 1144.It Li RAT_STALLS.ROB_READ_PORT 1145.Pq Event D2H , Umask 04H 1146Counts the number of cycles when ROB read port stalls occurred, which did 1147not allow new micro-ops to enter the out-of-order pipeline. Note that, at 1148this stage in the pipeline, additional stalls may occur at the same cycle 1149and prevent the stalled micro-ops from entering the pipe. In such a case, 1150micro-ops retry entering the execution pipe in the next cycle and the 1151ROB-read port stall is counted again. 1152.It Li RAT_STALLS.SCOREBOARD 1153.Pq Event D2H , Umask 08H 1154Counts the cycles where we stall due to microarchitecturally required 1155serialization. Microcode scoreboarding stalls. 1156.It Li RAT_STALLS.ANY 1157.Pq Event D2H , Umask 0FH 1158Counts all Register Allocation Table stall cycles due to: Cycles when ROB 1159read port stalls occurred, which did not allow new micro-ops to enter the 1160execution pipe. Cycles when partial register stalls occurred Cycles when 1161flag stalls occurred Cycles floating-point unit (FPU) status word stalls 1162occurred. To count each of these conditions separately use the events: 1163RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and 1164RAT_STALLS.FPSW. 1165.It Li SEG_RENAME_STALLS 1166.Pq Event D4H , Umask 01H 1167Counts the number of stall cycles due to the lack of renaming resources for 1168the ES, DS, FS, and GS segment registers. If a segment is renamed but not 1169retired and a second update to the same segment occurs, a stall occurs in 1170the front-end of the pipeline until the renamed segment retires. 1171.It Li ES_REG_RENAMES 1172.Pq Event D5H , Umask 01H 1173Counts the number of times the ES segment register is renamed. 1174.It Li UOP_UNFUSION 1175.Pq Event DBH , Umask 01H 1176Counts unfusion events due to floating point exception to a fused uop. 1177.It Li BR_INST_DECODED 1178.Pq Event E0H , Umask 01H 1179Counts the number of branch instructions decoded. 1180.It Li BPU_MISSED_CALL_RET 1181.Pq Event E5H , Umask 01H 1182Counts number of times the Branch Prediction Unit missed predicting a call 1183or return branch. 1184.It Li BACLEAR.CLEAR 1185.Pq Event E6H , Umask 01H 1186Counts the number of times the front end is resteered, mainly when the 1187Branch Prediction Unit cannot provide a correct prediction and this is 1188corrected by the Branch Address Calculator at the front end. This can occur 1189if the code has many branches such that they cannot be consumed by the BPU. 1190Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble 1191in the instruction fetch pipeline. The effect on total execution time 1192depends on the surrounding code. 1193.It Li BACLEAR.BAD_TARGET 1194.Pq Event E6H , Umask 02H 1195Counts number of Branch Address Calculator clears (BACLEAR) asserted due to 1196conditional branch instructions in which there was a target hit but the 1197direction was wrong. Each BACLEAR asserted by the BAC generates 1198approximately an 8 cycle bubble in the instruction fetch pipeline. 1199.It Li BPU_CLEARS.EARLY 1200.Pq Event E8H , Umask 01H 1201Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken 1202branch after incorrectly assuming that it was not taken. 1203The BPU clear leads to 2 cycle bubble in the Front End. 1204.It Li BPU_CLEARS.LATE 1205.Pq Event E8H , Umask 02H 1206Counts late Branch Prediction Unit clears due to Most Recently Used 1207conflicts. The PBU clear leads to a 3 cycle bubble in the Front End. 1208.It Li BPU_CLEARS.ANY 1209.Pq Event E8H , Umask 03H 1210Counts all BPU clears. 1211.It Li L2_TRANSACTIONS.LOAD 1212.Pq Event F0H , Umask 01H 1213Counts L2 load operations due to HW prefetch or demand loads. 1214.It Li L2_TRANSACTIONS.RFO 1215.Pq Event F0H , Umask 02H 1216Counts L2 RFO operations due to HW prefetch or demand RFOs. 1217.It Li L2_TRANSACTIONS.IFETCH 1218.Pq Event F0H , Umask 04H 1219Counts L2 instruction fetch operations due to HW prefetch or demand ifetch. 1220.It Li L2_TRANSACTIONS.PREFETCH 1221.Pq Event F0H , Umask 08H 1222Counts L2 prefetch operations. 1223.It Li L2_TRANSACTIONS.L1D_WB 1224.Pq Event F0H , Umask 10H 1225Counts L1D writeback operations to the L2. 1226.It Li L2_TRANSACTIONS.FILL 1227.Pq Event F0H , Umask 20H 1228Counts L2 cache line fill operations due to load, RFO, L1D writeback or 1229prefetch. 1230.It Li L2_TRANSACTIONS.WB 1231.Pq Event F0H , Umask 40H 1232Counts L2 writeback operations to the L3. 1233.It Li L2_TRANSACTIONS.ANY 1234.Pq Event F0H , Umask 80H 1235Counts all L2 cache operations. 1236.It Li L2_LINES_IN.S_STATE 1237.Pq Event F1H , Umask 02H 1238Counts the number of cache lines allocated in the L2 cache in the S (shared) 1239state. 1240.It Li L2_LINES_IN.E_STATE 1241.Pq Event F1H , Umask 04H 1242Counts the number of cache lines allocated in the L2 cache in the E 1243(exclusive) state. 1244.It Li L2_LINES_IN.ANY 1245.Pq Event F1H , Umask 07H 1246Counts the number of cache lines allocated in the L2 cache. 1247.It Li L2_LINES_OUT.DEMAND_CLEAN 1248.Pq Event F2H , Umask 01H 1249Counts L2 clean cache lines evicted by a demand request. 1250.It Li L2_LINES_OUT.DEMAND_DIRTY 1251.Pq Event F2H , Umask 02H 1252Counts L2 dirty (modified) cache lines evicted by a demand request. 1253.It Li L2_LINES_OUT.PREFETCH_CLEAN 1254.Pq Event F2H , Umask 04H 1255Counts L2 clean cache line evicted by a prefetch request. 1256.It Li L2_LINES_OUT.PREFETCH_DIRTY 1257.Pq Event F2H , Umask 08H 1258Counts L2 modified cache line evicted by a prefetch request. 1259.It Li L2_LINES_OUT.ANY 1260.Pq Event F2H , Umask 0FH 1261Counts all L2 cache lines evicted for any reason. 1262.It Li SQ_MISC.SPLIT_LOCK 1263.Pq Event F4H , Umask 10H 1264Counts the number of SQ lock splits across a cache line. 1265.It Li SQ_FULL_STALL_CYCLES 1266.Pq Event F6H , Umask 01H 1267Counts cycles the Super Queue is full. Neither of the threads on this core 1268will be able to access the uncore. 1269.It Li FP_ASSIST.ALL 1270.Pq Event F7H , Umask 01H 1271Counts the number of floating point operations executed that required 1272micro-code assist intervention. Assists are required in the following cases: 1273SSE instructions, (Denormal input when the DAZ flag is off or Underflow 1274result when the FTZ flag is off): x87 instructions, (NaN or denormal are 1275loaded to a register or used as input from memory, Division by 0 or 1276Underflow output). 1277.It Li FP_ASSIST.OUTPUT 1278.Pq Event F7H , Umask 02H 1279Counts number of floating point micro-code assist when the output value 1280(destination register) is invalid. 1281.It Li FP_ASSIST.INPUT 1282.Pq Event F7H , Umask 04H 1283Counts number of floating point micro-code assist when the input value (one 1284of the source operands to an FP instruction) is invalid. 1285.It Li SIMD_INT_64.PACKED_MPY 1286.Pq Event FDH , Umask 01H 1287Counts number of SID integer 64 bit packed multiply operations. 1288.It Li SIMD_INT_64.PACKED_SHIFT 1289.Pq Event FDH , Umask 02H 1290Counts number of SID integer 64 bit packed shift operations. 1291.It Li SIMD_INT_64.PACK 1292.Pq Event FDH , Umask 04H 1293Counts number of SID integer 64 bit pack operations. 1294.It Li SIMD_INT_64.UNPACK 1295.Pq Event FDH , Umask 08H 1296Counts number of SID integer 64 bit unpack operations. 1297.It Li SIMD_INT_64.PACKED_LOGICAL 1298.Pq Event FDH , Umask 10H 1299Counts number of SID integer 64 bit logical operations. 1300.It Li SIMD_INT_64.PACKED_ARITH 1301.Pq Event FDH , Umask 20H 1302Counts number of SID integer 64 bit arithmetic operations. 1303.It Li SIMD_INT_64.SHUFFLE_MOVE 1304.Pq Event FDH , Umask 40H 1305Counts number of SID integer 64 bit shift or move operations. 1306.El 1307.Ss Event Specifiers (Programmable PMCs) 1308Core i7 and Xeon 5500 programmable PMCs support the following events as 1309June 2009 document (removed in December 2009): 1310.Bl -tag -width indent 1311.It Li SB_FORWARD.ANY 1312.Pq Event 02H , Umask 01H 1313Counts the number of store forwards. 1314.It Li LOAD_BLOCK.STD 1315.Pq Event 03H , Umask 01H 1316Counts the number of loads blocked by a preceding store with unknown data. 1317.It Li LOAD_BLOCK.ADDRESS_OFFSET 1318.Pq Event 03H , Umask 04H 1319Counts the number of loads blocked by a preceding store address. 1320.It Li LOAD_BLOCK.ADDRESS_OFFSET 1321.Pq Event 01H , Umask 04H 1322Counts the cycles of store buffer drains. 1323.It Li MISALIGN_MEM_REF.LOAD 1324.Pq Event 05H , Umask 01H 1325Counts the number of misaligned load references 1326.It Li MISALIGN_MEM_REF.STORE 1327.Pq Event 05H , Umask 02H 1328Counts the number of misaligned store references 1329.It Li MISALIGN_MEM_REF.ANY 1330.Pq Event 05H , Umask 03H 1331Counts the number of misaligned memory references 1332.It Li STORE_BLOCKS.NOT_STA 1333.Pq Event 06H , Umask 01H 1334This event counts the number of load operations delayed caused by preceding 1335stores whose addresses are known but whose data is unknown, and preceding 1336stores that conflict with the load but which incompletely overlap the load. 1337.It Li STORE_BLOCKS.STA 1338.Pq Event 06H , Umask 02H 1339This event counts load operations delayed caused by preceding stores whose 1340addresses are unknown (STA block). 1341.It Li STORE_BLOCKS.ANY 1342.Pq Event 06H , Umask 0FH 1343All loads delayed due to store blocks 1344.It Li MEMORY_DISAMBIGURATION.RESET 1345.Pq Event 09H , Umask 01H 1346Counts memory disambiguration reset cycles 1347.It Li MEMORY_DISAMBIGURATION.SUCCESS 1348.Pq Event 09H , Umask 02H 1349Counts the number of loads that memory disambiguration succeeded 1350.It Li MEMORY_DISAMBIGURATION.WATCHDOG 1351.Pq Event 09H , Umask 04H 1352Counts the number of times the memory disambiguration watchdog kicked in. 1353.It Li MEMORY_DISAMBIGURATION.WATCH_CYCLES 1354.Pq Event 09H , Umask 08H 1355Counts the cycles that the memory disambiguration watchdog is active. 1356set invert=1, cmask = 1 1357.It Li HW_INT.RCV 1358.Pq Event 1DH , Umask 01H 1359Number of interrupt received 1360.It Li HW_INT.CYCLES_MASKED 1361.Pq Event 1DH , Umask 02H 1362Number of cycles interrupt are masked 1363.It Li HW_INT.CYCLES_PENDING_AND_MASKED 1364.Pq Event 1DH , Umask 04H 1365Number of cycles interrupts are pending and masked 1366.It Li HW_INT.CYCLES_PENDING_AND_MASKED 1367.Pq Event 04H , Umask 04H 1368Counts number of L2 store RFO requests where the cache line to be loaded is 1369in the E (exclusive) state. The L1D prefetcher does not issue a RFO 1370prefetch. 1371This is a demand RFO request 1372.It Li HW_INT.CYCLES_PENDING_AND_MASKED 1373.Pq Event 27H , Umask 04H 1374LONGEST_LAT_CACH E.MISS 1375.It Li UOPS_DECODED.DEC0 1376.Pq Event 3DH , Umask 01H 1377Counts micro-ops decoded by decoder 0. 1378.It Li UOPS_DECODED.DEC0 1379.Pq Event 01H , Umask 01H 1380Counts L1 data cache store RFO requests where the cache line to be loaded is 1381in the I state. 1382Counter 0, 1 only 1383.It Li 0FH 1384.Pq Event 41H , Umask 41H 1385L1D_CACHE_ST.MESI 1386Counts L1 data cache store RFO requests. 1387Counter 0, 1 only 1388.It Li DTLB_MISSES.PDE_MISS 1389.Pq Event 49H , Umask 20H 1390Number of DTLB cache misses where the low part of the linear to physical 1391address translation was missed. 1392.It Li DTLB_MISSES.PDP_MISS 1393.Pq Event 49H , Umask 40H 1394Number of DTLB misses where the high part of the linear to physical address 1395translation was missed. 1396.It Li DTLB_MISSES.LARGE_WALK_COMPLETED 1397.Pq Event 49H , Umask 80H 1398Counts number of completed large page walks due to misses in the STLB. 1399.It Li SSE_MEM_EXEC.NTA 1400.Pq Event 4BH , Umask 01H 1401Counts number of SSE NTA prefetch/weakly-ordered instructions which missed 1402the L1 data cache. 1403.It Li SSE_MEM_EXEC.STREAMING_STORES 1404.Pq Event 4BH , Umask 08H 1405Counts number of SSE non temporal stores 1406.It Li SFENCE_CYCLES 1407.Pq Event 4DH , Umask 01H 1408Counts store fence cycles 1409.It Li EPT.EPDE_MISS 1410.Pq Event 4FH , Umask 02H 1411Counts Extended Page Directory Entry misses. The Extended Page Directory 1412cache is used by Virtual Machine operating systems while the guest operating 1413systems use the standard TLB caches. 1414.It Li EPT.EPDPE_HIT 1415.Pq Event 4FH , Umask 04H 1416Counts Extended Page Directory Pointer Entry hits. 1417.It Li EPT.EPDPE_MISS 1418.Pq Event 4FH , Umask 08H 1419Counts Extended Page Directory Pointer Entry misses. T 1420.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA 1421.Pq Event 60H , Umask 01H 1422Counts weighted cycles of offcore demand data read requests. Does not 1423include L2 prefetch requests. 1424counter 0 1425.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE 1426.Pq Event 60H , Umask 02H 1427Counts weighted cycles of offcore demand code read requests. Does not 1428include L2 prefetch requests. 1429counter 0 1430.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO 1431.Pq Event 60H , Umask 04H 1432Counts weighted cycles of offcore demand RFO requests. Does not include L2 1433prefetch requests. 1434counter 0 1435.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ 1436.Pq Event 60H , Umask 08H 1437Counts weighted cycles of offcore read requests of any kind. Include L2 1438prefetch requests. 1439counter 0 1440.It Li IFU_IVC.FULL 1441.Pq Event 81H , Umask 01H 1442Instruction Fetche unit victim cache full. 1443.It Li IFU_IVC.L1I_EVICTION 1444.Pq Event 81H , Umask 02H 1445L1 Instruction cache evictions. 1446.It Li L1I_OPPORTUNISTIC_HITS 1447.Pq Event 83H , Umask 01H 1448Opportunistic hits in streaming. 1449.It Li ITLB_MISSES.WALK_CYCLES 1450.Pq Event 85H , Umask 04H 1451Counts ITLB miss page walk cycles. 1452.It Li ITLB_MISSES.PMH_BUSY_CYCLES 1453.Pq Event 85H , Umask 04H 1454Counts PMH busy cycles. 1455.It Li ITLB_MISSES.STLB_HIT 1456.Pq Event 85H , Umask 10H 1457Counts the number of ITLB misses that hit in the second level TLB. 1458.It Li ITLB_MISSES.PDE_MISS 1459.Pq Event 85H , Umask 20H 1460Number of ITLB misses where the low part of the linear to physical address 1461translation was missed. 1462.It Li ITLB_MISSES.PDP_MISS 1463.Pq Event 85H , Umask 40H 1464Number of ITLB misses where the high part of the linear to physical address 1465translation was missed. 1466.It Li ITLB_MISSES.LARGE_WALK_COMPLETED 1467.Pq Event 85H , Umask 80H 1468Counts number of completed large page walks due to misses in the STLB. 1469.It Li ITLB_MISSES.LARGE_WALK_COMPLETED 1470.Pq Event 01H , Umask 80H 1471Counts number of offcore demand data read requests. Does not count L2 1472prefetch requests. 1473.It Li OFFCORE_REQUESTS.DEMAND.READ_CODE 1474.Pq Event B0H , Umask 02H 1475Counts number of offcore demand code read requests. Does not count L2 1476prefetch requests. 1477.It Li OFFCORE_REQUESTS.DEMAND.RFO 1478.Pq Event B0H , Umask 04H 1479Counts number of offcore demand RFO requests. Does not count L2 prefetch 1480requests. 1481.It Li OFFCORE_REQUESTS.ANY.READ 1482.Pq Event B0H , Umask 08H 1483Counts number of offcore read requests. Includes L2 prefetch requests. 1484.It Li OFFCORE_REQUESTS.ANY.RFO 1485.Pq Event B0H , Umask 10H 1486Counts number of offcore RFO requests. Includes L2 prefetch requests. 1487.It Li OFFCORE_REQUESTS.UNCACHED_MEM 1488.Pq Event B0H , Umask 20H 1489Counts number of offcore uncached memory requests. 1490.It Li OFFCORE_REQUESTS.ANY 1491.Pq Event B0H , Umask 80H 1492Counts all offcore requests. 1493.It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA 1494.Pq Event B3H , Umask 01H 1495Counts weighted cycles of snoopq requests for data. Counter 0 only 1496Use cmask=1 to count cycles not empty. 1497.It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE 1498.Pq Event B3H , Umask 02H 1499Counts weighted cycles of snoopq invalidate requests. Counter 0 only 1500Use cmask=1 to count cycles not empty. 1501.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE 1502.Pq Event B3H , Umask 04H 1503Counts weighted cycles of snoopq requests for code. Counter 0 only 1504Use cmask=1 to count cycles not empty. 1505.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE 1506.Pq Event BAH , Umask 04H 1507Counts number of TPR reads 1508.It Li PIC_ACCESSES.TPR_WRITES 1509.Pq Event BAH , Umask 02H 1510Counts number of TPR writes 1511one or two micro-ops. Some instructions are decoded into longer sequences 1512.It Li MACHINE_CLEARS.FUSION_ASSIST 1513.Pq Event C3H , Umask 10H 1514Counts the number of macro-fusion assists 1515Counts SIMD packed single- precision floating point Uops retired. 1516.It Li BOGUS_BR 1517.Pq Event E4H , Umask 01H 1518Counts the number of bogus branches. 1519.It Li L2_HW_PREFETCH.HIT 1520.Pq Event F3H , Umask 01H 1521Count L2 HW prefetcher detector hits 1522.It Li L2_HW_PREFETCH.ALLOC 1523.Pq Event F3H , Umask 02H 1524Count L2 HW prefetcher allocations 1525.It Li L2_HW_PREFETCH.DATA_TRIGGER 1526.Pq Event F3H , Umask 04H 1527Count L2 HW data prefetcher triggered 1528.It Li L2_HW_PREFETCH.CODE_TRIGGER 1529.Pq Event F3H , Umask 08H 1530Count L2 HW code prefetcher triggered 1531.It Li L2_HW_PREFETCH.DCA_TRIGGER 1532.Pq Event F3H , Umask 10H 1533Count L2 HW DCA prefetcher triggered 1534.It Li L2_HW_PREFETCH.KICK_START 1535.Pq Event F3H , Umask 20H 1536Count L2 HW prefetcher kick started 1537.It Li SQ_MISC.PROMOTION 1538.Pq Event F4H , Umask 01H 1539Counts the number of L2 secondary misses that hit the Super Queue. 1540.It Li SQ_MISC.PROMOTION_POST_GO 1541.Pq Event F4H , Umask 02H 1542Counts the number of L2 secondary misses during the Super Queue filling L2. 1543.It Li SQ_MISC.LRU_HINTS 1544.Pq Event F4H , Umask 04H 1545Counts number of Super Queue LRU hints sent to L3. 1546.It Li SQ_MISC.FILL_DROPPED 1547.Pq Event F4H , Umask 08H 1548Counts the number of SQ L2 fills dropped due to L2 busy. 1549.It Li SEGMENT_REG_LOADS 1550.Pq Event F8H , Umask 01H 1551Counts number of segment register loads. 1552.El 1553.Sh SEE ALSO 1554.Xr pmc 3 , 1555.Xr pmc.atom 3 , 1556.Xr pmc.core 3 , 1557.Xr pmc.iaf 3 , 1558.Xr pmc.ucf 3 , 1559.Xr pmc.k7 3 , 1560.Xr pmc.k8 3 , 1561.Xr pmc.p4 3 , 1562.Xr pmc.p5 3 , 1563.Xr pmc.p6 3 , 1564.Xr pmc.corei7uc 3 , 1565.Xr pmc.westmere 3 , 1566.Xr pmc.westmereuc 3 , 1567.Xr pmc.tsc 3 , 1568.Xr pmc_cpuinfo 3 , 1569.Xr pmclog 3 , 1570.Xr hwpmc 4 1571.Sh HISTORY 1572The 1573.Nm pmc 1574library first appeared in 1575.Fx 6.0 . 1576.Sh AUTHORS 1577The 1578.Lb libpmc 1579library was written by 1580.An "Joseph Koshy" 1581.Aq jkoshy@FreeBSD.org . 1582