1.\" Copyright (c) 2008,2009 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd June 8, 2009 25.Dt PMC.CORE2 3 26.Os 27.Sh NAME 28.Nm pmc.core2 29.Nd measurement events for 30.Tn Intel 31.Tn Core2 32family CPUs 33.Sh LIBRARY 34.Lb libpmc 35.Sh SYNOPSIS 36.In pmc.h 37.Sh DESCRIPTION 38.Tn Intel 39.Tn "Core2" 40CPUs contain PMCs conforming to version 2 of the 41.Tn Intel 42performance measurement architecture. 43These CPUs may contain up to two classes of PMCs: 44.Bl -tag -width "Li PMC_CLASS_IAP" 45.It Li PMC_CLASS_IAF 46Fixed-function counters that count only one hardware event per counter. 47.It Li PMC_CLASS_IAP 48Programmable counters that may be configured to count one of a defined 49set of hardware events. 50.El 51.Pp 52The number of PMCs available in each class and their widths need to be 53determined at run time by calling 54.Xr pmc_cpuinfo 3 . 55.Pp 56Intel Core2 PMCs are documented in 57.Rs 58.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 59.%T "Volume 3: System Programming Guide" 60.%N "Order Number 253669-027US" 61.%D July 2008 62.%Q "Intel Corporation" 63.Re 64.Ss CORE2 FIXED FUNCTION PMCS 65These PMCs and their supported events are documented in 66.Xr pmc.iaf 3 . 67Not all CPUs in this family implement fixed-function counters. 68.Ss CORE2 PROGRAMMABLE PMCS 69The programmable PMCs support the following capabilities: 70.Bl -column "PMC_CAP_INTERRUPT" "Support" 71.It Em Capability Ta Em Support 72.It PMC_CAP_CASCADE Ta \&No 73.It PMC_CAP_EDGE Ta Yes 74.It PMC_CAP_INTERRUPT Ta Yes 75.It PMC_CAP_INVERT Ta Yes 76.It PMC_CAP_READ Ta Yes 77.It PMC_CAP_PRECISE Ta \&No 78.It PMC_CAP_SYSTEM Ta Yes 79.It PMC_CAP_TAGGING Ta \&No 80.It PMC_CAP_THRESHOLD Ta Yes 81.It PMC_CAP_USER Ta Yes 82.It PMC_CAP_WRITE Ta Yes 83.El 84.Ss Event Qualifiers 85Event specifiers for these PMCs support the following common 86qualifiers: 87.Bl -tag -width indent 88.It Li cmask= Ns Ar value 89Configure the PMC to increment only if the number of configured 90events measured in a cycle is greater than or equal to 91.Ar value . 92.It Li edge 93Configure the PMC to count the number of de-asserted to asserted 94transitions of the conditions expressed by the other qualifiers. 95If specified, the counter will increment only once whenever a 96condition becomes true, irrespective of the number of clocks during 97which the condition remains true. 98.It Li inv 99Invert the sense of comparison when the 100.Dq Li cmask 101qualifier is present, making the counter increment when the number of 102events per cycle is less than the value specified by the 103.Dq Li cmask 104qualifier. 105.It Li os 106Configure the PMC to count events happening at processor privilege 107level 0. 108.It Li usr 109Configure the PMC to count events occurring at privilege levels 1, 2 110or 3. 111.El 112.Pp 113If neither of the 114.Dq Li os 115or 116.Dq Li usr 117qualifiers are specified, the default is to enable both. 118.Pp 119Events that require core-specificity to be specified use a 120additional qualifier 121.Dq Li core= Ns Ar core , 122where argument 123.Ar core 124is one of: 125.Bl -tag -width indent 126.It Li all 127Measure event conditions on all cores. 128.It Li this 129Measure event conditions on this core. 130.El 131.Pp 132The default is 133.Dq Li this . 134.Pp 135Events that require an agent qualifier to be specified use an 136additional qualifier 137.Dq Li agent= Ns agent , 138where argument 139.Ar agent 140is one of: 141.Bl -tag -width indent 142.It Li this 143Measure events associated with this bus agent. 144.It Li any 145Measure events caused by any bus agent. 146.El 147.Pp 148The default is 149.Dq Li this . 150.Pp 151Events that require a hardware prefetch qualifier to be specified use an 152additional qualifier 153.Dq Li prefetch= Ns Ar prefetch , 154where argument 155.Ar prefetch 156is one of: 157.Bl -tag -width "exclude" 158.It Li both 159Include all prefetches. 160.It Li only 161Only count hardware prefetches. 162.It Li exclude 163Exclude hardware prefetches. 164.El 165.Pp 166The default is 167.Dq Li both . 168.Pp 169Events that require a cache coherence qualifier to be specified use an 170additional qualifier 171.Dq Li cachestate= Ns Ar state , 172where argument 173.Ar state 174contains one or more of the following letters: 175.Bl -tag -width indent 176.It Li e 177Count cache lines in the exclusive state. 178.It Li i 179Count cache lines in the invalid state. 180.It Li m 181Count cache lines in the modified state. 182.It Li s 183Count cache lines in the shared state. 184.El 185.Pp 186The default is 187.Dq Li eims . 188.Pp 189Events that require a snoop response qualifier to be specified use an 190additional qualifier 191.Dq Li snoopresponse= Ns Ar response , 192where argument 193.Ar response 194comprises of the following keywords separated by 195.Dq + 196signs: 197.Bl -tag -width indent 198.It Li clean 199Measure CLEAN responses. 200.It Li hit 201Measure HIT responses. 202.It Li hitm 203Measure HITM responses. 204.El 205.Pp 206The default is to measure all the above responses. 207.Pp 208Events that require a snoop type qualifier use an additional qualifier 209.Dq Li snooptype= Ns Ar type , 210where argument 211.Ar type 212comprises the one of the following keywords: 213.Bl -tag -width indent 214.It Li cmp2i 215Measure CMP2I snoops. 216.It Li cmp2s 217Measure CMP2S snoops. 218.El 219.Pp 220The default is to measure both snoops. 221.Ss Event Specifiers (Programmable PMCs) 222Core2 programmable PMCs support the following events: 223.Bl -tag -width indent 224.It Li BACLEARS 225.Pq Event E6H , Umask 00H 226The number of times the front end is resteered. 227.It Li BOGUS_BR 228.Pq Event E4H , Umask 00H 229The number of byte sequences mistakenly detected as taken branch 230instructions. 231.It Li BR_BAC_MISSP_EXEC 232.Pq Event 8AH , Umask 00H 233The number of branch instructions that were mispredicted when 234decoded. 235.It Li BR_CALL_MISSP_EXEC 236.Pq Event 93H , Umask 00H 237The number of mispredicted 238.Li CALL 239instructions that were executed. 240.It Li BR_CALL_EXEC 241.Pq Event 92H , Umask 00H 242The number of 243.Li CALL 244instructions executed. 245.It Li BR_CND_EXEC 246.Pq Event 8BH , Umask 00H 247The number of conditional branches executed, but not necessarily retired. 248.It Li BR_CND_MISSP_EXEC 249.Pq Event 8CH , Umask 00H 250The number of mispredicted conditional branches executed. 251.It Li BR_IND_CALL_EXEC 252.Pq Event 94H , Umask 00H 253The number of indirect 254.Li CALL 255instructions executed. 256.It Li BR_IND_EXEC 257.Pq Event 8DH , Umask 00H 258The number of indirect branch instructions executed. 259.It Li BR_IND_MISSP_EXEC 260.Pq Event 8EH , Umask 00H 261The number of mispredicted indirect branch instructions executed. 262.It Li BR_INST_DECODED 263.Pq Event E0H , Umask 00H 264The number of branch instructions decoded. 265.It Li BR_INST_EXEC 266.Pq Event 88H , Umask 00H 267The number of branches executed, but not necessarily retired. 268.It Li BR_INST_RETIRED.ANY 269.Pq Event C4H , Umask 00H 270.Pq Alias Qq "Branch Instruction Retired" 271The number of branch instructions retired. 272This is an architectural performance event. 273.It Li BR_INST_RETIRED.MISPRED 274.Pq Event C5H , Umask 00H 275.Pq Alias Qq "Branch Misses Retired" 276The number of mispredicted branch instructions retired. 277This is an architectural performance event. 278.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN 279.Pq Event C4H , Umask 02H 280The number of not taken branch instructions retired that were 281mispredicted. 282.It Li BR_INST_RETIRED.MISPRED_TAKEN 283.Pq Event C4H , Umask 08H 284The number taken branch instructions retired that were mispredicted. 285.It Li BR_INST_RETIRED.PRED_NOT_TAKEN 286.Pq Event C4H , Umask 01H 287The number of not taken branch instructions retired that were 288correctly predicted. 289.It Li BR_INST_RETIRED.PRED_TAKEN 290.Pq Event C4H , Umask 04H 291The number of taken branch instructions retired that were correctly 292predicted. 293.It Li BR_INST_RETIRED.TAKEN 294.Pq Event C4H , Umask 0CH 295The number of taken branch instructions retired. 296.It Li BR_MISSP_EXEC 297.Pq Event 89H , Umask 00H 298The number of mispredicted branch instructions that were executed. 299.It Li BR_RET_MISSP_EXEC 300.Pq Event 90H , Umask 00H 301The number of mispredicted 302.Li RET 303instructions executed. 304.It Li BR_RET_BAC_MISSP_EXEC 305.Pq Event 91H , Umask 00H 306The number of 307.Li RET 308instructions executed that were mispredicted at decode time. 309.It Li BR_RET_EXEC 310.Pq Event 8FH , Umask 00H 311The number of 312.Li RET 313instructions executed. 314.It Li BR_TKN_BUBBLE_1 315.Pq Event 97H , Umask 00H 316The number of branch predicted taken with bubble 1. 317.It Li BR_TKN_BUBBLE_2 318.Pq Event 98H , Umask 00H 319The number of branch predicted taken with bubble 2. 320.It Li BUSQ_EMPTY Op ,core= Ns Ar core 321.Pq Event 7DH 322The number of cycles during which the core did not have any pending 323transactions in the bus queue. 324.It Li BUS_BNR_DRV Op ,agent= Ns Ar agent 325.Pq Event 61H 326The number of Bus Not Ready signals asserted on the bus. 327.It Li BUS_DATA_RCV Op ,core= Ns Ar core 328.Pq Event 64H 329The number of bus cycles during which the processor is receiving data. 330.It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent 331.Pq Event 62H 332The number of bus cycles during which the Data Ready signal is asserted 333on the bus. 334.It Li BUS_HIT_DRV Op ,agent= Ns Ar agent 335.Pq Event 7AH 336The number of bus cycles during which the processor drives the 337.Li HIT# 338pin. 339.It Li BUS_HITM_DRV Op ,agent= Ns Ar agent 340.Pq Event 7BH 341The number of bus cycles during which the processor drives the 342.Li HITM# 343pin. 344.It Li BUS_IO_WAIT Op ,core= Ns Ar core 345.Pq Event 7FH 346The number of core cycles during which I/O requests wait in the bus 347queue. 348.It Li BUS_LOCK_CLOCKS Xo 349.Op ,agent= Ns Ar agent 350.Op ,core= Ns Ar core 351.Xc 352.Pq Event 63H 353The number of bus cycles during which the 354.Li LOCK 355signal was asserted on the bus. 356.It Li BUS_REQUEST_OUTSTANDING Xo 357.Op ,agent= Ns Ar agent 358.Op ,core= Ns Ar core 359.Xc 360.Pq Event 60H 361The number of pending full cache line read transactions on the bus 362occurring in each cycle. 363.It Li BUS_TRANS_P Xo 364.Op ,agent= Ns Ar agent 365.Op ,core= Ns Ar core 366.Xc 367.Pq Event 6BH 368The number of partial bus transactions. 369.It Li BUS_TRANS_IFETCH Xo 370.Op ,agent= Ns Ar agent 371.Op ,core= Ns Ar core 372.Xc 373.Pq Event 68H 374The number of instruction fetch full cache line bus transactions. 375.It Li BUS_TRANS_INVAL Xo 376.Op ,agent= Ns Ar agent 377.Op ,core= Ns Ar core 378.Xc 379.Pq Event 69H 380The number of invalidate bus transactions. 381.It Li BUS_TRANS_PWR Xo 382.Op ,agent= Ns Ar agent 383.Op ,core= Ns Ar core 384.Xc 385.Pq Event 6AH 386The number of partial write bus transactions. 387.It Li BUS_TRANS_DEF Xo 388.Op ,agent= Ns Ar agent 389.Op ,core= Ns Ar core 390.Xc 391.Pq Event 6DH 392The number of deferred bus transactions. 393.It Li BUS_TRANS_BURST Xo 394.Op ,agent= Ns Ar agent 395.Op ,core= Ns Ar core 396.Xc 397.Pq Event 6EH 398The number of burst transactions. 399.It Li BUS_TRANS_MEM Xo 400.Op ,agent= Ns Ar agent 401.Op ,core= Ns Ar core 402.Xc 403.Pq Event 6FH 404The number of memory bus transactions. 405.It Li BUS_TRANS_ANY Xo 406.Op ,agent= Ns Ar agent 407.Op ,core= Ns Ar core 408.Xc 409.Pq Event 70H 410The number of bus transactions of any kind. 411.It Li BUS_TRANS_BRD Xo 412.Op ,agent= Ns Ar agent 413.Op ,core= Ns Ar core 414.Xc 415.Pq Event 65H 416The number of burst read transactions. 417.It Li BUS_TRANS_IO Xo 418.Op ,agent= Ns Ar agent 419.Op ,core= Ns Ar core 420.Xc 421.Pq Event 6CH 422The number of completed I/O bus transactions due to 423.Li IN 424and 425.Li OUT 426instructions. 427.It Li BUS_TRANS_RFO Xo 428.Op ,agent= Ns Ar agent 429.Op ,core= Ns Ar core 430.Xc 431.Pq Event 66H 432The number of Read For Ownership bus transactions. 433.It Li BUS_TRANS_WB Xo 434.Op ,agent= Ns Ar agent 435.Op ,core= Ns Ar core 436.Xc 437.Pq Event 67H 438The number explicit write-back bus transactions due to dirty line 439evictions. 440.It Li CMP_SNOOP Xo 441.Op ,core= Ns Ar core 442.Op ,snooptype= Ns Ar snoop 443.Xc 444.Pq Event 78H 445The number of times the L1 data cache is snooped by the other core in 446the same processor. 447.It Li CPU_CLK_UNHALTED.BUS 448.Pq Event 3CH , Umask 01H 449.Pq Alias Qq "Unhalted Reference Cycles" 450The number of bus cycles when the core is not in the halt state. 451This is an architectural performance event. 452.It Li CPU_CLK_UNHALTED.CORE_P 453.Pq Event 3CH , Umask 00H 454.Pq Alias Qq "Unhalted Core Cycles" 455The number of core cycles while the core is not in a halt state. 456This is an architectural performance event. 457.It Li CPU_CLK_UNHALTED.NO_OTHER 458.Pq Event 3CH , Umask 02H 459The number of bus cycles during which the core remains unhalted and 460the other core is halted. 461.It Li CYCLES_DIV_BUSY 462.Pq Event 14H , Umask 00H 463The number of cycles the divider is busy. 464This event is only available on PMC0. 465.It Li CYCLES_INT_MASKED 466.Pq Event C6H , Umask 01H 467The number of cycles during which interrupts are disabled. 468.It Li CYCLES_INT_PENDING_AND_MASKED 469.Pq Event C6H , Umask 02H 470The number of cycles during which there were pending interrupts while 471interrupts were disabled. 472.It Li CYCLES_L1I_MEM_STALLED 473.Pq Event 86H , Umask 00H 474The number of cycles for which an instruction fetch stalls. 475.It Li DELAYED_BYPASS.FP 476.Pq Event 19H , Umask 00H 477The number of floating point operations that used data immediately 478after the data was generated by a non floating point execution unit. 479.It Li DELAYED_BYPASS.LOAD 480.Pq Event 19H , Umask 01H 481The number of delayed bypass penalty cycles that a load operation incurred. 482.It Li DELAYED_BYPASS.SIMD 483.Pq Event 19H , Umask 02H 484The number of times SIMD operations use data immediately after data, 485was generated by a non-SIMD execution unit. 486.It Li DIV 487.Pq Event 13H , Umask 00H 488The number of divide operations executed. 489This event is only available on PMC1. 490.It Li DTLB_MISSES.ANY 491.Pq Event 08H , Umask 01H 492The number of Data TLB misses, including misses that result from 493speculative accesses. 494.It Li DTLB_MISSES.L0_MISS_LD 495.Pq Event 08H , Umask 04H 496The number of level 0 DTLB misses due to load operations. 497.It Li DTLB_MISSES.MISS_LD 498.Pq Event 08H , Umask 02H 499The number of Data TLB misses due to load operations. 500.It Li DTLB_MISSES.MISS_ST 501.Pq Event 08H , Umask 08H 502The number of Data TLB misses due to store operations. 503.It Li EIST_TRANS 504.Pq Event 3AH , Umask 00H 505The number of Enhanced Intel SpeedStep Technology transitions. 506.It Li ESP.ADDITIONS 507.Pq Event ABH , Umask 02H 508The number of automatic additions to the 509.Li %esp 510register. 511.It Li ESP.SYNCH 512.Pq Event ABH , Umask 01H 513The number of times the 514.Li %esp 515register was explicitly used in an address expression after 516it is implicitly used by a 517.Li PUSH 518or 519.Li POP 520instruction. 521.It Li EXT_SNOOP Xo 522.Op ,agent= Ns Ar agent 523.Op ,snoopresponse= Ns Ar response 524.Xc 525.Pq Event 77H 526The number of snoop responses to bus transactions. 527.It Li FP_ASSIST 528.Pq Event 11H , Umask 00H 529The number of floating point operations executed that needed 530a microcode assist. 531.It Li FP_COMP_OPS_EXE 532.Pq Event 10H , Umask 00H 533The number of floating point computational micro-ops executed. 534The event is available only on PMC0. 535.It Li FP_MMX_TRANS_TO_FP 536.Pq Event CCH , Umask 02H 537The number of transitions from MMX instructions to floating point 538instructions. 539.It Li FP_MMX_TRANS_TO_MMX 540.Pq Event CCH , Umask 01H 541The number of transitions from floating point instructions to MMX 542instructions. 543.It Li HW_INT_RCV 544.Pq Event C8H , Umask 00H 545The number of hardware interrupts received. 546.It Li IDLE_DURING_DIV 547.Pq Event 18H , Umask 00H 548The number of cycles the divider is busy and no other execution unit 549or load operation was in progress. 550This event is available only on PMC0. 551.It Li ILD_STALL 552.Pq Event 87H , Umask 00H 553The number of cycles the instruction length decoder stalled due to a 554length changing prefix. 555.It Li INST_QUEUE.FULL 556.Pq Event 83H , Umask 02H 557The number of cycles during which the instruction queue is full. 558.It Li INST_RETIRED.ANY_P 559.Pq Event C0H , Umask 00H 560.Pq Alias Qq "Instruction Retired" 561The number of instructions retired. 562This is an architectural performance event. 563.It Li INST_RETIRED.LOADS 564.Pq Event C0H , Umask 01H 565The number of instructions retired that contained a load operation. 566.It Li INST_RETIRED.OTHER 567.Pq Event C0H , Umask 04H 568The number of instructions retired that did not contain a load or a 569store operation. 570.It Li INST_RETIRED.STORES 571.Pq Event C0H , Umask 02H 572The number of instructions retired that contained a store operation. 573.It Li INST_RETIRED.VM_H 574.Pq Event C0H , Umask 08H 575.Pq Tn Core2Extreme 576The number of instructions retired while in VMX root operation. 577.It Li ITLB.FLUSH 578.Pq Event 82H , Umask 40H 579The number of ITLB flushes. 580.It Li ITLB.LARGE_MISS 581.Pq Event 82H , Umask 10H 582The number of instruction fetches from large pages that miss the 583ITLB. 584.It Li ITLB.MISSES 585.Pq Event 82H , Umask 12H 586The number of instruction fetches from both large and small pages that 587miss the ITLB. 588.It Li ITLB.SMALL_MISS 589.Pq Event 82H , Umask 02H 590The number of instruction fetches from small pages that miss the ITLB. 591.It Li ITLB_MISS_RETIRED 592.Pq Event C9H , Umask 00H 593The number of retired instructions that missed the ITLB when they were 594fetched. 595.It Li L1D_ALL_REF 596.Pq Event 43H , Umask 01H 597The number of references to L1 data cache counting loads and stores of 598to all memory types. 599.It Li L1D_ALL_CACHE_REF 600.Pq Event 43H , Umask 02H 601The number of data reads and writes to cacheable memory. 602.It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state 603.Pq Event 42H 604The number of locked reads from cacheable memory. 605.It Li L1D_CACHE_LOCK_DURATION 606.Pq Event 42H , Umask 10H 607The number of cycles during which any cache line is locked by any 608locking instruction. 609.It Li L1D_CACHE_LD Op ,cachestate= Ns Ar state 610.Pq Event 40H 611The number of data reads from cacheable memory excluding locked 612reads. 613.It Li L1D_CACHE_ST Op ,cachestate= Ns Ar state 614.Pq Event 41H 615The number of data writes to cacheable memory excluding locked 616writes. 617.It Li L1D_M_EVICT 618.Pq Event 47H , Umask 00H 619The number of modified cache lines evicted from L1 data cache. 620.It Li L1D_M_REPL 621.Pq Event 46H , Umask 00H 622The number of modified lines allocated in L1 data cache. 623.It Li L1D_PEND_MISS 624.Pq Event 48H , Umask 00H 625The total number of outstanding L1 data cache misses at any clock. 626.It Li L1D_PREFETCH.REQUESTS 627.Pq Event 4EH , Umask 10H 628The number of times L1 data cache requested to prefetch a data cache 629line. 630.It Li L1D_REPL 631.Pq Event 45H , Umask 0FH 632The number of lines brought into L1 data cache. 633.It Li L1D_SPLIT.LOADS 634.Pq Event 49H , Umask 01H 635The number of load operations that span two cache lines. 636.It Li L1D_SPLIT.STORES 637.Pq Event 49H , Umask 02H 638The number of store operations that span two cache lines. 639.It Li L1I_MISSES 640.Pq Event 81H , Umask 00H 641The number of instruction fetch unit misses. 642.It Li L1I_READS 643.Pq Event 80H , Umask 00H 644The number of instruction fetches. 645.It Li L2_ADS Op ,core= Ns core 646.Pq Event 21H 647The number of cycles that the L2 address bus is in use. 648.It Li L2_DBUS_BUSY_RD Op ,core= Ns core 649.Pq Event 23H 650The number of cycles during which the L2 data bus is busy transferring 651data to the core. 652.It Li L2_IFETCH Xo 653.Op ,cachestate= Ns Ar state 654.Op ,core= Ns Ar core 655.Xc 656.Pq Event 28H 657The number of instruction cache line requests from the instruction 658fetch unit. 659.It Li L2_LD Xo 660.Op ,cachestate= Ns Ar state 661.Op ,core= Ns Ar core 662.Op ,prefetch= Ns Ar prefetch 663.Xc 664.Pq Event 29H 665The number of L2 cache read requests from L1 cache and L2 666prefetchers. 667.It Li L2_LINES_IN Xo 668.Op ,core= Ns Ar core 669.Op ,prefetch= Ns Ar prefetch 670.Xc 671.Pq Event 24H 672The number of cache lines allocated in L2 cache. 673.It Li L2_LINES_OUT Xo 674.Op ,core= Ns Ar core 675.Op ,prefetch= Ns Ar prefetch 676.Xc 677.Pq Event 26H 678The number of L2 cache lines evicted. 679.It Li L2_LOCK Xo 680.Op ,cachestate= Ns Ar state 681.Op ,core= Ns Ar core 682.Xc 683.Pq Event 2BH 684The number of locked accesses to cache lines that miss L1 data 685cache. 686.It Li L2_M_LINES_IN Op ,core= Ns Ar core 687.Pq Event 25H 688The number of L2 cache line modifications. 689.It Li L2_M_LINES_OUT Xo 690.Op ,core= Ns Ar core 691.Op ,prefetch= Ns Ar prefetch 692.Xc 693.Pq Event 27H 694The number of modified lines evicted from L2 cache. 695.It Li L2_NO_REQ Op ,core= Ns Ar core 696.Pq Event 32H 697The number of cycles during which no L2 cache requests were pending 698from a core. 699.It Li L2_REJECT_BUSQ Xo 700.Op ,cachestate= Ns Ar state 701.Op ,core= Ns Ar core 702.Op ,prefetch= Ns Ar prefetch 703.Xc 704.Pq Event 30H 705The number of L2 cache requests that were rejected. 706.It Li L2_RQSTS Xo 707.Op ,cachestate= Ns Ar state 708.Op ,core= Ns Ar core 709.Op ,prefetch= Ns Ar prefetch 710.Xc 711.Pq Event 2EH 712The number of completed L2 cache requests. 713.It Li L2_RQSTS.SELF.DEMAND.I_STATE 714.Pq Event 2EH , Umask 41H 715.Pq Alias Qq "LLC Misses" 716The number of completed L2 cache demand requests from this core that 717missed the L2 cache. 718This is an architectural performance event. 719.It Li L2_RQSTS.SELF.DEMAND.MESI 720.Pq Event 2EH , Umask 4FH 721.Pq Alias Qq "LLC References" 722The number of completed L2 cache demand requests from this core. 723This is an architectural performance event. 724.It Li L2_ST Xo 725.Op ,cachestate= Ns Ar state 726.Op ,core= Ns Ar core 727.Xc 728.Pq Event 2AH 729The number of store operations that miss the L1 cache and request data 730from the L2 cache. 731.It Li LOAD_BLOCK.L1D 732.Pq Event 03H , Umask 20H 733The number of loads blocked by the L1 data cache. 734.It Li LOAD_BLOCK.OVERLAP_STORE 735.Pq Event 03H , Umask 08H 736The number of loads that partially overlap an earlier store or are 737aliased with a previous store. 738.It Li LOAD_BLOCK.STA 739.Pq Event 03H , Umask 02H 740The number of loads blocked by preceding stores whose address is yet 741to be calculated. 742.It Li LOAD_BLOCK.STD 743.Pq Event 03H , Umask 04H 744The number of loads blocked by preceding stores to the same address 745whose data value is not known. 746.It Li LOAD_BLOCK.UNTIL_RETIRE 747.Pq Event 03H , Umask 10H 748The number of load operations that were blocked until retirement. 749.It Li LOAD_HIT_PRE 750.Pq Event 4CH , Umask 00H 751The number of load operations that conflicted with an prefetch to the 752same cache line. 753.It Li MACHINE_NUKES.SMC 754.Pq Event C3H , Umask 01H 755The number of times a program writes to a code section. 756.It Li MACHINE_NUKES.MEM_ORDER 757.Pq Event C3H , Umask 04H 758The number of times the execution pipeline was restarted due to a 759memory ordering conflict or memory disambiguation misprediction. 760.It Li MACRO_INSTS.CISC_DECODED 761.Pq Event AAH , Umask 08H 762The number of complex instructions decoded. 763.It Li MACRO_INSTS.DECODED 764.Pq Event AAH , Umask 01H 765The number of instructions decoded. 766.It Li MEMORY_DISAMBIGUATION.RESET 767.Pq Event 09H , Umask 01H 768The number of cycles during which memory disambiguation misprediction 769occurs. 770.It Li MEMORY_DISAMBIGUATION.SUCCESS 771.Pq Event 09H , Umask 02H 772The number of load operations that were successfully disambiguated. 773.It Li MEM_LOAD_RETIRED.DTLB_MISS 774.Pq Event CBH , Umask 10H 775The number of retired loads that missed the DTLB. 776.It Li MEM_LOAD_RETIRED.L1D_LINE_MISS 777.Pq Event CBH , Umask 02H 778The number of retired load operations that missed L1 data cache and 779that sent a request to L2 cache. 780This event is only available on PMC0. 781.It Li MEM_LOAD_RETIRED.L1D_MISS 782.Pq Event CBH , Umask 01H 783The number of retired load operations that missed L1 data cache. 784This event is only available on PMC0. 785.It Li MEM_LOAD_RETIRED.L2_LINE_MISS 786.Pq Event CBH , Umask 08H 787The number of load operations that missed L2 cache and that caused a 788bus request. 789.It Li MEM_LOAD_RETIRED.L2_MISS 790.Pq Event CBH , Umask 04H 791The number of load operations that missed L2 cache. 792.It Li MUL 793.Pq Event 12H , Umask 00H 794The number of multiply operations executed. 795This event is only available on PMC1. 796.It Li PAGE_WALKS.COUNT 797.Pq Event 0CH , Umask 01H 798The number of page walks executed due to an ITLB or DTLB miss. 799.It Li PAGE_WALKS.CYCLES 800.Pq Event 0CH , Umask 02H 801The number of cycles spent in a page walk caused by an ITLB or DTLB 802miss. 803.It Li PREF_RQSTS_DN 804.Pq Event F8H , Umask 00H 805The number of downward prefetches issued from the Data Prefetch Logic 806unit to L2 cache. 807.It Li PREF_RQSTS_UP 808.Pq Event F0H , Umask 00H 809The number of upward prefetches issued from the Data Prefetch Logic 810unit to L2 cache. 811.It Li RAT_STALLS.ANY 812.Pq Event D2H , Umask 0FH 813The number of stall cycles due to any of 814.Li RAT_STALLS.FLAGS 815.Li RAT_STALLS.FPSW , 816.Li RAT_STALLS.PARTIAL 817and 818.Li RAT_STALLS.ROB_READ_PORT . 819.It Li RAT_STALLS.FLAGS 820.Pq Event D2H , Umask 04H 821The number of cycles execution stalled due to a flag register induced 822stall. 823.It Li RAT_STALLS.FPSW 824.Pq Event D2H , Umask 08H 825The number of times the floating point status word was written. 826.It Li RAT_STALLS.OTHER_SERIALIZATION_STALLS 827.Pq Event D2H , Umask 10H , Tn Core2Extreme 828The number of stalls due to other RAT resource serialization not 829counted by umask 0FH. 830.It Li RAT_STALLS.PARTIAL_CYCLES 831.Pq Event D2H , Umask 02H 832The number of cycles of added instruction execution latency due to the 833use of a register that was partially written by previous instructions. 834.It Li RAT_STALLS.ROB_READ_PORT 835.Pq Event D2H , Umask 01H 836The number of cycles when ROB read port stalls occurred. 837.It Li RESOURCE_STALLS.ANY 838.Pq Event DCH , Umask 1FH 839The number of cycles during which any resource related stall 840occurred. 841.It Li RESOURCE_STALLS.BR_MISS_CLEAR 842.Pq Event DCH , Umask 10H 843The number of cycles stalled due to branch misprediction. 844.It Li RESOURCE_STALLS.FPCW 845.Pq Event DCH , Umask 08H 846The number of cycles stalled due to writing the floating point control 847word. 848.It Li RESOURCE_STALLS.LD_ST 849.Pq Event DCH , Umask 04H 850The number of cycles during which the number of loads and stores in 851the pipeline exceeded their limits. 852.It Li RESOURCE_STALLS.ROB_FULL 853.Pq Event DCH , Umask 01H 854The number of cycles when the reorder buffer was full. 855.It Li RESOURCE_STALLS.RS_FULL 856.Pq Event DCH , Umask 02H 857The number of cycles during which the RS was full. 858.It Li RS_UOPS_DISPATCHED 859.Pq Event A0H , Umask 00H 860The number of micro-ops dispatched for execution. 861.It Li RS_UOPS_DISPATCHED.PORT0 862.Pq Event A1H , Umask 01H 863The number of cycles micro-ops were dispatched for execution on port 8640. 865.It Li RS_UOPS_DISPATCHED.PORT1 866.Pq Event A1H , Umask 02H 867The number of cycles micro-ops were dispatched for execution on port 8681. 869.It Li RS_UOPS_DISPATCHED.PORT2 870.Pq Event A1H , Umask 04H 871The number of cycles micro-ops were dispatched for execution on port 8722. 873.It Li RS_UOPS_DISPATCHED.PORT3 874.Pq Event A1H , Umask 08H 875The number of cycles micro-ops were dispatched for execution on port 8763. 877.It Li RS_UOPS_DISPATCHED.PORT4 878.Pq Event A1H , Umask 10H 879The number of cycles micro-ops were dispatched for execution on port 8804. 881.It Li RS_UOPS_DISPATCHED.PORT5 882.Pq Event A1H , Umask 20H 883The number of cycles micro-ops were dispatched for execution on port 8845. 885.It Li SB_DRAIN_CYCLES 886.Pq Event 04H , Umask 01H 887The number of cycles while the store buffer is draining. 888.It Li SEGMENT_REG_LOADS 889.Pq Event 06H , Umask 00H 890The number of segment register loads. 891.It Li SEG_REG_RENAMES.ANY 892.Pq Event D5H , Umask 0FH 893The number of times the any segment register was renamed. 894.It Li SEG_REG_RENAMES.DS 895.Pq Event D5H , Umask 02H 896The number of times the 897.Li %ds 898register is renamed. 899.It Li SEG_REG_RENAMES.ES 900.Pq Event D5H , Umask 01H 901The number of times the 902.Li %es 903register is renamed. 904.It Li SEG_REG_RENAMES.FS 905.Pq Event D5H , Umask 04H 906The number of times the 907.Li %fs 908register is renamed. 909.It Li SEG_REG_RENAMES.GS 910.Pq Event D5H , Umask 08H 911The number of times the 912.Li %gs 913register is renamed. 914.It Li SEG_RENAME_STALLS.ANY 915.Pq Event D4H , Umask 0FH 916The number of stalls due to lack of resource to rename any segment 917register. 918.It Li SEG_RENAME_STALLS.DS 919.Pq Event D4H , Umask 02H 920The number of stalls due to lack of renaming resources for the 921.Li %ds 922register. 923.It Li SEG_RENAME_STALLS.ES 924.Pq Event D4H , Umask 01H 925The number of stalls due to lack of renaming resources for the 926.Li %es 927register. 928.It Li SEG_RENAME_STALLS.FS 929.Pq Event D4H , Umask 04H 930The number of stalls due to lack of renaming resources for the 931.Li %fs 932register. 933.It Li SEG_RENAME_STALLS.GS 934.Pq Event D4H , Umask 08H 935The number of stalls due to lack of renaming resources for the 936.Li %gs 937register. 938.It Li SIMD_ASSIST 939.Pq Event CDH , Umask 00H 940The number SIMD assists invoked. 941.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE 942.Pq Event CAH , Umask 04H 943Then number of computational SSE2 packed double precision instructions 944retired. 945.It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE 946.Pq Event CAH , Umask 01H 947Then number of computational SSE2 packed single precision instructions 948retired. 949.It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE 950.Pq Event CAH , Umask 08H 951Then number of computational SSE2 scalar double precision instructions 952retired. 953.It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE 954.Pq Event CAH , Umask 02H 955Then number of computational SSE2 scalar single precision instructions 956retired. 957.It Li SIMD_INSTR_RETIRED 958.Pq Event CEH , Umask 00H 959The number of retired SIMD instructions that use MMX registers. 960.It Li SIMD_INST_RETIRED.ANY 961.Pq Event C7H , Umask 1FH 962The number of streaming SIMD instructions retired. 963.It Li SIMD_INST_RETIRED.PACKED_DOUBLE 964.Pq Event C7H , Umask 04H 965The number of SSE2 packed double precision instructions retired. 966.It Li SIMD_INST_RETIRED.PACKED_SINGLE 967.Pq Event C7H , Umask 01H 968The number of SSE packed single precision instructions retired. 969.It Li SIMD_INST_RETIRED.SCALAR_DOUBLE 970.Pq Event C7H , Umask 08H 971The number of SSE2 scalar double precision instructions retired. 972.It Li SIMD_INST_RETIRED.SCALAR_SINGLE 973.Pq Event C7H , Umask 02H 974The number of SSE scalar single precision instructions retired. 975.It Li SIMD_INST_RETIRED.VECTOR 976.Pq Event C7H , Umask 10H 977The number of SSE2 vector instructions retired. 978.It Li SIMD_SAT_INSTR_RETIRED 979.Pq Event CFH , Umask 00H 980The number of saturated arithmetic SIMD instructions retired. 981.It Li SIMD_SAT_UOP_EXEC 982.Pq Event B1H , Umask 00H 983The number of SIMD saturated arithmetic micro-ops executed. 984.It Li SIMD_UOPS_EXEC 985.Pq Event B0H , Umask 00H 986The number of SIMD micro-ops executed. 987.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC 988.Pq Event B3H , Umask 20H 989The number of SIMD packed arithmetic micro-ops executed. 990.It Li SIMD_UOP_TYPE_EXEC.LOGICAL 991.Pq Event B3H , Umask 10H 992The number of SIMD packed logical micro-ops executed. 993.It Li SIMD_UOP_TYPE_EXEC.MUL 994.Pq Event B3H , Umask 01H 995The number of SIMD packed multiply micro-ops executed. 996.It Li SIMD_UOP_TYPE_EXEC.PACK 997.Pq Event B3H , Umask 04H 998The number of SIMD pack micro-ops executed. 999.It Li SIMD_UOP_TYPE_EXEC.SHIFT 1000.Pq Event B3H , Umask 02H 1001The number of SIMD packed shift micro-ops executed. 1002.It Li SIMD_UOP_TYPE_EXEC.UNPACK 1003.Pq Event B3H , Umask 08H 1004The number of SIMD unpack micro-ops executed. 1005.It Li SNOOP_STALL_DRV Xo 1006.Op ,agent= Ns Ar agent 1007.Op ,core= Ns Ar core 1008.Xc 1009.Pq Event 7EH 1010The number of times the bus stalled for snoops. 1011.It Li SSE_PRE_EXEC.L1 1012.Pq Event 07H , Umask 01H 1013The number of 1014.Li PREFETCHT0 1015instructions executed. 1016.It Li SSE_PRE_EXEC.L2 1017.Pq Event 07H , Umask 02H 1018The number of 1019.Li PREFETCHT1 1020instructions executed. 1021.It Li SSE_PRE_EXEC.NTA 1022.Pq Event 07H , Umask 00H 1023The number of 1024.Li PREFETCHNTA 1025instructions executed. 1026.It Li SSE_PRE_EXEC.STORES 1027.Pq Event 07H , Umask 03H 1028The number of times SSE non-temporal store instructions were executed. 1029.It Li SSE_PRE_MISS.L1 1030.Pq Event 4BH , Umask 01H 1031The number of times the 1032.Li PREFETCHT0 1033instruction executed and missed all cache levels. 1034.It Li SSE_PRE_MISS.L2 1035.Pq Event 4BH , Umask 02H 1036The number of times the 1037.Li PREFETCHT1 1038instruction executed and missed all cache levels. 1039.It Li SSE_PRE_MISS.NTA 1040.Pq Event 4BH , Umask 00H 1041The number of times the 1042.Li PREFETCHNTA 1043instruction executed and missed all cache levels. 1044.It Li STORE_BLOCK.ORDER 1045.Pq Event 04H , Umask 02H 1046The number of cycles while a store was waiting for another store to be 1047globally observed. 1048.It Li STORE_BLOCK.SNOOP 1049.Pq Event 04H , Umask 08H 1050The number of cycles while a store was blocked due to a conflict with 1051an internal or external snoop. 1052.It Li THERMAL_TRIP 1053.Pq Event 3BH , Umask C0H 1054The number of thermal trips. 1055.It Li UOPS_RETIRED.LD_IND_BR 1056.Pq Event C2H , Umask 01H 1057The number of micro-ops retired that fused a load with another 1058operation. 1059.It Li UOPS_RETIRED.STD_STA 1060.Pq Event C2H , Umask 02H 1061The number of store address calculations that fused into one micro-op. 1062.It Li UOPS_RETIRED.MACRO_FUSION 1063.Pq Event C2H , Umask 04H 1064The number of times retired instruction pairs were fused into one 1065micro-op. 1066.It Li UOPS_RETIRED.FUSED 1067.Pq Event C2H , Umask 07H 1068The number of fused micro-ops retired. 1069.It Li UOPS_RETIRED.NON_FUSED 1070.Pq Event C2H , Umask 8H 1071The number of non-fused micro-ops retired. 1072.It Li UOPS_RETIRED.ANY 1073.Pq Event C2H , Umask 0FH 1074The number of micro-ops retired. 1075.It Li X87_OPS_RETIRED.ANY 1076.Pq Event C1H , Umask FEH 1077The number of floating point computational instructions retired. 1078.It Li X87_OPS_RETIRED.FXCH 1079.Pq Event C1H , Umask 01H 1080The number of 1081.Li FXCH 1082instructions retired. 1083.El 1084.Ss Event Name Aliases 1085The following table shows the mapping between the PMC-independent 1086aliases supported by 1087.Lb libpmc 1088and the underlying hardware events used. 1089.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class" 1090.It Em Alias Ta Em Event Ta Em PMC Class 1091.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP 1092.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP 1093.It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP 1094.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF 1095.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP 1096.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF 1097.El 1098.Sh SEE ALSO 1099.Xr pmc 3 , 1100.Xr pmc.amd 3 , 1101.Xr pmc.atom 3 , 1102.Xr pmc.core 3 , 1103.Xr pmc.iaf 3 , 1104.Xr pmc.soft 3 , 1105.Xr pmc.tsc 3 , 1106.Xr pmc_cpuinfo 3 , 1107.Xr pmclog 3 , 1108.Xr hwpmc 4 1109.Sh HISTORY 1110The 1111.Nm pmc 1112library first appeared in 1113.Fx 6.0 . 1114.Sh AUTHORS 1115The 1116.Lb libpmc 1117library was written by 1118.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1119