1.\" Copyright (c) 2008,2009 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd June 8, 2009 27.Dt PMC.CORE2 3 28.Os 29.Sh NAME 30.Nm pmc.core2 31.Nd measurement events for 32.Tn Intel 33.Tn Core2 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core2" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs may contain up to two classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Core2 PMCs are documented in 59.Rs 60.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 61.%T "Volume 3: System Programming Guide" 62.%N "Order Number 253669-027US" 63.%D July 2008 64.%Q "Intel Corporation" 65.Re 66.Ss CORE2 FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69Not all CPUs in this family implement fixed-function counters. 70.Ss CORE2 PROGRAMMABLE PMCS 71The programmable PMCs support the following capabilities: 72.Bl -column "PMC_CAP_INTERRUPT" "Support" 73.It Em Capability Ta Em Support 74.It PMC_CAP_CASCADE Ta \&No 75.It PMC_CAP_EDGE Ta Yes 76.It PMC_CAP_INTERRUPT Ta Yes 77.It PMC_CAP_INVERT Ta Yes 78.It PMC_CAP_READ Ta Yes 79.It PMC_CAP_PRECISE Ta \&No 80.It PMC_CAP_SYSTEM Ta Yes 81.It PMC_CAP_TAGGING Ta \&No 82.It PMC_CAP_THRESHOLD Ta Yes 83.It PMC_CAP_USER Ta Yes 84.It PMC_CAP_WRITE Ta Yes 85.El 86.Ss Event Qualifiers 87Event specifiers for these PMCs support the following common 88qualifiers: 89.Bl -tag -width indent 90.It Li cmask= Ns Ar value 91Configure the PMC to increment only if the number of configured 92events measured in a cycle is greater than or equal to 93.Ar value . 94.It Li edge 95Configure the PMC to count the number of de-asserted to asserted 96transitions of the conditions expressed by the other qualifiers. 97If specified, the counter will increment only once whenever a 98condition becomes true, irrespective of the number of clocks during 99which the condition remains true. 100.It Li inv 101Invert the sense of comparison when the 102.Dq Li cmask 103qualifier is present, making the counter increment when the number of 104events per cycle is less than the value specified by the 105.Dq Li cmask 106qualifier. 107.It Li os 108Configure the PMC to count events happening at processor privilege 109level 0. 110.It Li usr 111Configure the PMC to count events occurring at privilege levels 1, 2 112or 3. 113.El 114.Pp 115If neither of the 116.Dq Li os 117or 118.Dq Li usr 119qualifiers are specified, the default is to enable both. 120.Pp 121Events that require core-specificity to be specified use a 122additional qualifier 123.Dq Li core= Ns Ar core , 124where argument 125.Ar core 126is one of: 127.Bl -tag -width indent 128.It Li all 129Measure event conditions on all cores. 130.It Li this 131Measure event conditions on this core. 132.El 133.Pp 134The default is 135.Dq Li this . 136.Pp 137Events that require an agent qualifier to be specified use an 138additional qualifier 139.Dq Li agent= Ns agent , 140where argument 141.Ar agent 142is one of: 143.Bl -tag -width indent 144.It Li this 145Measure events associated with this bus agent. 146.It Li any 147Measure events caused by any bus agent. 148.El 149.Pp 150The default is 151.Dq Li this . 152.Pp 153Events that require a hardware prefetch qualifier to be specified use an 154additional qualifier 155.Dq Li prefetch= Ns Ar prefetch , 156where argument 157.Ar prefetch 158is one of: 159.Bl -tag -width "exclude" 160.It Li both 161Include all prefetches. 162.It Li only 163Only count hardware prefetches. 164.It Li exclude 165Exclude hardware prefetches. 166.El 167.Pp 168The default is 169.Dq Li both . 170.Pp 171Events that require a cache coherence qualifier to be specified use an 172additional qualifier 173.Dq Li cachestate= Ns Ar state , 174where argument 175.Ar state 176contains one or more of the following letters: 177.Bl -tag -width indent 178.It Li e 179Count cache lines in the exclusive state. 180.It Li i 181Count cache lines in the invalid state. 182.It Li m 183Count cache lines in the modified state. 184.It Li s 185Count cache lines in the shared state. 186.El 187.Pp 188The default is 189.Dq Li eims . 190.Pp 191Events that require a snoop response qualifier to be specified use an 192additional qualifier 193.Dq Li snoopresponse= Ns Ar response , 194where argument 195.Ar response 196comprises of the following keywords separated by 197.Dq + 198signs: 199.Bl -tag -width indent 200.It Li clean 201Measure CLEAN responses. 202.It Li hit 203Measure HIT responses. 204.It Li hitm 205Measure HITM responses. 206.El 207.Pp 208The default is to measure all the above responses. 209.Pp 210Events that require a snoop type qualifier use an additional qualifier 211.Dq Li snooptype= Ns Ar type , 212where argument 213.Ar type 214comprises the one of the following keywords: 215.Bl -tag -width indent 216.It Li cmp2i 217Measure CMP2I snoops. 218.It Li cmp2s 219Measure CMP2S snoops. 220.El 221.Pp 222The default is to measure both snoops. 223.Ss Event Specifiers (Programmable PMCs) 224Core2 programmable PMCs support the following events: 225.Bl -tag -width indent 226.It Li BACLEARS 227.Pq Event E6H , Umask 00H 228The number of times the front end is resteered. 229.It Li BOGUS_BR 230.Pq Event E4H , Umask 00H 231The number of byte sequences mistakenly detected as taken branch 232instructions. 233.It Li BR_BAC_MISSP_EXEC 234.Pq Event 8AH , Umask 00H 235The number of branch instructions that were mispredicted when 236decoded. 237.It Li BR_CALL_MISSP_EXEC 238.Pq Event 93H , Umask 00H 239The number of mispredicted 240.Li CALL 241instructions that were executed. 242.It Li BR_CALL_EXEC 243.Pq Event 92H , Umask 00H 244The number of 245.Li CALL 246instructions executed. 247.It Li BR_CND_EXEC 248.Pq Event 8BH , Umask 00H 249The number of conditional branches executed, but not necessarily retired. 250.It Li BR_CND_MISSP_EXEC 251.Pq Event 8CH , Umask 00H 252The number of mispredicted conditional branches executed. 253.It Li BR_IND_CALL_EXEC 254.Pq Event 94H , Umask 00H 255The number of indirect 256.Li CALL 257instructions executed. 258.It Li BR_IND_EXEC 259.Pq Event 8DH , Umask 00H 260The number of indirect branch instructions executed. 261.It Li BR_IND_MISSP_EXEC 262.Pq Event 8EH , Umask 00H 263The number of mispredicted indirect branch instructions executed. 264.It Li BR_INST_DECODED 265.Pq Event E0H , Umask 00H 266The number of branch instructions decoded. 267.It Li BR_INST_EXEC 268.Pq Event 88H , Umask 00H 269The number of branches executed, but not necessarily retired. 270.It Li BR_INST_RETIRED.ANY 271.Pq Event C4H , Umask 00H 272.Pq Alias Qq "Branch Instruction Retired" 273The number of branch instructions retired. 274This is an architectural performance event. 275.It Li BR_INST_RETIRED.MISPRED 276.Pq Event C5H , Umask 00H 277.Pq Alias Qq "Branch Misses Retired" 278The number of mispredicted branch instructions retired. 279This is an architectural performance event. 280.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN 281.Pq Event C4H , Umask 02H 282The number of not taken branch instructions retired that were 283mispredicted. 284.It Li BR_INST_RETIRED.MISPRED_TAKEN 285.Pq Event C4H , Umask 08H 286The number taken branch instructions retired that were mispredicted. 287.It Li BR_INST_RETIRED.PRED_NOT_TAKEN 288.Pq Event C4H , Umask 01H 289The number of not taken branch instructions retired that were 290correctly predicted. 291.It Li BR_INST_RETIRED.PRED_TAKEN 292.Pq Event C4H , Umask 04H 293The number of taken branch instructions retired that were correctly 294predicted. 295.It Li BR_INST_RETIRED.TAKEN 296.Pq Event C4H , Umask 0CH 297The number of taken branch instructions retired. 298.It Li BR_MISSP_EXEC 299.Pq Event 89H , Umask 00H 300The number of mispredicted branch instructions that were executed. 301.It Li BR_RET_MISSP_EXEC 302.Pq Event 90H , Umask 00H 303The number of mispredicted 304.Li RET 305instructions executed. 306.It Li BR_RET_BAC_MISSP_EXEC 307.Pq Event 91H , Umask 00H 308The number of 309.Li RET 310instructions executed that were mispredicted at decode time. 311.It Li BR_RET_EXEC 312.Pq Event 8FH , Umask 00H 313The number of 314.Li RET 315instructions executed. 316.It Li BR_TKN_BUBBLE_1 317.Pq Event 97H , Umask 00H 318The number of branch predicted taken with bubble 1. 319.It Li BR_TKN_BUBBLE_2 320.Pq Event 98H , Umask 00H 321The number of branch predicted taken with bubble 2. 322.It Li BUSQ_EMPTY Op ,core= Ns Ar core 323.Pq Event 7DH 324The number of cycles during which the core did not have any pending 325transactions in the bus queue. 326.It Li BUS_BNR_DRV Op ,agent= Ns Ar agent 327.Pq Event 61H 328The number of Bus Not Ready signals asserted on the bus. 329.It Li BUS_DATA_RCV Op ,core= Ns Ar core 330.Pq Event 64H 331The number of bus cycles during which the processor is receiving data. 332.It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent 333.Pq Event 62H 334The number of bus cycles during which the Data Ready signal is asserted 335on the bus. 336.It Li BUS_HIT_DRV Op ,agent= Ns Ar agent 337.Pq Event 7AH 338The number of bus cycles during which the processor drives the 339.Li HIT# 340pin. 341.It Li BUS_HITM_DRV Op ,agent= Ns Ar agent 342.Pq Event 7BH 343The number of bus cycles during which the processor drives the 344.Li HITM# 345pin. 346.It Li BUS_IO_WAIT Op ,core= Ns Ar core 347.Pq Event 7FH 348The number of core cycles during which I/O requests wait in the bus 349queue. 350.It Li BUS_LOCK_CLOCKS Xo 351.Op ,agent= Ns Ar agent 352.Op ,core= Ns Ar core 353.Xc 354.Pq Event 63H 355The number of bus cycles during which the 356.Li LOCK 357signal was asserted on the bus. 358.It Li BUS_REQUEST_OUTSTANDING Xo 359.Op ,agent= Ns Ar agent 360.Op ,core= Ns Ar core 361.Xc 362.Pq Event 60H 363The number of pending full cache line read transactions on the bus 364occurring in each cycle. 365.It Li BUS_TRANS_P Xo 366.Op ,agent= Ns Ar agent 367.Op ,core= Ns Ar core 368.Xc 369.Pq Event 6BH 370The number of partial bus transactions. 371.It Li BUS_TRANS_IFETCH Xo 372.Op ,agent= Ns Ar agent 373.Op ,core= Ns Ar core 374.Xc 375.Pq Event 68H 376The number of instruction fetch full cache line bus transactions. 377.It Li BUS_TRANS_INVAL Xo 378.Op ,agent= Ns Ar agent 379.Op ,core= Ns Ar core 380.Xc 381.Pq Event 69H 382The number of invalidate bus transactions. 383.It Li BUS_TRANS_PWR Xo 384.Op ,agent= Ns Ar agent 385.Op ,core= Ns Ar core 386.Xc 387.Pq Event 6AH 388The number of partial write bus transactions. 389.It Li BUS_TRANS_DEF Xo 390.Op ,agent= Ns Ar agent 391.Op ,core= Ns Ar core 392.Xc 393.Pq Event 6DH 394The number of deferred bus transactions. 395.It Li BUS_TRANS_BURST Xo 396.Op ,agent= Ns Ar agent 397.Op ,core= Ns Ar core 398.Xc 399.Pq Event 6EH 400The number of burst transactions. 401.It Li BUS_TRANS_MEM Xo 402.Op ,agent= Ns Ar agent 403.Op ,core= Ns Ar core 404.Xc 405.Pq Event 6FH 406The number of memory bus transactions. 407.It Li BUS_TRANS_ANY Xo 408.Op ,agent= Ns Ar agent 409.Op ,core= Ns Ar core 410.Xc 411.Pq Event 70H 412The number of bus transactions of any kind. 413.It Li BUS_TRANS_BRD Xo 414.Op ,agent= Ns Ar agent 415.Op ,core= Ns Ar core 416.Xc 417.Pq Event 65H 418The number of burst read transactions. 419.It Li BUS_TRANS_IO Xo 420.Op ,agent= Ns Ar agent 421.Op ,core= Ns Ar core 422.Xc 423.Pq Event 6CH 424The number of completed I/O bus transactions due to 425.Li IN 426and 427.Li OUT 428instructions. 429.It Li BUS_TRANS_RFO Xo 430.Op ,agent= Ns Ar agent 431.Op ,core= Ns Ar core 432.Xc 433.Pq Event 66H 434The number of Read For Ownership bus transactions. 435.It Li BUS_TRANS_WB Xo 436.Op ,agent= Ns Ar agent 437.Op ,core= Ns Ar core 438.Xc 439.Pq Event 67H 440The number explicit write-back bus transactions due to dirty line 441evictions. 442.It Li CMP_SNOOP Xo 443.Op ,core= Ns Ar core 444.Op ,snooptype= Ns Ar snoop 445.Xc 446.Pq Event 78H 447The number of times the L1 data cache is snooped by the other core in 448the same processor. 449.It Li CPU_CLK_UNHALTED.BUS 450.Pq Event 3CH , Umask 01H 451.Pq Alias Qq "Unhalted Reference Cycles" 452The number of bus cycles when the core is not in the halt state. 453This is an architectural performance event. 454.It Li CPU_CLK_UNHALTED.CORE_P 455.Pq Event 3CH , Umask 00H 456.Pq Alias Qq "Unhalted Core Cycles" 457The number of core cycles while the core is not in a halt state. 458This is an architectural performance event. 459.It Li CPU_CLK_UNHALTED.NO_OTHER 460.Pq Event 3CH , Umask 02H 461The number of bus cycles during which the core remains unhalted and 462the other core is halted. 463.It Li CYCLES_DIV_BUSY 464.Pq Event 14H , Umask 00H 465The number of cycles the divider is busy. 466This event is only available on PMC0. 467.It Li CYCLES_INT_MASKED 468.Pq Event C6H , Umask 01H 469The number of cycles during which interrupts are disabled. 470.It Li CYCLES_INT_PENDING_AND_MASKED 471.Pq Event C6H , Umask 02H 472The number of cycles during which there were pending interrupts while 473interrupts were disabled. 474.It Li CYCLES_L1I_MEM_STALLED 475.Pq Event 86H , Umask 00H 476The number of cycles for which an instruction fetch stalls. 477.It Li DELAYED_BYPASS.FP 478.Pq Event 19H , Umask 00H 479The number of floating point operations that used data immediately 480after the data was generated by a non floating point execution unit. 481.It Li DELAYED_BYPASS.LOAD 482.Pq Event 19H , Umask 01H 483The number of delayed bypass penalty cycles that a load operation incurred. 484.It Li DELAYED_BYPASS.SIMD 485.Pq Event 19H , Umask 02H 486The number of times SIMD operations use data immediately after data, 487was generated by a non-SIMD execution unit. 488.It Li DIV 489.Pq Event 13H , Umask 00H 490The number of divide operations executed. 491This event is only available on PMC1. 492.It Li DTLB_MISSES.ANY 493.Pq Event 08H , Umask 01H 494The number of Data TLB misses, including misses that result from 495speculative accesses. 496.It Li DTLB_MISSES.L0_MISS_LD 497.Pq Event 08H , Umask 04H 498The number of level 0 DTLB misses due to load operations. 499.It Li DTLB_MISSES.MISS_LD 500.Pq Event 08H , Umask 02H 501The number of Data TLB misses due to load operations. 502.It Li DTLB_MISSES.MISS_ST 503.Pq Event 08H , Umask 08H 504The number of Data TLB misses due to store operations. 505.It Li EIST_TRANS 506.Pq Event 3AH , Umask 00H 507The number of Enhanced Intel SpeedStep Technology transitions. 508.It Li ESP.ADDITIONS 509.Pq Event ABH , Umask 02H 510The number of automatic additions to the 511.Li %esp 512register. 513.It Li ESP.SYNCH 514.Pq Event ABH , Umask 01H 515The number of times the 516.Li %esp 517register was explicitly used in an address expression after 518it is implicitly used by a 519.Li PUSH 520or 521.Li POP 522instruction. 523.It Li EXT_SNOOP Xo 524.Op ,agent= Ns Ar agent 525.Op ,snoopresponse= Ns Ar response 526.Xc 527.Pq Event 77H 528The number of snoop responses to bus transactions. 529.It Li FP_ASSIST 530.Pq Event 11H , Umask 00H 531The number of floating point operations executed that needed 532a microcode assist. 533.It Li FP_COMP_OPS_EXE 534.Pq Event 10H , Umask 00H 535The number of floating point computational micro-ops executed. 536The event is available only on PMC0. 537.It Li FP_MMX_TRANS_TO_FP 538.Pq Event CCH , Umask 02H 539The number of transitions from MMX instructions to floating point 540instructions. 541.It Li FP_MMX_TRANS_TO_MMX 542.Pq Event CCH , Umask 01H 543The number of transitions from floating point instructions to MMX 544instructions. 545.It Li HW_INT_RCV 546.Pq Event C8H , Umask 00H 547The number of hardware interrupts received. 548.It Li IDLE_DURING_DIV 549.Pq Event 18H , Umask 00H 550The number of cycles the divider is busy and no other execution unit 551or load operation was in progress. 552This event is available only on PMC0. 553.It Li ILD_STALL 554.Pq Event 87H , Umask 00H 555The number of cycles the instruction length decoder stalled due to a 556length changing prefix. 557.It Li INST_QUEUE.FULL 558.Pq Event 83H , Umask 02H 559The number of cycles during which the instruction queue is full. 560.It Li INST_RETIRED.ANY_P 561.Pq Event C0H , Umask 00H 562.Pq Alias Qq "Instruction Retired" 563The number of instructions retired. 564This is an architectural performance event. 565.It Li INST_RETIRED.LOADS 566.Pq Event C0H , Umask 01H 567The number of instructions retired that contained a load operation. 568.It Li INST_RETIRED.OTHER 569.Pq Event C0H , Umask 04H 570The number of instructions retired that did not contain a load or a 571store operation. 572.It Li INST_RETIRED.STORES 573.Pq Event C0H , Umask 02H 574The number of instructions retired that contained a store operation. 575.It Li INST_RETIRED.VM_H 576.Pq Event C0H , Umask 08H 577.Pq Tn Core2Extreme 578The number of instructions retired while in VMX root operation. 579.It Li ITLB.FLUSH 580.Pq Event 82H , Umask 40H 581The number of ITLB flushes. 582.It Li ITLB.LARGE_MISS 583.Pq Event 82H , Umask 10H 584The number of instruction fetches from large pages that miss the 585ITLB. 586.It Li ITLB.MISSES 587.Pq Event 82H , Umask 12H 588The number of instruction fetches from both large and small pages that 589miss the ITLB. 590.It Li ITLB.SMALL_MISS 591.Pq Event 82H , Umask 02H 592The number of instruction fetches from small pages that miss the ITLB. 593.It Li ITLB_MISS_RETIRED 594.Pq Event C9H , Umask 00H 595The number of retired instructions that missed the ITLB when they were 596fetched. 597.It Li L1D_ALL_REF 598.Pq Event 43H , Umask 01H 599The number of references to L1 data cache counting loads and stores of 600to all memory types. 601.It Li L1D_ALL_CACHE_REF 602.Pq Event 43H , Umask 02H 603The number of data reads and writes to cacheable memory. 604.It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state 605.Pq Event 42H 606The number of locked reads from cacheable memory. 607.It Li L1D_CACHE_LOCK_DURATION 608.Pq Event 42H , Umask 10H 609The number of cycles during which any cache line is locked by any 610locking instruction. 611.It Li L1D_CACHE_LD Op ,cachestate= Ns Ar state 612.Pq Event 40H 613The number of data reads from cacheable memory excluding locked 614reads. 615.It Li L1D_CACHE_ST Op ,cachestate= Ns Ar state 616.Pq Event 41H 617The number of data writes to cacheable memory excluding locked 618writes. 619.It Li L1D_M_EVICT 620.Pq Event 47H , Umask 00H 621The number of modified cache lines evicted from L1 data cache. 622.It Li L1D_M_REPL 623.Pq Event 46H , Umask 00H 624The number of modified lines allocated in L1 data cache. 625.It Li L1D_PEND_MISS 626.Pq Event 48H , Umask 00H 627The total number of outstanding L1 data cache misses at any clock. 628.It Li L1D_PREFETCH.REQUESTS 629.Pq Event 4EH , Umask 10H 630The number of times L1 data cache requested to prefetch a data cache 631line. 632.It Li L1D_REPL 633.Pq Event 45H , Umask 0FH 634The number of lines brought into L1 data cache. 635.It Li L1D_SPLIT.LOADS 636.Pq Event 49H , Umask 01H 637The number of load operations that span two cache lines. 638.It Li L1D_SPLIT.STORES 639.Pq Event 49H , Umask 02H 640The number of store operations that span two cache lines. 641.It Li L1I_MISSES 642.Pq Event 81H , Umask 00H 643The number of instruction fetch unit misses. 644.It Li L1I_READS 645.Pq Event 80H , Umask 00H 646The number of instruction fetches. 647.It Li L2_ADS Op ,core= Ns core 648.Pq Event 21H 649The number of cycles that the L2 address bus is in use. 650.It Li L2_DBUS_BUSY_RD Op ,core= Ns core 651.Pq Event 23H 652The number of cycles during which the L2 data bus is busy transferring 653data to the core. 654.It Li L2_IFETCH Xo 655.Op ,cachestate= Ns Ar state 656.Op ,core= Ns Ar core 657.Xc 658.Pq Event 28H 659The number of instruction cache line requests from the instruction 660fetch unit. 661.It Li L2_LD Xo 662.Op ,cachestate= Ns Ar state 663.Op ,core= Ns Ar core 664.Op ,prefetch= Ns Ar prefetch 665.Xc 666.Pq Event 29H 667The number of L2 cache read requests from L1 cache and L2 668prefetchers. 669.It Li L2_LINES_IN Xo 670.Op ,core= Ns Ar core 671.Op ,prefetch= Ns Ar prefetch 672.Xc 673.Pq Event 24H 674The number of cache lines allocated in L2 cache. 675.It Li L2_LINES_OUT Xo 676.Op ,core= Ns Ar core 677.Op ,prefetch= Ns Ar prefetch 678.Xc 679.Pq Event 26H 680The number of L2 cache lines evicted. 681.It Li L2_LOCK Xo 682.Op ,cachestate= Ns Ar state 683.Op ,core= Ns Ar core 684.Xc 685.Pq Event 2BH 686The number of locked accesses to cache lines that miss L1 data 687cache. 688.It Li L2_M_LINES_IN Op ,core= Ns Ar core 689.Pq Event 25H 690The number of L2 cache line modifications. 691.It Li L2_M_LINES_OUT Xo 692.Op ,core= Ns Ar core 693.Op ,prefetch= Ns Ar prefetch 694.Xc 695.Pq Event 27H 696The number of modified lines evicted from L2 cache. 697.It Li L2_NO_REQ Op ,core= Ns Ar core 698.Pq Event 32H 699The number of cycles during which no L2 cache requests were pending 700from a core. 701.It Li L2_REJECT_BUSQ Xo 702.Op ,cachestate= Ns Ar state 703.Op ,core= Ns Ar core 704.Op ,prefetch= Ns Ar prefetch 705.Xc 706.Pq Event 30H 707The number of L2 cache requests that were rejected. 708.It Li L2_RQSTS Xo 709.Op ,cachestate= Ns Ar state 710.Op ,core= Ns Ar core 711.Op ,prefetch= Ns Ar prefetch 712.Xc 713.Pq Event 2EH 714The number of completed L2 cache requests. 715.It Li L2_RQSTS.SELF.DEMAND.I_STATE 716.Pq Event 2EH , Umask 41H 717.Pq Alias Qq "LLC Misses" 718The number of completed L2 cache demand requests from this core that 719missed the L2 cache. 720This is an architectural performance event. 721.It Li L2_RQSTS.SELF.DEMAND.MESI 722.Pq Event 2EH , Umask 4FH 723.Pq Alias Qq "LLC References" 724The number of completed L2 cache demand requests from this core. 725This is an architectural performance event. 726.It Li L2_ST Xo 727.Op ,cachestate= Ns Ar state 728.Op ,core= Ns Ar core 729.Xc 730.Pq Event 2AH 731The number of store operations that miss the L1 cache and request data 732from the L2 cache. 733.It Li LOAD_BLOCK.L1D 734.Pq Event 03H , Umask 20H 735The number of loads blocked by the L1 data cache. 736.It Li LOAD_BLOCK.OVERLAP_STORE 737.Pq Event 03H , Umask 08H 738The number of loads that partially overlap an earlier store or are 739aliased with a previous store. 740.It Li LOAD_BLOCK.STA 741.Pq Event 03H , Umask 02H 742The number of loads blocked by preceding stores whose address is yet 743to be calculated. 744.It Li LOAD_BLOCK.STD 745.Pq Event 03H , Umask 04H 746The number of loads blocked by preceding stores to the same address 747whose data value is not known. 748.It Li LOAD_BLOCK.UNTIL_RETIRE 749.Pq Event 03H , Umask 10H 750The number of load operations that were blocked until retirement. 751.It Li LOAD_HIT_PRE 752.Pq Event 4CH , Umask 00H 753The number of load operations that conflicted with an prefetch to the 754same cache line. 755.It Li MACHINE_NUKES.SMC 756.Pq Event C3H , Umask 01H 757The number of times a program writes to a code section. 758.It Li MACHINE_NUKES.MEM_ORDER 759.Pq Event C3H , Umask 04H 760The number of times the execution pipeline was restarted due to a 761memory ordering conflict or memory disambiguation misprediction. 762.It Li MACRO_INSTS.CISC_DECODED 763.Pq Event AAH , Umask 08H 764The number of complex instructions decoded. 765.It Li MACRO_INSTS.DECODED 766.Pq Event AAH , Umask 01H 767The number of instructions decoded. 768.It Li MEMORY_DISAMBIGUATION.RESET 769.Pq Event 09H , Umask 01H 770The number of cycles during which memory disambiguation misprediction 771occurs. 772.It Li MEMORY_DISAMBIGUATION.SUCCESS 773.Pq Event 09H , Umask 02H 774The number of load operations that were successfully disambiguated. 775.It Li MEM_LOAD_RETIRED.DTLB_MISS 776.Pq Event CBH , Umask 10H 777The number of retired loads that missed the DTLB. 778.It Li MEM_LOAD_RETIRED.L1D_LINE_MISS 779.Pq Event CBH , Umask 02H 780The number of retired load operations that missed L1 data cache and 781that sent a request to L2 cache. 782This event is only available on PMC0. 783.It Li MEM_LOAD_RETIRED.L1D_MISS 784.Pq Event CBH , Umask 01H 785The number of retired load operations that missed L1 data cache. 786This event is only available on PMC0. 787.It Li MEM_LOAD_RETIRED.L2_LINE_MISS 788.Pq Event CBH , Umask 08H 789The number of load operations that missed L2 cache and that caused a 790bus request. 791.It Li MEM_LOAD_RETIRED.L2_MISS 792.Pq Event CBH , Umask 04H 793The number of load operations that missed L2 cache. 794.It Li MUL 795.Pq Event 12H , Umask 00H 796The number of multiply operations executed. 797This event is only available on PMC1. 798.It Li PAGE_WALKS.COUNT 799.Pq Event 0CH , Umask 01H 800The number of page walks executed due to an ITLB or DTLB miss. 801.It Li PAGE_WALKS.CYCLES 802.Pq Event 0CH , Umask 02H 803The number of cycles spent in a page walk caused by an ITLB or DTLB 804miss. 805.It Li PREF_RQSTS_DN 806.Pq Event F8H , Umask 00H 807The number of downward prefetches issued from the Data Prefetch Logic 808unit to L2 cache. 809.It Li PREF_RQSTS_UP 810.Pq Event F0H , Umask 00H 811The number of upward prefetches issued from the Data Prefetch Logic 812unit to L2 cache. 813.It Li RAT_STALLS.ANY 814.Pq Event D2H , Umask 0FH 815The number of stall cycles due to any of 816.Li RAT_STALLS.FLAGS 817.Li RAT_STALLS.FPSW , 818.Li RAT_STALLS.PARTIAL 819and 820.Li RAT_STALLS.ROB_READ_PORT . 821.It Li RAT_STALLS.FLAGS 822.Pq Event D2H , Umask 04H 823The number of cycles execution stalled due to a flag register induced 824stall. 825.It Li RAT_STALLS.FPSW 826.Pq Event D2H , Umask 08H 827The number of times the floating point status word was written. 828.It Li RAT_STALLS.OTHER_SERIALIZATION_STALLS 829.Pq Event D2H , Umask 10H , Tn Core2Extreme 830The number of stalls due to other RAT resource serialization not 831counted by umask 0FH. 832.It Li RAT_STALLS.PARTIAL_CYCLES 833.Pq Event D2H , Umask 02H 834The number of cycles of added instruction execution latency due to the 835use of a register that was partially written by previous instructions. 836.It Li RAT_STALLS.ROB_READ_PORT 837.Pq Event D2H , Umask 01H 838The number of cycles when ROB read port stalls occurred. 839.It Li RESOURCE_STALLS.ANY 840.Pq Event DCH , Umask 1FH 841The number of cycles during which any resource related stall 842occurred. 843.It Li RESOURCE_STALLS.BR_MISS_CLEAR 844.Pq Event DCH , Umask 10H 845The number of cycles stalled due to branch misprediction. 846.It Li RESOURCE_STALLS.FPCW 847.Pq Event DCH , Umask 08H 848The number of cycles stalled due to writing the floating point control 849word. 850.It Li RESOURCE_STALLS.LD_ST 851.Pq Event DCH , Umask 04H 852The number of cycles during which the number of loads and stores in 853the pipeline exceeded their limits. 854.It Li RESOURCE_STALLS.ROB_FULL 855.Pq Event DCH , Umask 01H 856The number of cycles when the reorder buffer was full. 857.It Li RESOURCE_STALLS.RS_FULL 858.Pq Event DCH , Umask 02H 859The number of cycles during which the RS was full. 860.It Li RS_UOPS_DISPATCHED 861.Pq Event A0H , Umask 00H 862The number of micro-ops dispatched for execution. 863.It Li RS_UOPS_DISPATCHED.PORT0 864.Pq Event A1H , Umask 01H 865The number of cycles micro-ops were dispatched for execution on port 8660. 867.It Li RS_UOPS_DISPATCHED.PORT1 868.Pq Event A1H , Umask 02H 869The number of cycles micro-ops were dispatched for execution on port 8701. 871.It Li RS_UOPS_DISPATCHED.PORT2 872.Pq Event A1H , Umask 04H 873The number of cycles micro-ops were dispatched for execution on port 8742. 875.It Li RS_UOPS_DISPATCHED.PORT3 876.Pq Event A1H , Umask 08H 877The number of cycles micro-ops were dispatched for execution on port 8783. 879.It Li RS_UOPS_DISPATCHED.PORT4 880.Pq Event A1H , Umask 10H 881The number of cycles micro-ops were dispatched for execution on port 8824. 883.It Li RS_UOPS_DISPATCHED.PORT5 884.Pq Event A1H , Umask 20H 885The number of cycles micro-ops were dispatched for execution on port 8865. 887.It Li SB_DRAIN_CYCLES 888.Pq Event 04H , Umask 01H 889The number of cycles while the store buffer is draining. 890.It Li SEGMENT_REG_LOADS 891.Pq Event 06H , Umask 00H 892The number of segment register loads. 893.It Li SEG_REG_RENAMES.ANY 894.Pq Event D5H , Umask 0FH 895The number of times the any segment register was renamed. 896.It Li SEG_REG_RENAMES.DS 897.Pq Event D5H , Umask 02H 898The number of times the 899.Li %ds 900register is renamed. 901.It Li SEG_REG_RENAMES.ES 902.Pq Event D5H , Umask 01H 903The number of times the 904.Li %es 905register is renamed. 906.It Li SEG_REG_RENAMES.FS 907.Pq Event D5H , Umask 04H 908The number of times the 909.Li %fs 910register is renamed. 911.It Li SEG_REG_RENAMES.GS 912.Pq Event D5H , Umask 08H 913The number of times the 914.Li %gs 915register is renamed. 916.It Li SEG_RENAME_STALLS.ANY 917.Pq Event D4H , Umask 0FH 918The number of stalls due to lack of resource to rename any segment 919register. 920.It Li SEG_RENAME_STALLS.DS 921.Pq Event D4H , Umask 02H 922The number of stalls due to lack of renaming resources for the 923.Li %ds 924register. 925.It Li SEG_RENAME_STALLS.ES 926.Pq Event D4H , Umask 01H 927The number of stalls due to lack of renaming resources for the 928.Li %es 929register. 930.It Li SEG_RENAME_STALLS.FS 931.Pq Event D4H , Umask 04H 932The number of stalls due to lack of renaming resources for the 933.Li %fs 934register. 935.It Li SEG_RENAME_STALLS.GS 936.Pq Event D4H , Umask 08H 937The number of stalls due to lack of renaming resources for the 938.Li %gs 939register. 940.It Li SIMD_ASSIST 941.Pq Event CDH , Umask 00H 942The number SIMD assists invoked. 943.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE 944.Pq Event CAH , Umask 04H 945Then number of computational SSE2 packed double precision instructions 946retired. 947.It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE 948.Pq Event CAH , Umask 01H 949Then number of computational SSE2 packed single precision instructions 950retired. 951.It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE 952.Pq Event CAH , Umask 08H 953Then number of computational SSE2 scalar double precision instructions 954retired. 955.It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE 956.Pq Event CAH , Umask 02H 957Then number of computational SSE2 scalar single precision instructions 958retired. 959.It Li SIMD_INSTR_RETIRED 960.Pq Event CEH , Umask 00H 961The number of retired SIMD instructions that use MMX registers. 962.It Li SIMD_INST_RETIRED.ANY 963.Pq Event C7H , Umask 1FH 964The number of streaming SIMD instructions retired. 965.It Li SIMD_INST_RETIRED.PACKED_DOUBLE 966.Pq Event C7H , Umask 04H 967The number of SSE2 packed double precision instructions retired. 968.It Li SIMD_INST_RETIRED.PACKED_SINGLE 969.Pq Event C7H , Umask 01H 970The number of SSE packed single precision instructions retired. 971.It Li SIMD_INST_RETIRED.SCALAR_DOUBLE 972.Pq Event C7H , Umask 08H 973The number of SSE2 scalar double precision instructions retired. 974.It Li SIMD_INST_RETIRED.SCALAR_SINGLE 975.Pq Event C7H , Umask 02H 976The number of SSE scalar single precision instructions retired. 977.It Li SIMD_INST_RETIRED.VECTOR 978.Pq Event C7H , Umask 10H 979The number of SSE2 vector instructions retired. 980.It Li SIMD_SAT_INSTR_RETIRED 981.Pq Event CFH , Umask 00H 982The number of saturated arithmetic SIMD instructions retired. 983.It Li SIMD_SAT_UOP_EXEC 984.Pq Event B1H , Umask 00H 985The number of SIMD saturated arithmetic micro-ops executed. 986.It Li SIMD_UOPS_EXEC 987.Pq Event B0H , Umask 00H 988The number of SIMD micro-ops executed. 989.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC 990.Pq Event B3H , Umask 20H 991The number of SIMD packed arithmetic micro-ops executed. 992.It Li SIMD_UOP_TYPE_EXEC.LOGICAL 993.Pq Event B3H , Umask 10H 994The number of SIMD packed logical micro-ops executed. 995.It Li SIMD_UOP_TYPE_EXEC.MUL 996.Pq Event B3H , Umask 01H 997The number of SIMD packed multiply micro-ops executed. 998.It Li SIMD_UOP_TYPE_EXEC.PACK 999.Pq Event B3H , Umask 04H 1000The number of SIMD pack micro-ops executed. 1001.It Li SIMD_UOP_TYPE_EXEC.SHIFT 1002.Pq Event B3H , Umask 02H 1003The number of SIMD packed shift micro-ops executed. 1004.It Li SIMD_UOP_TYPE_EXEC.UNPACK 1005.Pq Event B3H , Umask 08H 1006The number of SIMD unpack micro-ops executed. 1007.It Li SNOOP_STALL_DRV Xo 1008.Op ,agent= Ns Ar agent 1009.Op ,core= Ns Ar core 1010.Xc 1011.Pq Event 7EH 1012The number of times the bus stalled for snoops. 1013.It Li SSE_PRE_EXEC.L1 1014.Pq Event 07H , Umask 01H 1015The number of 1016.Li PREFETCHT0 1017instructions executed. 1018.It Li SSE_PRE_EXEC.L2 1019.Pq Event 07H , Umask 02H 1020The number of 1021.Li PREFETCHT1 1022instructions executed. 1023.It Li SSE_PRE_EXEC.NTA 1024.Pq Event 07H , Umask 00H 1025The number of 1026.Li PREFETCHNTA 1027instructions executed. 1028.It Li SSE_PRE_EXEC.STORES 1029.Pq Event 07H , Umask 03H 1030The number of times SSE non-temporal store instructions were executed. 1031.It Li SSE_PRE_MISS.L1 1032.Pq Event 4BH , Umask 01H 1033The number of times the 1034.Li PREFETCHT0 1035instruction executed and missed all cache levels. 1036.It Li SSE_PRE_MISS.L2 1037.Pq Event 4BH , Umask 02H 1038The number of times the 1039.Li PREFETCHT1 1040instruction executed and missed all cache levels. 1041.It Li SSE_PRE_MISS.NTA 1042.Pq Event 4BH , Umask 00H 1043The number of times the 1044.Li PREFETCHNTA 1045instruction executed and missed all cache levels. 1046.It Li STORE_BLOCK.ORDER 1047.Pq Event 04H , Umask 02H 1048The number of cycles while a store was waiting for another store to be 1049globally observed. 1050.It Li STORE_BLOCK.SNOOP 1051.Pq Event 04H , Umask 08H 1052The number of cycles while a store was blocked due to a conflict with 1053an internal or external snoop. 1054.It Li THERMAL_TRIP 1055.Pq Event 3BH , Umask C0H 1056The number of thermal trips. 1057.It Li UOPS_RETIRED.LD_IND_BR 1058.Pq Event C2H , Umask 01H 1059The number of micro-ops retired that fused a load with another 1060operation. 1061.It Li UOPS_RETIRED.STD_STA 1062.Pq Event C2H , Umask 02H 1063The number of store address calculations that fused into one micro-op. 1064.It Li UOPS_RETIRED.MACRO_FUSION 1065.Pq Event C2H , Umask 04H 1066The number of times retired instruction pairs were fused into one 1067micro-op. 1068.It Li UOPS_RETIRED.FUSED 1069.Pq Event C2H , Umask 07H 1070The number of fused micro-ops retired. 1071.It Li UOPS_RETIRED.NON_FUSED 1072.Pq Event C2H , Umask 8H 1073The number of non-fused micro-ops retired. 1074.It Li UOPS_RETIRED.ANY 1075.Pq Event C2H , Umask 0FH 1076The number of micro-ops retired. 1077.It Li X87_OPS_RETIRED.ANY 1078.Pq Event C1H , Umask FEH 1079The number of floating point computational instructions retired. 1080.It Li X87_OPS_RETIRED.FXCH 1081.Pq Event C1H , Umask 01H 1082The number of 1083.Li FXCH 1084instructions retired. 1085.El 1086.Ss Event Name Aliases 1087The following table shows the mapping between the PMC-independent 1088aliases supported by 1089.Lb libpmc 1090and the underlying hardware events used. 1091.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class" 1092.It Em Alias Ta Em Event Ta Em PMC Class 1093.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP 1094.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP 1095.It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP 1096.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF 1097.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP 1098.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF 1099.El 1100.Sh SEE ALSO 1101.Xr pmc 3 , 1102.Xr pmc.atom 3 , 1103.Xr pmc.core 3 , 1104.Xr pmc.iaf 3 , 1105.Xr pmc.k7 3 , 1106.Xr pmc.k8 3 , 1107.Xr pmc.p4 3 , 1108.Xr pmc.p5 3 , 1109.Xr pmc.p6 3 , 1110.Xr pmc.soft 3 , 1111.Xr pmc.tsc 3 , 1112.Xr pmc_cpuinfo 3 , 1113.Xr pmclog 3 , 1114.Xr hwpmc 4 1115.Sh HISTORY 1116The 1117.Nm pmc 1118library first appeared in 1119.Fx 6.0 . 1120.Sh AUTHORS 1121The 1122.Lb libpmc 1123library was written by 1124.An "Joseph Koshy" 1125.Aq jkoshy@FreeBSD.org . 1126