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Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" This software is provided by Joseph Koshy ``as is'' and 13.\" any express or implied warranties, including, but not limited to, the 14.\" implied warranties of merchantability and fitness for a particular purpose 15.\" are disclaimed. in no event shall Joseph Koshy be liable 16.\" for any direct, indirect, incidental, special, exemplary, or consequential 17.\" damages (including, but not limited to, procurement of substitute goods 18.\" or services; loss of use, data, or profits; or business interruption) 19.\" however caused and on any theory of liability, whether in contract, strict 20.\" liability, or tort (including negligence or otherwise) arising in any way 21.\" out of the use of this software, even if advised of the possibility of 22.\" such damage. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd November 12, 2008 27.Os 28.Dt PMC.CORE2 3 29.Sh NAME 30.Nm pmc.core2 31.Nd measurement events for 32.Tn Intel 33.Tn Core2 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core2" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs contains two classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Core2 PMCs are documented in 59.Rs 60.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 61.%T "Volume 3: System Programming Guide" 62.%N "Order Number 253669-027US" 63.%D July 2008 64.%Q "Intel Corporation" 65.Re 66.Ss CORE2 FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69.Ss CORE2 PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta Yes 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta Yes 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta Yes 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li cmask= Ns Ar value 90Configure the PMC to increment only if the number of configured 91events measured in a cycle is greater than or equal to 92.Ar value . 93.It Li edge 94Configure the PMC to count the number of deasserted to asserted 95transitions of the conditions expressed by the other qualifiers. 96If specified, the counter will increment only once whenever a 97condition becomes true, irrespective of the number of clocks during 98which the condition remains true. 99.It Li inv 100Invert the sense of comparision when the 101.Dq Li cmask 102qualifier is present, making the counter increment when the number of 103events per cycle is less than the value specified by the 104.Dq Li cmask 105qualifier. 106.It Li os 107Configure the PMC to count events happening at processor privilege 108level 0. 109.It Li usr 110Configure the PMC to count events occurring at privilege levels 1, 2 111or 3. 112.El 113.Pp 114If neither of the 115.Dq Li os 116or 117.Dq Li usr 118qualifiers are specified, the default is to enable both. 119.Pp 120Events that require core-specificity to be specified use a 121additional qualifier 122.Dq Li core= Ns Ar core , 123where argument 124.Ar core 125is one of: 126.Bl -tag -width indent 127.It Li all 128Measure event conditions on all cores. 129.It Li this 130Measure event conditions on this core. 131.El 132.Pp 133The default is 134.Dq Li this . 135.Pp 136Events that require an agent qualifier to be specified use an 137additional qualifier 138.Dq Li agent= Ns agent , 139where argument 140.Ar agent 141is one of: 142.Bl -tag -width indent 143.It Li this 144Measure events associated with this bus agent. 145.It Li any 146Measure events caused by any bus agent. 147.El 148.Pp 149The default is 150.Dq Li this . 151.Pp 152Events that require a hardware prefetch qualifier to be specified use an 153additional qualifier 154.Dq Li prefetch= Ns Ar prefetch , 155where argument 156.Ar prefetch 157is one of: 158.Bl -tag -width "exclude" 159.It Li both 160Include all prefetches. 161.It Li only 162Only count hardware prefetches. 163.It Li exclude 164Exclude hardware prefetches. 165.El 166.Pp 167The default is 168.Dq Li both . 169.Pp 170Events that require a cache coherence qualifier to be specified use an 171additional qualifer 172.Dq Li cachestate= Ns Ar state , 173where argument 174.Ar state 175contains one or more of the following letters: 176.Bl -tag -width indent 177.It Li e 178Count cache lines in the exclusive state. 179.It Li i 180Count cache lines in the invalid state. 181.It Li m 182Count cache lines in the modified state. 183.It Li s 184Count cache lines in the shared state. 185.El 186.Pp 187The default is 188.Dq Li eims . 189.Pp 190Events that require a snoop response qualifier to be specified use an 191additional qualifier 192.Dq Li snoopresponse= Ns Ar response , 193where argument 194.Ar response 195comprises of the following keywords separated by 196.Dq + 197signs: 198.Bl -tag -width indent 199.It Li clean 200Measure CLEAN responses. 201.It Li hit 202Measure HIT responses. 203.It Li hitm 204Measure HITM responses. 205.El 206.Pp 207The default is to measure all the above responses. 208.Pp 209Events that require a snoop type qualifier use an additional qualifier 210.Dq Li snooptype= Ns Ar type , 211where argument 212.Ar type 213comprises the one of the following keywords: 214.Bl -tag -width indent 215.It Li cmp2i 216Measure CMP2I snoops. 217.It Li cmp2s 218Measure CMP2S snoops. 219.El 220.Pp 221The default is to measure both snoops. 222.Ss Event Specifiers (Programmable PMCs) 223Core2 programmable PMCs support the following events: 224.Bl -tag -width indent 225.It Li BACLEARS 226.Pq Event E6H , Umask 00H 227The number of times the front end is resteered. 228.It Li BOGUS_BR 229.Pq Event E4H , Umask 00H 230The number of byte sequences mistakenly detected as taken branch 231instructions. 232.It Li BR_BAC_MISSP_EXEC 233.Pq Event 8AH , Umask 00H 234The number of branch instructions that were mispredicted when 235decoded. 236.It Li BR_CALL_MISSP_EXEC 237.Pq Event 93H , Umask 00H 238The number of mispredicted 239.Li CALL 240instructions that were executed. 241.It Li BR_CALL_EXEC 242.Pq Event 92H , Umask 00H 243The number of 244.Li CALL 245instructions executed. 246.It Li BR_CND_EXEC 247.Pq Event 8BH , Umask 00H 248The number of conditional branches executed, but not necessarily retired. 249.It Li BR_CND_MISSP_EXEC 250.Pq Event 8CH , Umask 00H 251The number of mispredicted conditional branches executed. 252.It Li BR_IND_CALL_EXEC 253.Pq Event 94H , Umask 00H 254The number of indirect 255.Li CALL 256instructions executed. 257.It Li BR_IND_EXEC 258.Pq Event 8DH , Umask 00H 259The number of indirect branch instructions executed. 260.It Li BR_IND_MISSP_EXEC 261.Pq Event 8EH , Umask 00H 262The number of mispredicted indirect branch instructions executed. 263.It Li BR_INST_DECODED 264.Pq Event E0H , Umask 00H 265The number of branch instructions decoded. 266.It Li BR_INST_EXEC 267.Pq Event 88H , Umask 00H 268The number of branches executed, but not necessarily retired. 269.It Li BR_INST_RETIRED.ANY 270.Pq Event C4H , Umask 00H 271.Pq Alias Qq "Branch Instruction Retired" 272The number of branch instructions retired. 273This is an architectural performance event. 274.It Li BR_INST_RETIRED.MISPRED 275.Pq Event C5H , Umask 00H 276.Pq Alias Qq "Branch Misses Retired" 277The number of mispredicted branch instructions retired. 278This is an architectural performance event. 279.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN 280.Pq Event C4H , Umask 02H 281The number of not taken branch instructions retired that were 282mispredicted. 283.It Li BR_INST_RETIRED.MISPRED_TAKEN 284.Pq Event C4H , Umask 08H 285The number taken branch instructions retired that were mispredicted. 286.It Li BR_INST_RETIRED.PRED_NOT_TAKEN 287.Pq Event C4H , Umask 01H 288The number of not taken branch instructions retired that were 289correctly predicted. 290.It Li BR_INST_RETIRED.PRED_TAKEN 291.Pq Event C4H , Umask 04H 292The number of taken branch instructions retired that were correctly 293predicted. 294.It Li BR_INST_RETIRED.TAKEN 295.Pq Event C4H , Umask 0CH 296The number of taken branch instructions retired. 297.It Li BR_MISSP_EXEC 298.Pq Event 89H , Umask 00H 299The number of mispredicted branch instructions that were executed. 300.It Li BR_RET_MISSP_EXEC 301.Pq Event 90H , Umask 00H 302The number of mispredicted 303.Li RET 304instructions executed. 305.It Li BR_RET_BAC_MISSP_EXEC 306.Pq Event 91H , Umask 00H 307The number of 308.Li RET 309instructions executed that were mispredicted at decode time. 310.It Li BR_RET_EXEC 311.Pq Event 8FH , Umask 00H 312The number of 313.Li RET 314instructions executed. 315.It Li BR_TKN_BUBBLE_1 316.Pq Event 97H , Umask 00H 317The number of branch predicted taken with bubble 1. 318.It Li BR_TKN_BUBBLE_2 319.Pq Event 98H , Umask 00H 320The number of branch predicted taken with bubble 2. 321.It Li BUSQ_EMPTY Op ,core= Ns Ar core 322.Pq Event 7DH 323The number of cycles during which the core did not have any pending 324transactions in the bus queue. 325.It Li BUS_BNR_DRV Op ,agent= Ns Ar agent 326.Pq Event 61H 327The number of Bus Not Ready signals asserted on the bus. 328.It Li BUS_DATA_RCV Op ,core= Ns Ar core 329.Pq Event 64H 330The number of bus cycles during which the processor is receiving data. 331.It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent 332.Pq Event 62H 333The number of bus cycles during which the Data Ready signal is asserted 334on the bus. 335.It Li BUS_HIT_DRV Op ,agent= Ns Ar agent 336.Pq Event 7AH 337The number of bus cycles during which the processor drives the 338.Li HIT# 339pin. 340.It Li BUS_HITM_DRV Op ,agent= Ns Ar agent 341.Pq Event 7BH 342The number of bus cycles during which the processor drives the 343.Li HITM# 344pin. 345.It Li BUS_IO_WAIT Op ,core= Ns Ar core 346.Pq Event 7FH 347The number of core cycles during which I/O requests wait in the bus 348queue. 349.It Li BUS_LOCK_CLOCKS Xo 350.Op ,agent= Ns Ar agent 351.Op ,core= Ns Ar core 352.Xc 353.Pq Event 63H 354The number of bus cycles during which the 355.Li LOCK 356signal was asserted on the bus. 357.It Li BUS_REQUEST_OUTSTANDING Xo 358.Op ,agent= Ns Ar agent 359.Op ,core= Ns Ar core 360.Xc 361.Pq Event 60H 362The number of pending full cache line read transactions on the bus 363occuring in each cycle. 364.It Li BUS_TRANS_P Xo 365.Op ,agent= Ns Ar agent 366.Op ,core= Ns Ar core 367.Xc 368.Pq Event 6BH 369The number of partial bus transactions. 370.It Li BUS_TRANS_IFETCH Xo 371.Op ,agent= Ns Ar agent 372.Op ,core= Ns Ar core 373.Xc 374.Pq Event 68H 375The number of instruction fetch full cache line bus transactions. 376.It Li BUS_TRANS_INVAL Xo 377.Op ,agent= Ns Ar agent 378.Op ,core= Ns Ar core 379.Xc 380.Pq Event 69H 381The number of invalidate bus transactions. 382.It Li BUS_TRANS_PWR Xo 383.Op ,agent= Ns Ar agent 384.Op ,core= Ns Ar core 385.Xc 386.Pq Event 6AH 387The number of partial write bus transactions. 388.It Li BUS_TRANS_DEF Xo 389.Op ,agent= Ns Ar agent 390.Op ,core= Ns Ar core 391.Xc 392.Pq Event 6DH 393The number of deferred bus transactions. 394.It Li BUS_TRANS_BURST Xo 395.Op ,agent= Ns Ar agent 396.Op ,core= Ns Ar core 397.Xc 398.Pq Event 6EH 399The number of burst transactions. 400.It Li BUS_TRANS_MEM Xo 401.Op ,agent= Ns Ar agent 402.Op ,core= Ns Ar core 403.Xc 404.Pq Event 6FH 405The number of memory bus transactions. 406.It Li BUS_TRANS_ANY Xo 407.Op ,agent= Ns Ar agent 408.Op ,core= Ns Ar core 409.Xc 410.Pq Event 70H 411The number of bus transactions of any kind. 412.It Li BUS_TRANS_BRD Xo 413.Op ,agent= Ns Ar agent 414.Op ,core= Ns Ar core 415.Xc 416.Pq Event 65H 417The number of burst read transactions. 418.It Li BUS_TRANS_IO Xo 419.Op ,agent= Ns Ar agent 420.Op ,core= Ns Ar core 421.Xc 422.Pq Event 6CH 423The number of completed I/O bus transaactions due to 424.Li IN 425and 426.Li OUT 427instructions. 428.It Li BUS_TRANS_RFO Xo 429.Op ,agent= Ns Ar agent 430.Op ,core= Ns Ar core 431.Xc 432.Pq Event 66H 433The number of Read For Ownership bus transactions. 434.It Li BUS_TRANS_WB Xo 435.Op ,agent= Ns Ar agent 436.Op ,core= Ns Ar core 437.Xc 438.Pq Event 67H 439The number explicit writeback bus transactions due to dirty line 440evictions. 441.It Li CMP_SNOOP Xo 442.Op ,core= Ns Ar core 443.Op ,snooptype= Ns Ar snoop 444.Xc 445.Pq Event 78H 446The number of times the L1 data cache is snooped by the other core in 447the same processor. 448.It Li CPU_CLK_UNHALTED.BUS 449.Pq Event 3CH , Umask 01H 450.Pq Alias Qq "Unhalted Reference Cycles" 451The number of bus cycles when the core is not in the halt state. 452This is an architectural performance event. 453.It Li CPU_CLK_UNHALTED.CORE_P 454.Pq Event 3CH , Umask 00H 455.Pq Alias Qq "Unhalted Core Cycles" 456The number of core cycles while the core is not in a halt state. 457This is an architectural performance event. 458.It Li CPU_CLK_UNHALTED.NO_OTHER 459.Pq Event 3CH , Umask 02H 460The number of bus cycles during which the core remains unhalted and 461the other core is halted. 462.It Li CYCLES_DIV_BUSY 463.Pq Event 14H , Umask 00H 464The number of cycles the divider is busy. 465This event is only available on PMC0. 466.It Li CYCLES_INT_MASKED 467.Pq Event C6H , Umask 01H 468The number of cycles during which interrupts are disabled. 469.It Li CYCLES_INT_PENDING_AND_MASKED 470.Pq Event C6H , Umask 02H 471The number of cycles during which there were pending interrupts while 472interrupts were disabled. 473.It Li CYCLES_L1I_MEM_STALLED 474.Pq Event 86H , Umask 00H 475The number of cycles for which an instruction fetch stalls. 476.It Li DELAYED_BYPASS.FP 477.Pq Event 19H , Umask 00H 478The number of floating point operations that used data immediately 479after the data was generated by a non floating point execution unit. 480.It Li DELAYED_BYPASS.LOAD 481.Pq Event 19H , Umask 01H 482The number of delayed bypass penalty cycles that a load operation incurred. 483.It Li DELAYED_BYPASS.SIMD 484.Pq Event 19H , Umask 02H 485The number of times SIMD operations use data immediately after data, 486was generated by a non-SIMD execution unit. 487.It Li DIV 488.Pq Event 13H , Umask 00H 489The number of divide operations executed. 490This event is only available on PMC1. 491.It Li DTLB_MISSES.ANY 492.Pq Event 08H , Umask 01H 493The number of Data TLB misses, including misses that result from 494speculative accesses. 495.It Li DTLB_MISSES.L0_MISS_LD 496.Pq Event 08H , Umask 04H 497The number of level 0 DTLB misses due to load operations. 498.It Li DTLB_MISSES.MISS_LD 499.Pq Event 08H , Umask 02H 500The number of Data TLB misses due to load operations. 501.It Li DTLB_MISSES.MISS_ST 502.Pq Event 08H , Umask 08H 503The number of Data TLB misses due to store operations. 504.It Li EIST_TRANS 505.Pq Event 3AH , Umask 00H 506The number of Enhanced Intel SpeedStep Technology transitions. 507.It Li ESP.ADDITIONS 508.Pq Event ABH , Umask 02H 509The number of automatic additions to the 510.Li %esp 511register. 512.It Li ESP.SYNCH 513.Pq Event ABH , Umask 01H 514The number of times the 515.Li %esp 516register was explicitly used in an address expression after 517it is implicitly used by a 518.Li PUSH 519or 520.Li POP 521instruction. 522.It Li EXT_SNOOP Xo 523.Op ,agent= Ns Ar agent 524.Op ,snoopresponse= Ns Ar response 525.Xc 526.Pq Event 77H 527The number of snoop responses to bus transactions. 528.It Li FP_ASSIST 529.Pq Event 11H , Umask 00H 530The number of floating point operations executed that needed 531a microcode assist. 532.It Li FP_COMP_OPS_EXE 533.Pq Event 10H , Umask 00H 534The number of floating point computational micro-ops executed. 535The event is available only on PMC0. 536.It Li FP_MMX_TRANS_TO_FP 537.Pq Event CCH , Umask 02H 538The number of transitions from MMX instructions to floating point 539instructions. 540.It Li FP_MMX_TRANS_TO_MMX 541.Pq Event CCH , Umask 01H 542The number of transitions from floating point instructions to MMX 543instructions. 544.It Li HW_INT_RCV 545.Pq Event C8H , Umask 00H 546The number of hardware interrupts recieved. 547.It Li IDLE_DURING_DIV 548.Pq Event 18H , Umask 00H 549The number of cycles the divider is busy and no other execution unit 550or load operation was in progress. 551This event is available only on PMC0. 552.It Li ILD_STALL 553.Pq Event 87H , Umask 00H 554The number of cycles the instruction length decoder stalled due to a 555length changing prefix. 556.It Li INST_QUEUE.FULL 557.Pq Event 83H , Umask 02H 558The number of cycles during which the instruction queue is full. 559.It Li INST_RETIRED.ANY_P 560.Pq Event C0H , Umask 00H 561.Pq Alias Qq "Instruction Retired" 562The number of instructions retired. 563This is an architectural performance event. 564.It Li INST_RETIRED.LOADS 565.Pq Event C0H , Umask 01H 566The number of instructions retired that contained a load operation. 567.It Li INST_RETIRED.OTHER 568.Pq Event C0H , Umask 04H 569The number of instructions retired that did not contain a load or a 570store operation. 571.It Li INST_RETIRED.STORES 572.Pq Event C0H , Umask 02H 573The number of instructions retired that contained a store operation. 574.It Li INST_RETIRED.VM_H 575.Pq Event C0H , Umask 08H 576.Pq Tn Core2Extreme 577The number of instructions retired while in VMX root operation. 578.It Li ITLB.FLUSH 579.Pq Event 82H , Umask 40H 580The number of ITLB flushes. 581.It Li ITLB.LARGE_MISS 582.Pq Event 82H , Umask 10H 583The number of instruction fetches from large pages that miss the 584ITLB. 585.It Li ITLB.MISSES 586.Pq Event 82H , Umask 12H 587The number of instruction fetches from both large and small pages that 588miss the ITLB. 589.It Li ITLB.SMALL_MISS 590.Pq Event 82H , Umask 02H 591The number of instruction fetches from small pages that miss the ITLB. 592.It Li ITLB_MISS_RETIRED 593.Pq Event C9H , Umask 00H 594The number of retired instructions that missed the ITLB when they were 595fetched. 596.It Li L1D_ALL_REF 597.Pq Event 43H , Umask 01H 598The number of references to L1 data cache counting loads and stores of 599to all memory types. 600.It Li L1D_ALL_CACHE_REF 601.Pq Event 43H , Umask 02H 602The number of data reads and writes to cacheable memory. 603.It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state 604.Pq Event 42H 605The number of locked reads from cacheable memory. 606.It Li L1D_CACHE_LOCK_DURATION 607.Pq Event 42H , Umask 10H 608The number of cycles during which any cache line is locked by any 609locking instruction. 610.It Li L1D_CACHE_LD Op ,cachestate= Ns Ar state 611.Pq Event 40H 612The number of data reads from cacheable memory excluding locked 613reads. 614.It Li L1D_CACHE_ST Op ,cachestate= Ns Ar state 615.Pq Event 41H 616The number of data writes to cacheable memory excluding locked 617writes. 618.It Li L1D_M_EVICT 619.Pq Event 47H , Umask 00H 620The number of modified cache lines evicted from L1 data cache. 621.It Li L1D_M_REPL 622.Pq Event 46H , Umask 00H 623The number of modified lines allocated in L1 data cache. 624.It Li L1D_PEND_MISS 625.Pq Event 48H , Umask 00H 626The total number of outstanding L1 data cache misses at any clock. 627.It Li L1D_PREFETCH.REQUESTS 628.Pq Event 4EH , Umask 10H 629The number of times L1 data cache requested to prefetch a data cache 630line. 631.It Li L1D_REPL 632.Pq Event 45H , Umask 0FH 633The number of lines brought into L1 data cache. 634.It Li L1D_SPLIT.LOADS 635.Pq Event 49H , Umask 01H 636The number of load operations that span two cache lines. 637.It Li L1D_SPLIT.STORES 638.Pq Event 49H , Umask 02H 639The number of store operations that span two cache lines. 640.It Li L1I_MISSES 641.Pq Event 81H , Umask 00H 642The number of instruction fetch unit misses. 643.It Li L1I_READS 644.Pq Event 80H , Umask 00H 645The number of instruction fetches. 646.It Li L2_ADS Op ,core= Ns core 647.Pq Event 21H 648The number of cycles that the L2 address bus is in use. 649.It Li L2_DBUS_BUSY_RD Op ,core= Ns core 650.Pq Event 23H 651The number of cycles during which the L2 data bus is busy transferring 652data to the core. 653.It Li L2_IFETCH Xo 654.Op ,cachestate= Ns Ar state 655.Op ,core= Ns Ar core 656.Xc 657.Pq Event 28H 658The number of instruction cache line requests from the instruction 659fetch unit. 660.It Li L2_LD Xo 661.Op ,cachestate= Ns Ar state 662.Op ,core= Ns Ar core 663.Op ,prefech= Ns Ar prefetch 664.Xc 665.Pq Event 29H 666The number of L2 cache read requests from L1 cache and L2 667prefetchers. 668.It Li L2_LINES_IN Xo 669.Op ,core= Ns Ar core 670.Op ,prefetch= Ns Ar prefetch 671.Xc 672.Pq Event 24H 673The number of cache lines allocated in L2 cache. 674.It Li L2_LINES_OUT Xo 675.Op ,core= Ns Ar core 676.Op ,prefetch= Ns Ar prefetch 677.Xc 678.Pq Event 26H 679The number of L2 cache lines evicted. 680.It Li L2_LOCK Xo 681.Op ,cachestate= Ns Ar state 682.Op ,core= Ns Ar core 683.Xc 684.Pq Event 2BH 685The number of locked accesses to cache lines that miss L1 data 686cache. 687.It Li L2_M_LINES_IN Op ,core= Ns Ar core 688.Pq Event 25H 689The number of L2 cache line modifications. 690.It Li L2_M_LINES_OUT Xo 691.Op ,core= Ns Ar core 692.Op ,prefetch= Ns Ar prefetch 693.Xc 694.Pq Event 27H 695The number of modified lines evicted from L2 cache. 696.It Li L2_NO_REQ Op ,core= Ns Ar core 697.Pq Event 32H 698The number of cycles during which no L2 cache requests were pending 699from a core. 700.It Li L2_REJECT_BUSQ Xo 701.Op ,cachestate= Ns Ar state 702.Op ,core= Ns Ar core 703.Op ,prefetch= Ns Ar prefetch 704.Xc 705.Pq Event 30H 706The number of L2 cache requests that were rejected. 707.It Li L2_RQSTS Xo 708.Op ,cachestate= Ns Ar state 709.Op ,core= Ns Ar core 710.Op ,prefetch= Ns Ar prefetch 711.Xc 712.Pq Event 2EH 713The number of completed L2 cache requests. 714.It Li L2_RQSTS.SELF.DEMAND.I_STATE 715.Pq Event 2EH , Umask 41H 716.Pq Alias Qq "LLC Misses" 717The number of completed L2 cache demand requests from this core that 718missed the L2 cache. 719This is an architectural performance event. 720.It Li L2_RQSTS.SELF.DEMAND.MESI 721.Pq Event 2EH , Umask 4FH 722.Pq Alias Qq "LLC References" 723The number of completed L2 cache demand requests from this core. 724This is an architectural performance event. 725.It Li L2_ST Xo 726.Op ,cachestate= Ns Ar state 727.Op ,core= Ns Ar core 728.Xc 729.Pq Event 2AH 730The number of store operations that miss the L1 cache and request data 731from the L2 cache. 732.It Li LOAD_BLOCK.L1D 733.Pq Event 03H , Umask 20H 734The number of loads blocked by the L1 data cache. 735.It Li LOAD_BLOCK.OVERLAP_STORE 736.Pq Event 03H , Umask 08H 737The number of loads that partially overlap an earlier store or are 738aliased with a previous store. 739.It Li LOAD_BLOCK.STA 740.Pq Event 03H , Umask 02H 741The number of loads blocked by preceding stores whose address is yet 742to be calculated. 743.It Li LOAD_BLOCK.STD 744.Pq Event 03H , Umask 04H 745The number of loads blocked by preceding stores to the same address 746whose data value is not known. 747.It Li LOAD_BLOCK.UNTIL_RETIRE 748.Pq Event 03H , Umask 10H 749The numer of load operations that were blocked until retirement. 750.It Li LOAD_HIT_PRE 751.Pq Event 4CH , Umask 00H 752The number of load operations that conflicted with an prefetch to the 753same cache line. 754.It Li MACHINE_NUKES.SMC 755.Pq Event C3H , Umask 01H 756The number of times a program writes to a code section. 757.It Li MACHINE_NUKES.MEM_ORDER 758.Pq Event C3H , Umask 04H 759The number of times the execution pipeline was restarted due to a 760memory ordering conflict or memory disambiguation misprediction. 761.It Li MACRO_INSTS.CISC_DECODED 762.Pq Event AAH , Umask 08H 763The number of complex instructions decoded. 764.It Li MACRO_INSTS.DECODED 765.Pq Event AAH , Umask 01H 766The number of instructions decoded. 767.It Li MEMORY_DISAMBIGUATION.RESET 768.Pq Event 09H , Umask 01H 769The number of cycles during which memory disambiguation misprediction 770occurs. 771.It Li MEMORY_DISAMBIGUATION.SUCCESS 772.Pq Event 09H , Umask 02H 773The number of load operations that were successfully disambiguated. 774.It Li MEM_LOAD_RETIRED.DTLB_MISS 775.Pq Event CBH , Umask 10H 776The number of retired loads that missed the DTLB. 777.It Li MEM_LOAD_RETIRED.L1D_LINE_MISS 778.Pq Event CBH , Umask 02H 779The number of retired load operations that missed L1 data cache and 780that sent a request to L2 cache. 781This event is only available on PMC0. 782.It Li MEM_LOAD_RETIRED.L1D_MISS 783.Pq Event CBH , Umask 01H 784The number of retired load operations that missed L1 data cache. 785This event is only available on PMC0. 786.It Li MEM_LOAD_RETIRED.L2_LINE_MISS 787.Pq Event CBH , Umask 08H 788The number of load operations that missed L2 cache and that caused a 789bus request. 790.It Li MEM_LOAD_RETIRED.L2_MISS 791.Pq Event CBH , Umask 04H 792The number of load operations that missed L2 cache. 793.It Li MUL 794.Pq Event 12H , Umask 00H 795The number of multiply operations executed. 796This event is only available on PMC1. 797.It Li PAGE_WALKS.COUNT 798.Pq Event 0CH , Umask 01H 799The number of page walks executed due to an ITLB or DTLB miss. 800.It Li PAGE_WALKS.CYCLES 801.Pq Event 0CH , Umask 02H 802The number of cycles spent in a page walk caused by an ITLB or DTLB 803miss. 804.It Li PREF_RQSTS_DN 805.Pq Event F8H , Umask 00H 806The number of downward prefetches issued from the Data Prefetch Logic 807unit to L2 cache. 808.It Li PREF_RQSTS_UP 809.Pq Event F0H , Umask 00H 810The number of upward prefetches issued from the Data Prefetch Logic 811unit to L2 cache. 812.It Li RAT_STALLS.ANY 813.Pq Event D2H , Umask 0FH 814The number of stall cycles due to any of 815.Li RAT_STALLS.FLAGS 816.Li RAT_STALLS.FPSW , 817.Li RAT_STALLS.PARTIAL 818and 819.Li RAT_STALLS.ROB_READ_PORT . 820.It Li RAT_STALLS.FLAGS 821.Pq Event D2H , Umask 04H 822The number of cycles execution stalled due to a flag register induced 823stall. 824.It Li RAT_STALLS.FPSW 825.Pq Event D2H , Umask 08H 826The number of times the floating point status word was written. 827.It Li RAT_STALLS.OTHER_SERIALIZATION_STALLS 828.Pq Event D2H , Umask 10H , Tn Core2Extreme 829The number of stalls due to other RAT resource serialization not 830counted by umask 0FH. 831.It Li RAT_STALLS.PARTIAL_CYCLES 832.Pq Event D2H , Umask 02H 833The number of cycles of added instruction execution latency due to the 834use of a register that was partially written by previous instructions. 835.It Li RAT_STALLS.ROB_READ_PORT 836.Pq Event D2H , Umask 01H 837The number of cycles when ROB read port stalls occurred. 838.It Li RESOURCE_STALLS.ANY 839.Pq Event DCH , Umask 1FH 840The number of cycles during which any resource related stall 841occurred. 842.It Li RESOURCE_STALLS.BR_MISS_CLEAR 843.Pq Event DCH , Umask 10H 844The number of cycles stalled due to branch misprediction. 845.It Li RESOURCE_STALLS.FPCW 846.Pq Event DCH , Umask 08H 847The number of cycles stalled due to writing the floating point control 848word. 849.It Li RESOURCE_STALLS.LD_ST 850.Pq Event DCH , Umask 04H 851The number of cycles during which the number of loads and stores in 852the pipeline exceeded their limits. 853.It Li RESOURCE_STALLS.ROB_FULL 854.Pq Event DCH , Umask 01H 855The number of cycles when the reorder buffer was full. 856.It Li RESOURCE_STALLS.RS_FULL 857.Pq Event DCH , Umask 02H 858The number of cycles during which the RS was full. 859.It Li RS_UOPS_DISPATCHED 860.Pq Event A0H , Umask 00H 861The number of micro-ops dispatched for execution. 862.It Li RS_UOPS_DISPATCHED.PORT0 863.Pq Event A1H , Umask 01H 864The number of cycles micro-ops were dispatched for execution on port 8650. 866.It Li RS_UOPS_DISPATCHED.PORT1 867.Pq Event A1H , Umask 02H 868The number of cycles micro-ops were dispatched for execution on port 8691. 870.It Li RS_UOPS_DISPATCHED.PORT2 871.Pq Event A1H , Umask 04H 872The number of cycles micro-ops were dispatched for execution on port 8732. 874.It Li RS_UOPS_DISPATCHED.PORT3 875.Pq Event A1H , Umask 08H 876The number of cycles micro-ops were dispatched for execution on port 8773. 878.It Li RS_UOPS_DISPATCHED.PORT4 879.Pq Event A1H , Umask 10H 880The number of cycles micro-ops were dispatched for execution on port 8814. 882.It Li RS_UOPS_DISPATCHED.PORT5 883.Pq Event A1H , Umask 20H 884The number of cycles micro-ops were dispatched for execution on port 8855. 886.It Li SB_DRAIN_CYCLES 887.Pq Event 04H , Umask 01H 888The number of cycles while the store buffer is draining. 889.It Li SEGMENT_REG_LOADS 890.Pq Event 06H , Umask 00H 891The number of segment register loads. 892.It Li SEG_REG_RENAMES.ANY 893.Pq Event D5H , Umask 0FH 894The number of times the any segment register was renamed. 895.It Li SEG_REG_RENAMES.DS 896.Pq Event D5H , Umask 02H 897The number of times the 898.Li %ds 899register is renamed. 900.It Li SEG_REG_RENAMES.ES 901.Pq Event D5H , Umask 01H 902The number of times the 903.Li %es 904register is renamed. 905.It Li SEG_REG_RENAMES.FS 906.Pq Event D5H , Umask 04H 907The number of times the 908.Li %fs 909register is renamed. 910.It Li SEG_REG_RENAMES.GS 911.Pq Event D5H , Umask 08H 912The number of times the 913.Li %gs 914register is renamed. 915.It Li SEG_RENAME_STALLS.ANY 916.Pq Event D4H , Umask 0FH 917The number of stalls due to lack of resource to rename any segment 918register. 919.It Li SEG_RENAME_STALLS.DS 920.Pq Event D4H , Umask 02H 921The number of stalls due to lack of renaming resources for the 922.Li %ds 923register. 924.It Li SEG_RENAME_STALLS.ES 925.Pq Event D4H , Umask 01H 926The number of stalls due to lack of renaming resources for the 927.Li %es 928register. 929.It Li SEG_RENAME_STALLS.FS 930.Pq Event D4H , Umask 04H 931The number of stalls due to lack of renaming resources for the 932.Li %fs 933register. 934.It Li SEG_RENAME_STALLS.GS 935.Pq Event D4H , Umask 08H 936The number of stalls due to lack of renaming resources for the 937.Li %gs 938register. 939.It Li SIMD_ASSIST 940.Pq Event CDH , Umask 00H 941The number SIMD assists invoked. 942.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE 943.Pq Event CAH , Umask 04H 944Then number of computational SSE2 packed double precision instructions 945retired. 946.It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE 947.Pq Event CAH , Umask 01H 948Then number of computational SSE2 packed single precision instructions 949retired. 950.It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE 951.Pq Event CAH , Umask 08H 952Then number of computational SSE2 scalar double precision instructions 953retired. 954.It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE 955.Pq Event CAH , Umask 02H 956Then number of computational SSE2 scalar single precision instructions 957retired. 958.It Li SIMD_INSTR_RETIRED 959.Pq Event CEH , Umask 00H 960The number of retired SIMD instructions that use MMX registers. 961.It Li SIMD_INST_RETIRED.ANY 962.Pq Event C7H , Umask 1FH 963The number of streaming SIMD instructions retired. 964.It Li SIMD_INST_RETIRED.PACKED_DOUBLE 965.Pq Event C7H , Umask 04H 966The number of SSE2 packed double precision instructions retired. 967.It Li SIMD_INST_RETIRED.PACKED_SINGLE 968.Pq Event C7H , Umask 01H 969The number of SSE packed single precision instructions retired. 970.It Li SIMD_INST_RETIRED.SCALAR_DOUBLE 971.Pq Event C7H , Umask 08H 972The number of SSE2 scalar double precision instructions retired. 973.It Li SIMD_INST_RETIRED.SCALAR_SINGLE 974.Pq Event C7H , Umask 02H 975The number of SSE scalar single precision instructions retired. 976.It Li SIMD_INST_RETIRED.VECTOR 977.Pq Event C7H , Umask 10H 978The number of SSE2 vector instructions retired. 979.It Li SIMD_SAT_INSTR_RETIRED 980.Pq Event CFH , Umask 00H 981The number of saturated arithmetic SIMD instructions retired. 982.It Li SIMD_SAT_UOP_EXEC 983.Pq Event B1H , Umask 00H 984The number of SIMD saturated arithmetic micro-ops executed. 985.It Li SIMD_UOPS_EXEC 986.Pq Event B0H , Umask 00H 987The number of SIMD micro-ops executed. 988.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC 989.Pq Event B3H , Umask 20H 990The number of SIMD packed arithmetic micro-ops executed. 991.It Li SIMD_UOP_TYPE_EXEC.LOGICAL 992.Pq Event B3H , Umask 10H 993The number of SIMD packed logical micro-ops executed. 994.It Li SIMD_UOP_TYPE_EXEC.MUL 995.Pq Event B3H , Umask 01H 996The number of SIMD packed multiply micro-ops executed. 997.It Li SIMD_UOP_TYPE_EXEC.PACK 998.Pq Event B3H , Umask 04H 999The number of SIMD pack micro-ops executed. 1000.It Li SIMD_UOP_TYPE_EXEC.SHIFT 1001.Pq Event B3H , Umask 02H 1002The number of SIMD packed shift micro-ops executed. 1003.It Li SIMD_UOP_TYPE_EXEC.UNPACK 1004.Pq Event B3H , Umask 08H 1005The number of SIMD unpack micro-ops executed. 1006.It Li SNOOP_STALL_DRV Xo 1007.Op ,agent= Ns Ar agent 1008.Op ,core= Ns Ar core 1009.Xc 1010.Pq Event 7EH 1011The number of times the bus stalled for snoops. 1012.It Li SSE_PRE_EXEC.L1 1013.Pq Event 07H , Umask 01H 1014The number of 1015.Li PREFETCHT0 1016instructions executed. 1017.It Li SSE_PRE_EXEC.L2 1018.Pq Event 07H , Umask 02H 1019The number of 1020.Li PREFETCHT1 1021instructions executed. 1022.It Li SSE_PRE_EXEC.NTA 1023.Pq Event 07H , Umask 00H 1024The number of 1025.Li PREFETCHNTA 1026instructions executed. 1027.It Li SSE_PRE_EXEC.STORES 1028.Pq Event 07H , Umask 03H 1029The number of times SSE non-temporal store instructions were executed. 1030.It Li SSE_PRE_MISS.L1 1031.Pq Event 4BH , Umask 01H 1032The number of times the 1033.Li PREFETCHT0 1034instruction executed and missed all cache levels. 1035.It Li SSE_PRE_MISS.L2 1036.Pq Event 4BH , Umask 02H 1037The number of times the 1038.Li PREFETCHT1 1039instruction executed and missed all cache levels. 1040.It Li SSE_PRE_MISS.NTA 1041.Pq Event 4BH , Umask 00H 1042The number of times the 1043.Li PREFETCHNTA 1044instruction executed and missed all cache levels. 1045.It Li STORE_BLOCK.ORDER 1046.Pq Event 04H , Umask 02H 1047The number of cycles while a store was waiting for another store to be 1048globally observed. 1049.It Li STORE_BLOCK.SNOOP 1050.Pq Event 04H , Umask 08H 1051The number of cycles while a store was blocked due to a conflict with 1052an internal or external snoop. 1053.It Li THERMAL_TRIP 1054.Pq Event 3BH , Umask C0H 1055The number of thermal trips. 1056.It Li UOPS_RETIRED.LD_IND_BR 1057.Pq Event C2H , Umask 01H 1058The number of micro-ops retired that fused a load with another 1059operation. 1060.It Li UOPS_RETIRED.STD_STA 1061.Pq Event C2H , Umask 02H 1062The number of store address calculations that fused into one micro-op. 1063.It Li UOPS_RETIRED.MACRO_FUSION 1064.Pq Event C2H , Umask 04H 1065The number of times retired instruction pairs were fused into one 1066micro-op. 1067.It Li UOPS_RETIRED.FUSED 1068.Pq Event C2H , Umask 07H 1069The number of fused micro-ops retired. 1070.It Li UOPS_RETIRED.NON_FUSED 1071.Pq Event C2H , Umask 8H 1072The number of non-fused micro-ops retired. 1073.It Li UOPS_RETIRED.ANY 1074.Pq Event C2H , Umask 0FH 1075The number of micro-ops retired. 1076.It Li X87_OPS_RETIRED.ANY 1077.Pq Event C1H , Umask FEH 1078The number of floating point computational instructions retired. 1079.It Li X87_OPS_RETIRED.FXCH 1080.Pq Event C1H , Umask 01H 1081The number of 1082.Li FXCH 1083instructions retired. 1084.El 1085.Ss Event Name Aliases 1086The following table shows the mapping between the PMC-independent 1087aliases supported by 1088.Lb libpmc 1089and the underlying hardware events used. 1090.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class" 1091.It Em Alias Ta Em Event Ta Em PMC Class 1092.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP 1093.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP 1094.It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP 1095.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF 1096.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP 1097.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF 1098.El 1099.Sh SEE ALSO 1100.Xr pmc 3 , 1101.Xr pmc.atom 3 , 1102.Xr pmc.core 3 , 1103.Xr pmc.iaf 3 , 1104.Xr pmc.k7 3 , 1105.Xr pmc.k8 3 , 1106.Xr pmc.p4 3 , 1107.Xr pmc.p5 3 , 1108.Xr pmc.p6 3 , 1109.Xr pmc.tsc 3 , 1110.Xr pmc_cpuinfo 3 , 1111.Xr pmclog 3 , 1112.Xr hwpmc 4 1113.Sh HISTORY 1114The 1115.Nm pmc 1116library first appeared in 1117.Fx 6.0 . 1118.Sh AUTHORS 1119The 1120.Lb libpmc 1121library was written by 1122.An "Joseph Koshy" 1123.Aq jkoshy@FreeBSD.org . 1124