1.\" Copyright (c) 2008 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" This software is provided by Joseph Koshy ``as is'' and 13.\" any express or implied warranties, including, but not limited to, the 14.\" implied warranties of merchantability and fitness for a particular purpose 15.\" are disclaimed. in no event shall Joseph Koshy be liable 16.\" for any direct, indirect, incidental, special, exemplary, or consequential 17.\" damages (including, but not limited to, procurement of substitute goods 18.\" or services; loss of use, data, or profits; or business interruption) 19.\" however caused and on any theory of liability, whether in contract, strict 20.\" liability, or tort (including negligence or otherwise) arising in any way 21.\" out of the use of this software, even if advised of the possibility of 22.\" such damage. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd September 24, 2008 27.Os 28.Dt PMC.CORE2 3 29.Sh NAME 30.Nm pmc.core2 31.Nd measurement events for 32.Tn Intel 33.Tn Core2 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core2" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs contains two classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Core2 PMCs are documented in 59.Rs 60.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 61.%T "Volume 3: System Programming Guide" 62.%N "Order Number 253669-027US" 63.%D July 2008 64.%Q "Intel Corporation" 65.Re 66.Ss CORE2 FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69.Ss CORE2 PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta Yes 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta Yes 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta Yes 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li cmask= Ns Ar value 90Configure the PMC to increment only if the number of configured 91events measured in a cycle is greater than or equal to 92.Ar value . 93.It Li edge 94Configure the PMC to count the number of deasserted to asserted 95transitions of the conditions expressed by the other qualifiers. 96If specified, the counter will increment only once whenever a 97condition becomes true, irrespective of the number of clocks during 98which the condition remains true. 99.It Li inv 100Invert the sense of comparision when the 101.Dq Li cmask 102qualifier is present, making the counter increment when the number of 103events per cycle is less than the value specified by the 104.Dq Li cmask 105qualifier. 106.It Li os 107Configure the PMC to count events happening at processor privilege 108level 0. 109.It Li umask= Ns Ar value 110This qualifier is used to further qualify the event selected (see 111below). 112.It Li usr 113Configure the PMC to count events occurring at privilege levels 1, 2 114or 3. 115.El 116.Pp 117If neither of the 118.Dq Li os 119or 120.Dq Li usr 121qualifiers are specified, the default is to enable both. 122.Pp 123Events that require core-specificity to be specified use a 124additional qualifier 125.Dq Li core= Ns Ar core , 126where argument 127.Ar core 128is one of: 129.Bl -tag -width indent 130.It Li all 131Measure event conditions on all cores. 132.It Li this 133Measure event conditions on this core. 134.El 135.Pp 136The default is 137.Dq Li this . 138.Pp 139Events that require an agent qualifier to be specified use an 140additional qualifier 141.Dq Li agent= Ns agent , 142where argument 143.Ar agent 144is one of: 145.Bl -tag -width indent 146.It Li this 147Measure events associated with this bus agent. 148.It Li any 149Measure events caused by any bus agent. 150.El 151.Pp 152The default is 153.Dq Li this . 154.Pp 155Events that require a hardware prefetch qualifier to be specified use an 156additional qualifier 157.Dq Li prefetch= Ns Ar prefetch , 158where argument 159.Ar prefetch 160is one of: 161.Bl -tag -width "exclude" 162.It Li both 163Include all prefetches. 164.It Li only 165Only count hardware prefetches. 166.It Li exclude 167Exclude hardware prefetches. 168.El 169.Pp 170The default is 171.Dq Li both . 172.Pp 173Events that require a cache coherence qualifier to be specified use an 174additional qualifer 175.Dq Li cachestate= Ns Ar state , 176where argument 177.Ar state 178contains one or more of the following letters: 179.Bl -tag -width indent 180.It Li e 181Count cache lines in the exclusive state. 182.It Li i 183Count cache lines in the invalid state. 184.It Li m 185Count cache lines in the modified state. 186.It Li s 187Count cache lines in the shared state. 188.El 189.Pp 190The default is 191.Dq Li eims . 192.Pp 193Events that require a snoop response qualifier to be specified use an 194additional qualifier 195.Dq Li snoopresponse= Ns Ar response , 196where argument 197.Ar response 198comprises of the following keywords separated by 199.Dq + 200signs: 201.Bl -tag -width indent 202.It Li clean 203Measure CLEAN responses. 204.It Li hit 205Measure HIT responses. 206.It Li hitm 207Measure HITM responses. 208.El 209.Pp 210The default is to measure all the above responses. 211.Pp 212Events that require a snoop type qualifier use an additional qualifier 213.Dq Li snooptype= Ns Ar type , 214where argument 215.Ar type 216comprises the one of the following keywords: 217.Bl -tag -width indent 218.It Li cmp2i 219Measure CMP2I snoops. 220.It Li cmp2s 221Measure CMP2S snoops. 222.El 223.Pp 224The default is to measure both snoops. 225.Ss Event Specifiers (Programmable PMCs) 226Core2 programmable PMCs support the following events: 227.Bl -tag -width indent 228.It Li BACLEARS 229.Pq Event E6H 230The number of times the front end is resteered. 231.It Li BOGUS_BR 232.Pq Event E4H 233The number of byte sequences mistakenly detected as taken branch 234instructions. 235.It Li BR_BAC_MISSP_EXEC 236.Pq Event 8AH 237The number of branch instructions that were mispredicted when 238decoded. 239.It Li BR_CALL_MISSP_EXEC 240.Pq Event 93H 241The number of mispredicted 242.Li CALL 243instructions that were executed. 244.It Li BR_CALL_EXEC 245.Pq Event 92H 246The number of 247.Li CALL 248instructions executed. 249.It Li BR_CND_EXEC 250.Pq Event 8BH 251The number of conditional branches executed, but not necessarily retired. 252.It Li BR_CND_MISSP_EXEC 253.Pq Event 8CH 254The number of mispredicted conditional branches executed. 255.It Li BR_IND_CALL_EXEC 256.Pq Event 94H 257The number of indirect 258.Li CALL 259instructions executed. 260.It Li BR_IND_EXEC 261.Pq Event 8DH 262The number of indirect branch instructions executed. 263.It Li BR_IND_MISSP_EXEC 264.Pq Event 8EH 265The number of mispredicted indirect branch instructions executed. 266.It Li BR_INST_DECODED 267.Pq Event E0H 268The number of branch instructions decoded. 269.It Li BR_INST_EXEC 270.Pq Event 88H 271The number of branches executed, but not necessarily retired. 272.It Li BR_INST_RETIRED.ANY 273.Pq Event C4H , Umask 00H 274The number of branch instructions retired. 275.It Li BR_INST_RETIRED.MISPRED 276.Pq Event C5H 277The number of mispredicted branch instructions retired. 278.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN 279.Pq Event C4H , Umask 02H 280The number of not taken branch instructions retired that were 281mispredicted. 282.It Li BR_INST_RETIRED.MISPRED_TAKEN 283.Pq Event C4H , Umask 08H 284The number taken branch instructions retired that were mispredicted. 285.It Li BR_INST_RETIRED.PRED_NOT_TAKEN 286.Pq Event C4H , Umask 01H 287The number of not taken branch instructions retired that were 288correctly predicted. 289.It Li BR_INST_RETIRED.PRED_TAKEN 290.Pq Event C4H , Umask 04H 291The number of taken branch instructions retired that were correctly 292predicted. 293.It Li BR_INST_RETIRED.TAKEN 294.Pq Event C4H , Umask 0CH 295The number of taken branch instructions retired. 296.It Li BR_MISSP_EXEC 297.Pq Event 89H 298The number of mispredicted branch instructions that were executed. 299.It Li BR_RET_MISSP_EXEC 300.Pq Event 90H 301The number of mispredicted 302.Li RET 303instructions executed. 304.It Li BR_RET_BAC_MISSP_EXEC 305.Pq Event 91H 306The number of 307.Li RET 308instructions executed that were mispredicted at decode time. 309.It Li BR_RET_EXEC 310.Pq Event 8FH 311The number of 312.Li RET 313instructions executed. 314.It Li BR_TKN_BUBBLE_1 315.Pq Event 97H 316The number of branch predicted taken with bubble 1. 317.It Li BR_TKN_BUBBLE_2 318.Pq Event 98H 319The number of branch predicted taken with bubble 2. 320.It Li BUSQ_EMPTY Op ,core= Ns Ar core 321.Pq Event 7DH 322The number of cycles during which the core did not have any pending 323transactions in the bus queue. 324.It Li BUS_BNR_DRV Op ,agent= Ns Ar agent 325.Pq Event 61H 326The number of Bus Not Ready signals asserted on the bus. 327.It Li BUS_DATA_RCV Op ,core= Ns Ar core 328.Pq Event 64H 329The number of bus cycles during which the processor is receiving data. 330.It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent 331.Pq Event 62H 332The number of bus cycles during which the Data Ready signal is asserted 333on the bus. 334.It Li BUS_HIT_DRV Op ,agent= Ns Ar agent 335.Pq Event 7AH 336The number of bus cycles during which the processor drives the 337.Li HIT# 338pin. 339.It Li BUS_HITM_DRV Op ,agent= Ns Ar agent 340.Pq Event 7BH 341The number of bus cycles during which the processor drives the 342.Li HITM# 343pin. 344.It Li BUS_IO_WAIT Op ,core= Ns Ar core 345.Pq Event 7FH 346The number of core cycles during which I/O requests wait in the bus 347queue. 348.It Li BUS_LOCK_CLOCKS Xo 349.Op ,agent= Ns Ar agent 350.Op ,core= Ns Ar core 351.Xc 352.Pq Event 63H 353The number of bus cycles during which the 354.Li LOCK 355signal was asserted on the bus. 356.It Li BUS_REQUEST_OUTSTANDING Xo 357.Op ,agent= Ns Ar agent 358.Op ,core= Ns Ar core 359.Xc 360.Pq Event 60H 361The number of pending full cache line read transactions on the bus 362occuring in each cycle. 363.It Li BUS_TRANS_P Xo 364.Op ,agent= Ns Ar agent 365.Op ,core= Ns Ar core 366.Xc 367.Pq Event 6BH 368The number of partial bus transactions. 369.It Li BUS_TRANS_IFETCH Xo 370.Op ,agent= Ns Ar agent 371.Op ,core= Ns Ar core 372.Xc 373.Pq Event 68H 374The number of instruction fetch full cache line bus transactions. 375.It Li BUS_TRANS_INVAL Xo 376.Op ,agent= Ns Ar agent 377.Op ,core= Ns Ar core 378.Xc 379.Pq Event 69H 380The number of invalidate bus transactions. 381.It Li BUS_TRANS_PWR Xo 382.Op ,agent= Ns Ar agent 383.Op ,core= Ns Ar core 384.Xc 385.Pq Event 6AH 386The number of partial write bus transactions. 387.It Li BUS_TRANS_DEF Xo 388.Op ,agent= Ns Ar agent 389.Op ,core= Ns Ar core 390.Xc 391.Pq Event 6DH 392The number of deferred bus transactions. 393.It Li BUS_TRANS_BURST Xo 394.Op ,agent= Ns Ar agent 395.Op ,core= Ns Ar core 396.Xc 397.Pq Event 6EH 398The number of burst transactions. 399.It Li BUS_TRANS_MEM Xo 400.Op ,agent= Ns Ar agent 401.Op ,core= Ns Ar core 402.Xc 403.Pq Event 6FH 404The number of memory bus transactions. 405.It Li BUS_TRANS_ANY Xo 406.Op ,agent= Ns Ar agent 407.Op ,core= Ns Ar core 408.Xc 409.Pq Event 70H 410The number of bus transactions of any kind. 411.It Li BUS_TRANS_BRD Xo 412.Op ,agent= Ns Ar agent 413.Op ,core= Ns Ar core 414.Xc 415.Pq Event 65H 416The number of burst read transactions. 417.It Li BUS_TRANS_IO Xo 418.Op ,agent= Ns Ar agent 419.Op ,core= Ns Ar core 420.Xc 421.Pq Event 6CH 422The number of completed I/O bus transaactions due to 423.Li IN 424and 425.Li OUT 426instructions. 427.It Li BUS_TRANS_RFO Xo 428.Op ,agent= Ns Ar agent 429.Op ,core= Ns Ar core 430.Xc 431.Pq Event 66H 432The number of Read For Ownership bus transactions. 433.It Li BUS_TRANS_WB Xo 434.Op ,agent= Ns Ar agent 435.Op ,core= Ns Ar core 436.Xc 437.Pq Event 67H 438The number explicit writeback bus transactions due to dirty line 439evictions. 440.It Li CMP_SNOOP Xo 441.Op ,core= Ns Ar core 442.Op ,snooptype= Ns Ar snoop 443.Xc 444.Pq Event 78H 445The number of times the L1 data cache is snooped by the other core in 446the same processor. 447.It Li CPU_CLK_UNHALTED.BUS 448.Pq Event 3CH , Umask 01H 449The number of bus cycles when the core is not in the halt state. 450.It Li CPU_CLK_UNHALTED.CORE_P 451.Pq Event 3CH , Umask 00H 452The number of core cycles while the core is not in a halt state. 453.It Li CPU_CLK_UNHALTED.NO_OTHER 454.Pq Event 3CH , Umask 02H 455The number of bus cycles during which the core remains unhalted and 456the other core is halted. 457.It Li CYCLES_DIV_BUSY 458.Pq Event 14H 459The number of cycles the divider is busy. 460This event is only available on PMC0. 461.It Li CYCLES_INT_MASKED 462.Pq Event C6H , Umask 01H 463The number of cycles during which interrupts are disabled. 464.It Li CYCLES_INT_PENDING_AND_MASKED 465.Pq Event C6H , Umask 02H 466The number of cycles during which there were pending interrupts while 467interrupts were disabled. 468.It Li CYCLES_L1I_MEM_STALLED 469.Pq Event 86H 470The number of cycles for which an instruction fetch stalls. 471.It Li DELAYED_BYPASS.FP 472.Pq Event 19H , Umask 00H 473The number of floating point operations that used data immediately 474after the data was generated by a non floating point execution unit. 475.It Li DELAYED_BYPASS.LOAD 476.Pq Event 19H , Umask 01H 477The number of delayed bypass penalty cycles that a load operation incurred. 478.It Li DELAYED_BYPASS.SIMD 479.Pq Event 19H , Umask 02H 480The number of times SIMD operations use data immediately after data, 481was generated by a non-SIMD execution unit. 482.It Li DIV 483.Pq Event 13H 484The number of divide operations executed. 485This event is only available on PMC1. 486.It Li DTLB_MISSES.ANY 487.Pq Event 08H , Umask 01H 488The number of Data TLB misses, including misses that result from 489speculative accesses. 490.It Li DTLB_MISSES.L0_MISS_LD 491.Pq Event 08H , Umask 04H 492The number of level 0 DTLB misses due to load operations. 493.It Li DTLB_MISSES.MISS_LD 494.Pq Event 08H , Umask 02H 495The number of Data TLB misses due to load operations. 496.It Li DTLB_MISSES.MISS_ST 497.Pq Event 08H , Umask 08H 498The number of Data TLB misses due to store operations. 499.It Li EIST_TRANS 500.Pq Event 3AH 501The number of Enhanced Intel SpeedStep Technology transitions. 502.It Li ESP.ADDITIONS 503.Pq Event ABH , Umask 02H 504The number of automatic additions to the 505.Li %esp 506register. 507.It Li ESP.SYNCH 508.Pq Event ABH , Umask 01H 509The number of times the 510.Li %esp 511register was explicitly used in an address expression after 512it is implicitly used by a 513.Li PUSH 514or 515.Li POP 516instruction. 517.It Li EXT_SNOOP Xo 518.Op ,agent= Ns Ar agent 519.Op ,snoopresponse= Ns Ar response 520.Xc 521.Pq Event 77H 522The number of snoop responses to bus transactions. 523.It Li FP_ASSIST 524.Pq Event 11H 525The number of floating point operations executed that needed 526a microcode assist. 527.It Li FP_COMP_OPS_EXE 528.Pq Event 10H 529The number of floating point computational micro-ops executed. 530The event is available only on PMC0. 531.It Li FP_MMX_TRANS_TO_FP 532.Pq Event CCH , Umask 02H 533The number of transitions from MMX instructions to floating point 534instructions. 535.It Li FP_MMX_TRANS_TO_MMX 536.Pq Event CCH , Umask 01H 537The number of transitions from floating point instructions to MMX 538instructions. 539.It Li HW_INT_RCV 540.Pq Event C8H 541The number of hardware interrupts recieved. 542.It Li IDLE_DURING_DIV 543.Pq Event 18H 544The number of cycles the divider is busy and no other execution unit 545or load operation was in progress. 546This event is available only on PMC0. 547.It Li ILD_STALL 548.Pq Event 87H 549The number of cycles the instruction length decoder stalled due to a 550length changing prefix. 551.It Li INST_QUEUE.FULL 552.Pq Event 83H 553The number of cycles during which the instruction queue is full. 554.It Li INST_RETIRED.ANY_P 555.Pq Event C0H , Umask 00H 556The number of instructions retired. 557.It Li INST_RETIRED.LOADS 558.Pq Event C0H , Umask 01H 559The number of instructions retired that contained a load operation. 560.It Li INST_RETIRED.OTHER 561.Pq Event C0H 562The number of instructions retired that did not contain a load or a 563store operation. 564.It Li INST_RETIRED.STORES 565.Pq Event C0H 566The number of instructions retired that contained a store operation. 567.It Li INST_RETIRED.VM_H 568.Pq Event C0H , Tn Core2Extreme 569The number of instructions retired while in VMX root operation. 570.It Li ITLB.FLUSH 571.Pq Event 82H , Umask 40H 572The number of ITLB flushes. 573.It Li ITLB.LARGE_MISS 574.Pq Event 82H , Umask 10H 575The number of instruction fetches from large pages that miss the 576ITLB. 577.It Li ITLB.MISSES 578.Pq Event 82H , Umask 12H 579The number of instruction fetches from both large and small pages that 580miss the ITLB. 581.It Li ITLB.SMALL_MISS 582.Pq Event 82H , Umask 02H 583The number of instruction fetches from small pages that miss the ITLB. 584.It Li ITLB_MISS_RETIRED 585.Pq Event C9H 586The number of retired instructions that missed the ITLB when they were 587fetched. 588.It Li L1D_ALL_REF 589.Pq Event 43H , Umask 01H 590The number of references to L1 data cache counting loads and stores of 591to all memory types. 592.It Li L1D_ALL_CACHE_REF 593.Pq Event 43H , Umask 02H 594The number of data reads and writes to cacheable memory. 595.It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state 596.Pq Event 42H 597The number of locked reads from cacheable memory. 598.It Li L1D_CACHE_LOCK_DURATION 599.Pq Event 42H 600The number of cycles during which any cache line is locked by any 601locking instruction. 602.It Li L1D_CACHE_LD Op ,cachestate= Ns Ar state 603.Pq Event 40H 604The number of data reads from cacheable memory excluding locked 605reads. 606.It Li L1D_CACHE_ST Op ,cachestate= Ns Ar state 607.Pq Event 41H 608The number of data writes to cacheable memory excluding locked 609writes. 610.It Li L1D_M_EVICT 611.Pq Event 47H 612The number of modified cache lines evicted from L1 data cache. 613.It Li L1D_M_REPL 614.Pq Event 46H 615The number of modified lines allocated in L1 data cache. 616.It Li L1D_PEND_MISS 617.Pq Event 48H 618The total number of outstanding L1 data cache misses at any clock. 619.It Li L1D_PREFETCH. 620.Pq Event 4EH 621The number of times L1 data cache requested to prefetch a data cache 622line. 623.It Li L1D_REPL 624.Pq Event 45H 625The number of lines brought into L1 data cache. 626.It Li L1D_SPLIT.LOADS 627.Pq Event 49H , Umask 01H 628The number of load operations that span two cache lines. 629.It Li L1D_SPLIT.STORES 630.Pq Event 49H , Umask 02H 631The number of store operations that span two cache lines. 632.It Li L1I_MISSES 633.Pq Event 81H 634The number of instruction fetch unit misses. 635.It Li L1I_READS 636.Pq Event 80H 637The number of instruction fetches. 638.It Li L2_ADS Op ,core= Ns core 639.Pq Event 21H 640The number of cycles that the L2 address bus is in use. 641.It Li L2_DBUS_BUSY_RD Op ,core= Ns core 642.Pq Event 23H 643The number of cycles during which the L2 data bus is busy transferring 644data to the core. 645.It Li L2_IFETCH Xo 646.Op ,cachestate= Ns Ar state 647.Op ,core= Ns Ar core 648.Xc 649.Pq Event 28H 650The number of instruction cache line requests from the instruction 651fetch unit. 652.It Li L2_LD Xo 653.Op ,cachestate= Ns Ar state 654.Op ,core= Ns Ar core 655.Op ,prefech= Ns Ar prefetch 656.Xc 657.Pq Event 29H 658The number of L2 cache read requests from L1 cache and L2 659prefetchers. 660.It Li L2_LINES_IN Xo 661.Op ,core= Ns Ar core 662.Op ,prefetch= Ns Ar prefetch 663.Xc 664.Pq Event 24H 665The number of cache lines allocated in L2 cache. 666.It Li L2_LINES_OUT Xo 667.Op ,core= Ns Ar core 668.Op ,prefetch= Ns Ar prefetch 669.Xc 670.Pq Event 26H 671The number of L2 cache lines evicted. 672.It Li L2_LOCK Xo 673.Op ,cachestate= Ns Ar state 674.Op ,core= Ns Ar core 675.Xc 676.Pq Event 2BH 677The number of locked accesses to cache lines that miss L1 data 678cache. 679.It Li L2_M_LINES_IN Op ,core= Ns Ar core 680.Pq Event 25H 681The number of L2 cache line modifications. 682.It Li L2_M_LINES_OUT Xo 683.Op ,core= Ns Ar core 684.Op ,prefetch= Ns Ar prefetch 685.Xc 686.Pq Event 27H 687The number of modified lines evicted from L2 cache. 688.It Li L2_NO_REQ Op ,core= Ns Ar core 689.Pq Event 32H 690The number of cycles during which no L2 cache requests were pending 691from a core. 692.It Li L2_REJECT_BUSQ Xo 693.Op ,cachestate= Ns Ar state 694.Op ,core= Ns Ar core 695.Op ,prefetch= Ns Ar prefetch 696.Xc 697.Pq Event 30H 698The number of L2 cache requests that were rejected. 699.It Li L2_RQSTS Xo 700.Op ,cachestate= Ns Ar state 701.Op ,core= Ns Ar core 702.Op ,prefetch= Ns Ar prefetch 703.Xc 704.Pq Event 2EH 705The number of completed L2 cache requests. 706.It Li L2_RQSTS.SELF.DEMAND.I_STATE 707.Pq Event 2EH , Umask 41H 708The number of completed L2 cache demand requests from this core that 709missed the L2 cache. 710.It Li L2_RQSTS.SELF.DEMAND.MESI 711.Pq Event 2EH , Umask 4FH 712The number of completed L2 cache demand requests from this core. 713.It Li L2_ST Xo 714.Op ,cachestate= Ns Ar state 715.Op ,core= Ns Ar core 716.Xc 717.Pq Event 2AH 718The number of store operations that miss the L1 cache and request data 719from the L2 cache. 720.It Li LOAD_BLOCK.L1D 721.Pq Event 03H , Umask 20H 722The number of loads blocked by the L1 data cache. 723.It Li LOAD_BLOCK.OVERLAP_STORE 724.Pq Event 03H , Umask 08H 725The number of loads that partially overlap an earlier store or are 726aliased with a previous store. 727.It Li LOAD_BLOCK.STA 728.Pq Event 03H , Umask 02H 729The number of loads blocked by preceding stores whose address is yet 730to be calculated. 731.It Li LOAD_BLOCK.STD 732.Pq Event 03H , Umask 04H 733The number of loads blocked by preceding stores to the same address 734whose data value is not known. 735.It Li LOAD_BLOCK.UNTIL_RETIRE 736.Pq Event 03H , Umask 10H 737The numer of load operations that were blocked until retirement. 738.It Li LOAD_HIT_PRE 739.Pq Event 4CH 740The number of load operations that conflicted with an prefetch to the 741same cache line. 742.It Li MACHINE_NUKES.SMC 743.Pq Event C3H , Umask 01H 744The number of times a program writes to a code section. 745.It Li MACHINE_NUKES.MEM_ORDER 746.Pq Event C3H , Umask 04H 747The number of times the execution pipeline was restarted due to a 748memory ordering conflict or memory disambiguation misprediction. 749.It Li MACRO_INSTS.CISC_DECODED 750.Pq Event AAH , Umask 08H 751The number of complex instructions decoded. 752.It Li MACRO_INSTS.DECODED 753.Pq Event AAH , Umask 01H 754The number of instructions decoded. 755.It Li MEMORY_DISAMBIGUATION.RESET 756.Pq Event 09H , Umask 01H 757The number of cycles during which memory disambiguation misprediction 758occurs. 759.It Li MEMORY_DISAMBIGUATION.SUCCESS 760.Pq Event 09H , Umask 02H 761The number of load operations that were successfully disambiguated. 762.It Li MEM_LOAD_RETIRED.DTLB_MISS 763.Pq Event CBH , Umask 10H 764The number of retired loads that missed the DTLB. 765.It Li MEM_LOAD_RETIRED.L1D_LINE_MISS 766.Pq Event CBH , Umask 02H 767The number of retired load operations that missed L1 data cache and 768that sent a request to L2 cache. 769This event is only available on PMC0. 770.It Li MEM_LOAD_RETIRED.L1D_MISS 771.Pq Event CBH , Umask 01H 772The number of retired load operations that missed L1 data cache. 773This event is only available on PMC0. 774.It Li MEM_LOAD_RETIRED.L2_LINE_MISS 775.Pq Event CBH , Umask 08H 776The number of load operations that missed L2 cache and that caused a 777bus request. 778.It Li MEM_LOAD_RETIRED.L2_MISS 779.Pq Event CBH , Umask 04H 780The number of load operations that missed L2 cache. 781.It Li MUL 782.Pq Event 12H 783The number of multiply operations executed. 784This event is only available on PMC1. 785.It Li PAGE_WALKS.COUNT 786.Pq Event 0CH , Umask 01H 787The number of page walks executed due to an ITLB or DTLB miss. 788.It Li PAGE_WALKS.CYCLES 789.Pq Event 0CH , Umask 02H 790The number of cycles spent in a page walk caused by an ITLB or DTLB 791miss. 792.It Li PREF_RQSTS_DN 793.Pq Event F8H 794The number of downward prefetches issued from the Data Prefetch Logic 795unit to L2 cache. 796.It Li PREF_RQSTS_UP 797.Pq Event F0H 798The number of upward prefetches issued from the Data Prefetch Logic 799unit to L2 cache. 800.It Li RAT_STALLS.ANY 801.Pq Event D2H , Umask 0FH 802The number of stall cycles due to any of 803.Li RAT_STALLS.FLAGS 804.Li RAT_STALLS.FPSW , 805.Li RAT_STALLS.PARTIAL 806and 807.Li RAT_STALLS.ROB_READ_PORT . 808.It Li RAT_STALLS.FLAGS 809.Pq Event D2H , Umask 04H 810The number of cycles execution stalled due to a flag register induced 811stall. 812.It Li RAT_STALLS.FPSW 813.Pq Event D2H , Umask 08H 814The number of times the floating point status word was written. 815.It Li RAT_STALLS.OTHER_SERIALIZATION_STALLS 816.Pq Event D2H , Umask 10H , Tn Core2Extreme 817The number of stalls due to other RAT resource serialization not 818counted by umask 0FH. 819.It Li RAT_STALLS.PARTIAL_CYCLES 820.Pq Event D2H , Umask 02H 821The number of cycles of added instruction execution latency due to the 822use of a register that was partially written by previous instructions. 823.It Li RAT_STALLS.ROB_READ_PORT 824.Pq Event D2H , Umask 01H 825The number of cycles when ROB read port stalls occurred. 826.It Li RESOURCE_STALLS.ANY 827.Pq Event DCH , Umask 1FH 828The number of cycles during which any resource related stall 829occurred. 830.It Li RESOURCE_STALLS.BR_MISS_CLEAR 831.Pq Event DCH , Umask 10H 832The number of cycles stalled due to branch misprediction. 833.It Li RESOURCE_STALLS.FPCW 834.Pq Event DCH , Umask 08H 835The number of cycles stalled due to writing the floating point control 836word. 837.It Li RESOURCE_STALLS.LD_ST 838.Pq Event DCH , Umask 04H 839The number of cycles during which the number of loads and stores in 840the pipeline exceeded their limits. 841.It Li RESOURCE_STALLS.ROB_FULL 842.Pq Event DCH , Umask 01H 843The number of cycles when the reorder buffer was full. 844.It Li RESOURCE_STALLS.RS_FULL 845.Pq Event DCH , Umask 02H 846The number of cycles during which the RS was full. 847.It Li RS_UOPS_DISPATCHED 848.Pq Event A0H , Umask 00H 849The number of micro-ops dispatched for execution. 850.It Li RS_UOPS_DISPATCHED.PORT0 851.Pq Event A1H , Umask 01H 852The number of cycles micro-ops were dispatched for execution on port 8530. 854.It Li RS_UOPS_DISPATCHED.PORT1 855.Pq Event A1H , Umask 02H 856The number of cycles micro-ops were dispatched for execution on port 8571. 858.It Li RS_UOPS_DISPATCHED.PORT2 859.Pq Event A1H , Umask 04H 860The number of cycles micro-ops were dispatched for execution on port 8612. 862.It Li RS_UOPS_DISPATCHED.PORT3 863.Pq Event A1H , Umask 08H 864The number of cycles micro-ops were dispatched for execution on port 8653. 866.It Li RS_UOPS_DISPATCHED.PORT4 867.Pq Event A1H , Umask 10H 868The number of cycles micro-ops were dispatched for execution on port 8694. 870.It Li RS_UOPS_DISPATCHED.PORT5 871.Pq Event A1H , Umask 20 872The number of cycles micro-ops were dispatched for execution on port 8735. 874.It Li SB_DRAIN_CYCLES 875.Pq Event 04H , Umask 01H 876The number of cycles while the store buffer is draining. 877.It Li SEGMENT_REG_LOADS 878.Pq Event 06H 879The number of segment register loads. 880.It Li SEG_REG_RENAMES.ANY 881.Pq Event D5H , Umask 0FH 882The number of times the any segment register was renamed. 883.It Li SEG_REG_RENAMES.DS 884.Pq Event D5H , Umask 02H 885The number of times the 886.Li %ds 887register is renamed. 888.It Li SEG_REG_RENAMES.ES 889.Pq Event D5H , Umask 01H 890The number of times the 891.Li %es 892register is renamed. 893.It Li SEG_REG_RENAMES.FS 894.Pq Event D5H , Umask 04H 895The number of times the 896.Li %fs 897register is renamed. 898.It Li SEG_REG_RENAMES.GS 899.Pq Event D5H , Umask 08H 900The number of times the 901.Li %gs 902register is renamed. 903.It Li SEG_RENAME_STALLS.ANY 904.Pq Event D4H , Umask 0FH 905The number of stalls due to lack of resource to rename any segment 906register. 907.It Li SEG_RENAME_STALLS.DS 908.Pq Event D4H , Umask 02H 909The number of stalls due to lack of renaming resources for the 910.Li %ds 911register. 912.It Li SEG_RENAME_STALLS.ES 913.Pq Event D4H , Umask 01H 914The number of stalls due to lack of renaming resources for the 915.Li %es 916register. 917.It Li SEG_RENAME_STALLS.FS 918.Pq Event D4H , Umask 04H 919The number of stalls due to lack of renaming resources for the 920.Li %fs 921register. 922.It Li SEG_RENAME_STALLS.GS 923.Pq Event D4H , Umask 08H 924The number of stalls due to lack of renaming resources for the 925.Li %gs 926register. 927.It Li SIMD_ASSIST 928.Pq Event CDH 929The number SIMD assists invoked. 930.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE 931.Pq Event CAH , Umask 04H 932Then number of computational SSE2 packed double precision instructions 933retired. 934.It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE 935.Pq Event CAH , Umask 01H 936Then number of computational SSE2 packed single precision instructions 937retired. 938.It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE 939.Pq Event CAH , Umask 08H 940Then number of computational SSE2 scalar double precision instructions 941retired. 942.It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE 943.Pq Event CAH , Umask 02H 944Then number of computational SSE2 scalar single precision instructions 945retired. 946.It Li SIMD_INSTR_RETIRED 947.Pq Event CEH 948The number of retired SIMD instructions that use MMX registers. 949.It Li SIMD_INST_RETIRED.ANY 950.Pq Event C7H , Umask 1FH 951The number of streaming SIMD instructions retired. 952.It Li SIMD_INST_RETIRED.PACKED_DOUBLE 953.Pq Event C7H , Umask 04H 954The number of SSE2 packed double precision instructions retired. 955.It Li SIMD_INST_RETIRED.PACKED_SINGLE 956.Pq Event C7H , Umask 01H 957The number of SSE packed single precision instructions retired. 958.It Li SIMD_INST_RETIRED.SCALAR_DOUBLE 959.Pq Event C7H , Umask 08H 960The number of SSE2 scalar double precision instructions retired. 961.It Li SIMD_INST_RETIRED.SCALAR_SINGLE 962.Pq Event C7H , Umask 02H 963The number of SSE scalar single precision instructions retired. 964.It Li SIMD_INST_RETIRED.VECTOR 965.Pq Event C7H , Umask 10H 966The number of SSE2 vector instructions retired. 967.It Li SIMD_SAT_INSTR_RETIRED 968.Pq Event CFH 969The number of saturated arithmetic SIMD instructions retired. 970.It Li SIMD_SAT_UOP_EXEC 971.Pq Event B1H 972The number of SIMD saturated arithmetic micro-ops executed. 973.It Li SIMD_UOPS_EXEC 974.Pq Event B0H 975The number of SIMD micro-ops executed. 976.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC 977.Pq Event B3H , Umask 20H 978The number of SIMD packed arithmetic micro-ops executed. 979.It Li SIMD_UOP_TYPE_EXEC.LOGICAL 980.Pq Event B3H , Umask 10H 981The number of SIMD packed logical micro-ops executed. 982.It Li SIMD_UOP_TYPE_EXEC.MUL 983.Pq Event B3H , Umask 01H 984The number of SIMD packed multiply micro-ops executed. 985.It Li SIMD_UOP_TYPE_EXEC.PACK 986.Pq Event B3H , Umask 04H 987The number of SIMD pack micro-ops executed. 988.It Li SIMD_UOP_TYPE_EXEC.SHIFT 989.Pq Event B3H , Umask 02H 990The number of SIMD packed shift micro-ops executed. 991.It Li SIMD_UOP_TYPE_EXEC.UNPACK 992.Pq Event B3H , Umask 08H 993The number of SIMD unpack micro-ops executed. 994.It Li SNOOP_STALL_DRV Xo 995.Op ,agent= Ns Ar agent 996.Op ,core= Ns Ar core 997.Xc 998.Pq Event 7EH 999The number of times the bus stalled for snoops. 1000.It Li SSE_PRE_EXEC.L1 1001.Pq Event 07H , Umask 01H 1002The number of 1003.Li PREFETCHT0 1004instructions executed. 1005.It Li SSE_PRE_EXEC.L2 1006.Pq Event 07H , Umask 02H 1007The number of 1008.Li PREFETCHT1 1009instructions executed. 1010.It Li SSE_PRE_EXEC.NTA 1011.Pq Event 07H , Umask 00H 1012The number of 1013.Li PREFETCHNTA 1014instructions executed. 1015.It Li SSE_PRE_EXEC.STORES 1016.Pq Event 07H , Umask 03H 1017The number of times SSE non-temporal store instructions were executed. 1018.It Li SSE_PRE_MISS.L1 1019.Pq Event 4BH , Umask 01H 1020The number of times the 1021.Li PREFETCHT0 1022instruction executed and missed all cache levels. 1023.It Li SSE_PRE_MISS.L2 1024.Pq Event 4BH , Umask 02H 1025The number of times the 1026.Li PREFETCHT1 1027instruction executed and missed all cache levels. 1028.It Li SSE_PRE_MISS.NTA 1029.Pq Event 4BH , Umask 00H 1030The number of times the 1031.Li PREFETCHNTA 1032instruction executed and missed all cache levels. 1033.It Li STORE_BLOCK.ORDER 1034.Pq Event 04H , Umask 02H 1035The number of cycles while a store was waiting for another store to be 1036globally observed. 1037.It Li STORE_BLOCK.SNOOP 1038.Pq Event 04H , Umask 08H 1039The number of cycles while a store was blocked due to a conflict with 1040an internal or external snoop. 1041.It Li THERMAL_TRIP 1042.Pq Event 3BH 1043The number of thermal trips. 1044.It Li UOPS_RETIRED.LD_IND_BR 1045.Pq Event C2H , Umask 01H 1046The number of micro-ops retired that fused a load with another 1047operation. 1048.It Li UOPS_RETIRED.STD_STA 1049.Pq Event C2H , Umask 02H 1050The number of store address calculations that fused into one micro-op. 1051.It Li UOPS_RETIRED.MACRO_FUSION 1052.Pq Event C2H , Umask 04H 1053The number of times retired instruction pairs were fused into one 1054micro-op. 1055.It Li UOPS_RETIRED.FUSED 1056.Pq Event C2H , Umask 07H 1057The number of fused micro-ops retired. 1058.It Li UOPS_RETIRED.NON_FUSED 1059.Pq Event C2H , Umask 8H 1060The number of non-fused micro-ops retired. 1061.It Li UOPS_RETIRED.ANY 1062.Pq Event C2H , Umask 0FH 1063The number of micro-ops retired. 1064.It Li X87_OPS_RETIRED.ANY 1065.Pq Event C1H , Umask FEH 1066The number of floating point computational instructions retired. 1067.It Li X87_OPS_RETIRED.FXCH 1068.Pq Event C1H , Umask 01H 1069The number of 1070.Li FXCH 1071instructions retired. 1072.El 1073.Ss Event Name Aliases 1074The following table shows the mapping between the PMC-independent 1075aliases supported by 1076.Lb libpmc 1077and the underlying hardware events used. 1078.Bl -column "branch-mispredicts" "Description" 1079.It Em Alias Ta Em Event 1080.It Li branches Ta Li BR_INST_RETIRED.ANY 1081.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED 1082.It Li dc-misses Ta Li L2_ST,core=this,cachestate=mesi 1083.It Li ic-misses Ta Li L1I_MISSES 1084.It Li instructions Ta Li INST_RETIRED.ANY_P 1085.It Li interrupts Ta Li HW_INT_RCV 1086.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P 1087.El 1088.Sh SEE ALSO 1089.Xr pmc 3 , 1090.Xr pmc.atom 3 , 1091.Xr pmc.core 3 , 1092.Xr pmc.iaf 3 , 1093.Xr pmc.k7 3 , 1094.Xr pmc.k8 3 , 1095.Xr pmc.p4 3 , 1096.Xr pmc.p5 3 , 1097.Xr pmc.p6 3 , 1098.Xr pmc.tsc 3 , 1099.Xr pmc_cpuinfo 3 , 1100.Xr pmclog 3 , 1101.Xr hwpmc 4 1102.Sh HISTORY 1103The 1104.Nm pmc 1105library first appeared in 1106.Fx 6.0 . 1107.Sh AUTHORS 1108The 1109.Lb libpmc 1110library was written by 1111.An "Joseph Koshy" 1112.Aq jkoshy@FreeBSD.org . 1113