1.\" Copyright (c) 2008 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd November 12, 2008 25.Dt PMC.CORE 3 26.Os 27.Sh NAME 28.Nm pmc.core 29.Nd measurement events for 30.Tn Intel 31.Tn Core Solo 32and 33.Tn Core Duo 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Core Solo" 42and 43.Tn "Core Duo" 44CPUs contain PMCs conforming to version 1 of the 45.Tn Intel 46performance measurement architecture. 47.Pp 48These PMCs are documented in 49.Rs 50.%B IA-32 Intel\(rg Architecture Software Developer's Manual 51.%T Volume 3: System Programming Guide 52.%N Order Number 253669-027US 53.%D July 2008 54.%Q Intel Corporation 55.Re 56.Ss PMC Features 57CPUs conforming to version 1 of the 58.Tn Intel 59performance measurement architecture contain two programmable PMCs of 60class 61.Li PMC_CLASS_IAP . 62The PMCs are 40 bits width and offer the following capabilities: 63.Bl -column "PMC_CAP_INTERRUPT" "Support" 64.It Em Capability Ta Em Support 65.It PMC_CAP_CASCADE Ta \&No 66.It PMC_CAP_EDGE Ta Yes 67.It PMC_CAP_INTERRUPT Ta Yes 68.It PMC_CAP_INVERT Ta Yes 69.It PMC_CAP_READ Ta Yes 70.It PMC_CAP_PRECISE Ta \&No 71.It PMC_CAP_SYSTEM Ta Yes 72.It PMC_CAP_TAGGING Ta \&No 73.It PMC_CAP_THRESHOLD Ta Yes 74.It PMC_CAP_USER Ta Yes 75.It PMC_CAP_WRITE Ta Yes 76.El 77.Ss Event Qualifiers 78Event specifiers for these PMCs support the following common 79qualifiers: 80.Bl -tag -width indent 81.It Li cmask= Ns Ar value 82Configure the PMC to increment only if the number of configured 83events measured in a cycle is greater than or equal to 84.Ar value . 85.It Li edge 86Configure the PMC to count the number of de-asserted to asserted 87transitions of the conditions expressed by the other qualifiers. 88If specified, the counter will increment only once whenever a 89condition becomes true, irrespective of the number of clocks during 90which the condition remains true. 91.It Li inv 92Invert the sense of comparison when the 93.Dq Li cmask 94qualifier is present, making the counter increment when the number of 95events per cycle is less than the value specified by the 96.Dq Li cmask 97qualifier. 98.It Li os 99Configure the PMC to count events happening at processor privilege 100level 0. 101.It Li usr 102Configure the PMC to count events occurring at privilege levels 1, 2 103or 3. 104.El 105.Pp 106If neither of the 107.Dq Li os 108or 109.Dq Li usr 110qualifiers are specified, the default is to enable both. 111.Pp 112Events that require core-specificity to be specified use a 113additional qualifier 114.Dq Li core= Ns Ar value , 115where argument 116.Ar value 117is one of: 118.Bl -tag -width indent -compact 119.It Li all 120Measure event conditions on all cores. 121.It Li this 122Measure event conditions on this core. 123.El 124The default is 125.Dq Li this . 126.Pp 127Events that require an agent qualifier to be specified use an 128additional qualifier 129.Dq Li agent= Ns value , 130where argument 131.Ar value 132is one of: 133.Bl -tag -width indent -compact 134.It Li this 135Measure events associated with this bus agent. 136.It Li any 137Measure events caused by any bus agent. 138.El 139The default is 140.Dq Li this . 141.Pp 142Events that require a hardware prefetch qualifier to be specified use an 143additional qualifier 144.Dq Li prefetch= Ns Ar value , 145where argument 146.Ar value 147is one of: 148.Bl -tag -width "exclude" -compact 149.It Li both 150Include all prefetches. 151.It Li only 152Only count hardware prefetches. 153.It Li exclude 154Exclude hardware prefetches. 155.El 156The default is 157.Dq Li both . 158.Pp 159Events that require a cache coherence qualifier to be specified use an 160additional qualifier 161.Dq Li cachestate= Ns Ar value , 162where argument 163.Ar value 164contains one or more of the following letters: 165.Bl -tag -width indent -compact 166.It Li e 167Count cache lines in the exclusive state. 168.It Li i 169Count cache lines in the invalid state. 170.It Li m 171Count cache lines in the modified state. 172.It Li s 173Count cache lines in the shared state. 174.El 175The default is 176.Dq Li eims . 177.Ss Event Specifiers 178The following event names are case insensitive. 179Whitespace, hyphens and underscore characters in these names are 180ignored. 181.Pp 182Core PMCs support the following events: 183.Bl -tag -width indent 184.It Li BAClears 185.Pq Event E6H , Umask 00H 186The number of BAClear conditions asserted. 187.It Li BTB_Misses 188.Pq Event E2H , Umask 00H 189The number of branches for which the branch table buffer did not 190produce a prediction. 191.It Li Br_BAC_Missp_Exec 192.Pq Event 8AH , Umask 00H 193The number of branch instructions executed that were mispredicted at 194the front end. 195.It Li Br_Bogus 196.Pq Event E4H , Umask 00H 197The number of bogus branches. 198.It Li Br_Call_Exec 199.Pq Event 92H , Umask 00H 200The number of 201.Li CALL 202instructions executed. 203.It Li Br_Call_Missp_Exec 204.Pq Event 93H , Umask 00H 205The number of 206.Li CALL 207instructions executed that were mispredicted. 208.It Li Br_Cnd_Exec 209.Pq Event 8BH , Umask 00H 210The number of conditional branch instructions executed. 211.It Li Br_Cnd_Missp_Exec 212.Pq Event 8CH , Umask 00H 213The number of conditional branch instructions executed that were mispredicted. 214.It Li Br_Ind_Call_Exec 215.Pq Event 94H , Umask 00H 216The number of indirect 217.Li CALL 218instructions executed. 219.It Li Br_Ind_Exec 220.Pq Event 8DH , Umask 00H 221The number of indirect branches executed. 222.It Li Br_Ind_Missp_Exec 223.Pq Event 8EH , Umask 00H 224The number of indirect branch instructions executed that were mispredicted. 225.It Li Br_Inst_Exec 226.Pq Event 88H , Umask 00H 227The number of branch instructions executed including speculative branches. 228.It Li Br_Instr_Decoded 229.Pq Event E0H , Umask 00H 230The number of branch instructions decoded. 231.It Li Br_Instr_Ret 232.Pq Event C4H , Umask 00H 233.Pq Alias Qq "Branch Instruction Retired" 234The number of branch instructions retired. 235This is an architectural performance event. 236.It Li Br_MisPred_Ret 237.Pq Event C5H , Umask 00H 238.Pq Alias Qq "Branch Misses Retired" 239The number of mispredicted branch instructions retired. 240This is an architectural performance event. 241.It Li Br_MisPred_Taken_Ret 242.Pq Event CAH , Umask 00H 243The number of taken and mispredicted branches retired. 244.It Li Br_Missp_Exec 245.Pq Event 89H , Umask 00H 246The number of branch instructions executed and mispredicted at 247execution including branches that were not predicted. 248.It Li Br_Ret_BAC_Missp_Exec 249.Pq Event 91H , Umask 00H 250The number of return branch instructions that were mispredicted at the 251front end. 252.It Li Br_Ret_Exec 253.Pq Event 8FH , Umask 00H 254The number of return branch instructions executed. 255.It Li Br_Ret_Missp_Exec 256.Pq Event 90H , Umask 00H 257The number of return branch instructions executed that were mispredicted. 258.It Li Br_Taken_Ret 259.Pq Event C9H , Umask 00H 260The number of taken branches retired. 261.It Li Bus_BNR_Clocks 262.Pq Event 61H , Umask 00H 263The number of external bus cycles while BNR (bus not ready) was asserted. 264.It Li Bus_DRDY_Clocks Op ,agent= Ns Ar agent 265.Pq Event 62H , Umask 00H 266The number of external bus cycles while DRDY was asserted. 267.It Li Bus_Data_Rcv 268.Pq Event 64H , Umask 40H 269.\" XXX Using the description in Core2 PMC documentation. 270The number of cycles during which the processor is busy receiving data. 271.It Li Bus_Locks_Clocks Op ,core= Ns Ar core 272.Pq Event 63H 273The number of external bus cycles while the bus lock signal was asserted. 274.It Li Bus_Not_In_Use Op ,core= Ns Ar core 275.Pq Event 7DH 276The number of cycles when there is no transaction from the core. 277.It Li Bus_Req_Outstanding Xo 278.Op ,agent= Ns Ar agent 279.Op ,core= Ns Ar core 280.Xc 281.Pq Event 60H 282The weighted cycles of cacheable bus data read requests 283from the data cache unit or hardware prefetcher. 284.It Li Bus_Snoop_Stall 285.Pq Event 7EH , Umask 00H 286The number bus cycles while a bus snoop is stalled. 287.It Li Bus_Snoops Xo 288.Op ,agent= Ns Ar agent 289.Op ,cachestate= Ns Ar mesi 290.Xc 291.Pq Event 77H 292.\" XXX Using the description in Core2 PMC documentation. 293The number of snoop responses to bus transactions. 294.It Li Bus_Trans_Any Op ,agent= Ns Ar agent 295.Pq Event 70H 296The number of completed bus transactions. 297.It Li Bus_Trans_Brd Op ,core= Ns Ar core 298.Pq Event 65H 299The number of read bus transactions. 300.It Li Bus_Trans_Burst Op ,agent= Ns Ar agent 301.Pq Event 6EH 302The number of completed burst transactions. 303Retried transactions may be counted more than once. 304.It Li Bus_Trans_Def Op ,core= Ns Ar core 305.Pq Event 6DH 306The number of completed deferred transactions. 307.It Li Bus_Trans_IO Xo 308.Op ,agent= Ns Ar agent 309.Op ,core= Ns Ar core 310.Xc 311.Pq Event 6CH 312The number of completed I/O transactions counting both reads and 313writes. 314.It Li Bus_Trans_Ifetch Xo 315.Op ,agent= Ns Ar agent 316.Op ,core= Ns Ar core 317.Xc 318.Pq Event 68H 319Completed instruction fetch transactions. 320.It Li Bus_Trans_Inval Xo 321.Op ,agent= Ns Ar agent 322.Op ,core= Ns Ar core 323.Xc 324.Pq Event 69H 325The number completed invalidate transactions. 326.It Li Bus_Trans_Mem Op ,agent= Ns Ar agent 327.Pq Event 6FH 328The number of completed memory transactions. 329.It Li Bus_Trans_P Xo 330.Op ,agent= Ns Ar agent 331.Op ,core= Ns Ar core 332.Xc 333.Pq Event 6BH 334The number of completed partial transactions. 335.It Li Bus_Trans_Pwr Xo 336.Op ,agent= Ns Ar agent 337.Op ,core= Ns Ar core 338.Xc 339.Pq Event 6AH 340The number of completed partial write transactions. 341.It Li Bus_Trans_RFO Xo 342.Op ,agent= Ns Ar agent 343.Op ,core= Ns Ar core 344.Xc 345.Pq Event 66H 346The number of completed read-for-ownership transactions. 347.It Li Bus_Trans_WB Op ,agent= Ns Ar agent 348.Pq Event 67H 349The number of completed write-back transactions from the data cache 350unit, excluding L2 write-backs. 351.It Li Cycles_Div_Busy 352.Pq Event 14H , Umask 00H 353The number of cycles the divider is busy. 354The event is only available on PMC0. 355.It Li Cycles_Int_Masked 356.Pq Event C6H , Umask 00H 357The number of cycles while interrupts were disabled. 358.It Li Cycles_Int_Pending_Masked 359.Pq Event C7H , Umask 00H 360The number of cycles while interrupts were disabled and interrupts 361were pending. 362.It Li DCU_Snoop_To_Share Op ,core= Ns core 363.Pq Event 78H 364The number of data cache unit snoops to L1 cache lines in the shared 365state. 366.It Li DCache_Cache_Lock Op ,cachestate= Ns Ar mesi 367.\" XXX needs clarification 368.Pq Event 42H 369The number of cacheable locked read operations to invalid state. 370.It Li DCache_Cache_LD Op ,cachestate= Ns Ar mesi 371.Pq Event 40H 372The number of cacheable L1 data read operations. 373.It Li DCache_Cache_ST Op ,cachestate= Ns Ar mesi 374.Pq Event 41H 375The number cacheable L1 data write operations. 376.It Li DCache_M_Evict 377.Pq Event 47H , Umask 00H 378The number of M state data cache lines that were evicted. 379.It Li DCache_M_Repl 380.Pq Event 46H , Umask 00H 381The number of M state data cache lines that were allocated. 382.It Li DCache_Pend_Miss 383.Pq Event 48H , Umask 00H 384The weighted cycles an L1 miss was outstanding. 385.It Li DCache_Repl 386.Pq Event 45H , Umask 0FH 387The number of data cache line replacements. 388.It Li Data_Mem_Cache_Ref 389.Pq Event 44H , Umask 02H 390The number of cacheable read and write operations to L1 data cache. 391.It Li Data_Mem_Ref 392.Pq Event 43H , Umask 01H 393The number of L1 data reads and writes, both cacheable and 394un-cacheable. 395.It Li Dbus_Busy Op ,core= Ns Ar core 396.Pq Event 22H 397The number of core cycles during which the data bus was busy. 398.It Li Dbus_Busy_Rd Op ,core= Ns Ar core 399.Pq Event 23H 400The number of cycles during which the data bus was busy transferring 401data to a core. 402.It Li Div 403.Pq Event 13H , Umask 00H 404The number of divide operations including speculative operations for 405integer and floating point divides. 406This event can only be counted on PMC1. 407.It Li Dtlb_Miss 408.Pq Event 49H , Umask 00H 409The number of data references that missed the TLB. 410.It Li ESP_Uops 411.Pq Event D7H , Umask 00H 412The number of ESP folding instructions decoded. 413.It Li EST_Trans Op ,trans= Ns Ar transition 414.Pq Event 3AH 415Count the number of Intel Enhanced SpeedStep transitions. 416The argument 417.Ar transition 418can be one of the following values: 419.Bl -tag -width indent -compact 420.It Li any 421(Umask 00H) Count all transitions. 422.It Li frequency 423(Umask 01H) Count frequency transitions. 424.El 425The default is 426.Dq Li any . 427.It Li FP_Assist 428.Pq Event 11H , Umask 00H 429The number of floating point operations that required microcode 430assists. 431The event is only available on PMC1. 432.It Li FP_Comp_Instr_Ret 433.Pq Event C1H , Umask 00H 434The number of X87 floating point compute instructions retired. 435The event is only available on PMC0. 436.It Li FP_Comps_Op_Exe 437.Pq Event 10H , Umask 00H 438The number of floating point computational instructions executed. 439.It Li FP_MMX_Trans 440.Pq Event CCH , Umask 01H 441The number of transitions from X87 to MMX. 442.It Li Fused_Ld_Uops_Ret 443.Pq Event DAH , Umask 01H 444The number of fused load uops retired. 445.It Li Fused_St_Uops_Ret 446.Pq Event DAH , Umask 02H 447The number of fused store uops retired. 448.It Li Fused_Uops_Ret 449.Pq Event DAH , Umask 00H 450The number of fused uops retired. 451.It Li HW_Int_Rx 452.Pq Event C8H , Umask 00H 453The number of hardware interrupts received. 454.It Li ICache_Misses 455.Pq Event 81H , Umask 00H 456The number of instruction fetch misses in the instruction cache and 457streaming buffers. 458.It Li ICache_Reads 459.Pq Event 80H , Umask 00H 460The number of instruction fetches from the instruction cache and 461streaming buffers counting both cacheable and un-cacheable fetches. 462.It Li IFU_Mem_Stall 463.Pq Event 86H , Umask 00H 464The number of cycles the instruction fetch unit was stalled while 465waiting for data from memory. 466.It Li ILD_Stall 467.Pq Event 87H , Umask 00H 468The number of instruction length decoder stalls. 469.It Li ITLB_Misses 470.Pq Event 85H , Umask 00H 471The number of instruction TLB misses. 472.It Li Instr_Decoded 473.Pq Event D0H , Umask 00H 474The number of instructions decoded. 475.It Li Instr_Ret 476.Pq Event C0H , Umask 00H 477.Pq Alias Qq "Instruction Retired" 478The number of instructions retired. 479This is an architectural performance event. 480.It Li L1_Pref_Req 481.Pq Event 4FH , Umask 00H 482The number of L1 prefetch request due to data cache misses. 483.It Li L2_ADS Op ,core= Ns core 484.Pq Event 21H 485The number of L2 address strobes. 486.It Li L2_IFetch Xo 487.Op ,cachestate= Ns Ar mesi 488.Op ,core= Ns Ar core 489.Xc 490.Pq Event 28H 491The number of instruction fetches by the instruction fetch unit from 492L2 cache including speculative fetches. 493.It Li L2_LD Xo 494.Op ,cachestate= Ns Ar mesi 495.Op ,core= Ns Ar core 496.Xc 497.Pq Event 29H 498The number of L2 cache reads. 499.It Li L2_Lines_In Xo 500.Op ,core= Ns Ar core 501.Op ,prefetch= Ns Ar prefetch 502.Xc 503.Pq Event 24H 504The number of L2 cache lines allocated. 505.It Li L2_Lines_Out Xo 506.Op ,core= Ns Ar core 507.Op ,prefetch= Ns Ar prefetch 508.Xc 509.Pq Event 26H 510The number of L2 cache lines evicted. 511.It Li L2_M_Lines_In Op ,core= Ns Ar core 512.Pq Event 25H 513The number of L2 M state cache lines allocated. 514.It Li L2_M_Lines_Out Xo 515.Op ,core= Ns Ar core 516.Op ,prefetch= Ns Ar prefetch 517.Xc 518.Pq Event 27H 519The number of L2 M state cache lines evicted. 520.It Li L2_No_Request_Cycles Xo 521.Op ,cachestate= Ns Ar mesi 522.Op ,core= Ns Ar core 523.Op ,prefetch= Ns Ar prefetch 524.Xc 525.Pq Event 32H 526The number of cycles there was no request to access L2 cache. 527.It Li L2_Reject_Cycles Xo 528.Op ,cachestate= Ns Ar mesi 529.Op ,core= Ns Ar core 530.Op ,prefetch= Ns Ar prefetch 531.Xc 532.Pq Event 30H 533The number of cycles the L2 cache was busy and rejecting new requests. 534.It Li L2_Rqsts Xo 535.Op ,cachestate= Ns Ar mesi 536.Op ,core= Ns Ar core 537.Op ,prefetch= Ns Ar prefetch 538.Xc 539.Pq Event 2EH 540The number of L2 cache requests. 541.It Li L2_ST Xo 542.Op ,cachestate= Ns Ar mesi 543.Op ,core= Ns Ar core 544.Xc 545.Pq Event 2AH 546The number of L2 cache writes including speculative writes. 547.It Li LD_Blocks 548.Pq Event 03H , Umask 00H 549The number of load operations delayed due to store buffer blocks. 550.It Li LLC_Misses 551.Pq Event 2EH , Umask 41H 552The number of cache misses for references to the last level cache, 553excluding misses due to hardware prefetches. 554This is an architectural performance event. 555.It Li LLC_Reference 556The number of references to the last level cache, 557excluding those due to hardware prefetches. 558This is an architectural performance event. 559.Pq Event 2EH , Umask 4FH 560This is an architectural performance event. 561.It Li MMX_Assist 562.Pq Event CDH , Umask 00H 563The number of EMMX instructions executed. 564.It Li MMX_FP_Trans 565.Pq Event CCH , Umask 00H 566The number of transitions from MMX to X87. 567.It Li MMX_Instr_Exec 568.Pq Event B0H , Umask 00H 569The number of MMX instructions executed excluding 570.Li MOVQ 571and 572.Li MOVD 573stores. 574.It Li MMX_Instr_Ret 575.Pq Event CEH , Umask 00H 576The number of MMX instructions retired. 577.It Li Misalign_Mem_Ref 578.Pq Event 05H , Umask 00H 579The number of misaligned data memory references, counting loads and 580stores. 581.It Li Mul 582.Pq Event 12H , Umask 00H 583The number of multiply operations include speculative floating point 584and integer multiplies. 585This event is available on PMC1 only. 586.It Li NonHlt_Ref_Cycles 587.Pq Event 3CH , Umask 01H 588.Pq Alias Qq "Unhalted Reference Cycles" 589The number of non-halted bus cycles. 590This is an architectural performance event. 591.It Li Pref_Rqsts_Dn 592.Pq Event F8H , Umask 00H 593The number of hardware prefetch requests issued in backward streams. 594.It Li Pref_Rqsts_Up 595.Pq Event F0H , Umask 00H 596The number of hardware prefetch requests issued in forward streams. 597.It Li Resource_Stall 598.Pq Event A2H , Umask 00H 599The number of cycles where there is a resource related stall. 600.It Li SD_Drains 601.Pq Event 04H , Umask 00H 602The number of cycles while draining store buffers. 603.It Li SIMD_FP_DP_P_Ret 604.Pq Event D8H , Umask 02H 605The number of SSE/SSE2 packed double precision instructions retired. 606.It Li SIMD_FP_DP_P_Comp_Ret 607.Pq Event D9H , Umask 02H 608The number of SSE/SSE2 packed double precision compute instructions 609retired. 610.It Li SIMD_FP_DP_S_Ret 611.Pq Event D8H , Umask 03H 612The number of SSE/SSE2 scalar double precision instructions retired. 613.It Li SIMD_FP_DP_S_Comp_Ret 614.Pq Event D9H , Umask 03H 615The number of SSE/SSE2 scalar double precision compute instructions 616retired. 617.It Li SIMD_FP_SP_P_Comp_Ret 618.Pq Event D9H , Umask 00H 619The number of SSE/SSE2 packed single precision compute instructions 620retired. 621.It Li SIMD_FP_SP_Ret 622.Pq Event D8H , Umask 00H 623The number of SSE/SSE2 scalar single precision instructions retired, 624both packed and scalar. 625.It Li SIMD_FP_SP_S_Ret 626.Pq Event D8H , Umask 01H 627The number of SSE/SSE2 scalar single precision instructions retired. 628.It Li SIMD_FP_SP_S_Comp_Ret 629.Pq Event D9H , Umask 01H 630The number of SSE/SSE2 single precision compute instructions retired. 631.It Li SIMD_Int_128_Ret 632.Pq Event D8H , Umask 04H 633The number of SSE2 128-bit integer instructions retired. 634.It Li SIMD_Int_Pari_Exec 635.Pq Event B3H , Umask 20H 636The number of SIMD integer packed arithmetic instructions executed. 637.It Li SIMD_Int_Pck_Exec 638.Pq Event B3H , Umask 04H 639The number of SIMD integer pack operations instructions executed. 640.It Li SIMD_Int_Plog_Exec 641.Pq Event B3H , Umask 10H 642The number of SIMD integer packed logical instructions executed. 643.It Li SIMD_Int_Pmul_Exec 644.Pq Event B3H , Umask 01H 645The number of SIMD integer packed multiply instructions executed. 646.It Li SIMD_Int_Psft_Exec 647.Pq Event B3H , Umask 02H 648The number of SIMD integer packed shift instructions executed. 649.It Li SIMD_Int_Sat_Exec 650.Pq Event B1H , Umask 00H 651The number of SIMD integer saturating instructions executed. 652.It Li SIMD_Int_Upck_Exec 653.Pq Event B3H , Umask 08H 654The number of SIMD integer unpack instructions executed. 655.It Li SMC_Detected 656.Pq Event C3H , Umask 00H 657The number of times self-modifying code was detected. 658.It Li SSE_NTStores_Miss 659.Pq Event 4BH , Umask 03H 660The number of times an SSE streaming store instruction missed all caches. 661.It Li SSE_NTStores_Ret 662.Pq Event 07H , Umask 03H 663The number of SSE streaming store instructions executed. 664.It Li SSE_PrefNta_Miss 665.Pq Event 4BH , Umask 00H 666The number of times 667.Li PREFETCHNTA 668missed all caches. 669.It Li SSE_PrefNta_Ret 670.Pq Event 07H , Umask 00H 671The number of 672.Li PREFETCHNTA 673instructions retired. 674.It Li SSE_PrefT1_Miss 675.Pq Event 4BH , Umask 01H 676The number of times 677.Li PREFETCHT1 678missed all caches. 679.It Li SSE_PrefT1_Ret 680.Pq Event 07H , Umask 01H 681The number of 682.Li PREFETCHT1 683instructions retired. 684.It Li SSE_PrefT2_Miss 685.Pq Event 4BH , Umask 02H 686The number of times 687.Li PREFETCHNT2 688missed all caches. 689.It Li SSE_PrefT2_Ret 690.Pq Event 07H , Umask 02H 691The number of 692.Li PREFETCHT2 693instructions retired. 694.It Li Seg_Reg_Loads 695.Pq Event 06H , Umask 00H 696The number of segment register loads. 697.It Li Serial_Execution_Cycles 698.Pq Event 3CH , Umask 02H 699The number of non-halted bus cycles of this code while the other core 700was halted. 701.It Li Thermal_Trip 702.Pq Event 3BH , Umask C0H 703The duration in a thermal trip based on the current core clock. 704.It Li Unfusion 705.Pq Event DBH , Umask 00H 706The number of unfusion events. 707.It Li Unhalted_Core_Cycles 708.Pq Event 3CH , Umask 00H 709The number of core clock cycles when the clock signal on a specific 710core is not halted. 711This is an architectural performance event. 712.It Li Uops_Ret 713.Pq Event C2H , Umask 00H 714The number of micro-ops retired. 715.El 716.Ss Event Name Aliases 717The following table shows the mapping between the PMC-independent 718aliases supported by 719.Lb libpmc 720and the underlying hardware events used. 721.Bl -column "branch-mispredicts" "Description" 722.It Em Alias Ta Em Event 723.It Li branches Ta Li Br_Instr_Ret 724.It Li branch-mispredicts Ta Li Br_MisPred_Ret 725.It Li dc-misses Ta (unsupported) 726.It Li ic-misses Ta Li ICache_Misses 727.It Li instructions Ta Li Instr_Ret 728.It Li interrupts Ta Li HW_Int_Rx 729.It Li unhalted-cycles Ta (unsupported) 730.El 731.Sh PROCESSOR ERRATA 732The following errata affect performance measurement on these 733processors. 734These errata are documented in 735.Rs 736.%B Specification Update 737.%T Intel\(rg CoreTM Duo Processor and Intel\(rg CoreTM Solo Processor on 65 nm Process 738.%N Order Number 309222-017 739.%D July 2008 740.%Q Intel Corporation 741.Re 742.Bl -tag -width indent -compact 743.It AE19 744Data prefetch performance monitoring events can only be enabled 745on a single core. 746.It AE25 747Performance monitoring counters that count external bus events 748may report incorrect values after processor power state transitions. 749.It AE28 750Performance monitoring events for retired floating point operations 751(C1H) may not be accurate. 752.It AE29 753DR3 address match on MOVD/MOVQ/MOVNTQ memory store 754instruction may incorrectly increment performance monitoring count 755for saturating SIMD instructions retired (Event CFH). 756.It AE33 757Hardware prefetch performance monitoring events may be counted 758inaccurately. 759.It AE36 760The 761.Li CPU_CLK_UNHALTED 762performance monitoring event (Event 3CH) counts 763clocks when the processor is in the C1/C2 processor power states. 764.It AE39 765Certain performance monitoring counters related to bus, L2 cache 766and power management are inaccurate. 767.It AE51 768Performance monitoring events for retired instructions (Event C0H) may 769not be accurate. 770.It AE67 771Performance monitoring event 772.Li FP_ASSIST 773may not be accurate. 774.It AE78 775Performance monitoring event for hardware prefetch requests (Event 7764EH) and hardware prefetch request cache misses (Event 4FH) may not be 777accurate. 778.It AE82 779Performance monitoring event 780.Li FP_MMX_TRANS_TO_MMX 781may not count some transitions. 782.El 783.Sh SEE ALSO 784.Xr pmc 3 , 785.Xr pmc.amd 3 , 786.Xr pmc.atom 3 , 787.Xr pmc.core2 3 , 788.Xr pmc.iaf 3 , 789.Xr pmc.soft 3 , 790.Xr pmc.tsc 3 , 791.Xr pmclog 3 , 792.Xr hwpmc 4 793.Sh HISTORY 794The 795.Nm pmc 796library first appeared in 797.Fx 6.0 . 798.Sh AUTHORS 799The 800.Lb libpmc 801library was written by 802.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 803