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Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" This software is provided by Joseph Koshy ``as is'' and 13.\" any express or implied warranties, including, but not limited to, the 14.\" implied warranties of merchantability and fitness for a particular purpose 15.\" are disclaimed. in no event shall Joseph Koshy be liable 16.\" for any direct, indirect, incidental, special, exemplary, or consequential 17.\" damages (including, but not limited to, procurement of substitute goods 18.\" or services; loss of use, data, or profits; or business interruption) 19.\" however caused and on any theory of liability, whether in contract, strict 20.\" liability, or tort (including negligence or otherwise) arising in any way 21.\" out of the use of this software, even if advised of the possibility of 22.\" such damage. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd November 12, 2008 27.Dt PMC.CORE 3 28.Os 29.Sh NAME 30.Nm pmc.core 31.Nd measurement events for 32.Tn Intel 33.Tn Core Solo 34and 35.Tn Core Duo 36family CPUs 37.Sh LIBRARY 38.Lb libpmc 39.Sh SYNOPSIS 40.In pmc.h 41.Sh DESCRIPTION 42.Tn Intel 43.Tn "Core Solo" 44and 45.Tn "Core Duo" 46CPUs contain PMCs conforming to version 1 of the 47.Tn Intel 48performance measurement architecture. 49.Pp 50These PMCs are documented in 51.Rs 52.%B IA-32 Intel\(rg Architecture Software Developer's Manual 53.%T Volume 3: System Programming Guide 54.%N Order Number 253669-027US 55.%D July 2008 56.%Q Intel Corporation 57.Re 58.Ss PMC Features 59CPUs conforming to version 1 of the 60.Tn Intel 61performance measurement architecture contain two programmable PMCs of 62class 63.Li PMC_CLASS_IAP . 64The PMCs are 40 bits width and offer the following capabilities: 65.Bl -column "PMC_CAP_INTERRUPT" "Support" 66.It Em Capability Ta Em Support 67.It PMC_CAP_CASCADE Ta \&No 68.It PMC_CAP_EDGE Ta Yes 69.It PMC_CAP_INTERRUPT Ta Yes 70.It PMC_CAP_INVERT Ta Yes 71.It PMC_CAP_READ Ta Yes 72.It PMC_CAP_PRECISE Ta \&No 73.It PMC_CAP_SYSTEM Ta Yes 74.It PMC_CAP_TAGGING Ta \&No 75.It PMC_CAP_THRESHOLD Ta Yes 76.It PMC_CAP_USER Ta Yes 77.It PMC_CAP_WRITE Ta Yes 78.El 79.Ss Event Qualifiers 80Event specifiers for these PMCs support the following common 81qualifiers: 82.Bl -tag -width indent 83.It Li cmask= Ns Ar value 84Configure the PMC to increment only if the number of configured 85events measured in a cycle is greater than or equal to 86.Ar value . 87.It Li edge 88Configure the PMC to count the number of de-asserted to asserted 89transitions of the conditions expressed by the other qualifiers. 90If specified, the counter will increment only once whenever a 91condition becomes true, irrespective of the number of clocks during 92which the condition remains true. 93.It Li inv 94Invert the sense of comparison when the 95.Dq Li cmask 96qualifier is present, making the counter increment when the number of 97events per cycle is less than the value specified by the 98.Dq Li cmask 99qualifier. 100.It Li os 101Configure the PMC to count events happening at processor privilege 102level 0. 103.It Li usr 104Configure the PMC to count events occurring at privilege levels 1, 2 105or 3. 106.El 107.Pp 108If neither of the 109.Dq Li os 110or 111.Dq Li usr 112qualifiers are specified, the default is to enable both. 113.Pp 114Events that require core-specificity to be specified use a 115additional qualifier 116.Dq Li core= Ns Ar value , 117where argument 118.Ar value 119is one of: 120.Bl -tag -width indent -compact 121.It Li all 122Measure event conditions on all cores. 123.It Li this 124Measure event conditions on this core. 125.El 126The default is 127.Dq Li this . 128.Pp 129Events that require an agent qualifier to be specified use an 130additional qualifier 131.Dq Li agent= Ns value , 132where argument 133.Ar value 134is one of: 135.Bl -tag -width indent -compact 136.It Li this 137Measure events associated with this bus agent. 138.It Li any 139Measure events caused by any bus agent. 140.El 141The default is 142.Dq Li this . 143.Pp 144Events that require a hardware prefetch qualifier to be specified use an 145additional qualifier 146.Dq Li prefetch= Ns Ar value , 147where argument 148.Ar value 149is one of: 150.Bl -tag -width "exclude" -compact 151.It Li both 152Include all prefetches. 153.It Li only 154Only count hardware prefetches. 155.It Li exclude 156Exclude hardware prefetches. 157.El 158The default is 159.Dq Li both . 160.Pp 161Events that require a cache coherence qualifier to be specified use an 162additional qualifier 163.Dq Li cachestate= Ns Ar value , 164where argument 165.Ar value 166contains one or more of the following letters: 167.Bl -tag -width indent -compact 168.It Li e 169Count cache lines in the exclusive state. 170.It Li i 171Count cache lines in the invalid state. 172.It Li m 173Count cache lines in the modified state. 174.It Li s 175Count cache lines in the shared state. 176.El 177The default is 178.Dq Li eims . 179.Ss Event Specifiers 180The following event names are case insensitive. 181Whitespace, hyphens and underscore characters in these names are 182ignored. 183.Pp 184Core PMCs support the following events: 185.Bl -tag -width indent 186.It Li BAClears 187.Pq Event E6H , Umask 00H 188The number of BAClear conditions asserted. 189.It Li BTB_Misses 190.Pq Event E2H , Umask 00H 191The number of branches for which the branch table buffer did not 192produce a prediction. 193.It Li Br_BAC_Missp_Exec 194.Pq Event 8AH , Umask 00H 195The number of branch instructions executed that were mispredicted at 196the front end. 197.It Li Br_Bogus 198.Pq Event E4H , Umask 00H 199The number of bogus branches. 200.It Li Br_Call_Exec 201.Pq Event 92H , Umask 00H 202The number of 203.Li CALL 204instructions executed. 205.It Li Br_Call_Missp_Exec 206.Pq Event 93H , Umask 00H 207The number of 208.Li CALL 209instructions executed that were mispredicted. 210.It Li Br_Cnd_Exec 211.Pq Event 8BH , Umask 00H 212The number of conditional branch instructions executed. 213.It Li Br_Cnd_Missp_Exec 214.Pq Event 8CH , Umask 00H 215The number of conditional branch instructions executed that were mispredicted. 216.It Li Br_Ind_Call_Exec 217.Pq Event 94H , Umask 00H 218The number of indirect 219.Li CALL 220instructions executed. 221.It Li Br_Ind_Exec 222.Pq Event 8DH , Umask 00H 223The number of indirect branches executed. 224.It Li Br_Ind_Missp_Exec 225.Pq Event 8EH , Umask 00H 226The number of indirect branch instructions executed that were mispredicted. 227.It Li Br_Inst_Exec 228.Pq Event 88H , Umask 00H 229The number of branch instructions executed including speculative branches. 230.It Li Br_Instr_Decoded 231.Pq Event E0H , Umask 00H 232The number of branch instructions decoded. 233.It Li Br_Instr_Ret 234.Pq Event C4H , Umask 00H 235.Pq Alias Qq "Branch Instruction Retired" 236The number of branch instructions retired. 237This is an architectural performance event. 238.It Li Br_MisPred_Ret 239.Pq Event C5H , Umask 00H 240.Pq Alias Qq "Branch Misses Retired" 241The number of mispredicted branch instructions retired. 242This is an architectural performance event. 243.It Li Br_MisPred_Taken_Ret 244.Pq Event CAH , Umask 00H 245The number of taken and mispredicted branches retired. 246.It Li Br_Missp_Exec 247.Pq Event 89H , Umask 00H 248The number of branch instructions executed and mispredicted at 249execution including branches that were not predicted. 250.It Li Br_Ret_BAC_Missp_Exec 251.Pq Event 91H , Umask 00H 252The number of return branch instructions that were mispredicted at the 253front end. 254.It Li Br_Ret_Exec 255.Pq Event 8FH , Umask 00H 256The number of return branch instructions executed. 257.It Li Br_Ret_Missp_Exec 258.Pq Event 90H , Umask 00H 259The number of return branch instructions executed that were mispredicted. 260.It Li Br_Taken_Ret 261.Pq Event C9H , Umask 00H 262The number of taken branches retired. 263.It Li Bus_BNR_Clocks 264.Pq Event 61H , Umask 00H 265The number of external bus cycles while BNR (bus not ready) was asserted. 266.It Li Bus_DRDY_Clocks Op ,agent= Ns Ar agent 267.Pq Event 62H , Umask 00H 268The number of external bus cycles while DRDY was asserted. 269.It Li Bus_Data_Rcv 270.Pq Event 64H , Umask 40H 271.\" XXX Using the description in Core2 PMC documentation. 272The number of cycles during which the processor is busy receiving data. 273.It Li Bus_Locks_Clocks Op ,core= Ns Ar core 274.Pq Event 63H 275The number of external bus cycles while the bus lock signal was asserted. 276.It Li Bus_Not_In_Use Op ,core= Ns Ar core 277.Pq Event 7DH 278The number of cycles when there is no transaction from the core. 279.It Li Bus_Req_Outstanding Xo 280.Op ,agent= Ns Ar agent 281.Op ,core= Ns Ar core 282.Xc 283.Pq Event 60H 284The weighted cycles of cacheable bus data read requests 285from the data cache unit or hardware prefetcher. 286.It Li Bus_Snoop_Stall 287.Pq Event 7EH , Umask 00H 288The number bus cycles while a bus snoop is stalled. 289.It Li Bus_Snoops Xo 290.Op ,agent= Ns Ar agent 291.Op ,cachestate= Ns Ar mesi 292.Xc 293.Pq Event 77H 294.\" XXX Using the description in Core2 PMC documentation. 295The number of snoop responses to bus transactions. 296.It Li Bus_Trans_Any Op ,agent= Ns Ar agent 297.Pq Event 70H 298The number of completed bus transactions. 299.It Li Bus_Trans_Brd Op ,core= Ns Ar core 300.Pq Event 65H 301The number of read bus transactions. 302.It Li Bus_Trans_Burst Op ,agent= Ns Ar agent 303.Pq Event 6EH 304The number of completed burst transactions. 305Retried transactions may be counted more than once. 306.It Li Bus_Trans_Def Op ,core= Ns Ar core 307.Pq Event 6DH 308The number of completed deferred transactions. 309.It Li Bus_Trans_IO Xo 310.Op ,agent= Ns Ar agent 311.Op ,core= Ns Ar core 312.Xc 313.Pq Event 6CH 314The number of completed I/O transactions counting both reads and 315writes. 316.It Li Bus_Trans_Ifetch Xo 317.Op ,agent= Ns Ar agent 318.Op ,core= Ns Ar core 319.Xc 320.Pq Event 68H 321Completed instruction fetch transactions. 322.It Li Bus_Trans_Inval Xo 323.Op ,agent= Ns Ar agent 324.Op ,core= Ns Ar core 325.Xc 326.Pq Event 69H 327The number completed invalidate transactions. 328.It Li Bus_Trans_Mem Op ,agent= Ns Ar agent 329.Pq Event 6FH 330The number of completed memory transactions. 331.It Li Bus_Trans_P Xo 332.Op ,agent= Ns Ar agent 333.Op ,core= Ns Ar core 334.Xc 335.Pq Event 6BH 336The number of completed partial transactions. 337.It Li Bus_Trans_Pwr Xo 338.Op ,agent= Ns Ar agent 339.Op ,core= Ns Ar core 340.Xc 341.Pq Event 6AH 342The number of completed partial write transactions. 343.It Li Bus_Trans_RFO Xo 344.Op ,agent= Ns Ar agent 345.Op ,core= Ns Ar core 346.Xc 347.Pq Event 66H 348The number of completed read-for-ownership transactions. 349.It Li Bus_Trans_WB Op ,agent= Ns Ar agent 350.Pq Event 67H 351The number of completed write-back transactions from the data cache 352unit, excluding L2 write-backs. 353.It Li Cycles_Div_Busy 354.Pq Event 14H , Umask 00H 355The number of cycles the divider is busy. 356The event is only available on PMC0. 357.It Li Cycles_Int_Masked 358.Pq Event C6H , Umask 00H 359The number of cycles while interrupts were disabled. 360.It Li Cycles_Int_Pending_Masked 361.Pq Event C7H , Umask 00H 362The number of cycles while interrupts were disabled and interrupts 363were pending. 364.It Li DCU_Snoop_To_Share Op ,core= Ns core 365.Pq Event 78H 366The number of data cache unit snoops to L1 cache lines in the shared 367state. 368.It Li DCache_Cache_Lock Op ,cachestate= Ns Ar mesi 369.\" XXX needs clarification 370.Pq Event 42H 371The number of cacheable locked read operations to invalid state. 372.It Li DCache_Cache_LD Op ,cachestate= Ns Ar mesi 373.Pq Event 40H 374The number of cacheable L1 data read operations. 375.It Li DCache_Cache_ST Op ,cachestate= Ns Ar mesi 376.Pq Event 41H 377The number cacheable L1 data write operations. 378.It Li DCache_M_Evict 379.Pq Event 47H , Umask 00H 380The number of M state data cache lines that were evicted. 381.It Li DCache_M_Repl 382.Pq Event 46H , Umask 00H 383The number of M state data cache lines that were allocated. 384.It Li DCache_Pend_Miss 385.Pq Event 48H , Umask 00H 386The weighted cycles an L1 miss was outstanding. 387.It Li DCache_Repl 388.Pq Event 45H , Umask 0FH 389The number of data cache line replacements. 390.It Li Data_Mem_Cache_Ref 391.Pq Event 44H , Umask 02H 392The number of cacheable read and write operations to L1 data cache. 393.It Li Data_Mem_Ref 394.Pq Event 43H , Umask 01H 395The number of L1 data reads and writes, both cacheable and 396un-cacheable. 397.It Li Dbus_Busy Op ,core= Ns Ar core 398.Pq Event 22H 399The number of core cycles during which the data bus was busy. 400.It Li Dbus_Busy_Rd Op ,core= Ns Ar core 401.Pq Event 23H 402The number of cycles during which the data bus was busy transferring 403data to a core. 404.It Li Div 405.Pq Event 13H , Umask 00H 406The number of divide operations including speculative operations for 407integer and floating point divides. 408This event can only be counted on PMC1. 409.It Li Dtlb_Miss 410.Pq Event 49H , Umask 00H 411The number of data references that missed the TLB. 412.It Li ESP_Uops 413.Pq Event D7H , Umask 00H 414The number of ESP folding instructions decoded. 415.It Li EST_Trans Op ,trans= Ns Ar transition 416.Pq Event 3AH 417Count the number of Intel Enhanced SpeedStep transitions. 418The argument 419.Ar transition 420can be one of the following values: 421.Bl -tag -width indent -compact 422.It Li any 423(Umask 00H) Count all transitions. 424.It Li frequency 425(Umask 01H) Count frequency transitions. 426.El 427The default is 428.Dq Li any . 429.It Li FP_Assist 430.Pq Event 11H , Umask 00H 431The number of floating point operations that required microcode 432assists. 433The event is only available on PMC1. 434.It Li FP_Comp_Instr_Ret 435.Pq Event C1H , Umask 00H 436The number of X87 floating point compute instructions retired. 437The event is only available on PMC0. 438.It Li FP_Comps_Op_Exe 439.Pq Event 10H , Umask 00H 440The number of floating point computational instructions executed. 441.It Li FP_MMX_Trans 442.Pq Event CCH , Umask 01H 443The number of transitions from X87 to MMX. 444.It Li Fused_Ld_Uops_Ret 445.Pq Event DAH , Umask 01H 446The number of fused load uops retired. 447.It Li Fused_St_Uops_Ret 448.Pq Event DAH , Umask 02H 449The number of fused store uops retired. 450.It Li Fused_Uops_Ret 451.Pq Event DAH , Umask 00H 452The number of fused uops retired. 453.It Li HW_Int_Rx 454.Pq Event C8H , Umask 00H 455The number of hardware interrupts received. 456.It Li ICache_Misses 457.Pq Event 81H , Umask 00H 458The number of instruction fetch misses in the instruction cache and 459streaming buffers. 460.It Li ICache_Reads 461.Pq Event 80H , Umask 00H 462The number of instruction fetches from the the instruction cache and 463streaming buffers counting both cacheable and un-cacheable fetches. 464.It Li IFU_Mem_Stall 465.Pq Event 86H , Umask 00H 466The number of cycles the instruction fetch unit was stalled while 467waiting for data from memory. 468.It Li ILD_Stall 469.Pq Event 87H , Umask 00H 470The number of instruction length decoder stalls. 471.It Li ITLB_Misses 472.Pq Event 85H , Umask 00H 473The number of instruction TLB misses. 474.It Li Instr_Decoded 475.Pq Event D0H , Umask 00H 476The number of instructions decoded. 477.It Li Instr_Ret 478.Pq Event C0H , Umask 00H 479.Pq Alias Qq "Instruction Retired" 480The number of instructions retired. 481This is an architectural performance event. 482.It Li L1_Pref_Req 483.Pq Event 4FH , Umask 00H 484The number of L1 prefetch request due to data cache misses. 485.It Li L2_ADS Op ,core= Ns core 486.Pq Event 21H 487The number of L2 address strobes. 488.It Li L2_IFetch Xo 489.Op ,cachestate= Ns Ar mesi 490.Op ,core= Ns Ar core 491.Xc 492.Pq Event 28H 493The number of instruction fetches by the instruction fetch unit from 494L2 cache including speculative fetches. 495.It Li L2_LD Xo 496.Op ,cachestate= Ns Ar mesi 497.Op ,core= Ns Ar core 498.Xc 499.Pq Event 29H 500The number of L2 cache reads. 501.It Li L2_Lines_In Xo 502.Op ,core= Ns Ar core 503.Op ,prefetch= Ns Ar prefetch 504.Xc 505.Pq Event 24H 506The number of L2 cache lines allocated. 507.It Li L2_Lines_Out Xo 508.Op ,core= Ns Ar core 509.Op ,prefetch= Ns Ar prefetch 510.Xc 511.Pq Event 26H 512The number of L2 cache lines evicted. 513.It Li L2_M_Lines_In Op ,core= Ns Ar core 514.Pq Event 25H 515The number of L2 M state cache lines allocated. 516.It Li L2_M_Lines_Out Xo 517.Op ,core= Ns Ar core 518.Op ,prefetch= Ns Ar prefetch 519.Xc 520.Pq Event 27H 521The number of L2 M state cache lines evicted. 522.It Li L2_No_Request_Cycles Xo 523.Op ,cachestate= Ns Ar mesi 524.Op ,core= Ns Ar core 525.Op ,prefetch= Ns Ar prefetch 526.Xc 527.Pq Event 32H 528The number of cycles there was no request to access L2 cache. 529.It Li L2_Reject_Cycles Xo 530.Op ,cachestate= Ns Ar mesi 531.Op ,core= Ns Ar core 532.Op ,prefetch= Ns Ar prefetch 533.Xc 534.Pq Event 30H 535The number of cycles the L2 cache was busy and rejecting new requests. 536.It Li L2_Rqsts Xo 537.Op ,cachestate= Ns Ar mesi 538.Op ,core= Ns Ar core 539.Op ,prefetch= Ns Ar prefetch 540.Xc 541.Pq Event 2EH 542The number of L2 cache requests. 543.It Li L2_ST Xo 544.Op ,cachestate= Ns Ar mesi 545.Op ,core= Ns Ar core 546.Xc 547.Pq Event 2AH 548The number of L2 cache writes including speculative writes. 549.It Li LD_Blocks 550.Pq Event 03H , Umask 00H 551The number of load operations delayed due to store buffer blocks. 552.It Li LLC_Misses 553.Pq Event 2EH , Umask 41H 554The number of cache misses for references to the last level cache, 555excluding misses due to hardware prefetches. 556This is an architectural performance event. 557.It Li LLC_Reference 558The number of references to the last level cache, 559excluding those due to hardware prefetches. 560This is an architectural performance event. 561.Pq Event 2EH , Umask 4FH 562This is an architectural performance event. 563.It Li MMX_Assist 564.Pq Event CDH , Umask 00H 565The number of EMMX instructions executed. 566.It Li MMX_FP_Trans 567.Pq Event CCH , Umask 00H 568The number of transitions from MMX to X87. 569.It Li MMX_Instr_Exec 570.Pq Event B0H , Umask 00H 571The number of MMX instructions executed excluding 572.Li MOVQ 573and 574.Li MOVD 575stores. 576.It Li MMX_Instr_Ret 577.Pq Event CEH , Umask 00H 578The number of MMX instructions retired. 579.It Li Misalign_Mem_Ref 580.Pq Event 05H , Umask 00H 581The number of misaligned data memory references, counting loads and 582stores. 583.It Li Mul 584.Pq Event 12H , Umask 00H 585The number of multiply operations include speculative floating point 586and integer multiplies. 587This event is available on PMC1 only. 588.It Li NonHlt_Ref_Cycles 589.Pq Event 3CH , Umask 01H 590.Pq Alias Qq "Unhalted Reference Cycles" 591The number of non-halted bus cycles. 592This is an architectural performance event. 593.It Li Pref_Rqsts_Dn 594.Pq Event F8H , Umask 00H 595The number of hardware prefetch requests issued in backward streams. 596.It Li Pref_Rqsts_Up 597.Pq Event F0H , Umask 00H 598The number of hardware prefetch requests issued in forward streams. 599.It Li Resource_Stall 600.Pq Event A2H , Umask 00H 601The number of cycles where there is a resource related stall. 602.It Li SD_Drains 603.Pq Event 04H , Umask 00H 604The number of cycles while draining store buffers. 605.It Li SIMD_FP_DP_P_Ret 606.Pq Event D8H , Umask 02H 607The number of SSE/SSE2 packed double precision instructions retired. 608.It Li SIMD_FP_DP_P_Comp_Ret 609.Pq Event D9H , Umask 02H 610The number of SSE/SSE2 packed double precision compute instructions 611retired. 612.It Li SIMD_FP_DP_S_Ret 613.Pq Event D8H , Umask 03H 614The number of SSE/SSE2 scalar double precision instructions retired. 615.It Li SIMD_FP_DP_S_Comp_Ret 616.Pq Event D9H , Umask 03H 617The number of SSE/SSE2 scalar double precision compute instructions 618retired. 619.It Li SIMD_FP_SP_P_Comp_Ret 620.Pq Event D9H , Umask 00H 621The number of SSE/SSE2 packed single precision compute instructions 622retired. 623.It Li SIMD_FP_SP_Ret 624.Pq Event D8H , Umask 00H 625The number of SSE/SSE2 scalar single precision instructions retired, 626both packed and scalar. 627.It Li SIMD_FP_SP_S_Ret 628.Pq Event D8H , Umask 01H 629The number of SSE/SSE2 scalar single precision instructions retired. 630.It Li SIMD_FP_SP_S_Comp_Ret 631.Pq Event D9H , Umask 01H 632The number of SSE/SSE2 single precision compute instructions retired. 633.It Li SIMD_Int_128_Ret 634.Pq Event D8H , Umask 04H 635The number of SSE2 128-bit integer instructions retired. 636.It Li SIMD_Int_Pari_Exec 637.Pq Event B3H , Umask 20H 638The number of SIMD integer packed arithmetic instructions executed. 639.It Li SIMD_Int_Pck_Exec 640.Pq Event B3H , Umask 04H 641The number of SIMD integer pack operations instructions executed. 642.It Li SIMD_Int_Plog_Exec 643.Pq Event B3H , Umask 10H 644The number of SIMD integer packed logical instructions executed. 645.It Li SIMD_Int_Pmul_Exec 646.Pq Event B3H , Umask 01H 647The number of SIMD integer packed multiply instructions executed. 648.It Li SIMD_Int_Psft_Exec 649.Pq Event B3H , Umask 02H 650The number of SIMD integer packed shift instructions executed. 651.It Li SIMD_Int_Sat_Exec 652.Pq Event B1H , Umask 00H 653The number of SIMD integer saturating instructions executed. 654.It Li SIMD_Int_Upck_Exec 655.Pq Event B3H , Umask 08H 656The number of SIMD integer unpack instructions executed. 657.It Li SMC_Detected 658.Pq Event C3H , Umask 00H 659The number of times self-modifying code was detected. 660.It Li SSE_NTStores_Miss 661.Pq Event 4BH , Umask 03H 662The number of times an SSE streaming store instruction missed all caches. 663.It Li SSE_NTStores_Ret 664.Pq Event 07H , Umask 03H 665The number of SSE streaming store instructions executed. 666.It Li SSE_PrefNta_Miss 667.Pq Event 4BH , Umask 00H 668The number of times 669.Li PREFETCHNTA 670missed all caches. 671.It Li SSE_PrefNta_Ret 672.Pq Event 07H , Umask 00H 673The number of 674.Li PREFETCHNTA 675instructions retired. 676.It Li SSE_PrefT1_Miss 677.Pq Event 4BH , Umask 01H 678The number of times 679.Li PREFETCHT1 680missed all caches. 681.It Li SSE_PrefT1_Ret 682.Pq Event 07H , Umask 01H 683The number of 684.Li PREFETCHT1 685instructions retired. 686.It Li SSE_PrefT2_Miss 687.Pq Event 4BH , Umask 02H 688The number of times 689.Li PREFETCHNT2 690missed all caches. 691.It Li SSE_PrefT2_Ret 692.Pq Event 07H , Umask 02H 693The number of 694.Li PREFETCHT2 695instructions retired. 696.It Li Seg_Reg_Loads 697.Pq Event 06H , Umask 00H 698The number of segment register loads. 699.It Li Serial_Execution_Cycles 700.Pq Event 3CH , Umask 02H 701The number of non-halted bus cycles of this code while the other core 702was halted. 703.It Li Thermal_Trip 704.Pq Event 3BH , Umask C0H 705The duration in a thermal trip based on the current core clock. 706.It Li Unfusion 707.Pq Event DBH , Umask 00H 708The number of unfusion events. 709.It Li Unhalted_Core_Cycles 710.Pq Event 3CH , Umask 00H 711The number of core clock cycles when the clock signal on a specific 712core is not halted. 713This is an architectural performance event. 714.It Li Uops_Ret 715.Pq Event C2H , Umask 00H 716The number of micro-ops retired. 717.El 718.Ss Event Name Aliases 719The following table shows the mapping between the PMC-independent 720aliases supported by 721.Lb libpmc 722and the underlying hardware events used. 723.Bl -column "branch-mispredicts" "Description" 724.It Em Alias Ta Em Event 725.It Li branches Ta Li Br_Instr_Ret 726.It Li branch-mispredicts Ta Li Br_MisPred_Ret 727.It Li dc-misses Ta (unsupported) 728.It Li ic-misses Ta Li ICache_Misses 729.It Li instructions Ta Li Instr_Ret 730.It Li interrupts Ta Li HW_Int_Rx 731.It Li unhalted-cycles Ta (unsupported) 732.El 733.Sh PROCESSOR ERRATA 734The following errata affect performance measurement on these 735processors. 736These errata are documented in 737.Rs 738.%B Specification Update 739.%T Intel\(rg CoreTM Duo Processor and Intel\(rg CoreTM Solo Processor on 65 nm Process 740.%N Order Number 309222-017 741.%D July 2008 742.%Q Intel Corporation 743.Re 744.Bl -tag -width indent -compact 745.It AE19 746Data prefetch performance monitoring events can only be enabled 747on a single core. 748.It AE25 749Performance monitoring counters that count external bus events 750may report incorrect values after processor power state transitions. 751.It AE28 752Performance monitoring events for retired floating point operations 753(C1H) may not be accurate. 754.It AE29 755DR3 address match on MOVD/MOVQ/MOVNTQ memory store 756instruction may incorrectly increment performance monitoring count 757for saturating SIMD instructions retired (Event CFH). 758.It AE33 759Hardware prefetch performance monitoring events may be counted 760inaccurately. 761.It AE36 762The 763.Li CPU_CLK_UNHALTED 764performance monitoring event (Event 3CH) counts 765clocks when the processor is in the C1/C2 processor power states. 766.It AE39 767Certain performance monitoring counters related to bus, L2 cache 768and power management are inaccurate. 769.It AE51 770Performance monitoring events for retired instructions (Event C0H) may 771not be accurate. 772.It AE67 773Performance monitoring event 774.Li FP_ASSIST 775may not be accurate. 776.It AE78 777Performance monitoring event for hardware prefetch requests (Event 7784EH) and hardware prefetch request cache misses (Event 4FH) may not be 779accurate. 780.It AE82 781Performance monitoring event 782.Li FP_MMX_TRANS_TO_MMX 783may not count some transitions. 784.El 785.Sh SEE ALSO 786.Xr pmc 3 , 787.Xr pmc.atom 3 , 788.Xr pmc.core2 3 , 789.Xr pmc.iaf 3 , 790.Xr pmc.k7 3 , 791.Xr pmc.k8 3 , 792.Xr pmc.p4 3 , 793.Xr pmc.p5 3 , 794.Xr pmc.p6 3 , 795.Xr pmc.tsc 3 , 796.Xr pmclog 3 , 797.Xr hwpmc 4 798.Sh HISTORY 799The 800.Nm pmc 801library first appeared in 802.Fx 6.0 . 803.Sh AUTHORS 804The 805.Lb libpmc 806library was written by 807.An "Joseph Koshy" 808.Aq jkoshy@FreeBSD.org . 809