1.\" Copyright (c) 2008 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" This software is provided by Joseph Koshy ``as is'' and 13.\" any express or implied warranties, including, but not limited to, the 14.\" implied warranties of merchantability and fitness for a particular purpose 15.\" are disclaimed. in no event shall Joseph Koshy be liable 16.\" for any direct, indirect, incidental, special, exemplary, or consequential 17.\" damages (including, but not limited to, procurement of substitute goods 18.\" or services; loss of use, data, or profits; or business interruption) 19.\" however caused and on any theory of liability, whether in contract, strict 20.\" liability, or tort (including negligence or otherwise) arising in any way 21.\" out of the use of this software, even if advised of the possibility of 22.\" such damage. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd September 21, 2008 27.Os 28.Dt PMC.CORE 3 29.Sh NAME 30.Nm pmc.core 31.Nd measurement events for 32.Tn Intel 33.Tn Core Solo 34and 35.Tn Core Duo 36family CPUs 37.Sh LIBRARY 38.Lb libpmc 39.Sh SYNOPSIS 40.In pmc.h 41.Sh DESCRIPTION 42.Tn Intel 43.Tn "Core Solo" 44and 45.Tn "Core Duo" 46CPUs contain PMCs conforming to version 1 of the 47.Tn Intel 48performance measurement architecture. 49.Pp 50These PMCs are documented in 51.Rs 52.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 53.%T "Volume 3: System Programming Guide" 54.%N "Order Number 253669-027US" 55.%D July 2008 56.%Q "Intel Corporation" 57.Re 58.Ss PMC Features 59CPUs conforming to version 1 of the 60.Tn Intel 61performance measurement architecture contain two programmable PMCs of 62class 63.Li PMC_CLASS_IAP . 64The PMCs are 40 bits width and offer the following capabilities: 65.Bl -column "PMC_CAP_INTERRUPT" "Support" 66.It Em Capability Ta Em Support 67.It PMC_CAP_CASCADE Ta \&No 68.It PMC_CAP_EDGE Ta Yes 69.It PMC_CAP_INTERRUPT Ta Yes 70.It PMC_CAP_INVERT Ta Yes 71.It PMC_CAP_READ Ta Yes 72.It PMC_CAP_PRECISE Ta \&No 73.It PMC_CAP_SYSTEM Ta Yes 74.It PMC_CAP_TAGGING Ta \&No 75.It PMC_CAP_THRESHOLD Ta Yes 76.It PMC_CAP_USER Ta Yes 77.It PMC_CAP_WRITE Ta Yes 78.El 79.Ss Event Qualifiers 80Event specifiers for these PMCs support the following common 81qualifiers: 82.Bl -tag -width indent 83.It Li cmask= Ns Ar value 84Configure the PMC to increment only if the number of configured 85events measured in a cycle is greater than or equal to 86.Ar value . 87.It Li edge 88Configure the PMC to count the number of deasserted to asserted 89transitions of the conditions expressed by the other qualifiers. 90If specified, the counter will increment only once whenever a 91condition becomes true, irrespective of the number of clocks during 92which the condition remains true. 93.It Li inv 94Invert the sense of comparision when the 95.Dq Li cmask 96qualifier is present, making the counter increment when the number of 97events per cycle is less than the value specified by the 98.Dq Li cmask 99qualifier. 100.It Li os 101Configure the PMC to count events happening at processor privilege 102level 0. 103.It Li umask= Ns Ar value 104This qualifier is used to further qualify the event selected (see 105below). 106.It Li usr 107Configure the PMC to count events occurring at privilege levels 1, 2 108or 3. 109.El 110.Pp 111If neither of the 112.Dq Li os 113or 114.Dq Li usr 115qualifiers are specified, the default is to enable both. 116.Pp 117Events that require core-specificity to be specified use a 118additional qualifier 119.Dq Li core= Ns Ar value , 120where argument 121.Ar value 122is one of: 123.Bl -tag -width indent -compact 124.It Li all 125Measure event conditions on all cores. 126.It Li this 127Measure event conditions on this core. 128.El 129The default is 130.Dq Li this . 131.Pp 132Events that require an agent qualifier to be specified use an 133additional qualifier 134.Dq Li agent= Ns value , 135where argument 136.Ar value 137is one of: 138.Bl -tag -width indent -compact 139.It Li this 140Measure events associated with this bus agent. 141.It Li any 142Measure events caused by any bus agent. 143.El 144The default is 145.Dq Li this . 146.Pp 147Events that require a hardware prefetch qualifier to be specified use an 148additional qualifier 149.Dq Li prefetch= Ns Ar value , 150where argument 151.Ar value 152is one of: 153.Bl -tag -width "exclude" -compact 154.It Li both 155Include all prefetches. 156.It Li only 157Only count hardware prefetches. 158.It Li exclude 159Exclude hardware prefetches. 160.El 161The default is 162.Dq Li both . 163.Pp 164Events that require a cache coherence qualifier to be specified use an 165additional qualifer 166.Dq Li cachestate= Ns Ar value , 167where argument 168.Ar value 169contains one or more of the following letters: 170.Bl -tag -width indent -compact 171.It Li e 172Count cache lines in the exclusive state. 173.It Li i 174Count cache lines in the invalid state. 175.It Li m 176Count cache lines in the modified state. 177.It Li s 178Count cache lines in the shared state. 179.El 180The default is 181.Dq Li eims . 182.Ss Event Specifiers 183The following event names are case insensitive. 184Whitespace, hyphens and underscore characters in these names are 185ignored. 186.Pp 187Core PMCs support the following events: 188.Bl -tag -width indent 189.It Li BAClears 190.Pq Event E6H 191The number of BAClear conditions asserted. 192.It Li BTB_Misses 193.Pq Event E2H 194The number of branches for which the branch table buffer did not 195produce a prediction. 196.It Li Br_BAC_Missp_Exec 197.Pq Event 8AH 198The number of branch instructions executed that were mispredicted at 199the front end. 200.It Li Br_Bogus 201.Pq Event E4H 202The number of bogus branches. 203.It Li Br_Call_Exec 204.Pq Event 92H 205The number of 206.Li CALL 207instructions executed. 208.It Li Br_Call_Missp_Exec 209.Pq Event 93H 210The number of 211.Li CALL 212instructions executed that were mispredicted. 213.It Li Br_Cnd_Exec 214.Pq Event 8BH 215The number of conditional branch instructions executed. 216.It Li Br_Cnd_Missp_Exec 217.Pq Event 8CH 218The number of conditional branch instructions executed that were mispredicted. 219.It Li Br_Ind_Call_Exec 220.Pq Event 94H 221The number of indirect 222.Li CALL 223instructions executed. 224.It Li Br_Ind_Exec 225.Pq Event 8DH 226The number of indirect branches executed. 227.It Li Br_Ind_Missp_Exec 228.Pq Event 8EH 229The number of indirect branch instructions executed that were mispredicted. 230.It Li Br_Inst_Exec 231.Pq Event 88H 232The number of branch instructions executed including speculative branches. 233.It Li Br_Instr_Decoded 234.Pq Event E0H 235The number of branch instructions decoded. 236.It Li Br_Instr_Ret 237.Pq Event C4H 238The number of branch instructions retired. 239.It Li Br_MisPred_Ret 240.Pq Event C5H 241The number of mispredicted branch instructions retired. 242.It Li Br_MisPred_Taken_Ret 243.Pq Event CAH 244The number of taken and mispredicted branches retired. 245.It Li Br_Missp_Exec 246.Pq Event 89H 247The number of branch instructions executed and mispredicted at 248execution including branches that were not predicted. 249.It Li Br_Ret_BAC_Missp_Exec 250.Pq Event 91H 251The number of return branch instructions that were mispredicted at the 252front end. 253.It Li Br_Ret_Exec 254.Pq Event 8FH 255The number of return branch instructions executed. 256.It Li Br_Ret_Missp_Exec 257.Pq Event 90H 258The number of return branch instructions executed that were mispredicted. 259.It Li Br_Taken_Ret 260.Pq Event C9H 261The number of taken branches retired. 262.It Li Bus_BNR_Clocks 263.Pq Event 61H 264The number of external bus cycles while BNR (bus not ready) was asserted. 265.It Li Bus_DRDY_Clocks Op ,agent= Ns Ar agent 266.Pq Event 62H 267The number of external bus cycles while DRDY was asserted. 268.It Li Bus_Data_Rcv 269.Pq Event 64H 270.\" XXX Using the description in Core2 PMC documentation. 271The number of cycles during which the processor is busy receiving data. 272.It Li Bus_Locks_Clocks Op ,core= Ns Ar core 273.Pq Event 63H 274The number of external bus cycles while the bus lock signal was asserted. 275.It Li Bus_Not_In_Use Op ,core= Ns Ar core 276.Pq Event 7DH 277The number of cycles when there is no transaction from the core. 278.It Li Bus_Req_Outstanding Xo 279.Op ,agent= Ns Ar agent 280.Op ,core= Ns Ar core 281.Xc 282.Pq Event 60H 283The weighted cycles of cacheable bus data read requests 284from the data cache unit or hardware prefetcher. 285.It Li Bus_Snoop_Stall 286.Pq Event 7EH 287The number bus cycles while a bus snoop is stalled. 288.It Li Bus_Snoops Xo 289.Op ,agent= Ns Ar agent 290.Op ,cachestate= Ns Ar mesi 291.Xc 292.Pq Event 77H 293.\" XXX Using the description in Core2 PMC documentation. 294The number of snoop responses to bus transactions. 295.It Li Bus_Trans_Any Op ,agent= Ns Ar agent 296.Pq Event 70H 297The number of completed bus transactions. 298.It Li Bus_Trans_Brd Op ,core= Ns Ar core 299.Pq Event 65H 300The number of read bus transactions. 301.It Li Bus_Trans_Burst Op ,agent= Ns Ar agent 302.Pq Event 6EH 303The number of completed burst transactions. 304Retried transactions may be counted more than once. 305.It Li Bus_Trans_Def Op ,core= Ns Ar core 306.Pq Event 6DH 307The number of completed deferred transactions. 308.It Li Bus_Trans_IO Xo 309.Op ,agent= Ns Ar agent 310.Op ,core= Ns Ar core 311.Xc 312.Pq Event 6CH 313The number of completed I/O transactions counting both reads and 314writes. 315.It Li Bus_Trans_Ifetch Xo 316.Op ,agent= Ns Ar agent 317.Op ,core= Ns Ar core 318.Xc 319.Pq Event 68H 320Completed instruction fetch transactions. 321.It Li Bus_Trans_Inval Xo 322.Op ,agent= Ns Ar agent 323.Op ,core= Ns Ar core 324.Xc 325.Pq Event 69H 326The number completed invalidate transactions. 327.It Li Bus_Trans_Mem Op ,agent= Ns Ar agent 328.Pq Event 6FH 329The number of completed memory transactions. 330.It Li Bus_Trans_P Xo 331.Op ,agent= Ns Ar agent 332.Op ,core= Ns Ar core 333.Xc 334.Pq Event 6BH 335The number of completed partial transactions. 336.It Li Bus_Trans_Pwr Xo 337.Op ,agent= Ns Ar agent 338.Op ,core= Ns Ar core 339.Xc 340.Pq Event 6AH 341The number of completed partial write transactions. 342.It Li Bus_Trans_RFO Xo 343.Op ,agent= Ns Ar agent 344.Op ,core= Ns Ar core 345.Xc 346.Pq Event 66H 347The number of completed read-for-ownership transactions. 348.It Li Bus_Trans_WB Op ,agent= Ns Ar agent 349.Pq Event 67H 350The number of completed writeback transactions from the data cache 351unit, excluding L2 writebacks. 352.It Li Cycles_Div_Busy 353.Pq Event 14H 354The number of cycles the divider is busy. 355The event is only only available for on PMC0. 356.It Li Cycles_Int_Masked 357.Pq Event C6H 358The number of cycles while interrupts were disabled. 359.It Li Cycles_Int_Pending_Masked 360.Pq Event C7H 361The number of cycles while interrupts were disabled and interrupts 362were pending. 363.It Li DCU_Snoop_To_Share Op ,core= Ns core 364.Pq Event 78H 365The number of data cache unit snoops to L1 cache lines in the shared 366state. 367.It Li DCache_Cache_Lock Op ,cachestate= Ns Ar mesi 368.\" XXX needs clarification 369.Pq Event 42H 370The number of cacheable locked read operations to invalid state. 371.It Li DCache_Cache_LD Op ,cachestate= Ns Ar mesi 372.Pq Event 40H 373The number of cacheable L1 data read operations. 374.It Li DCache_Cache_ST Op ,cachestate= Ns Ar mesi 375.Pq Event 41H 376The number cacheable L1 data write operations. 377.It Li DCache_M_Evict 378.Pq Event 47H 379The number of M state data cache lines that were evicted. 380.It Li DCache_M_Repl 381.Pq Event 46H 382The number of M state data cache lines that were allocated. 383.It Li DCache_Pend_Miss 384.Pq Event 48H 385The weighted cycles an L1 miss was outstanding. 386.It Li DCache_Repl 387.Pq Event 45H 388The number of data cache line replacements. 389.It Li Data_Mem_Cache_Ref 390.Pq Event 44H 391The number of cacheable read and write operations to L1 data cache. 392.It Li Data_Mem_Ref 393.Pq Event 43H 394The number of L1 data reads and writes, both cacheable and 395uncacheable. 396.It Li Dbus_Busy Op ,core= Ns Ar core 397.Pq Event 22H 398The number of core cycles during which the data bus was busy. 399.It Li Dbus_Busy_Rd Op ,core= Ns Ar core 400.Pq Event 23H 401The nunber of cycles during which the data bus was busy transferring 402data to a core. 403.It Li Div 404.Pq Event 13H 405The number of divide operations including speculative operations for 406integer and floating point divides. 407This event can only be counted on PMC1. 408.It Li Dtlb_Miss 409.Pq Event 49H 410The number of data references that missed the TLB. 411.It Li ESP_Uops 412.Pq Event D7H 413The number of ESP folding instructions decoded. 414.It Li EST_Trans Op ,trans= Ns Ar transition 415.Pq Event 3AH 416Count the number of Intel Enhanced SpeedStep transitions. 417The argument 418.Ar transition 419can be one of the following values: 420.Bl -tag -width indent -compact 421.It Li any 422(Umask 00H) Count all transitions. 423.It Li frequency 424(Umask 01H) Count frequency transitions. 425.El 426The default is 427.Dq Li any . 428.It Li FP_Assist 429.Pq Event 11H 430The number of floating point operations that required microcode 431assists. 432The event is only available on PMC1. 433.It Li FP_Comp_Instr_Ret 434.Pq Event C1H 435The number of X87 floating point compute instructions retired. 436The event is only available on PMC0. 437.It Li FP_Comps_Op_Exe 438.Pq Event 10H 439The number of floating point computational instructions executed. 440.It Li FP_MMX_Trans 441.Pq Event CCH , Umask 01H 442The number of transitions from X87 to MMX. 443.It Li Fused_Ld_Uops_Ret 444.Pq Event DAH , Umask 01H 445The number of fused load uops retired. 446.It Li Fused_St_Uops_Ret 447.Pq Event DAH , Umask 02H 448The number of fused store uops retired. 449.It Li Fused_Uops_Ret 450.Pq Event DAH , Umask 00H 451The number of fused uops retired. 452.It Li HW_Int_Rx 453.Pq Event C8H 454The number of hardware interrupts received. 455.It Li ICache_Misses 456.Pq Event 81H 457The number of instruction fetch misses in the instruction cache and 458streaming buffers. 459.It Li ICache_Reads 460.Pq Event 80H 461The number of instruction fetches from the the instruction cache and 462streaming buffers counting both cacheable and uncacheable fetches. 463.It Li IFU_Mem_Stall 464.Pq Event 86H 465The number of cycles the instruction fetch unit was stalled while 466waiting for data from memory. 467.It Li ILD_Stall 468.Pq Event 87H 469The number of instruction length decoder stalls. 470.It Li ITLB_Misses 471.Pq Event 85H 472The number of instruction TLB misses. 473.It Li Instr_Decoded 474.Pq Event D0H 475The number of instructions decoded. 476.It Li Instr_Ret 477.Pq Event C0H 478The number of instructions retired. 479.It Li L1_Pref_Req 480.Pq Event 4FH 481The number of L1 prefetch request due to data cache misses. 482.It Li L2_ADS Op ,core= Ns core 483.Pq Event 21H 484The number of L2 address strobes. 485.It Li L2_IFetch Xo 486.Op ,cachestate= Ns Ar mesi 487.Op ,core= Ns Ar core 488.Xc 489.Pq Event 28H 490The number of instruction fetches by the instruction fetch unit from 491L2 cache including speculative fetches. 492.It Li L2_LD Xo 493.Op ,cachestate= Ns Ar mesi 494.Op ,core= Ns Ar core 495.Xc 496.Pq Event 29H 497The number of L2 cache reads. 498.It Li L2_Lines_In Xo 499.Op ,core= Ns Ar core 500.Op ,prefetch= Ns Ar prefetch 501.Xc 502.Pq Event 24H 503The number of L2 cache lines allocated. 504.It Li L2_Lines_Out Xo 505.Op ,core= Ns Ar core 506.Op ,prefetch= Ns Ar prefetch 507.Xc 508.Pq Event 26H 509The number of L2 cache lines evicted. 510.It Li L2_M_Lines_In Op ,core= Ns Ar core 511.Pq Event 25H 512The number of L2 M state cache lines allocated. 513.It Li L2_M_Lines_Out Xo 514.Op ,core= Ns Ar core 515.Op ,prefetch= Ns Ar prefetch 516.Xc 517.Pq Event 27H 518The number of L2 M state cache lines evicted. 519.It Li L2_No_Request_Cycles Xo 520.Op ,cachestate= Ns Ar mesi 521.Op ,core= Ns Ar core 522.Op ,prefetch= Ns Ar prefetch 523.Xc 524.Pq Event 32H 525The number of cycles there was no request to access L2 cache. 526.It Li L2_Reject_Cycles Xo 527.Op ,cachestate= Ns Ar mesi 528.Op ,core= Ns Ar core 529.Op ,prefetch= Ns Ar prefetch 530.Xc 531.Pq Event 30H 532The number of cycles the L2 cache was busy and rejecting new requests. 533.It Li L2_Rqsts Xo 534.Op ,cachestate= Ns Ar mesi 535.Op ,core= Ns Ar core 536.Op ,prefetch= Ns Ar prefetch 537.Xc 538.Pq Event 2EH 539The number of L2 cache requests. 540.It Li L2_ST Xo 541.Op ,cachestate= Ns Ar mesi 542.Op ,core= Ns Ar core 543.Xc 544.Pq Event 2AH 545The number of L2 cache writes including speculative writes. 546.It Li LD_Blocks 547.Pq Event 03H 548The number of load operations delayed due to store buffer blocks. 549.It Li MMX_Assist 550.Pq Event CDH 551The number of EMMX instructions executed. 552.It Li MMX_FP_Trans 553.Pq Event CCH , Umask 00H 554The number of transitions from MMX to X87. 555.It Li MMX_Instr_Exec 556.Pq Event B0H 557The number of MMX instructions executed excluding 558.Li MOVQ 559and 560.Li MOVD 561stores. 562.It Li MMX_Instr_Ret 563.Pq Event CEH 564The number of MMX instructions retired. 565.It Li Misalign_Mem_Ref 566.Pq Event 05H 567The number of misaligned data memory references, counting loads and 568stores. 569.It Li Mul 570.Pq Event 12H 571The number of multiply operations include speculative floating point 572and integer multiplies. 573This event is available on PMC1 only. 574.It Li NonHlt_Ref_Cycles 575.Pq Event 3CH , Umask 01H 576The number of non-halted bus cycles. 577.It Li Pref_Rqsts_Dn 578.Pq Event F8H 579The number of hardware prefetch requests issued in backward streams. 580.It Li Pref_Rqsts_Up 581.Pq Event F0H 582The number of hardware prefetch requests issued in forward streams. 583.It Li Resource_Stall 584.Pq Event A2H 585The number of cycles where there is a resource related stall. 586.It Li SD_Drains 587.Pq Event 04H 588The number of cycles while draining store buffers. 589.It Li SIMD_FP_DP_P_Ret 590.Pq Event D8H , Umask 02H 591The number of SSE/SSE2 packed double precision instructions retired. 592.It Li SIMD_FP_DP_P_Comp_Ret 593.Pq Event D9H , Umask 02H 594The number of SSE/SSE2 packed double precision compute instructions 595retired. 596.It Li SIMD_FP_DP_S_Ret 597.Pq Event D8H , Umask 03H 598The number of SSE/SSE2 scalar double precision instructions retired. 599.It Li SIMD_FP_DP_S_Comp_Ret 600.Pq Event D9H , Umask 03H 601The number of SSE/SSE2 scalar double precision compute instructions 602retired. 603.It Li SIMD_FP_SP_P_Comp_Ret 604.Pq Event D9H , Umask 00H 605The number of SSE/SSE2 packed single precision compute instructions 606retired. 607.It Li SIMD_FP_SP_Ret 608.Pq Event D8H , Umask 00H 609The number of SSE/SSE2 scalar single precision instructions retired, 610both packed and scalar. 611.It Li SIMD_FP_SP_S_Ret 612.Pq Event D8H , Umask 01H 613The number of SSE/SSE2 scalar single precision instructions retired. 614.It Li SIMD_FP_SP_S_Comp_Ret 615.Pq Event D9H , Umask 01H 616The number of SSE/SSE2 single precision compute instructions retired. 617.It Li SIMD_Int_128_Ret 618.Pq Event D8H , Umask 04H 619The number of SSE2 128-bit integer instructions retired. 620.It Li SIMD_Int_Pari_Exec 621.Pq Event B3H , Umask 20H 622The number of SIMD integer packed arithmetic instructions executed. 623.It Li SIMD_Int_Pck_Exec 624.Pq Event B3H , Umask 04H 625The number of SIMD integer pack operations instructions executed. 626.It Li SIMD_Int_Plog_Exec 627.Pq Event B3H , Umask 10H 628The number of SIMD integer packed logical instructions executed. 629.It Li SIMD_Int_Pmul_Exec 630.Pq Event B3H , Umask 01H 631The number of SIMD integer packed multiply instructions executed. 632.It Li SIMD_Int_Psft_Exec 633.Pq Event B3H , Umask 02H 634The number of SIMD integer packed shift instructions executed. 635.It Li SIMD_Int_Sat_Exec 636.Pq Event B1H 637The number of SIMD integer saturating instructions executed. 638.It Li SIMD_Int_Upck_Exec 639.Pq Event B3H , Umask 08H 640The number of SIMD integer unpack instructions executed. 641.It Li SMC_Detected 642.Pq Event C3H 643The number of times self-modifying code was detected. 644.It Li SSE_NTStores_Miss 645.Pq Event 4BH , Umask 03H 646The number of times an SSE streaming store instruction missed all caches. 647.It Li SSE_NTStores_Ret 648.Pq Event 07H , Umask 03H 649The number of SSE streaming store instructions executed. 650.It Li SSE_PrefNta_Miss 651.Pq Event 4BH , Umask 00H 652The number of times 653.Li PREFETCHNTA 654missed all caches. 655.It Li SSE_PrefNta_Ret 656.Pq Event 07H , Umask 00H 657The number of 658.Li PREFETCHNTA 659instructions retired. 660.It Li SSE_PrefT1_Miss 661.Pq Event 4BH , Umask 01H 662The number of times 663.Li PREFETCHT1 664missed all caches. 665.It Li SSE_PrefT1_Ret 666.Pq Event 07H , Umask 01H 667The number of 668.Li PREFETCHT1 669instructions retired. 670.It Li SSE_PrefT2_Miss 671.Pq Event 4BH , Umask 02H 672The number of times 673.Li PREFETCHNT2 674missed all caches. 675.It Li SSE_PrefT2_Ret 676.Pq Event 07H , Umask 02H 677The number of 678.Li PREFETCHT2 679instructions retired. 680.It Li Seg_Reg_Loads 681.Pq Event 06H 682The number of segment register loads. 683.It Li Serial_Execution_Cycles 684.Pq Event 3CH , Umask 02H 685The number of non-halted bus cycles of this code while the other core 686was halted. 687.It Li Thermal_Trip 688.Pq Event 3BH , Umask C0H 689The duration in a thermal trip based on the current core clock. 690.It Li Unfusion 691.Pq Event DBH 692The number of unfusion events. 693.It Li Uops_Ret 694.Pq Event C2H 695The number of micro-ops retired. 696.El 697.Ss Event Name Aliases 698The following table shows the mapping between the PMC-independent 699aliases supported by 700.Lb libpmc 701and the underlying hardware events used. 702.Bl -column "branch-mispredicts" "Description" 703.It Em Alias Ta Em Event 704.It Li branches Ta Li Br_Instr_Ret 705.It Li branch-mispredicts Ta Li Br_MisPred_Ret 706.It Li dc-misses Ta (unsupported) 707.It Li ic-misses Ta Li ICache_Misses 708.It Li instructions Ta Li Instr_Ret 709.It Li interrupts Ta Li HW_Int_Rx 710.It Li unhalted-cycles Ta (unsupported) 711.El 712.Sh SEE ALSO 713.Xr pmc 3 , 714.Xr pmc.atom 3 , 715.Xr pmc.core2 3 , 716.Xr pmc.iaf 3 , 717.Xr pmc.k7 3 , 718.Xr pmc.k8 3 , 719.Xr pmc.p4 3 , 720.Xr pmc.p5 3 , 721.Xr pmc.p6 3 , 722.Xr pmc.tsc 3 , 723.Xr pmclog 3 , 724.Xr hwpmc 4 725.Sh HISTORY 726The 727.Nm pmc 728library first appeared in 729.Fx 6.0 . 730.Sh AUTHORS 731The 732.Lb libpmc 733library was written by 734.An "Joseph Koshy" 735.Aq jkoshy@FreeBSD.org . 736