1.\" Copyright (c) 2008 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 20, 2014 27.Dt PMC.ATOM 3 28.Os 29.Sh NAME 30.Nm pmc.atom 31.Nd measurement events for 32.Tn Intel 33.Tn Atom 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn Atom 42CPUs contain PMCs conforming to version 3 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs contains two classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Atom PMCs are documented in 59.Rs 60.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 61.%T "Volume 3: System Programming Guide" 62.%N "Order Number 253669-027US" 63.%D July 2008 64.%Q "Intel Corporation" 65.Re 66.Ss ATOM FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69.Ss ATOM PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta Yes 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta Yes 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta Yes 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li any 90Count matching events seen on any logical processor in a package. 91.It Li cmask= Ns Ar value 92Configure the PMC to increment only if the number of configured 93events measured in a cycle is greater than or equal to 94.Ar value . 95.It Li edge 96Configure the PMC to count the number of de-asserted to asserted 97transitions of the conditions expressed by the other qualifiers. 98If specified, the counter will increment only once whenever a 99condition becomes true, irrespective of the number of clocks during 100which the condition remains true. 101.It Li inv 102Invert the sense of comparison when the 103.Dq Li cmask 104qualifier is present, making the counter increment when the number of 105events per cycle is less than the value specified by the 106.Dq Li cmask 107qualifier. 108.It Li os 109Configure the PMC to count events happening at processor privilege 110level 0. 111.It Li usr 112Configure the PMC to count events occurring at privilege levels 1, 2 113or 3. 114.El 115.Pp 116If neither of the 117.Dq Li os 118or 119.Dq Li usr 120qualifiers are specified, the default is to enable both. 121.Pp 122Events that require core-specificity to be specified use a 123additional qualifier 124.Dq Li core= Ns Ar core , 125where argument 126.Ar core 127is one of: 128.Bl -tag -width indent 129.It Li all 130Measure event conditions on all cores. 131.It Li this 132Measure event conditions on this core. 133.El 134.Pp 135The default is 136.Dq Li this . 137.Pp 138Events that require an agent qualifier to be specified use an 139additional qualifier 140.Dq Li agent= Ns agent , 141where argument 142.Ar agent 143is one of: 144.Bl -tag -width indent 145.It Li this 146Measure events associated with this bus agent. 147.It Li any 148Measure events caused by any bus agent. 149.El 150.Pp 151The default is 152.Dq Li this . 153.Pp 154Events that require a hardware prefetch qualifier to be specified use an 155additional qualifier 156.Dq Li prefetch= Ns Ar prefetch , 157where argument 158.Ar prefetch 159is one of: 160.Bl -tag -width "exclude" 161.It Li both 162Include all prefetches. 163.It Li only 164Only count hardware prefetches. 165.It Li exclude 166Exclude hardware prefetches. 167.El 168.Pp 169The default is 170.Dq Li both . 171.Pp 172Events that require a cache coherence qualifier to be specified use an 173additional qualifier 174.Dq Li cachestate= Ns Ar state , 175where argument 176.Ar state 177contains one or more of the following letters: 178.Bl -tag -width indent 179.It Li e 180Count cache lines in the exclusive state. 181.It Li i 182Count cache lines in the invalid state. 183.It Li m 184Count cache lines in the modified state. 185.It Li s 186Count cache lines in the shared state. 187.El 188.Pp 189The default is 190.Dq Li eims . 191.Pp 192Events that require a snoop response qualifier to be specified use an 193additional qualifier 194.Dq Li snoopresponse= Ns Ar response , 195where argument 196.Ar response 197comprises of the following keywords separated by 198.Dq + 199signs: 200.Bl -tag -width indent 201.It Li clean 202Measure CLEAN responses. 203.It Li hit 204Measure HIT responses. 205.It Li hitm 206Measure HITM responses. 207.El 208.Pp 209The default is to measure all the above responses. 210.Pp 211Events that require a snoop type qualifier use an additional qualifier 212.Dq Li snooptype= Ns Ar type , 213where argument 214.Ar type 215comprises the one of the following keywords: 216.Bl -tag -width indent 217.It Li cmp2i 218Measure CMP2I snoops. 219.It Li cmp2s 220Measure CMP2S snoops. 221.El 222.Pp 223The default is to measure both snoops. 224.Ss Event Specifiers (Programmable PMCs) 225Atom programmable PMCs support the following events: 226.Bl -tag -width indent 227.It Li BACLEARS 228.Pq Event E6H , Umask 01H 229The number of times the front end is resteered. 230.It Li BOGUS_BR 231.Pq Event E4H , Umask 00H 232The number of byte sequences mistakenly detected as taken branch 233instructions. 234.It Li BR_BAC_MISSP_EXEC 235.Pq Event 8AH , Umask 00H 236The number of branch instructions that were mispredicted when 237decoded. 238.It Li BR_CALL_MISSP_EXEC 239.Pq Event 93H , Umask 00H 240The number of mispredicted 241.Li CALL 242instructions that were executed. 243.It Li BR_CALL_EXEC 244.Pq Event 92H , Umask 00H 245The number of 246.Li CALL 247instructions executed. 248.It Li BR_CND_EXEC 249.Pq Event 8BH , Umask 00H 250The number of conditional branches executed, but not necessarily retired. 251.It Li BR_CND_MISSP_EXEC 252.Pq Event 8CH , Umask 00H 253The number of mispredicted conditional branches executed. 254.It Li BR_IND_CALL_EXEC 255.Pq Event 94H , Umask 00H 256The number of indirect 257.Li CALL 258instructions executed. 259.It Li BR_IND_EXEC 260.Pq Event 8DH , Umask 00H 261The number of indirect branch instructions executed. 262.It Li BR_IND_MISSP_EXEC 263.Pq Event 8EH , Umask 00H 264The number of mispredicted indirect branch instructions executed. 265.It Li BR_INST_DECODED 266.Pq Event E0H , Umask 01H 267The number of branch instructions decoded. 268.It Li BR_INST_EXEC 269.Pq Event 88H , Umask 00H 270The number of branches executed, but not necessarily retired. 271.It Li BR_INST_RETIRED.ANY 272.Pq Event C4H , Umask 00H 273.Pq Alias Qq "Branch Instruction Retired" 274The number of branch instructions retired. 275This is an architectural performance event. 276.It Li BR_INST_RETIRED.ANY1 277.Pq Event C4H , Umask 0FH 278The number of branch instructions retired that were mispredicted. 279.It Li BR_INST_RETIRED.MISPRED 280.Pq Event C5H , Umask 00H 281.Pq Alias Qq "Branch Misses Retired" 282The number of mispredicted branch instructions retired. 283This is an architectural performance event. 284.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN 285.Pq Event C4H , Umask 02H 286The number of not taken branch instructions retired that were 287mispredicted. 288.It Li BR_INST_RETIRED.MISPRED_TAKEN 289.Pq Event C4H , Umask 08H 290The number taken branch instructions retired that were mispredicted. 291.It Li BR_INST_RETIRED.PRED_NOT_TAKEN 292.Pq Event C4H , Umask 01H 293The number of not taken branch instructions retired that were 294correctly predicted. 295.It Li BR_INST_RETIRED.PRED_TAKEN 296.Pq Event C4H , Umask 04H 297The number of taken branch instructions retired that were correctly 298predicted. 299.It Li BR_INST_RETIRED.TAKEN 300.Pq Event C4H , Umask 0CH 301The number of taken branch instructions retired. 302.It Li BR_MISSP_EXEC 303.Pq Event 89H , Umask 00H 304The number of mispredicted branch instructions that were executed. 305.It Li BR_RET_MISSP_EXEC 306.Pq Event 90H , Umask 00H 307The number of mispredicted 308.Li RET 309instructions executed. 310.It Li BR_RET_BAC_MISSP_EXEC 311.Pq Event 91H , Umask 00H 312The number of 313.Li RET 314instructions executed that were mispredicted at decode time. 315.It Li BR_RET_EXEC 316.Pq Event 8FH , Umask 00H 317The number of 318.Li RET 319instructions executed. 320.It Li BR_TKN_BUBBLE_1 321.Pq Event 97H , Umask 00H 322The number of branch predicted taken with bubble 1. 323.It Li BR_TKN_BUBBLE_2 324.Pq Event 98H , Umask 00H 325The number of branch predicted taken with bubble 2. 326.It Li BUSQ_EMPTY Op ,core= Ns Ar core 327.Pq Event 7DH 328The number of cycles during which the core did not have any pending 329transactions in the bus queue. 330.It Li BUS_BNR_DRV Op ,agent= Ns Ar agent 331.Pq Event 61H 332The number of Bus Not Ready signals asserted on the bus. 333This event is thread-independent. 334.It Li BUS_DATA_RCV Op ,core= Ns Ar core 335.Pq Event 64H 336The number of bus cycles during which the processor is receiving data. 337This event is thread-independent. 338.It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent 339.Pq Event 62H 340The number of bus cycles during which the Data Ready signal is asserted 341on the bus. 342This event is thread-independent. 343.It Li BUS_HIT_DRV Op ,agent= Ns Ar agent 344.Pq Event 7AH 345The number of bus cycles during which the processor drives the 346.Li HIT# 347pin. 348This event is thread-independent. 349.It Li BUS_HITM_DRV Op ,agent= Ns Ar agent 350.Pq Event 7BH 351The number of bus cycles during which the processor drives the 352.Li HITM# 353pin. 354This event is thread-independent. 355.It Li BUS_IO_WAIT Op ,core= Ns Ar core 356.Pq Event 7FH 357The number of core cycles during which I/O requests wait in the bus 358queue. 359.It Li BUS_LOCK_CLOCKS Xo 360.Op ,agent= Ns Ar agent 361.Op ,core= Ns Ar core 362.Xc 363.Pq Event 63H 364The number of bus cycles during which the 365.Li LOCK 366signal was asserted on the bus. 367This event is thread independent. 368.It Li BUS_REQUEST_OUTSTANDING Xo 369.Op ,agent= Ns Ar agent 370.Op ,core= Ns Ar core 371.Xc 372.Pq Event 60H 373The number of pending full cache line read transactions on the bus 374occurring in each cycle. 375This event is thread independent. 376.It Li BUS_TRANS_P Xo 377.Op ,agent= Ns Ar agent 378.Op ,core= Ns Ar core 379.Xc 380.Pq Event 6BH 381The number of partial bus transactions. 382.It Li BUS_TRANS_IFETCH Xo 383.Op ,agent= Ns Ar agent 384.Op ,core= Ns Ar core 385.Xc 386.Pq Event 68H 387The number of instruction fetch full cache line bus transactions. 388.It Li BUS_TRANS_INVAL Xo 389.Op ,agent= Ns Ar agent 390.Op ,core= Ns Ar core 391.Xc 392.Pq Event 69H 393The number of invalidate bus transactions. 394.It Li BUS_TRANS_PWR Xo 395.Op ,agent= Ns Ar agent 396.Op ,core= Ns Ar core 397.Xc 398.Pq Event 6AH 399The number of partial write bus transactions. 400.It Li BUS_TRANS_DEF Xo 401.Op ,agent= Ns Ar agent 402.Op ,core= Ns Ar core 403.Xc 404.Pq Event 6DH 405The number of deferred bus transactions. 406.It Li BUS_TRANS_BURST Xo 407.Op ,agent= Ns Ar agent 408.Op ,core= Ns Ar core 409.Xc 410.Pq Event 6EH 411The number of burst transactions. 412.It Li BUS_TRANS_MEM Xo 413.Op ,agent= Ns Ar agent 414.Op ,core= Ns Ar core 415.Xc 416.Pq Event 6FH 417The number of memory bus transactions. 418.It Li BUS_TRANS_ANY Xo 419.Op ,agent= Ns Ar agent 420.Op ,core= Ns Ar core 421.Xc 422.Pq Event 70H 423The number of bus transactions of any kind. 424.It Li BUS_TRANS_BRD Xo 425.Op ,agent= Ns Ar agent 426.Op ,core= Ns Ar core 427.Xc 428.Pq Event 65H 429The number of burst read transactions. 430.It Li BUS_TRANS_IO Xo 431.Op ,agent= Ns Ar agent 432.Op ,core= Ns Ar core 433.Xc 434.Pq Event 6CH 435The number of completed I/O bus transactions due to 436.Li IN 437and 438.Li OUT 439instructions. 440.It Li BUS_TRANS_RFO Xo 441.Op ,agent= Ns Ar agent 442.Op ,core= Ns Ar core 443.Xc 444.Pq Event 66H 445The number of Read For Ownership bus transactions. 446.It Li BUS_TRANS_WB Xo 447.Op ,agent= Ns Ar agent 448.Op ,core= Ns Ar core 449.Xc 450.Pq Event 67H 451The number explicit write-back bus transactions due to dirty line 452evictions. 453.It Li CMP_SNOOP Xo 454.Op ,core= Ns Ar core 455.Op ,snooptype= Ns Ar snoop 456.Xc 457.Pq Event 78H 458The number of times the L1 data cache is snooped by the other core in 459the same processor. 460.It Li CPU_CLK_UNHALTED.BUS 461.Pq Event 3CH , Umask 01H 462.Pq Alias Qq "Unhalted Reference Cycles" 463The number of bus cycles when the core is not in the halt state. 464This is an architectural performance event. 465.It Li CPU_CLK_UNHALTED.CORE_P 466.Pq Event 3CH , Umask 00H 467.Pq Alias Qq "Unhalted Core Cycles" 468The number of core cycles while the core is not in a halt state. 469This is an architectural performance event. 470.It Li CPU_CLK_UNHALTED.NO_OTHER 471.Pq Event 3CH , Umask 02H 472The number of bus cycles during which the core remains unhalted and 473the other core is halted. 474.It Li CYCLES_DIV_BUSY 475.Pq Event 14H , Umask 01H 476The number of cycles the divider is busy. 477.It Li CYCLES_INT_MASKED.CYCLES_INT_MASKED 478.Pq Event C6H , Umask 01H 479The number of cycles during which interrupts are disabled. 480.It Li CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED 481.Pq Event C6H , Umask 02H 482The number of cycles during which there were pending interrupts while 483interrupts were disabled. 484.It Li CYCLES_L1I_MEM_STALLED 485.Pq Event 86H , Umask 00H 486The number of cycles for which an instruction fetch stalls. 487.It Li DATA_TLB_MISSES.DTLB_MISS 488.Pq Event 08H , Umask 07H 489The number of memory access that missed the Data TLB 490.It Li DATA_TLB_MISSES.DTLB_MISS_LD 491.Pq Event 08H , Umask 05H 492The number of loads that missed the Data TLB. 493.It Li DATA_TLB_MISSES.DTLB_MISS_ST 494.Pq Event 08H , Umask 06H 495The number of stores that missed the Data TLB. 496.It Li DATA_TLB_MISSES.UTLB_MISS_LD 497.Pq Event 08H , Umask 09H 498The number of loads that missed the UTLB. 499.It Li DELAYED_BYPASS.FP 500.Pq Event 19H , Umask 00H 501The number of floating point operations that used data immediately 502after the data was generated by a non floating point execution unit. 503.It Li DELAYED_BYPASS.LOAD 504.Pq Event 19H , Umask 01H 505The number of delayed bypass penalty cycles that a load operation incurred. 506.It Li DELAYED_BYPASS.SIMD 507.Pq Event 19H , Umask 02H 508The number of times SIMD operations use data immediately after data, 509was generated by a non-SIMD execution unit. 510.It Li DIV 511.Pq Event 13H , Umask 00H 512The number of divide operations executed. 513This event is only available on PMC1. 514.It Li DIV.AR 515.Pq Event 13H , Umask 81H 516The number of divide operations retired. 517.It Li DIV.S 518.Pq Event 13H , Umask 01H 519The number of divide operations executed. 520.It Li DTLB_MISSES.ANY 521.Pq Event 08H , Umask 01H 522The number of Data TLB misses, including misses that result from 523speculative accesses. 524.It Li DTLB_MISSES.L0_MISS_LD 525.Pq Event 08H , Umask 04H 526The number of level 0 DTLB misses due to load operations. 527.It Li DTLB_MISSES.MISS_LD 528.Pq Event 08H , Umask 02H 529The number of Data TLB misses due to load operations. 530.It Li DTLB_MISSES.MISS_ST 531.Pq Event 08H , Umask 08H 532The number of Data TLB misses due to store operations. 533.It Li EIST_TRANS 534.Pq Event 3AH , Umask 00H 535The number of Enhanced Intel SpeedStep Technology transitions. 536.It Li ESP.ADDITIONS 537.Pq Event ABH , Umask 02H 538The number of automatic additions to the 539.Li %esp 540register. 541.It Li ESP.SYNCH 542.Pq Event ABH , Umask 01H 543The number of times the 544.Li %esp 545register was explicitly used in an address expression after 546it is implicitly used by a 547.Li PUSH 548or 549.Li POP 550instruction. 551.It Li EXT_SNOOP Xo 552.Op ,agent= Ns Ar agent 553.Op ,snoopresponse= Ns Ar response 554.Xc 555.Pq Event 77H 556The number of snoop responses to bus transactions. 557.It Li FP_ASSIST 558.Pq Event 11H , Umask 01H 559The number of floating point operations executed that needed 560a microcode assist, including speculatively executed instructions. 561.It Li FP_ASSIST.AR 562.Pq Event 11H , Umask 81H 563The number of floating point operations retired that needed 564a microcode assist. 565.It Li FP_COMP_OPS_EXE 566.Pq Event 10H , Umask 00H 567The number of floating point computational micro-ops executed. 568The event is available only on PMC0. 569.It Li FP_MMX_TRANS_TO_FP 570.Pq Event CCH , Umask 02H 571The number of transitions from MMX instructions to floating point 572instructions. 573.It Li FP_MMX_TRANS_TO_MMX 574.Pq Event CCH , Umask 01H 575The number of transitions from floating point instructions to MMX 576instructions. 577.It Li HW_INT_RCV 578.Pq Event C8H , Umask 00H 579The number of hardware interrupts received. 580.It Li ICACHE.ACCESSES 581.Pq Event 80H , Umask 03H 582The number of instruction fetches. 583.It Li ICACHE.MISSES 584.Pq Event 80H , Umask 02H 585The number of instruction fetches that miss the instruction cache. 586.It Li IDLE_DURING_DIV 587.Pq Event 18H , Umask 00H 588The number of cycles the divider is busy and no other execution unit 589or load operation was in progress. 590This event is available only on PMC0. 591.It Li ILD_STALL 592.Pq Event 87H , Umask 00H 593The number of cycles the instruction length decoder stalled due to a 594length changing prefix. 595.It Li INST_QUEUE.FULL 596.Pq Event 83H , Umask 02H 597The number of cycles during which the instruction queue is full. 598.It Li INST_RETIRED.ANY_P 599.Pq Event C0H , Umask 00H 600.Pq Alias Qq "Instruction Retired" 601The number of instructions retired. 602This is an architectural performance event. 603.It Li INST_RETIRED.LOADS 604.Pq Event C0H , Umask 01H 605The number of instructions retired that contained a load operation. 606.It Li INST_RETIRED.OTHER 607.Pq Event C0H , Umask 04H 608The number of instructions retired that did not contain a load or a 609store operation. 610.It Li INST_RETIRED.STORES 611.Pq Event C0H , Umask 02H 612The number of instructions retired that contained a store operation. 613.It Li ITLB.FLUSH 614.Pq Event 82H , Umask 04H 615The number of ITLB flushes. 616.It Li ITLB.LARGE_MISS 617.Pq Event 82H , Umask 10H 618The number of instruction fetches from large pages that miss the 619ITLB. 620.It Li ITLB.MISSES 621.Pq Event 82H , Umask 02H 622The number of instruction fetches from both large and small pages that 623miss the ITLB. 624.It Li ITLB.SMALL_MISS 625.Pq Event 82H , Umask 02H 626The number of instruction fetches from small pages that miss the ITLB. 627.It Li ITLB_MISS_RETIRED 628.Pq Event C9H , Umask 00H 629The number of retired instructions that missed the ITLB when they were 630fetched. 631.It Li L1D_ALL_REF 632.Pq Event 43H , Umask 01H 633The number of references to L1 data cache counting loads and stores of 634to all memory types. 635.It Li L1D_ALL_CACHE_REF 636.Pq Event 43H , Umask 02H 637The number of data reads and writes to cacheable memory. 638.It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state 639.Pq Event 42H 640The number of locked reads from cacheable memory. 641.It Li L1D_CACHE_LOCK_DURATION 642.Pq Event 42H , Umask 10H 643The number of cycles during which any cache line is locked by any 644locking instruction. 645.It Li L1D_CACHE.LD 646.Pq Event 40H , Umask 21H 647The number of data reads from cacheable memory. 648.It Li L1D_CACHE.ST 649.Pq Event 41H , Umask 22H 650The number of data writes to cacheable memory. 651.It Li L1D_M_EVICT 652.Pq Event 47H , Umask 00H 653The number of modified cache lines evicted from L1 data cache. 654.It Li L1D_M_REPL 655.Pq Event 46H , Umask 00H 656The number of modified lines allocated in L1 data cache. 657.It Li L1D_PEND_MISS 658.Pq Event 48H , Umask 00H 659The total number of outstanding L1 data cache misses at any clock. 660.It Li L1D_PREFETCH.REQUESTS 661.Pq Event 4EH , Umask 10H 662The number of times L1 data cache requested to prefetch a data cache 663line. 664.It Li L1D_REPL 665.Pq Event 45H , Umask 0FH 666The number of lines brought into L1 data cache. 667.It Li L1D_SPLIT.LOADS 668.Pq Event 49H , Umask 01H 669The number of load operations that span two cache lines. 670.It Li L1D_SPLIT.STORES 671.Pq Event 49H , Umask 02H 672The number of store operations that span two cache lines. 673.It Li L1I_MISSES 674.Pq Event 81H , Umask 00H 675The number of instruction fetch unit misses. 676.It Li L1I_READS 677.Pq Event 80H , Umask 00H 678The number of instruction fetches. 679.It Li L2_ADS Op ,core= Ns core 680.Pq Event 21H 681The number of cycles that the L2 address bus is in use. 682.It Li L2_DBUS_BUSY_RD Op ,core= Ns core 683.Pq Event 23H 684The number of core cycles during which the L2 data bus is busy 685transferring data to the core. 686.It Li L2_IFETCH Xo 687.Op ,cachestate= Ns Ar state 688.Op ,core= Ns Ar core 689.Xc 690.Pq Event 28H 691The number of instruction cache line requests from the instruction 692fetch unit. 693.It Li L2_LD Xo 694.Op ,cachestate= Ns Ar state 695.Op ,core= Ns Ar core 696.Op ,prefetch= Ns Ar prefetch 697.Xc 698.Pq Event 29H 699The number of L2 cache read requests from L1 cache and L2 700prefetchers. 701.It Li L2_LINES_IN Xo 702.Op ,core= Ns Ar core 703.Op ,prefetch= Ns Ar prefetch 704.Xc 705.Pq Event 24H 706The number of cache lines allocated in L2 cache. 707.It Li L2_LINES_OUT Xo 708.Op ,core= Ns Ar core 709.Op ,prefetch= Ns Ar prefetch 710.Xc 711.Pq Event 26H 712The number of L2 cache lines evicted. 713.It Li L2_LOCK Xo 714.Op ,cachestate= Ns Ar state 715.Op ,core= Ns Ar core 716.Xc 717.Pq Event 2BH 718The number of locked accesses to cache lines that miss L1 data 719cache. 720.It Li L2_M_LINES_IN Op ,core= Ns Ar core 721.Pq Event 25H 722The number of L2 cache line modifications. 723.It Li L2_M_LINES_OUT Xo 724.Op ,core= Ns Ar core 725.Op ,prefetch= Ns Ar prefetch 726.Xc 727.Pq Event 27H 728The number of modified lines evicted from L2 cache. 729.It Li L2_NO_REQ Op ,core= Ns Ar core 730.Pq Event 32H 731The number of cycles during which no L2 cache requests were pending 732from a core. 733.It Li L2_REJECT_BUSQ Xo 734.Op ,cachestate= Ns Ar state 735.Op ,core= Ns Ar core 736.Op ,prefetch= Ns Ar prefetch 737.Xc 738.Pq Event 30H 739The number of L2 cache requests that were rejected. 740.It Li L2_RQSTS Xo 741.Op ,cachestate= Ns Ar state 742.Op ,core= Ns Ar core 743.Op ,prefetch= Ns Ar prefetch 744.Xc 745.Pq Event 2EH 746The number of completed L2 cache requests. 747.It Li L2_RQSTS.SELF.DEMAND.I_STATE 748.Pq Event 2EH , Umask 41H 749.Pq Alias Qq "LLC Misses" 750The number of completed L2 cache demand requests from this core that 751missed the L2 cache. 752This is an architectural performance event. 753.It Li L2_RQSTS.SELF.DEMAND.MESI 754.Pq Event 2EH , Umask 4FH 755.Pq Alias Qq "LLC References" 756The number of completed L2 cache demand requests from this core. 757.It Li L2_ST Xo 758.Op ,cachestate= Ns Ar state 759.Op ,core= Ns Ar core 760.Xc 761.Pq Event 2AH 762The number of store operations that miss the L1 cache and request data 763from the L2 cache. 764.It Li LOAD_BLOCK.L1D 765.Pq Event 03H , Umask 20H 766The number of loads blocked by the L1 data cache. 767.It Li LOAD_BLOCK.OVERLAP_STORE 768.Pq Event 03H , Umask 08H 769The number of loads that partially overlap an earlier store or are 770aliased with a previous store. 771.It Li LOAD_BLOCK.STA 772.Pq Event 03H , Umask 02H 773The number of loads blocked by preceding stores whose address is yet 774to be calculated. 775.It Li LOAD_BLOCK.STD 776.Pq Event 03H , Umask 04H 777The number of loads blocked by preceding stores to the same address 778whose data value is not known. 779.It Li LOAD_BLOCK.UNTIL_RETIRE 780.Pq Event 03H , Umask 10H 781The number of load operations that were blocked until retirement. 782.It Li LOAD_HIT_PRE 783.Pq Event 4CH , Umask 00H 784The number of load operations that conflicted with an prefetch to the 785same cache line. 786.It Li MACHINE_CLEARS.SMC 787.Pq Event C3H , Umask 01H 788The number of times a program writes to a code section. 789.It Li MACHINE_NUKES.MEM_ORDER 790.Pq Event C3H , Umask 04H 791The number of times the execution pipeline was restarted due to a 792memory ordering conflict or memory disambiguation misprediction. 793.It Li MACRO_INSTS.ALL_DECODED 794.Pq Event AAH , Umask 03H 795The number of instructions decoded. 796.It Li MACRO_INSTS.CISC_DECODED 797.Pq Event AAH , Umask 02H 798The number of complex instructions decoded. 799.It Li MEMORY_DISAMBIGUATION.RESET 800.Pq Event 09H , Umask 01H 801The number of cycles during which memory disambiguation misprediction 802occurs. 803.It Li MEMORY_DISAMBIGUATION.SUCCESS 804.Pq Event 09H , Umask 02H 805The number of load operations that were successfully disambiguated. 806.It Li MEM_LOAD_RETIRED.DTLB_MISS 807.Pq Event CBH , Umask 04H 808The number of retired load operations that missed the DTLB. 809.It Li MEM_LOAD_RETIRED.L2_MISS 810.Pq Event CBH , Umask 02H 811The number of retired load operations that miss L2 cache. 812.It Li MEM_LOAD_RETIRED.L2_HIT 813.Pq Event CBH , Umask 01H 814The number of retired load operations that hit L2 cache. 815.It Li MEM_LOAD_RETIRED.L2_LINE_MISS 816.Pq Event CBH , Umask 08H 817The number of load operations that missed L2 cache and that caused a 818bus request. 819.It Li MUL 820.Pq Event 12H , Umask 00H 821The number of multiply operations executed. 822This event is only available on PMC1. 823.It Li MUL.AR 824.Pq Event 12H , Umask 81H 825The number of multiply operations retired. 826.It Li MUL.S 827.Pq Event 12H , Umask 01H 828The number of multiply operations executed. 829.It Li PAGE_WALKS.WALKS 830.Pq Event 0CH , Umask 03H 831The number of page walks executed due to an ITLB or DTLB miss. 832.It Li PAGE_WALKS.CYCLES 833.Pq Event 0CH , Umask 03H 834.\" XXX Clarify. Identical event umask/event numbers. 835The number of cycles spent in a page walk caused by an ITLB or DTLB 836miss. 837.It Li PREF_RQSTS_DN 838.Pq Event F8H , Umask 00H 839The number of downward prefetches issued from the Data Prefetch Logic 840unit to L2 cache. 841.It Li PREF_RQSTS_UP 842.Pq Event F0H , Umask 00H 843The number of upward prefetches issued from the Data Prefetch Logic 844unit to L2 cache. 845.It Li PREFETCH.PREFETCHNTA 846.Pq Event 07H , Umask 08H 847The number of 848.Li PREFETCHNTA 849instructions executed. 850.It Li PREFETCH.PREFETCHT0 851.Pq Event 07H , Umask 01H 852The number of 853.Li PREFETCHT0 854instructions executed. 855.It Li PREFETCH.SW_L2 856.Pq Event 07H , Umask 06H 857The number of 858.Li PREFETCHT1 859and 860.Li PREFETCHT2 861instructions executed. 862.It Li RAT_STALLS.ANY 863.Pq Event D2H , Umask 0FH 864The number of stall cycles due to any of 865.Li RAT_STALLS.FLAGS 866.Li RAT_STALLS.FPSW , 867.Li RAT_STALLS.PARTIAL 868and 869.Li RAT_STALLS.ROB_READ_PORT . 870.It Li RAT_STALLS.FLAGS 871.Pq Event D2H , Umask 04H 872The number of cycles execution stalled due to a flag register induced 873stall. 874.It Li RAT_STALLS.FPSW 875.Pq Event D2H , Umask 08H 876The number of times the floating point status word was written. 877.It Li RAT_STALLS.PARTIAL_CYCLES 878.Pq Event D2H , Umask 02H 879The number of cycles of added instruction execution latency due to the 880use of a register that was partially written by previous instructions. 881.It Li RAT_STALLS.ROB_READ_PORT 882.Pq Event D2H , Umask 01H 883The number of cycles when ROB read port stalls occurred. 884.It Li RESOURCE_STALLS.ANY 885.Pq Event DCH , Umask 1FH 886The number of cycles during which any resource related stall 887occurred. 888.It Li RESOURCE_STALLS.BR_MISS_CLEAR 889.Pq Event DCH , Umask 10H 890The number of cycles stalled due to branch misprediction. 891.It Li RESOURCE_STALLS.FPCW 892.Pq Event DCH , Umask 08H 893The number of cycles stalled due to writing the floating point control 894word. 895.It Li RESOURCE_STALLS.LD_ST 896.Pq Event DCH , Umask 04H 897The number of cycles during which the number of loads and stores in 898the pipeline exceeded their limits. 899.It Li RESOURCE_STALLS.ROB_FULL 900.Pq Event DCH , Umask 01H 901The number of cycles when the reorder buffer was full. 902.It Li RESOURCE_STALLS.RS_FULL 903.Pq Event DCH , Umask 02H 904The number of cycles during which the RS was full. 905.It Li RS_UOPS_DISPATCHED 906.Pq Event A0H , Umask 00H 907The number of micro-ops dispatched for execution. 908.It Li RS_UOPS_DISPATCHED.PORT0 909.Pq Event A1H , Umask 01H 910The number of cycles micro-ops were dispatched for execution on port 9110. 912.It Li RS_UOPS_DISPATCHED.PORT1 913.Pq Event A1H , Umask 02H 914The number of cycles micro-ops were dispatched for execution on port 9151. 916.It Li RS_UOPS_DISPATCHED.PORT2 917.Pq Event A1H , Umask 04H 918The number of cycles micro-ops were dispatched for execution on port 9192. 920.It Li RS_UOPS_DISPATCHED.PORT3 921.Pq Event A1H , Umask 08H 922The number of cycles micro-ops were dispatched for execution on port 9233. 924.It Li RS_UOPS_DISPATCHED.PORT4 925.Pq Event A1H , Umask 10H 926The number of cycles micro-ops were dispatched for execution on port 9274. 928.It Li RS_UOPS_DISPATCHED.PORT5 929.Pq Event A1H , Umask 20H 930The number of cycles micro-ops were dispatched for execution on port 9315. 932.It Li SB_DRAIN_CYCLES 933.Pq Event 04H , Umask 01H 934The number of cycles while the store buffer is draining. 935.It Li SEGMENT_REG_LOADS.ANY 936.Pq Event 06H , Umask 00H 937The number of segment register loads. 938.It Li SEG_REG_RENAMES.ANY 939.Pq Event D5H , Umask 0FH 940The number of times the any segment register was renamed. 941.It Li SEG_REG_RENAMES.DS 942.Pq Event D5H , Umask 02H 943The number of times the 944.Li %ds 945register is renamed. 946.It Li SEG_REG_RENAMES.ES 947.Pq Event D5H , Umask 01H 948The number of times the 949.Li %es 950register is renamed. 951.It Li SEG_REG_RENAMES.FS 952.Pq Event D5H , Umask 04H 953The number of times the 954.Li %fs 955register is renamed. 956.It Li SEG_REG_RENAMES.GS 957.Pq Event D5H , Umask 08H 958The number of times the 959.Li %gs 960register is renamed. 961.It Li SEG_RENAME_STALLS.ANY 962.Pq Event D4H , Umask 0FH 963The number of stalls due to lack of resource to rename any segment 964register. 965.It Li SEG_RENAME_STALLS.DS 966.Pq Event D4H , Umask 02H 967The number of stalls due to lack of renaming resources for the 968.Li %ds 969register. 970.It Li SEG_RENAME_STALLS.ES 971.Pq Event D4H , Umask 01H 972The number of stalls due to lack of renaming resources for the 973.Li %es 974register. 975.It Li SEG_RENAME_STALLS.FS 976.Pq Event D4H , Umask 04H 977The number of stalls due to lack of renaming resources for the 978.Li %fs 979register. 980.It Li SEG_RENAME_STALLS.GS 981.Pq Event D4H , Umask 08H 982The number of stalls due to lack of renaming resources for the 983.Li %gs 984register. 985.It Li SIMD_ASSIST 986.Pq Event CDH , Umask 00H 987The number SIMD assists invoked. 988.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE 989.Pq Event CAH , Umask 04H 990Then number of computational SSE2 packed double precision instructions 991retired. 992.It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE 993.Pq Event CAH , Umask 01H 994Then number of computational SSE2 packed single precision instructions 995retired. 996.It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE 997.Pq Event CAH , Umask 08H 998Then number of computational SSE2 scalar double precision instructions 999retired. 1000.It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE 1001.Pq Event CAH , Umask 02H 1002Then number of computational SSE2 scalar single precision instructions 1003retired. 1004.It Li SIMD_INSTR_RETIRED 1005.Pq Event CEH , Umask 00H 1006The number of retired SIMD instructions that use MMX registers. 1007.It Li SIMD_INST_RETIRED.ANY 1008.Pq Event C7H , Umask 1FH 1009The number of streaming SIMD instructions retired. 1010.It Li SIMD_INST_RETIRED.PACKED_DOUBLE 1011.Pq Event C7H , Umask 04H 1012The number of SSE2 packed double precision instructions retired. 1013.It Li SIMD_INST_RETIRED.PACKED_SINGLE 1014.Pq Event C7H , Umask 01H 1015The number of SSE packed single precision instructions retired. 1016.It Li SIMD_INST_RETIRED.SCALAR_DOUBLE 1017.Pq Event C7H , Umask 08H 1018The number of SSE2 scalar double precision instructions retired. 1019.It Li SIMD_INST_RETIRED.SCALAR_SINGLE 1020.Pq Event C7H , Umask 02H 1021The number of SSE scalar single precision instructions retired. 1022.It Li SIMD_INST_RETIRED.VECTOR 1023.Pq Event C7H , Umask 10H 1024The number of SSE2 vector instructions retired. 1025.It Li SIMD_SAT_INSTR_RETIRED 1026.Pq Event CFH , Umask 00H 1027The number of saturated arithmetic SIMD instructions retired. 1028.It Li SIMD_SAT_UOP_EXEC.AR 1029.Pq Event B1H , Umask 80H 1030The number of SIMD saturated arithmetic micro-ops retired. 1031.It Li SIMD_SAT_UOP_EXEC.S 1032.Pq Event B1H , Umask 00H 1033The number of SIMD saturated arithmetic micro-ops executed. 1034.It Li SIMD_UOPS_EXEC.AR 1035.Pq Event B0H , Umask 80H 1036The number of SIMD micro-ops retired. 1037.It Li SIMD_UOPS_EXEC.S 1038.Pq Event B0H , Umask 00H 1039The number of SIMD micro-ops executed. 1040.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR 1041.Pq Event B3H , Umask A0H 1042The number of SIMD packed arithmetic micro-ops executed. 1043.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.S 1044.Pq Event B3H , Umask 20H 1045The number of SIMD packed arithmetic micro-ops executed. 1046.It Li SIMD_UOP_TYPE_EXEC.LOGICAL.AR 1047.Pq Event B3H , Umask 90H 1048The number of SIMD packed logical micro-ops executed. 1049.It Li SIMD_UOP_TYPE_EXEC.LOGICAL.S 1050.Pq Event B3H , Umask 10H 1051The number of SIMD packed logical micro-ops executed. 1052.It Li SIMD_UOP_TYPE_EXEC.MUL.AR 1053.Pq Event B3H , Umask 81H 1054The number of SIMD packed multiply micro-ops retired. 1055.It Li SIMD_UOP_TYPE_EXEC.MUL.S 1056.Pq Event B3H , Umask 01H 1057The number of SIMD packed multiply micro-ops executed. 1058.It Li SIMD_UOP_TYPE_EXEC.PACK.AR 1059.Pq Event B3H , Umask 84H 1060The number of SIMD pack micro-ops retired. 1061.It Li SIMD_UOP_TYPE_EXEC.PACK.S 1062.Pq Event B3H , Umask 04H 1063The number of SIMD pack micro-ops executed. 1064.It Li SIMD_UOP_TYPE_EXEC.SHIFT.AR 1065.Pq Event B3H , Umask 82H 1066The number of SIMD packed shift micro-ops retired. 1067.It Li SIMD_UOP_TYPE_EXEC.SHIFT.S 1068.Pq Event B3H , Umask 02H 1069The number of SIMD packed shift micro-ops executed. 1070.It Li SIMD_UOP_TYPE_EXEC.UNPACK.AR 1071.Pq Event B3H , Umask 88H 1072The number of SIMD unpack micro-ops executed. 1073.It Li SIMD_UOP_TYPE_EXEC.UNPACK.S 1074.Pq Event B3H , Umask 08H 1075The number of SIMD unpack micro-ops executed. 1076.It Li SNOOP_STALL_DRV Xo 1077.Op ,agent= Ns Ar agent 1078.Op ,core= Ns Ar core 1079.Xc 1080.Pq Event 7EH 1081The number of times the bus stalled for snoops. 1082This event is thread-independent. 1083.It Li SSE_PRE_EXEC.L2 1084.Pq Event 07H , Umask 02H 1085The number of 1086.Li PREFETCHT1 1087instructions executed. 1088.It Li SSE_PRE_EXEC.STORES 1089.Pq Event 07H , Umask 03H 1090The number of times SSE non-temporal store instructions were executed. 1091.It Li SSE_PRE_MISS.L1 1092.Pq Event 4BH , Umask 01H 1093The number of times the 1094.Li PREFETCHT0 1095instruction executed and missed all cache levels. 1096.It Li SSE_PRE_MISS.L2 1097.Pq Event 4BH , Umask 02H 1098The number of times the 1099.Li PREFETCHT1 1100instruction executed and missed all cache levels. 1101.It Li SSE_PRE_MISS.NTA 1102.Pq Event 4BH , Umask 00H 1103The number of times the 1104.Li PREFETCHNTA 1105instruction executed and missed all cache levels. 1106.It Li STORE_BLOCK.ORDER 1107.Pq Event 04H , Umask 02H 1108The number of cycles while a store was waiting for another store to be 1109globally observed. 1110.It Li STORE_BLOCK.SNOOP 1111.Pq Event 04H , Umask 08H 1112The number of cycles while a store was blocked due to a conflict with 1113an internal or external snoop. 1114.It Li STORE_FORWARDS.GOOD 1115.Pq Event 02H , Umask 81H 1116The number of times stored data was forwarded directly to a load. 1117.It Li THERMAL_TRIP 1118.Pq Event 3BH , Umask C0H 1119The number of thermal trips. 1120.It Li UOPS_RETIRED.LD_IND_BR 1121.Pq Event C2H , Umask 01H 1122The number of micro-ops retired that fused a load with another 1123operation. 1124.It Li UOPS_RETIRED.STD_STA 1125.Pq Event C2H , Umask 02H 1126The number of store address calculations that fused into one micro-op. 1127.It Li UOPS_RETIRED.MACRO_FUSION 1128.Pq Event C2H , Umask 04H 1129The number of times retired instruction pairs were fused into one 1130micro-op. 1131.It Li UOPS_RETIRED.FUSED 1132.Pq Event C2H , Umask 07H 1133The number of fused micro-ops retired. 1134.It Li UOPS_RETIRED.NON_FUSED 1135.Pq Event C2H , Umask 8H 1136The number of non-fused micro-ops retired. 1137.It Li UOPS_RETIRED.ANY 1138.Pq Event C2H , Umask 10H 1139The number of micro-ops retired. 1140.It Li X87_COMP_OPS_EXE.ANY.AR 1141.Pq Event 10H , Umask 81H 1142The number of x87 floating-point computational micro-ops retired. 1143.It Li X87_COMP_OPS_EXE.ANY.S 1144.Pq Event 10H , Umask 01H 1145The number of x87 floating-point computational micro-ops executed. 1146.It Li X87_OPS_RETIRED.ANY 1147.Pq Event C1H , Umask FEH 1148The number of floating point computational instructions retired. 1149.It Li X87_OPS_RETIRED.FXCH 1150.Pq Event C1H , Umask 01H 1151The number of 1152.Li FXCH 1153instructions retired. 1154.El 1155.Ss Event Name Aliases 1156The following table shows the mapping between the PMC-independent 1157aliases supported by 1158.Lb libpmc 1159and the underlying hardware events used on these CPUs. 1160.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class" 1161.It Em Alias Ta Em Event Ta Em PMC Class 1162.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP 1163.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP 1164.It Li ic-misses Ta Li ICACHE.MISSES Ta Li PMC_CLASS_IAP 1165.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF 1166.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP 1167.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF 1168.El 1169.Sh SEE ALSO 1170.Xr pmc 3 , 1171.Xr pmc.atomsilvermont 3 , 1172.Xr pmc.core 3 , 1173.Xr pmc.core2 3 , 1174.Xr pmc.iaf 3 , 1175.Xr pmc.k7 3 , 1176.Xr pmc.k8 3 , 1177.Xr pmc.soft 3 , 1178.Xr pmc.tsc 3 , 1179.Xr pmc_cpuinfo 3 , 1180.Xr pmclog 3 , 1181.Xr hwpmc 4 1182.Sh HISTORY 1183The 1184.Nm pmc 1185library first appeared in 1186.Fx 6.0 . 1187.Sh AUTHORS 1188The 1189.Lb libpmc 1190library was written by 1191.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1192