xref: /freebsd/lib/libpmc/pmc.atom.3 (revision 13014ca04aad1931d41958b56f71a2c65b9a7a2c)
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24.\" $FreeBSD$
25.\"
26.Dd September 24, 2008
27.Os
28.Dt PMC.ATOM 3
29.Sh NAME
30.Nm pmc.atom
31.Nd measurement events for
32.Tn Intel
33.Tn Atom
34family CPUs
35.Sh LIBRARY
36.Lb libpmc
37.Sh SYNOPSIS
38.In pmc.h
39.Sh DESCRIPTION
40.Tn Intel
41.Tn Atom
42CPUs contain PMCs conforming to version 3 of the
43.Tn Intel
44performance measurement architecture.
45These CPUs contains two classes of PMCs:
46.Bl -tag -width "Li PMC_CLASS_IAP"
47.It Li PMC_CLASS_IAF
48Fixed-function counters that count only one hardware event per counter.
49.It Li PMC_CLASS_IAP
50Programmable counters that may be configured to count one of a defined
51set of hardware events.
52.El
53.Pp
54The number of PMCs available in each class and their widths need to be
55determined at run time by calling
56.Xr pmc_cpuinfo 3 .
57.Pp
58Intel Atom PMCs are documented in
59.Rs
60.%B "IA-32 Intel(R) Architecture Software Developer's Manual"
61.%T "Volume 3: System Programming Guide"
62.%N "Order Number 253669-027US"
63.%D July 2008
64.%Q "Intel Corporation"
65.Re
66.Ss ATOM FIXED FUNCTION PMCS
67These PMCs and their supported events are documented in
68.Xr pmc.iaf 3 .
69.Ss ATOM PROGRAMMABLE PMCS
70The programmable PMCs support the following capabilities:
71.Bl -column "PMC_CAP_INTERRUPT" "Support"
72.It Em Capability Ta Em Support
73.It PMC_CAP_CASCADE Ta \&No
74.It PMC_CAP_EDGE Ta Yes
75.It PMC_CAP_INTERRUPT Ta Yes
76.It PMC_CAP_INVERT Ta Yes
77.It PMC_CAP_READ Ta Yes
78.It PMC_CAP_PRECISE Ta \&No
79.It PMC_CAP_SYSTEM Ta Yes
80.It PMC_CAP_TAGGING Ta \&No
81.It PMC_CAP_THRESHOLD Ta Yes
82.It PMC_CAP_USER Ta Yes
83.It PMC_CAP_WRITE Ta Yes
84.El
85.Ss Event Qualifiers
86Event specifiers for these PMCs support the following common
87qualifiers:
88.Bl -tag -width indent
89.It Li any
90Count matching events seen on any logical processor in a package.
91.It Li cmask= Ns Ar value
92Configure the PMC to increment only if the number of configured
93events measured in a cycle is greater than or equal to
94.Ar value .
95.It Li edge
96Configure the PMC to count the number of deasserted to asserted
97transitions of the conditions expressed by the other qualifiers.
98If specified, the counter will increment only once whenever a
99condition becomes true, irrespective of the number of clocks during
100which the condition remains true.
101.It Li inv
102Invert the sense of comparision when the
103.Dq Li cmask
104qualifier is present, making the counter increment when the number of
105events per cycle is less than the value specified by the
106.Dq Li cmask
107qualifier.
108.It Li os
109Configure the PMC to count events happening at processor privilege
110level 0.
111.It Li umask= Ns Ar value
112This qualifier is used to further qualify the event selected (see
113below).
114.It Li usr
115Configure the PMC to count events occurring at privilege levels 1, 2
116or 3.
117.El
118.Pp
119If neither of the
120.Dq Li os
121or
122.Dq Li usr
123qualifiers are specified, the default is to enable both.
124.Pp
125Events that require core-specificity to be specified use a
126additional qualifier
127.Dq Li core= Ns Ar core ,
128where argument
129.Ar core
130is one of:
131.Bl -tag -width indent
132.It Li all
133Measure event conditions on all cores.
134.It Li this
135Measure event conditions on this core.
136.El
137.Pp
138The default is
139.Dq Li this .
140.Pp
141Events that require an agent qualifier to be specified use an
142additional qualifier
143.Dq Li agent= Ns agent ,
144where argument
145.Ar agent
146is one of:
147.Bl -tag -width indent
148.It Li this
149Measure events associated with this bus agent.
150.It Li any
151Measure events caused by any bus agent.
152.El
153.Pp
154The default is
155.Dq Li this .
156.Pp
157Events that require a hardware prefetch qualifier to be specified use an
158additional qualifier
159.Dq Li prefetch= Ns Ar prefetch ,
160where argument
161.Ar prefetch
162is one of:
163.Bl -tag -width "exclude"
164.It Li both
165Include all prefetches.
166.It Li only
167Only count hardware prefetches.
168.It Li exclude
169Exclude hardware prefetches.
170.El
171.Pp
172The default is
173.Dq Li both .
174.Pp
175Events that require a cache coherence qualifier to be specified use an
176additional qualifer
177.Dq Li cachestate= Ns Ar state ,
178where argument
179.Ar state
180contains one or more of the following letters:
181.Bl -tag -width indent
182.It Li e
183Count cache lines in the exclusive state.
184.It Li i
185Count cache lines in the invalid state.
186.It Li m
187Count cache lines in the modified state.
188.It Li s
189Count cache lines in the shared state.
190.El
191.Pp
192The default is
193.Dq Li eims .
194.Pp
195Events that require a snoop response qualifier to be specified use an
196additional qualifier
197.Dq Li snoopresponse= Ns Ar response ,
198where argument
199.Ar response
200comprises of the following keywords separated by
201.Dq +
202signs:
203.Bl -tag -width indent
204.It Li clean
205Measure CLEAN responses.
206.It Li hit
207Measure HIT responses.
208.It Li hitm
209Measure HITM responses.
210.El
211.Pp
212The default is to measure all the above responses.
213.Pp
214Events that require a snoop type qualifier use an additional qualifier
215.Dq Li snooptype= Ns Ar type ,
216where argument
217.Ar type
218comprises the one of the following keywords:
219.Bl -tag -width indent
220.It Li cmp2i
221Measure CMP2I snoops.
222.It Li cmp2s
223Measure CMP2S snoops.
224.El
225.Pp
226The default is to measure both snoops.
227.Ss Event Specifiers (Programmable PMCs)
228Core2 programmable PMCs support the following events:
229.Bl -tag -width indent
230.It Li BACLEARS
231.Pq Event E6H , Umask 01H
232The number of times the front end is resteered.
233.It Li BOGUS_BR
234.Pq Event E4H
235The number of byte sequences mistakenly detected as taken branch
236instructions.
237.It Li BR_BAC_MISSP_EXEC
238.Pq Event 8AH
239The number of branch instructions that were mispredicted when
240decoded.
241.It Li BR_CALL_MISSP_EXEC
242.Pq Event 93H
243The number of mispredicted
244.Li CALL
245instructions that were executed.
246.It Li BR_CALL_EXEC
247.Pq Event 92H
248The number of
249.Li CALL
250instructions executed.
251.It Li BR_CND_EXEC
252.Pq Event 8BH
253The number of conditional branches executed, but not necessarily retired.
254.It Li BR_CND_MISSP_EXEC
255.Pq Event 8CH
256The number of mispredicted conditional branches executed.
257.It Li BR_IND_CALL_EXEC
258.Pq Event 94H
259The number of indirect
260.Li CALL
261instructions executed.
262.It Li BR_IND_EXEC
263.Pq Event 8DH
264The number of indirect branch instructions executed.
265.It Li BR_IND_MISSP_EXEC
266.Pq Event 8EH
267The number of mispredicted indirect branch instructions executed.
268.It Li BR_INST_DECODED
269.Pq Event E0H , Umask 01H
270The number of branch instructions decoded.
271.It Li BR_INST_EXEC
272.Pq Event 88H
273The number of branches executed, but not necessarily retired.
274.It Li BR_INST_RETIRED.ANY
275.Pq Event C4H , Umask 00H
276The number of branch instructions retired.
277.It Li BR_INST_RETIRED.ANY1
278.Pq Event C4H , Umask 0FH
279The number of branch instructions retired that were mispredicted.
280.It Li BR_INST_RETIRED.MISPRED
281.Pq Event C5, Umask 00H
282The number of mispredicted branch instructions retired.
283.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN
284.Pq Event C4H , Umask 02H
285The number of not taken branch instructions retired that were
286mispredicted.
287.It Li BR_INST_RETIRED.MISPRED_TAKEN
288.Pq Event C4H , Umask 08H
289The number taken branch instructions retired that were mispredicted.
290.It Li BR_INST_RETIRED.PRED_NOT_TAKEN
291.Pq Event C4H , Umask 01H
292The number of not taken branch instructions retired that were
293correctly predicted.
294.It Li BR_INST_RETIRED.PRED_TAKEN
295.Pq Event C4H , Umask 04H
296The number of taken branch instructions retired that were correctly
297predicted.
298.It Li BR_INST_RETIRED.TAKEN
299.Pq Event C4H , Umask 0CH
300The number of taken branch instructions retired.
301.It Li BR_MISSP_EXEC
302.Pq Event 89H
303The number of mispredicted branch instructions that were executed.
304.It Li BR_RET_MISSP_EXEC
305.Pq Event 90H
306The number of mispredicted
307.Li RET
308instructions executed.
309.It Li BR_RET_BAC_MISSP_EXEC
310.Pq Event 91H
311The number of
312.Li RET
313instructions executed that were mispredicted at decode time.
314.It Li BR_RET_EXEC
315.Pq Event 8FH
316The number of
317.Li RET
318instructions executed.
319.It Li BR_TKN_BUBBLE_1
320.Pq Event 97H
321The number of branch predicted taken with bubble 1.
322.It Li BR_TKN_BUBBLE_2
323.Pq Event 98H
324The number of branch predicted taken with bubble 2.
325.It Li BUSQ_EMPTY Op ,core= Ns Ar core
326.Pq Event 7DH
327The number of cycles during which the core did not have any pending
328transactions in the bus queue.
329.It Li BUS_BNR_DRV Op ,agent= Ns Ar agent
330.Pq Event 61H
331The number of Bus Not Ready signals asserted on the bus.
332This event is thread-independent.
333.It Li BUS_DATA_RCV Op ,core= Ns Ar core
334.Pq Event 64H
335The number of bus cycles during which the processor is receiving data.
336This event is thread-independent.
337.It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent
338.Pq Event 62H
339The number of bus cycles during which the Data Ready signal is asserted
340on the bus.
341This event is thread-independent.
342.It Li BUS_HIT_DRV Op ,agent= Ns Ar agent
343.Pq Event 7AH
344The number of bus cycles during which the processor drives the
345.Li HIT#
346pin.
347This event is thread-independent.
348.It Li BUS_HITM_DRV Op ,agent= Ns Ar agent
349.Pq Event 7BH
350The number of bus cycles during which the processor drives the
351.Li HITM#
352pin.
353This event is thread-independent.
354.It Li BUS_IO_WAIT Op ,core= Ns Ar core
355.Pq Event 7FH
356The number of core cycles during which I/O requests wait in the bus
357queue.
358.It Li BUS_LOCK_CLOCKS Xo
359.Op ,agent= Ns Ar agent
360.Op ,core= Ns Ar core
361.Xc
362.Pq Event 63H
363The number of bus cycles during which the
364.Li LOCK
365signal was asserted on the bus.
366This event is thread independent.
367.It Li BUS_REQUEST_OUTSTANDING Xo
368.Op ,agent= Ns Ar agent
369.Op ,core= Ns Ar core
370.Xc
371.Pq Event 60H
372The number of pending full cache line read transactions on the bus
373occuring in each cycle.
374This event is thread independent.
375.It Li BUS_TRANS_P Xo
376.Op ,agent= Ns Ar agent
377.Op ,core= Ns Ar core
378.Xc
379.Pq Event 6BH
380The number of partial bus transactions.
381.It Li BUS_TRANS_IFETCH Xo
382.Op ,agent= Ns Ar agent
383.Op ,core= Ns Ar core
384.Xc
385.Pq Event 68H
386The number of instruction fetch full cache line bus transactions.
387.It Li BUS_TRANS_INVAL Xo
388.Op ,agent= Ns Ar agent
389.Op ,core= Ns Ar core
390.Xc
391.Pq Event 69H
392The number of invalidate bus transactions.
393.It Li BUS_TRANS_PWR Xo
394.Op ,agent= Ns Ar agent
395.Op ,core= Ns Ar core
396.Xc
397.Pq Event 6AH
398The number of partial write bus transactions.
399.It Li BUS_TRANS_DEF Xo
400.Op ,agent= Ns Ar agent
401.Op ,core= Ns Ar core
402.Xc
403.Pq Event 6DH
404The number of deferred bus transactions.
405.It Li BUS_TRANS_BURST Xo
406.Op ,agent= Ns Ar agent
407.Op ,core= Ns Ar core
408.Xc
409.Pq Event 6EH
410The number of burst transactions.
411.It Li BUS_TRANS_MEM Xo
412.Op ,agent= Ns Ar agent
413.Op ,core= Ns Ar core
414.Xc
415.Pq Event 6FH
416The number of memory bus transactions.
417.It Li BUS_TRANS_ANY Xo
418.Op ,agent= Ns Ar agent
419.Op ,core= Ns Ar core
420.Xc
421.Pq Event 70H
422The number of bus transactions of any kind.
423.It Li BUS_TRANS_BRD Xo
424.Op ,agent= Ns Ar agent
425.Op ,core= Ns Ar core
426.Xc
427.Pq Event 65H
428The number of burst read transactions.
429.It Li BUS_TRANS_IO Xo
430.Op ,agent= Ns Ar agent
431.Op ,core= Ns Ar core
432.Xc
433.Pq Event 6CH
434The number of completed I/O bus transaactions due to
435.Li IN
436and
437.Li OUT
438instructions.
439.It Li BUS_TRANS_RFO Xo
440.Op ,agent= Ns Ar agent
441.Op ,core= Ns Ar core
442.Xc
443.Pq Event 66H
444The number of Read For Ownership bus transactions.
445.It Li BUS_TRANS_WB Xo
446.Op ,agent= Ns Ar agent
447.Op ,core= Ns Ar core
448.Xc
449.Pq Event 67H
450The number explicit writeback bus transactions due to dirty line
451evictions.
452.It Li CMP_SNOOP Xo
453.Op ,core= Ns Ar core
454.Op ,snooptype= Ns Ar snoop
455.Xc
456.Pq Event 78H
457The number of times the L1 data cache is snooped by the other core in
458the same processor.
459.It Li CPU_CLK_UNHALTED.BUS
460.Pq Event 3CH , Umask 01H
461The number of bus cycles when the core is not in the halt state.
462.It Li CPU_CLK_UNHALTED.CORE_P
463.Pq Event 3CH , Umask 00H
464The number of core cycles while the core is not in a halt state.
465.It Li CPU_CLK_UNHALTED.NO_OTHER
466.Pq Event 3CH , Umask 02H
467The number of bus cycles during which the core remains unhalted and
468the other core is halted.
469.It Li CYCLES_DIV_BUSY
470.Pq Event 14H , Umask 01H
471The number of cycles the divider is busy.
472.It Li CYCLES_INT_MASKED.CYCLES_INT_MASKED
473.Pq Event C6H , Umask 01H
474The number of cycles during which interrupts are disabled.
475.It Li CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED
476.Pq Event C6H , Umask 02H
477The number of cycles during which there were pending interrupts while
478interrupts were disabled.
479.It Li CYCLES_L1I_MEM_STALLED
480.Pq Event 86H
481The number of cycles for which an instruction fetch stalls.
482.It Li DATA_TLB_MISSES.DTLB_MISS
483.Pq Event 08H , Umask 07H
484The number of memory access that missed the Data TLB
485.It Li DATA_TLB_MISSES.DTLB_MISS_LD
486.Pq Event 08H , Umask 05H
487The number of loads that missed the Data TLB.
488.It Li DATA_TLB_MISSES.DTLB_MISS_ST
489.Pq Event 08H , Umask 06H
490The number of stores that missed the Data TLB.
491.It Li DATA_TLB_MISSES.UTLB_MISS_LD
492.Pq Event 08H , Umask 09H
493The number of loads that missed the UTLB.
494.It Li DELAYED_BYPASS.FP
495.Pq Event 19H , Umask 00H
496The number of floating point operations that used data immediately
497after the data was generated by a non floating point execution unit.
498.It Li DELAYED_BYPASS.LOAD
499.Pq Event 19H , Umask 01H
500The number of delayed bypass penalty cycles that a load operation incurred.
501.It Li DELAYED_BYPASS.SIMD
502.Pq Event 19H , Umask 02H
503The number of times SIMD operations use data immediately after data,
504was generated by a non-SIMD execution unit.
505.It Li DIV
506.Pq Event 13H , Umask 00H
507The number of divide operations executed.
508This event is only available on PMC1.
509.It Li DIV.AR
510.Pq Event 13H , Umask 81H
511The number of divide operations retired.
512.It Li DIV.S
513.Pq Event 13H , Umask 01H
514The number of divide operations executed.
515.It Li DTLB_MISSES.ANY
516.Pq Event 08H , Umask 01H
517The number of Data TLB misses, including misses that result from
518speculative accesses.
519.It Li DTLB_MISSES.L0_MISS_LD
520.Pq Event 08H , Umask 04H
521The number of level 0 DTLB misses due to load operations.
522.It Li DTLB_MISSES.MISS_LD
523.Pq Event 08H , Umask 02H
524The number of Data TLB misses due to load operations.
525.It Li DTLB_MISSES.MISS_ST
526.Pq Event 08H , Umask 08H
527The number of Data TLB misses due to store operations.
528.It Li EIST_TRANS
529.Pq Event 3AH
530The number of Enhanced Intel SpeedStep Technology transitions.
531.It Li ESP.ADDITIONS
532.Pq Event ABH , Umask 02H
533The number of automatic additions to the
534.Li %esp
535register.
536.It Li ESP.SYNCH
537.Pq Event ABH , Umask 01H
538The number of times the
539.Li %esp
540register was explicitly used in an address expression after
541it is implicitly used by a
542.Li PUSH
543or
544.Li POP
545instruction.
546.It Li EXT_SNOOP Xo
547.Op ,agent= Ns Ar agent
548.Op ,snoopresponse= Ns Ar response
549.Xc
550.Pq Event 77H
551The number of snoop responses to bus transactions.
552.It Li FP_ASSIST
553.Pq Event 11H , Umask 01H
554The number of floating point operations executed that needed
555a microcode assist.
556.It Li FP_ASSIST
557.Pq Event 11H , Umask 01H
558The number of floating point operations executed that needed
559a microcode assist.
560.It Li FP_ASSIST.AR
561.Pq Event 11H , Umask 01H
562.\" XXX to be confirmed
563The number of floating point operations retired that needed
564a microcode assist.
565.It Li FP_COMP_OPS_EXE
566.Pq Event 10H , Umask 00H
567The number of floating point computational micro-ops executed.
568The event is available only on PMC0.
569.It Li FP_MMX_TRANS_TO_FP
570.Pq Event CCH , Umask 02H
571The number of transitions from MMX instructions to floating point
572instructions.
573.It Li FP_MMX_TRANS_TO_MMX
574.Pq Event CCH , Umask 01H
575The number of transitions from floating point instructions to MMX
576instructions.
577.It Li HW_INT_RCV
578.Pq Event C8H
579The number of hardware interrupts recieved.
580.It Li ICACHE.ACCESSES
581.Pq Event 80H , Umask 03H
582The number of instruction fetches.
583.It Li ICACHE.MISSES
584.Pq Event 80H , Umask 02H
585The number of instruction fetches that miss the instruction cache.
586.It Li IDLE_DURING_DIV
587.Pq Event 18H
588The number of cycles the divider is busy and no other execution unit
589or load operation was in progress.
590This event is available only on PMC0.
591.It Li ILD_STALL
592.Pq Event 87H
593The number of cycles the instruction length decoder stalled due to a
594length changing prefix.
595.It Li INST_QUEUE.FULL
596.Pq Event 83H
597The number of cycles during which the instruction queue is full.
598.It Li INST_RETIRED.ANY_P
599.Pq Event C0H , Umask 00H
600The number of instructions retired.
601.It Li INST_RETIRED.LOADS
602.Pq Event C0H , Umask 01H
603The number of instructions retired that contained a load operation.
604.It Li INST_RETIRED.OTHER
605.Pq Event C0H
606The number of instructions retired that did not contain a load or a
607store operation.
608.It Li INST_RETIRED.STORES
609.Pq Event C0H
610The number of instructions retired that contained a store operation.
611.It Li ITLB.FLUSH
612.Pq Event 82H , Umask 04H
613The number of ITLB flushes.
614.It Li ITLB.LARGE_MISS
615.Pq Event 82H , Umask 10H
616The number of instruction fetches from large pages that miss the
617ITLB.
618.It Li ITLB.MISSES
619.Pq Event 82H , Umask 02H
620The number of instruction fetches from both large and small pages that
621miss the ITLB.
622.It Li ITLB.SMALL_MISS
623.Pq Event 82H , Umask 02H
624The number of instruction fetches from small pages that miss the ITLB.
625.It Li ITLB_MISS_RETIRED
626.Pq Event C9H
627The number of retired instructions that missed the ITLB when they were
628fetched.
629.It Li L1D_ALL_REF
630.Pq Event 43H , Umask 01H
631The number of references to L1 data cache counting loads and stores of
632to all memory types.
633.It Li L1D_ALL_CACHE_REF
634.Pq Event 43H , Umask 02H
635The number of data reads and writes to cacheable memory.
636.It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state
637.Pq Event 42H
638The number of locked reads from cacheable memory.
639.It Li L1D_CACHE_LOCK_DURATION
640.Pq Event 42H
641The number of cycles during which any cache line is locked by any
642locking instruction.
643.It Li L1D_CACHE.LD
644.Pq Event 40H , Umask 21H
645The number of data reads from cacheable memory.
646.It Li L1D_CACHE.ST
647.Pq Event 41H , Umask 22H
648The number of data writes to cacheable memory.
649.It Li L1D_M_EVICT
650.Pq Event 47H
651The number of modified cache lines evicted from L1 data cache.
652.It Li L1D_M_REPL
653.Pq Event 46H
654The number of modified lines allocated in L1 data cache.
655.It Li L1D_PEND_MISS
656.Pq Event 48H
657The total number of outstanding L1 data cache misses at any clock.
658.It Li L1D_PREFETCH.
659.Pq Event 4EH
660The number of times L1 data cache requested to prefetch a data cache
661line.
662.It Li L1D_REPL
663.Pq Event 45H
664The number of lines brought into L1 data cache.
665.It Li L1D_SPLIT.LOADS
666.Pq Event 49H , Umask 01H
667The number of load operations that span two cache lines.
668.It Li L1D_SPLIT.STORES
669.Pq Event 49H , Umask 02H
670The number of store operations that span two cache lines.
671.It Li L1I_MISSES
672.Pq Event 81H
673The number of instruction fetch unit misses.
674.It Li L1I_READS
675.Pq Event 80H
676The number of instruction fetches.
677.It Li L2_ADS Op ,core= Ns core
678.Pq Event 21H
679The number of cycles that the L2 address bus is in use.
680.It Li L2_DBUS_BUSY_RD Op ,core= Ns core
681.Pq Event 23H
682The number of core cycles during which the L2 data bus is busy
683transferring data to the core.
684.It Li L2_IFETCH Xo
685.Op ,cachestate= Ns Ar state
686.Op ,core= Ns Ar core
687.Xc
688.Pq Event 28H
689The number of instruction cache line requests from the instruction
690fetch unit.
691.It Li L2_LD Xo
692.Op ,cachestate= Ns Ar state
693.Op ,core= Ns Ar core
694.Op ,prefech= Ns Ar prefetch
695.Xc
696.Pq Event 29H
697The number of L2 cache read requests from L1 cache and L2
698prefetchers.
699.It Li L2_LINES_IN Xo
700.Op ,core= Ns Ar core
701.Op ,prefetch= Ns Ar prefetch
702.Xc
703.Pq Event 24H
704The number of cache lines allocated in L2 cache.
705.It Li L2_LINES_OUT Xo
706.Op ,core= Ns Ar core
707.Op ,prefetch= Ns Ar prefetch
708.Xc
709.Pq Event 26H
710The number of L2 cache lines evicted.
711.It Li L2_LOCK Xo
712.Op ,cachestate= Ns Ar state
713.Op ,core= Ns Ar core
714.Xc
715.Pq Event 2BH
716The number of locked accesses to cache lines that miss L1 data
717cache.
718.It Li L2_M_LINES_IN Op ,core= Ns Ar core
719.Pq Event 25H
720The number of L2 cache line modifications.
721.It Li L2_M_LINES_OUT Xo
722.Op ,core= Ns Ar core
723.Op ,prefetch= Ns Ar prefetch
724.Xc
725.Pq Event 27H
726The number of modified lines evicted from L2 cache.
727.It Li L2_NO_REQ Op ,core= Ns Ar core
728.Pq Event 32H
729The number of cycles during which no L2 cache requests were pending
730from a core.
731.It Li L2_REJECT_BUSQ Xo
732.Op ,cachestate= Ns Ar state
733.Op ,core= Ns Ar core
734.Op ,prefetch= Ns Ar prefetch
735.Xc
736.Pq Event 30H
737The number of L2 cache requests that were rejected.
738.It Li L2_RQSTS Xo
739.Op ,cachestate= Ns Ar state
740.Op ,core= Ns Ar core
741.Op ,prefetch= Ns Ar prefetch
742.Xc
743.Pq Event 2EH
744The number of completed L2 cache requests.
745.It Li L2_RQSTS.SELF.DEMAND.I_STATE
746.Pq Event 2EH , Umask 41H
747The number of completed L2 cache demand requests from this core that
748missed the L2 cache.
749.It Li L2_RQSTS.SELF.DEMAND.MESI
750.Pq Event 2EH , Umask 4FH
751The number of completed L2 cache demand requests from this core.
752.It Li L2_ST Xo
753.Op ,cachestate= Ns Ar state
754.Op ,core= Ns Ar core
755.Xc
756.Pq Event 2AH
757The number of store operations that miss the L1 cache and request data
758from the L2 cache.
759.It Li LOAD_BLOCK.L1D
760.Pq Event 03H , Umask 20H
761The number of loads blocked by the L1 data cache.
762.It Li LOAD_BLOCK.OVERLAP_STORE
763.Pq Event 03H , Umask 08H
764The number of loads that partially overlap an earlier store or are
765aliased with a previous store.
766.It Li LOAD_BLOCK.STA
767.Pq Event 03H , Umask 02H
768The number of loads blocked by preceding stores whose address is yet
769to be calculated.
770.It Li LOAD_BLOCK.STD
771.Pq Event 03H , Umask 04H
772The number of loads blocked by preceding stores to the same address
773whose data value is not known.
774.It Li LOAD_BLOCK.UNTIL_RETIRE
775.Pq Event 03H , Umask 10H
776The numer of load operations that were blocked until retirement.
777.It Li LOAD_HIT_PRE
778.Pq Event 4CH
779The number of load operations that conflicted with an prefetch to the
780same cache line.
781.It Li MACHINE_CLEARS.SMC
782.Pq Event C3H , Umask 01H
783The number of times a program writes to a code section.
784.It Li MACHINE_NUKES.MEM_ORDER
785.Pq Event C3H , Umask 04H
786The number of times the execution pipeline was restarted due to a
787memory ordering conflict or memory disambiguation misprediction.
788.It Li MACRO_INSTS.ALL_DECODED
789.Pq Event AAH , Umask 03H
790The number of instructions decoded.
791.It Li MACRO_INSTS.CISC_DECODED
792.Pq Event AAH , Umask 02H
793The number of complex instructions decoded.
794.It Li MEMORY_DISAMBIGUATION.RESET
795.Pq Event 09H , Umask 01H
796The number of cycles during which memory disambiguation misprediction
797occurs.
798.It Li MEMORY_DISAMBIGUATION.SUCCESS
799.Pq Event 09H , Umask 02H
800The number of load operations that were successfully disambiguated.
801.It Li MEM_LOAD_RETIRED.DTLB_MISS
802.Pq Event CBH , Umask 10H
803The number of retired loads that missed the DTLB.
804.It Li MEM_LOAD_RETIRED.L2_MISS
805.Pq Event CBH , Umask 02H
806The number of retired load operations that miss L2 cache.
807.It Li MEM_LOAD_RETIRED.L2_HIT
808.Pq Event CBH , Umask 01H
809The number of retired load operations that hit L2 cache.
810.It Li MEM_LOAD_RETIRED.L2_LINE_MISS
811.Pq Event CBH , Umask 08H
812The number of load operations that missed L2 cache and that caused a
813bus request.
814.It Li MEM_LOAD_RETIRED.DTLB_MISS
815.Pq Event CBH , Umask 04H
816The number of load operations that missed the DTLB.
817.It Li MUL
818.Pq Event 12H , Umask 00H
819The number of multiply operations executed.
820This event is only available on PMC1.
821.It Li MUL.AR
822.Pq Event 12H , Umask 81H
823The number of multiply operations retired.
824.It Li MUL.S
825.Pq Event 12H , Umask 01H
826The number of multiply operations executed.
827.It Li PAGE_WALKS.WALKS
828.Pq Event 0CH , Umask 03H
829The number of page walks executed due to an ITLB or DTLB miss.
830.It Li PAGE_WALKS.CYCLES
831.Pq Event 0CH , Umask 03H
832.\" XXX Clarify.  Identical event umask/event numbers.
833The number of cycles spent in a page walk caused by an ITLB or DTLB
834miss.
835.It Li PREF_RQSTS_DN
836.Pq Event F8H
837The number of downward prefetches issued from the Data Prefetch Logic
838unit to L2 cache.
839.It Li PREF_RQSTS_UP
840.Pq Event F0H
841The number of upward prefetches issued from the Data Prefetch Logic
842unit to L2 cache.
843.It Li PREFETCH.PREFETCHNTA
844.Pq Event 07H , Umask 08H
845The number of
846.Li PREFETCHNTA
847instructions executed.
848.It Li PREFETCH.PREFETCHT0
849.Pq Event 07H , Umask 01H
850The number of
851.Li PREFETCHT0
852instructions executed.
853.It Li PREFETCH.SW_L2
854.Pq Event 07H , Umask 06H
855The number of
856.Li PREFETCHT1
857and
858.Li PREFETCHT2
859instructions executed.
860.It Li RAT_STALLS.ANY
861.Pq Event D2H , Umask 0FH
862The number of stall cycles due to any of
863.Li RAT_STALLS.FLAGS
864.Li RAT_STALLS.FPSW ,
865.Li RAT_STALLS.PARTIAL
866and
867.Li RAT_STALLS.ROB_READ_PORT .
868.It Li RAT_STALLS.FLAGS
869.Pq Event D2H , Umask 04H
870The number of cycles execution stalled due to a flag register induced
871stall.
872.It Li RAT_STALLS.FPSW
873.Pq Event D2H , Umask 08H
874The number of times the floating point status word was written.
875.It Li RAT_STALLS.PARTIAL_CYCLES
876.Pq Event D2H , Umask 02H
877The number of cycles of added instruction execution latency due to the
878use of a register that was partially written by previous instructions.
879.It Li RAT_STALLS.ROB_READ_PORT
880.Pq Event D2H , Umask 01H
881The number of cycles when ROB read port stalls occurred.
882.It Li RESOURCE_STALLS.ANY
883.Pq Event DCH , Umask 1FH
884The number of cycles during which any resource related stall
885occurred.
886.It Li RESOURCE_STALLS.BR_MISS_CLEAR
887.Pq Event DCH , Umask 10H
888The number of cycles stalled due to branch misprediction.
889.It Li RESOURCE_STALLS.FPCW
890.Pq Event DCH , Umask 08H
891The number of cycles stalled due to writing the floating point control
892word.
893.It Li RESOURCE_STALLS.LD_ST
894.Pq Event DCH , Umask 04H
895The number of cycles during which the number of loads and stores in
896the pipeline exceeded their limits.
897.It Li RESOURCE_STALLS.ROB_FULL
898.Pq Event DCH , Umask 01H
899The number of cycles when the reorder buffer was full.
900.It Li RESOURCE_STALLS.RS_FULL
901.Pq Event DCH , Umask 02H
902The number of cycles during which the RS was full.
903.It Li RS_UOPS_DISPATCHED
904.Pq Event A0H , Umask 00H
905The number of micro-ops dispatched for execution.
906.It Li RS_UOPS_DISPATCHED.PORT0
907.Pq Event A1H , Umask 01H
908The number of cycles micro-ops were dispatched for execution on port
9090.
910.It Li RS_UOPS_DISPATCHED.PORT1
911.Pq Event A1H , Umask 02H
912The number of cycles micro-ops were dispatched for execution on port
9131.
914.It Li RS_UOPS_DISPATCHED.PORT2
915.Pq Event A1H , Umask 04H
916The number of cycles micro-ops were dispatched for execution on port
9172.
918.It Li RS_UOPS_DISPATCHED.PORT3
919.Pq Event A1H , Umask 08H
920The number of cycles micro-ops were dispatched for execution on port
9213.
922.It Li RS_UOPS_DISPATCHED.PORT4
923.Pq Event A1H , Umask 10H
924The number of cycles micro-ops were dispatched for execution on port
9254.
926.It Li RS_UOPS_DISPATCHED.PORT5
927.Pq Event A1H , Umask 20
928The number of cycles micro-ops were dispatched for execution on port
9295.
930.It Li SB_DRAIN_CYCLES
931.Pq Event 04H , Umask 01H
932The number of cycles while the store buffer is draining.
933.It Li SEGMENT_REG_LOADS.ANY
934.Pq Event 06H
935The number of segment register loads.
936.It Li SEG_REG_RENAMES.ANY
937.Pq Event D5H , Umask 0FH
938The number of times the any segment register was renamed.
939.It Li SEG_REG_RENAMES.DS
940.Pq Event D5H , Umask 02H
941The number of times the
942.Li %ds
943register is renamed.
944.It Li SEG_REG_RENAMES.ES
945.Pq Event D5H , Umask 01H
946The number of times the
947.Li %es
948register is renamed.
949.It Li SEG_REG_RENAMES.FS
950.Pq Event D5H , Umask 04H
951The number of times the
952.Li %fs
953register is renamed.
954.It Li SEG_REG_RENAMES.GS
955.Pq Event D5H , Umask 08H
956The number of times the
957.Li %gs
958register is renamed.
959.It Li SEG_RENAME_STALLS.ANY
960.Pq Event D4H , Umask 0FH
961The number of stalls due to lack of resource to rename any segment
962register.
963.It Li SEG_RENAME_STALLS.DS
964.Pq Event D4H , Umask 02H
965The number of stalls due to lack of renaming resources for the
966.Li %ds
967register.
968.It Li SEG_RENAME_STALLS.ES
969.Pq Event D4H , Umask 01H
970The number of stalls due to lack of renaming resources for the
971.Li %es
972register.
973.It Li SEG_RENAME_STALLS.FS
974.Pq Event D4H , Umask 04H
975The number of stalls due to lack of renaming resources for the
976.Li %fs
977register.
978.It Li SEG_RENAME_STALLS.GS
979.Pq Event D4H , Umask 08H
980The number of stalls due to lack of renaming resources for the
981.Li %gs
982register.
983.It Li SIMD_ASSIST
984.Pq Event CDH
985The number SIMD assists invoked.
986.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
987.Pq Event CAH , Umask 04H
988Then number of computational SSE2 packed double precision instructions
989retired.
990.It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE
991.Pq Event CAH , Umask 01H
992Then number of computational SSE2 packed single precision instructions
993retired.
994.It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE
995.Pq Event CAH , Umask 08H
996Then number of computational SSE2 scalar double precision instructions
997retired.
998.It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE
999.Pq Event CAH , Umask 02H
1000Then number of computational SSE2 scalar single precision instructions
1001retired.
1002.It Li SIMD_INSTR_RETIRED
1003.Pq Event CEH
1004The number of retired SIMD instructions that use MMX registers.
1005.It Li SIMD_INST_RETIRED.ANY
1006.Pq Event C7H , Umask 1FH
1007The number of streaming SIMD instructions retired.
1008.It Li SIMD_INST_RETIRED.PACKED_DOUBLE
1009.Pq Event C7H , Umask 04H
1010The number of SSE2 packed double precision instructions retired.
1011.It Li SIMD_INST_RETIRED.PACKED_SINGLE
1012.Pq Event C7H , Umask 01H
1013The number of SSE packed single precision instructions retired.
1014.It Li SIMD_INST_RETIRED.SCALAR_DOUBLE
1015.Pq Event C7H , Umask 08H
1016The number of SSE2 scalar double precision instructions retired.
1017.It Li SIMD_INST_RETIRED.SCALAR_SINGLE
1018.Pq Event C7H , Umask 02H
1019The number of SSE scalar single precision instructions retired.
1020.It Li SIMD_INST_RETIRED.VECTOR
1021.Pq Event C7H , Umask 10H
1022The number of SSE2 vector instructions retired.
1023.It Li SIMD_SAT_INSTR_RETIRED
1024.Pq Event CFH
1025The number of saturated arithmetic SIMD instructions retired.
1026.It Li SIMD_SAT_UOP_EXEC.AR
1027.Pq Event B1H , Umask 80H
1028The number of SIMD saturated arithmetic micro-ops retired.
1029.It Li SIMD_SAT_UOP_EXEC.S
1030.Pq Event B1H , Umask 00H
1031The number of SIMD saturated arithmetic micro-ops executed.
1032.It Li SIMD_UOPS_EXEC.AR
1033.Pq Event B0H , Umask 80H
1034The number of SIMD micro-ops retired.
1035.It Li SIMD_UOPS_EXEC.S
1036.Pq Event B0H , Umask 00H
1037The number of SIMD micro-ops executed.
1038.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR
1039.Pq Event B3H , Umask A0H
1040The number of SIMD packed arithmetic micro-ops executed.
1041.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.S
1042.Pq Event B3H , Umask 20H
1043The number of SIMD packed arithmetic micro-ops executed.
1044.It Li SIMD_UOP_TYPE_EXEC.LOGICAL.AR
1045.Pq Event B3H , Umask 90H
1046The number of SIMD packed logical micro-ops executed.
1047.It Li SIMD_UOP_TYPE_EXEC.LOGICAL.S
1048.Pq Event B3H , Umask 10H
1049The number of SIMD packed logical micro-ops executed.
1050.It Li SIMD_UOP_TYPE_EXEC.MUL.AR
1051.Pq Event B3H , Umask 81H
1052The number of SIMD packed multiply micro-ops retired.
1053.It Li SIMD_UOP_TYPE_EXEC.MUL.S
1054.Pq Event B3H , Umask 01H
1055The number of SIMD packed multiply micro-ops executed.
1056.It Li SIMD_UOP_TYPE_EXEC.PACK.AR
1057.Pq Event B3H , Umask 84H
1058The number of SIMD pack micro-ops retired.
1059.It Li SIMD_UOP_TYPE_EXEC.PACK.S
1060.Pq Event B3H , Umask 04H
1061The number of SIMD pack micro-ops executed.
1062.It Li SIMD_UOP_TYPE_EXEC.SHIFT.AR
1063.Pq Event B3H , Umask 82H
1064The number of SIMD packed shift micro-ops retired.
1065.It Li SIMD_UOP_TYPE_EXEC.SHIFT.S
1066.Pq Event B3H , Umask 02H
1067The number of SIMD packed shift micro-ops executed.
1068.It Li SIMD_UOP_TYPE_EXEC.UNPACK.AR
1069.Pq Event B3H , Umask 88H
1070The number of SIMD unpack micro-ops executed.
1071.It Li SIMD_UOP_TYPE_EXEC.UNPACK.S
1072.Pq Event B3H , Umask 08H
1073The number of SIMD unpack micro-ops executed.
1074.It Li SNOOP_STALL_DRV Xo
1075.Op ,agent= Ns Ar agent
1076.Op ,core= Ns Ar core
1077.Xc
1078.Pq Event 7EH
1079The number of times the bus stalled for snoops.
1080This event is thread-independent.
1081.It Li SSE_PRE_EXEC.L2
1082.Pq Event 07H , Umask 02H
1083The number of
1084.Li PREFETCHT1
1085instructions executed.
1086.It Li SSE_PRE_EXEC.STORES
1087.Pq Event 07H , Umask 03H
1088The number of times SSE non-temporal store instructions were executed.
1089.It Li SSE_PRE_MISS.L1
1090.Pq Event 4BH , Umask 01H
1091The number of times the
1092.Li PREFETCHT0
1093instruction executed and missed all cache levels.
1094.It Li SSE_PRE_MISS.L2
1095.Pq Event 4BH , Umask 02H
1096The number of times the
1097.Li PREFETCHT1
1098instruction executed and missed all cache levels.
1099.It Li SSE_PRE_MISS.NTA
1100.Pq Event 4BH , Umask 00H
1101The number of times the
1102.Li PREFETCHNTA
1103instruction executed and missed all cache levels.
1104.It Li STORE_BLOCK.ORDER
1105.Pq Event 04H , Umask 02H
1106The number of cycles while a store was waiting for another store to be
1107globally observed.
1108.It Li STORE_BLOCK.SNOOP
1109.Pq Event 04H , Umask 08H
1110The number of cycles while a store was blocked due to a conflict with
1111an internal or external snoop.
1112.It Li STORE_FORWARDS.GOOD
1113.Pq Event 02, Umask 81H
1114The number of times stored data was forwarded directly to a load.
1115.It Li THERMAL_TRIP
1116.Pq Event 3BH
1117The number of thermal trips.
1118.It Li UOPS_RETIRED.LD_IND_BR
1119.Pq Event C2H , Umask 01H
1120The number of micro-ops retired that fused a load with another
1121operation.
1122.It Li UOPS_RETIRED.STD_STA
1123.Pq Event C2H , Umask 02H
1124The number of store address calculations that fused into one micro-op.
1125.It Li UOPS_RETIRED.MACRO_FUSION
1126.Pq Event C2H , Umask 04H
1127The number of times retired instruction pairs were fused into one
1128micro-op.
1129.It Li UOPS_RETIRED.FUSED
1130.Pq Event C2H , Umask 07H
1131The number of fused micro-ops retired.
1132.It Li UOPS_RETIRED.NON_FUSED
1133.Pq Event C2H , Umask 8H
1134The number of non-fused micro-ops retired.
1135.It Li UOPS_RETIRED.ANY
1136.Pq Event C2H , Umask 10H
1137The number of micro-ops retired.
1138.It Li X87_COMP_OPS_EXE.ANY.AR
1139.Pq Event 10H , Umask 81H
1140The number of x87 floating-point computational micro-ops retired.
1141.It Li X87_COMP_OPS_EXE.ANY.S
1142.Pq Event 10H , Umask 01H
1143The number of x87 floating-point computational micro-ops executed.
1144.It Li X87_OPS_RETIRED.ANY
1145.Pq Event C1H , Umask FEH
1146The number of floating point computational instructions retired.
1147.It Li X87_OPS_RETIRED.FXCH
1148.Pq Event C1H , Umask 01H
1149The number of
1150.Li FXCH
1151instructions retired.
1152.El
1153.Ss Event Name Aliases
1154The following table shows the mapping between the PMC-independent
1155aliases supported by
1156.Lb libpmc
1157and the underlying hardware events used.
1158.Bl -column "branch-mispredicts" "Description"
1159.It Em Alias Ta Em Event
1160.It Li branches Ta Li BR_INST_RETIRED.ANY
1161.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED
1162.It Li dc-misses Ta Li L2_ST,core=this,cachestate=mesi
1163.It Li ic-misses Ta Li ICACHE.MISSES
1164.It Li instructions Ta Li INST_RETIRED.ANY_P
1165.It Li interrupts Ta Li HW_INT_RCV
1166.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P
1167.El
1168.Sh SEE ALSO
1169.Xr pmc 3 ,
1170.Xr pmc.core 3 ,
1171.Xr pmc.core2 3 ,
1172.Xr pmc.iaf 3 ,
1173.Xr pmc.k7 3 ,
1174.Xr pmc.k8 3 ,
1175.Xr pmc.p4 3 ,
1176.Xr pmc.p5 3 ,
1177.Xr pmc.p6 3 ,
1178.Xr pmc.tsc 3 ,
1179.Xr pmc_cpuinfo 3 ,
1180.Xr pmclog 3 ,
1181.Xr hwpmc 4
1182.Sh HISTORY
1183The
1184.Nm pmc
1185library first appeared in
1186.Fx 6.0 .
1187.Sh AUTHORS
1188The
1189.Lb libpmc
1190library was written by
1191.An "Joseph Koshy"
1192.Aq jkoshy@FreeBSD.org .
1193