1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/module.h> 35 #include <sys/pmc.h> 36 #include <sys/syscall.h> 37 38 #include <ctype.h> 39 #include <errno.h> 40 #include <err.h> 41 #include <fcntl.h> 42 #include <pmc.h> 43 #include <stdio.h> 44 #include <stdlib.h> 45 #include <string.h> 46 #include <strings.h> 47 #include <sysexits.h> 48 #include <unistd.h> 49 50 #include "libpmcinternal.h" 51 52 /* Function prototypes */ 53 #if defined(__amd64__) || defined(__i386__) 54 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56 #endif 57 #if defined(__amd64__) || defined(__i386__) 58 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60 #endif 61 #if defined(__arm__) 62 #if defined(__XSCALE__) 63 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65 #endif 66 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 67 struct pmc_op_pmcallocate *_pmc_config); 68 #endif 69 #if defined(__aarch64__) 70 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72 #endif 73 #if defined(__mips__) 74 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 #endif /* __mips__ */ 77 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 78 struct pmc_op_pmcallocate *_pmc_config); 79 80 #if defined(__powerpc__) 81 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 82 struct pmc_op_pmcallocate *_pmc_config); 83 #endif /* __powerpc__ */ 84 85 #define PMC_CALL(cmd, params) \ 86 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 87 88 /* 89 * Event aliases provide a way for the user to ask for generic events 90 * like "cache-misses", or "instructions-retired". These aliases are 91 * mapped to the appropriate canonical event descriptions using a 92 * lookup table. 93 */ 94 struct pmc_event_alias { 95 const char *pm_alias; 96 const char *pm_spec; 97 }; 98 99 static const struct pmc_event_alias *pmc_mdep_event_aliases; 100 101 /* 102 * The pmc_event_descr structure maps symbolic names known to the user 103 * to integer codes used by the PMC KLD. 104 */ 105 struct pmc_event_descr { 106 const char *pm_ev_name; 107 enum pmc_event pm_ev_code; 108 }; 109 110 /* 111 * The pmc_class_descr structure maps class name prefixes for 112 * event names to event tables and other PMC class data. 113 */ 114 struct pmc_class_descr { 115 const char *pm_evc_name; 116 size_t pm_evc_name_size; 117 enum pmc_class pm_evc_class; 118 const struct pmc_event_descr *pm_evc_event_table; 119 size_t pm_evc_event_table_size; 120 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 121 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 122 }; 123 124 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 125 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 126 127 #undef __PMC_EV 128 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 129 130 /* 131 * PMC_CLASSDEP_TABLE(NAME, CLASS) 132 * 133 * Define a table mapping event names and aliases to HWPMC event IDs. 134 */ 135 #define PMC_CLASSDEP_TABLE(N, C) \ 136 static const struct pmc_event_descr N##_event_table[] = \ 137 { \ 138 __PMC_EV_##C() \ 139 } 140 141 PMC_CLASSDEP_TABLE(iaf, IAF); 142 PMC_CLASSDEP_TABLE(k8, K8); 143 PMC_CLASSDEP_TABLE(xscale, XSCALE); 144 PMC_CLASSDEP_TABLE(armv7, ARMV7); 145 PMC_CLASSDEP_TABLE(armv8, ARMV8); 146 PMC_CLASSDEP_TABLE(beri, BERI); 147 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 148 PMC_CLASSDEP_TABLE(mips74k, MIPS74K); 149 PMC_CLASSDEP_TABLE(octeon, OCTEON); 150 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 151 PMC_CLASSDEP_TABLE(ppc970, PPC970); 152 PMC_CLASSDEP_TABLE(power8, POWER8); 153 PMC_CLASSDEP_TABLE(e500, E500); 154 155 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 156 157 #undef __PMC_EV_ALIAS 158 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 159 160 static const struct pmc_event_descr cortex_a8_event_table[] = 161 { 162 __PMC_EV_ALIAS_ARMV7_CORTEX_A8() 163 }; 164 165 static const struct pmc_event_descr cortex_a9_event_table[] = 166 { 167 __PMC_EV_ALIAS_ARMV7_CORTEX_A9() 168 }; 169 170 static const struct pmc_event_descr cortex_a53_event_table[] = 171 { 172 __PMC_EV_ALIAS_ARMV8_CORTEX_A53() 173 }; 174 175 static const struct pmc_event_descr cortex_a57_event_table[] = 176 { 177 __PMC_EV_ALIAS_ARMV8_CORTEX_A57() 178 }; 179 180 static const struct pmc_event_descr cortex_a76_event_table[] = 181 { 182 __PMC_EV_ALIAS_ARMV8_CORTEX_A76() 183 }; 184 185 /* 186 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 187 * 188 * Map a CPU to the PMC classes it supports. 189 */ 190 #define PMC_MDEP_TABLE(N,C,...) \ 191 static const enum pmc_class N##_pmc_classes[] = { \ 192 PMC_CLASS_##C, __VA_ARGS__ \ 193 } 194 195 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 196 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 197 PMC_MDEP_TABLE(beri, BERI, PMC_CLASS_SOFT, PMC_CLASS_BERI); 198 PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 199 PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 200 PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); 201 PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); 202 PMC_MDEP_TABLE(cortex_a76, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); 203 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 204 PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); 205 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 206 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450, PMC_CLASS_TSC); 207 PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970, PMC_CLASS_TSC); 208 PMC_MDEP_TABLE(power8, POWER8, PMC_CLASS_SOFT, PMC_CLASS_POWER8, PMC_CLASS_TSC); 209 PMC_MDEP_TABLE(e500, E500, PMC_CLASS_SOFT, PMC_CLASS_E500, PMC_CLASS_TSC); 210 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 211 212 static const struct pmc_event_descr tsc_event_table[] = 213 { 214 __PMC_EV_TSC() 215 }; 216 217 #undef PMC_CLASS_TABLE_DESC 218 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 219 static const struct pmc_class_descr NAME##_class_table_descr = \ 220 { \ 221 .pm_evc_name = #CLASS "-", \ 222 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 223 .pm_evc_class = PMC_CLASS_##CLASS , \ 224 .pm_evc_event_table = EVENTS##_event_table , \ 225 .pm_evc_event_table_size = \ 226 PMC_EVENT_TABLE_SIZE(EVENTS), \ 227 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 228 } 229 230 #if defined(__i386__) || defined(__amd64__) 231 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 232 #endif 233 #if defined(__i386__) || defined(__amd64__) 234 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 235 #endif 236 #if defined(__arm__) 237 #if defined(__XSCALE__) 238 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 239 #endif 240 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7); 241 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); 242 #endif 243 #if defined(__aarch64__) 244 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); 245 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); 246 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64); 247 #endif 248 #if defined(__mips__) 249 PMC_CLASS_TABLE_DESC(beri, BERI, beri, mips); 250 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 251 PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); 252 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 253 #endif /* __mips__ */ 254 #if defined(__powerpc__) 255 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 256 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 257 PMC_CLASS_TABLE_DESC(power8, POWER8, power8, powerpc); 258 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); 259 #endif 260 261 static struct pmc_class_descr soft_class_table_descr = 262 { 263 .pm_evc_name = "SOFT-", 264 .pm_evc_name_size = sizeof("SOFT-") - 1, 265 .pm_evc_class = PMC_CLASS_SOFT, 266 .pm_evc_event_table = NULL, 267 .pm_evc_event_table_size = 0, 268 .pm_evc_allocate_pmc = soft_allocate_pmc 269 }; 270 271 #undef PMC_CLASS_TABLE_DESC 272 273 static const struct pmc_class_descr **pmc_class_table; 274 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 275 276 static const enum pmc_class *pmc_mdep_class_list; 277 static size_t pmc_mdep_class_list_size; 278 279 /* 280 * Mapping tables, mapping enumeration values to human readable 281 * strings. 282 */ 283 284 static const char * pmc_capability_names[] = { 285 #undef __PMC_CAP 286 #define __PMC_CAP(N,V,D) #N , 287 __PMC_CAPS() 288 }; 289 290 struct pmc_class_map { 291 enum pmc_class pm_class; 292 const char *pm_name; 293 }; 294 295 static const struct pmc_class_map pmc_class_names[] = { 296 #undef __PMC_CLASS 297 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } , 298 __PMC_CLASSES() 299 }; 300 301 struct pmc_cputype_map { 302 enum pmc_cputype pm_cputype; 303 const char *pm_name; 304 }; 305 306 static const struct pmc_cputype_map pmc_cputype_names[] = { 307 #undef __PMC_CPU 308 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 309 __PMC_CPUS() 310 }; 311 312 static const char * pmc_disposition_names[] = { 313 #undef __PMC_DISP 314 #define __PMC_DISP(D) #D , 315 __PMC_DISPOSITIONS() 316 }; 317 318 static const char * pmc_mode_names[] = { 319 #undef __PMC_MODE 320 #define __PMC_MODE(M,N) #M , 321 __PMC_MODES() 322 }; 323 324 static const char * pmc_state_names[] = { 325 #undef __PMC_STATE 326 #define __PMC_STATE(S) #S , 327 __PMC_STATES() 328 }; 329 330 /* 331 * Filled in by pmc_init(). 332 */ 333 static int pmc_syscall = -1; 334 static struct pmc_cpuinfo cpu_info; 335 static struct pmc_op_getdyneventinfo soft_event_info; 336 337 /* Event masks for events */ 338 struct pmc_masks { 339 const char *pm_name; 340 const uint64_t pm_value; 341 }; 342 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 343 #define NULLMASK { .pm_name = NULL } 344 345 #if defined(__amd64__) || defined(__i386__) 346 static int 347 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 348 { 349 const struct pmc_masks *pm; 350 char *q, *r; 351 int c; 352 353 if (pmask == NULL) /* no mask keywords */ 354 return (-1); 355 q = strchr(p, '='); /* skip '=' */ 356 if (*++q == '\0') /* no more data */ 357 return (-1); 358 c = 0; /* count of mask keywords seen */ 359 while ((r = strsep(&q, "+")) != NULL) { 360 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 361 pm++) 362 ; 363 if (pm->pm_name == NULL) /* not found */ 364 return (-1); 365 *evmask |= pm->pm_value; 366 c++; 367 } 368 return (c); 369 } 370 #endif 371 372 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 373 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 374 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 375 376 #if defined(__amd64__) || defined(__i386__) 377 /* 378 * AMD K8 PMCs. 379 * 380 */ 381 382 static struct pmc_event_alias k8_aliases[] = { 383 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 384 EV_ALIAS("branch-mispredicts", 385 "k8-fr-retired-taken-branches-mispredicted"), 386 EV_ALIAS("cycles", "tsc"), 387 EV_ALIAS("dc-misses", "k8-dc-miss"), 388 EV_ALIAS("ic-misses", "k8-ic-miss"), 389 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 390 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 391 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 392 EV_ALIAS(NULL, NULL) 393 }; 394 395 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 396 397 /* 398 * Parsing tables 399 */ 400 401 /* fp dispatched fpu ops */ 402 static const struct pmc_masks k8_mask_fdfo[] = { 403 __K8MASK(add-pipe-excluding-junk-ops, 0), 404 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 405 __K8MASK(store-pipe-excluding-junk-ops, 2), 406 __K8MASK(add-pipe-junk-ops, 3), 407 __K8MASK(multiply-pipe-junk-ops, 4), 408 __K8MASK(store-pipe-junk-ops, 5), 409 NULLMASK 410 }; 411 412 /* ls segment register loads */ 413 static const struct pmc_masks k8_mask_lsrl[] = { 414 __K8MASK(es, 0), 415 __K8MASK(cs, 1), 416 __K8MASK(ss, 2), 417 __K8MASK(ds, 3), 418 __K8MASK(fs, 4), 419 __K8MASK(gs, 5), 420 __K8MASK(hs, 6), 421 NULLMASK 422 }; 423 424 /* ls locked operation */ 425 static const struct pmc_masks k8_mask_llo[] = { 426 __K8MASK(locked-instructions, 0), 427 __K8MASK(cycles-in-request, 1), 428 __K8MASK(cycles-to-complete, 2), 429 NULLMASK 430 }; 431 432 /* dc refill from {l2,system} and dc copyback */ 433 static const struct pmc_masks k8_mask_dc[] = { 434 __K8MASK(invalid, 0), 435 __K8MASK(shared, 1), 436 __K8MASK(exclusive, 2), 437 __K8MASK(owner, 3), 438 __K8MASK(modified, 4), 439 NULLMASK 440 }; 441 442 /* dc one bit ecc error */ 443 static const struct pmc_masks k8_mask_dobee[] = { 444 __K8MASK(scrubber, 0), 445 __K8MASK(piggyback, 1), 446 NULLMASK 447 }; 448 449 /* dc dispatched prefetch instructions */ 450 static const struct pmc_masks k8_mask_ddpi[] = { 451 __K8MASK(load, 0), 452 __K8MASK(store, 1), 453 __K8MASK(nta, 2), 454 NULLMASK 455 }; 456 457 /* dc dcache accesses by locks */ 458 static const struct pmc_masks k8_mask_dabl[] = { 459 __K8MASK(accesses, 0), 460 __K8MASK(misses, 1), 461 NULLMASK 462 }; 463 464 /* bu internal l2 request */ 465 static const struct pmc_masks k8_mask_bilr[] = { 466 __K8MASK(ic-fill, 0), 467 __K8MASK(dc-fill, 1), 468 __K8MASK(tlb-reload, 2), 469 __K8MASK(tag-snoop, 3), 470 __K8MASK(cancelled, 4), 471 NULLMASK 472 }; 473 474 /* bu fill request l2 miss */ 475 static const struct pmc_masks k8_mask_bfrlm[] = { 476 __K8MASK(ic-fill, 0), 477 __K8MASK(dc-fill, 1), 478 __K8MASK(tlb-reload, 2), 479 NULLMASK 480 }; 481 482 /* bu fill into l2 */ 483 static const struct pmc_masks k8_mask_bfil[] = { 484 __K8MASK(dirty-l2-victim, 0), 485 __K8MASK(victim-from-l2, 1), 486 NULLMASK 487 }; 488 489 /* fr retired fpu instructions */ 490 static const struct pmc_masks k8_mask_frfi[] = { 491 __K8MASK(x87, 0), 492 __K8MASK(mmx-3dnow, 1), 493 __K8MASK(packed-sse-sse2, 2), 494 __K8MASK(scalar-sse-sse2, 3), 495 NULLMASK 496 }; 497 498 /* fr retired fastpath double op instructions */ 499 static const struct pmc_masks k8_mask_frfdoi[] = { 500 __K8MASK(low-op-pos-0, 0), 501 __K8MASK(low-op-pos-1, 1), 502 __K8MASK(low-op-pos-2, 2), 503 NULLMASK 504 }; 505 506 /* fr fpu exceptions */ 507 static const struct pmc_masks k8_mask_ffe[] = { 508 __K8MASK(x87-reclass-microfaults, 0), 509 __K8MASK(sse-retype-microfaults, 1), 510 __K8MASK(sse-reclass-microfaults, 2), 511 __K8MASK(sse-and-x87-microtraps, 3), 512 NULLMASK 513 }; 514 515 /* nb memory controller page access event */ 516 static const struct pmc_masks k8_mask_nmcpae[] = { 517 __K8MASK(page-hit, 0), 518 __K8MASK(page-miss, 1), 519 __K8MASK(page-conflict, 2), 520 NULLMASK 521 }; 522 523 /* nb memory controller turnaround */ 524 static const struct pmc_masks k8_mask_nmct[] = { 525 __K8MASK(dimm-turnaround, 0), 526 __K8MASK(read-to-write-turnaround, 1), 527 __K8MASK(write-to-read-turnaround, 2), 528 NULLMASK 529 }; 530 531 /* nb memory controller bypass saturation */ 532 static const struct pmc_masks k8_mask_nmcbs[] = { 533 __K8MASK(memory-controller-hi-pri-bypass, 0), 534 __K8MASK(memory-controller-lo-pri-bypass, 1), 535 __K8MASK(dram-controller-interface-bypass, 2), 536 __K8MASK(dram-controller-queue-bypass, 3), 537 NULLMASK 538 }; 539 540 /* nb sized commands */ 541 static const struct pmc_masks k8_mask_nsc[] = { 542 __K8MASK(nonpostwrszbyte, 0), 543 __K8MASK(nonpostwrszdword, 1), 544 __K8MASK(postwrszbyte, 2), 545 __K8MASK(postwrszdword, 3), 546 __K8MASK(rdszbyte, 4), 547 __K8MASK(rdszdword, 5), 548 __K8MASK(rdmodwr, 6), 549 NULLMASK 550 }; 551 552 /* nb probe result */ 553 static const struct pmc_masks k8_mask_npr[] = { 554 __K8MASK(probe-miss, 0), 555 __K8MASK(probe-hit, 1), 556 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 557 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 558 NULLMASK 559 }; 560 561 /* nb hypertransport bus bandwidth */ 562 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 563 __K8MASK(command, 0), 564 __K8MASK(data, 1), 565 __K8MASK(buffer-release, 2), 566 __K8MASK(nop, 3), 567 NULLMASK 568 }; 569 570 #undef __K8MASK 571 572 #define K8_KW_COUNT "count" 573 #define K8_KW_EDGE "edge" 574 #define K8_KW_INV "inv" 575 #define K8_KW_MASK "mask" 576 #define K8_KW_OS "os" 577 #define K8_KW_USR "usr" 578 579 static int 580 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 581 struct pmc_op_pmcallocate *pmc_config) 582 { 583 char *e, *p, *q; 584 int n; 585 uint32_t count; 586 uint64_t evmask; 587 const struct pmc_masks *pm, *pmask; 588 589 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 590 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 591 592 pmask = NULL; 593 evmask = 0; 594 595 #define __K8SETMASK(M) pmask = k8_mask_##M 596 597 /* setup parsing tables */ 598 switch (pe) { 599 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 600 __K8SETMASK(fdfo); 601 break; 602 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 603 __K8SETMASK(lsrl); 604 break; 605 case PMC_EV_K8_LS_LOCKED_OPERATION: 606 __K8SETMASK(llo); 607 break; 608 case PMC_EV_K8_DC_REFILL_FROM_L2: 609 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 610 case PMC_EV_K8_DC_COPYBACK: 611 __K8SETMASK(dc); 612 break; 613 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 614 __K8SETMASK(dobee); 615 break; 616 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 617 __K8SETMASK(ddpi); 618 break; 619 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 620 __K8SETMASK(dabl); 621 break; 622 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 623 __K8SETMASK(bilr); 624 break; 625 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 626 __K8SETMASK(bfrlm); 627 break; 628 case PMC_EV_K8_BU_FILL_INTO_L2: 629 __K8SETMASK(bfil); 630 break; 631 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 632 __K8SETMASK(frfi); 633 break; 634 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 635 __K8SETMASK(frfdoi); 636 break; 637 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 638 __K8SETMASK(ffe); 639 break; 640 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 641 __K8SETMASK(nmcpae); 642 break; 643 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 644 __K8SETMASK(nmct); 645 break; 646 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 647 __K8SETMASK(nmcbs); 648 break; 649 case PMC_EV_K8_NB_SIZED_COMMANDS: 650 __K8SETMASK(nsc); 651 break; 652 case PMC_EV_K8_NB_PROBE_RESULT: 653 __K8SETMASK(npr); 654 break; 655 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 656 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 657 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 658 __K8SETMASK(nhbb); 659 break; 660 661 default: 662 break; /* no options defined */ 663 } 664 665 while ((p = strsep(&ctrspec, ",")) != NULL) { 666 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 667 q = strchr(p, '='); 668 if (*++q == '\0') /* skip '=' */ 669 return (-1); 670 671 count = strtol(q, &e, 0); 672 if (e == q || *e != '\0') 673 return (-1); 674 675 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 676 pmc_config->pm_md.pm_amd.pm_amd_config |= 677 AMD_PMC_TO_COUNTER(count); 678 679 } else if (KWMATCH(p, K8_KW_EDGE)) { 680 pmc_config->pm_caps |= PMC_CAP_EDGE; 681 } else if (KWMATCH(p, K8_KW_INV)) { 682 pmc_config->pm_caps |= PMC_CAP_INVERT; 683 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 684 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 685 return (-1); 686 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 687 } else if (KWMATCH(p, K8_KW_OS)) { 688 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 689 } else if (KWMATCH(p, K8_KW_USR)) { 690 pmc_config->pm_caps |= PMC_CAP_USER; 691 } else 692 return (-1); 693 } 694 695 /* other post processing */ 696 switch (pe) { 697 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 698 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 699 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 700 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 701 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 702 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 703 /* XXX only available in rev B and later */ 704 break; 705 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 706 /* XXX only available in rev C and later */ 707 break; 708 case PMC_EV_K8_LS_LOCKED_OPERATION: 709 /* XXX CPU Rev A,B evmask is to be zero */ 710 if (evmask & (evmask - 1)) /* > 1 bit set */ 711 return (-1); 712 if (evmask == 0) { 713 evmask = 0x01; /* Rev C and later: #instrs */ 714 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 715 } 716 break; 717 default: 718 if (evmask == 0 && pmask != NULL) { 719 for (pm = pmask; pm->pm_name; pm++) 720 evmask |= pm->pm_value; 721 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 722 } 723 } 724 725 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 726 pmc_config->pm_md.pm_amd.pm_amd_config = 727 AMD_PMC_TO_UNITMASK(evmask); 728 729 return (0); 730 } 731 732 #endif 733 734 #if defined(__i386__) || defined(__amd64__) 735 static int 736 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 737 struct pmc_op_pmcallocate *pmc_config) 738 { 739 if (pe != PMC_EV_TSC_TSC) 740 return (-1); 741 742 /* TSC events must be unqualified. */ 743 if (ctrspec && *ctrspec != '\0') 744 return (-1); 745 746 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 747 pmc_config->pm_caps |= PMC_CAP_READ; 748 749 return (0); 750 } 751 #endif 752 753 static struct pmc_event_alias generic_aliases[] = { 754 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 755 EV_ALIAS(NULL, NULL) 756 }; 757 758 static int 759 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 760 struct pmc_op_pmcallocate *pmc_config) 761 { 762 (void)ctrspec; 763 (void)pmc_config; 764 765 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 766 return (-1); 767 768 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 769 return (0); 770 } 771 772 #if defined(__arm__) 773 #if defined(__XSCALE__) 774 775 static struct pmc_event_alias xscale_aliases[] = { 776 EV_ALIAS("branches", "BRANCH_RETIRED"), 777 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 778 EV_ALIAS("dc-misses", "DC_MISS"), 779 EV_ALIAS("ic-misses", "IC_MISS"), 780 EV_ALIAS("instructions", "INSTR_RETIRED"), 781 EV_ALIAS(NULL, NULL) 782 }; 783 static int 784 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 785 struct pmc_op_pmcallocate *pmc_config __unused) 786 { 787 switch (pe) { 788 default: 789 break; 790 } 791 792 return (0); 793 } 794 #endif 795 796 static struct pmc_event_alias cortex_a8_aliases[] = { 797 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 798 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 799 EV_ALIAS("instructions", "INSTR_EXECUTED"), 800 EV_ALIAS(NULL, NULL) 801 }; 802 803 static struct pmc_event_alias cortex_a9_aliases[] = { 804 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 805 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 806 EV_ALIAS("instructions", "INSTR_EXECUTED"), 807 EV_ALIAS(NULL, NULL) 808 }; 809 810 static int 811 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 812 struct pmc_op_pmcallocate *pmc_config __unused) 813 { 814 switch (pe) { 815 default: 816 break; 817 } 818 819 return (0); 820 } 821 #endif 822 823 #if defined(__aarch64__) 824 static struct pmc_event_alias cortex_a53_aliases[] = { 825 EV_ALIAS(NULL, NULL) 826 }; 827 static struct pmc_event_alias cortex_a57_aliases[] = { 828 EV_ALIAS(NULL, NULL) 829 }; 830 static struct pmc_event_alias cortex_a76_aliases[] = { 831 EV_ALIAS(NULL, NULL) 832 }; 833 static int 834 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 835 struct pmc_op_pmcallocate *pmc_config __unused) 836 { 837 switch (pe) { 838 default: 839 break; 840 } 841 842 return (0); 843 } 844 #endif 845 846 #if defined(__mips__) 847 848 static struct pmc_event_alias beri_aliases[] = { 849 EV_ALIAS("instructions", "INST"), 850 EV_ALIAS(NULL, NULL) 851 }; 852 853 static struct pmc_event_alias mips24k_aliases[] = { 854 EV_ALIAS("instructions", "INSTR_EXECUTED"), 855 EV_ALIAS("branches", "BRANCH_COMPLETED"), 856 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 857 EV_ALIAS(NULL, NULL) 858 }; 859 860 static struct pmc_event_alias mips74k_aliases[] = { 861 EV_ALIAS("instructions", "INSTR_EXECUTED"), 862 EV_ALIAS("branches", "BRANCH_INSNS"), 863 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"), 864 EV_ALIAS(NULL, NULL) 865 }; 866 867 static struct pmc_event_alias octeon_aliases[] = { 868 EV_ALIAS("instructions", "RET"), 869 EV_ALIAS("branches", "BR"), 870 EV_ALIAS("branch-mispredicts", "BRMIS"), 871 EV_ALIAS(NULL, NULL) 872 }; 873 874 #define MIPS_KW_OS "os" 875 #define MIPS_KW_USR "usr" 876 #define MIPS_KW_ANYTHREAD "anythread" 877 878 static int 879 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 880 struct pmc_op_pmcallocate *pmc_config __unused) 881 { 882 char *p; 883 884 (void) pe; 885 886 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 887 888 while ((p = strsep(&ctrspec, ",")) != NULL) { 889 if (KWMATCH(p, MIPS_KW_OS)) 890 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 891 else if (KWMATCH(p, MIPS_KW_USR)) 892 pmc_config->pm_caps |= PMC_CAP_USER; 893 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 894 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 895 else 896 return (-1); 897 } 898 899 return (0); 900 } 901 902 #endif /* __mips__ */ 903 904 #if defined(__powerpc__) 905 906 static struct pmc_event_alias ppc7450_aliases[] = { 907 EV_ALIAS("instructions", "INSTR_COMPLETED"), 908 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 909 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 910 EV_ALIAS(NULL, NULL) 911 }; 912 913 static struct pmc_event_alias ppc970_aliases[] = { 914 EV_ALIAS("instructions", "INSTR_COMPLETED"), 915 EV_ALIAS("cycles", "CYCLES"), 916 EV_ALIAS(NULL, NULL) 917 }; 918 919 static struct pmc_event_alias power8_aliases[] = { 920 EV_ALIAS("instructions", "INSTR_COMPLETED"), 921 EV_ALIAS("cycles", "CYCLES"), 922 EV_ALIAS(NULL, NULL) 923 }; 924 925 static struct pmc_event_alias e500_aliases[] = { 926 EV_ALIAS("instructions", "INSTR_COMPLETED"), 927 EV_ALIAS("cycles", "CYCLES"), 928 EV_ALIAS(NULL, NULL) 929 }; 930 931 #define POWERPC_KW_OS "os" 932 #define POWERPC_KW_USR "usr" 933 #define POWERPC_KW_ANYTHREAD "anythread" 934 935 static int 936 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 937 struct pmc_op_pmcallocate *pmc_config __unused) 938 { 939 char *p; 940 941 (void) pe; 942 943 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 944 945 while ((p = strsep(&ctrspec, ",")) != NULL) { 946 if (KWMATCH(p, POWERPC_KW_OS)) 947 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 948 else if (KWMATCH(p, POWERPC_KW_USR)) 949 pmc_config->pm_caps |= PMC_CAP_USER; 950 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 951 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 952 else 953 return (-1); 954 } 955 956 return (0); 957 } 958 959 #endif /* __powerpc__ */ 960 961 962 /* 963 * Match an event name `name' with its canonical form. 964 * 965 * Matches are case insensitive and spaces, periods, underscores and 966 * hyphen characters are considered to match each other. 967 * 968 * Returns 1 for a match, 0 otherwise. 969 */ 970 971 static int 972 pmc_match_event_name(const char *name, const char *canonicalname) 973 { 974 int cc, nc; 975 const unsigned char *c, *n; 976 977 c = (const unsigned char *) canonicalname; 978 n = (const unsigned char *) name; 979 980 for (; (nc = *n) && (cc = *c); n++, c++) { 981 982 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 983 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 984 continue; 985 986 if (toupper(nc) == toupper(cc)) 987 continue; 988 989 990 return (0); 991 } 992 993 if (*n == '\0' && *c == '\0') 994 return (1); 995 996 return (0); 997 } 998 999 /* 1000 * Match an event name against all the event named supported by a 1001 * PMC class. 1002 * 1003 * Returns an event descriptor pointer on match or NULL otherwise. 1004 */ 1005 static const struct pmc_event_descr * 1006 pmc_match_event_class(const char *name, 1007 const struct pmc_class_descr *pcd) 1008 { 1009 size_t n; 1010 const struct pmc_event_descr *ev; 1011 1012 ev = pcd->pm_evc_event_table; 1013 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 1014 if (pmc_match_event_name(name, ev->pm_ev_name)) 1015 return (ev); 1016 1017 return (NULL); 1018 } 1019 1020 static int 1021 pmc_mdep_is_compatible_class(enum pmc_class pc) 1022 { 1023 size_t n; 1024 1025 for (n = 0; n < pmc_mdep_class_list_size; n++) 1026 if (pmc_mdep_class_list[n] == pc) 1027 return (1); 1028 return (0); 1029 } 1030 1031 /* 1032 * API entry points 1033 */ 1034 1035 int 1036 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 1037 uint32_t flags, int cpu, pmc_id_t *pmcid, 1038 uint64_t count) 1039 { 1040 size_t n; 1041 int retval; 1042 char *r, *spec_copy; 1043 const char *ctrname; 1044 const struct pmc_event_descr *ev; 1045 const struct pmc_event_alias *alias; 1046 struct pmc_op_pmcallocate pmc_config; 1047 const struct pmc_class_descr *pcd; 1048 1049 spec_copy = NULL; 1050 retval = -1; 1051 1052 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 1053 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 1054 errno = EINVAL; 1055 goto out; 1056 } 1057 bzero(&pmc_config, sizeof(pmc_config)); 1058 pmc_config.pm_cpu = cpu; 1059 pmc_config.pm_mode = mode; 1060 pmc_config.pm_flags = flags; 1061 pmc_config.pm_count = count; 1062 if (PMC_IS_SAMPLING_MODE(mode)) 1063 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 1064 /* 1065 * Can we pull this straight from the pmu table? 1066 */ 1067 r = spec_copy = strdup(ctrspec); 1068 ctrname = strsep(&r, ","); 1069 if (pmc_pmu_enabled()) { 1070 if (pmc_pmu_pmcallocate(ctrname, &pmc_config) == 0) { 1071 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) { 1072 goto out; 1073 } 1074 retval = 0; 1075 *pmcid = pmc_config.pm_pmcid; 1076 goto out; 1077 } 1078 errx(EX_USAGE, "ERROR: pmc_pmu_allocate failed, check for ctrname %s\n", ctrname); 1079 } else { 1080 free(spec_copy); 1081 spec_copy = NULL; 1082 } 1083 1084 /* replace an event alias with the canonical event specifier */ 1085 if (pmc_mdep_event_aliases) 1086 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 1087 if (!strcasecmp(ctrspec, alias->pm_alias)) { 1088 spec_copy = strdup(alias->pm_spec); 1089 break; 1090 } 1091 1092 if (spec_copy == NULL) 1093 spec_copy = strdup(ctrspec); 1094 1095 r = spec_copy; 1096 ctrname = strsep(&r, ","); 1097 1098 /* 1099 * If a explicit class prefix was given by the user, restrict the 1100 * search for the event to the specified PMC class. 1101 */ 1102 ev = NULL; 1103 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 1104 pcd = pmc_class_table[n]; 1105 if (pcd && pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 1106 strncasecmp(ctrname, pcd->pm_evc_name, 1107 pcd->pm_evc_name_size) == 0) { 1108 if ((ev = pmc_match_event_class(ctrname + 1109 pcd->pm_evc_name_size, pcd)) == NULL) { 1110 errno = EINVAL; 1111 goto out; 1112 } 1113 break; 1114 } 1115 } 1116 1117 /* 1118 * Otherwise, search for this event in all compatible PMC 1119 * classes. 1120 */ 1121 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 1122 pcd = pmc_class_table[n]; 1123 if (pcd && pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 1124 ev = pmc_match_event_class(ctrname, pcd); 1125 } 1126 1127 if (ev == NULL) { 1128 errno = EINVAL; 1129 goto out; 1130 } 1131 1132 pmc_config.pm_ev = ev->pm_ev_code; 1133 pmc_config.pm_class = pcd->pm_evc_class; 1134 1135 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 1136 errno = EINVAL; 1137 goto out; 1138 } 1139 1140 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 1141 goto out; 1142 1143 *pmcid = pmc_config.pm_pmcid; 1144 1145 retval = 0; 1146 1147 out: 1148 if (spec_copy) 1149 free(spec_copy); 1150 1151 return (retval); 1152 } 1153 1154 int 1155 pmc_attach(pmc_id_t pmc, pid_t pid) 1156 { 1157 struct pmc_op_pmcattach pmc_attach_args; 1158 1159 pmc_attach_args.pm_pmc = pmc; 1160 pmc_attach_args.pm_pid = pid; 1161 1162 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 1163 } 1164 1165 int 1166 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 1167 { 1168 unsigned int i; 1169 enum pmc_class cl; 1170 1171 cl = PMC_ID_TO_CLASS(pmcid); 1172 for (i = 0; i < cpu_info.pm_nclass; i++) 1173 if (cpu_info.pm_classes[i].pm_class == cl) { 1174 *caps = cpu_info.pm_classes[i].pm_caps; 1175 return (0); 1176 } 1177 errno = EINVAL; 1178 return (-1); 1179 } 1180 1181 int 1182 pmc_configure_logfile(int fd) 1183 { 1184 struct pmc_op_configurelog cla; 1185 1186 cla.pm_logfd = fd; 1187 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 1188 return (-1); 1189 return (0); 1190 } 1191 1192 int 1193 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 1194 { 1195 if (pmc_syscall == -1) { 1196 errno = ENXIO; 1197 return (-1); 1198 } 1199 1200 *pci = &cpu_info; 1201 return (0); 1202 } 1203 1204 int 1205 pmc_detach(pmc_id_t pmc, pid_t pid) 1206 { 1207 struct pmc_op_pmcattach pmc_detach_args; 1208 1209 pmc_detach_args.pm_pmc = pmc; 1210 pmc_detach_args.pm_pid = pid; 1211 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 1212 } 1213 1214 int 1215 pmc_disable(int cpu, int pmc) 1216 { 1217 struct pmc_op_pmcadmin ssa; 1218 1219 ssa.pm_cpu = cpu; 1220 ssa.pm_pmc = pmc; 1221 ssa.pm_state = PMC_STATE_DISABLED; 1222 return (PMC_CALL(PMCADMIN, &ssa)); 1223 } 1224 1225 int 1226 pmc_enable(int cpu, int pmc) 1227 { 1228 struct pmc_op_pmcadmin ssa; 1229 1230 ssa.pm_cpu = cpu; 1231 ssa.pm_pmc = pmc; 1232 ssa.pm_state = PMC_STATE_FREE; 1233 return (PMC_CALL(PMCADMIN, &ssa)); 1234 } 1235 1236 /* 1237 * Return a list of events known to a given PMC class. 'cl' is the 1238 * PMC class identifier, 'eventnames' is the returned list of 'const 1239 * char *' pointers pointing to the names of the events. 'nevents' is 1240 * the number of event name pointers returned. 1241 * 1242 * The space for 'eventnames' is allocated using malloc(3). The caller 1243 * is responsible for freeing this space when done. 1244 */ 1245 int 1246 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 1247 int *nevents) 1248 { 1249 int count; 1250 const char **names; 1251 const struct pmc_event_descr *ev; 1252 1253 switch (cl) 1254 { 1255 case PMC_CLASS_IAF: 1256 ev = iaf_event_table; 1257 count = PMC_EVENT_TABLE_SIZE(iaf); 1258 break; 1259 case PMC_CLASS_TSC: 1260 ev = tsc_event_table; 1261 count = PMC_EVENT_TABLE_SIZE(tsc); 1262 break; 1263 case PMC_CLASS_K8: 1264 ev = k8_event_table; 1265 count = PMC_EVENT_TABLE_SIZE(k8); 1266 break; 1267 case PMC_CLASS_XSCALE: 1268 ev = xscale_event_table; 1269 count = PMC_EVENT_TABLE_SIZE(xscale); 1270 break; 1271 case PMC_CLASS_ARMV7: 1272 switch (cpu_info.pm_cputype) { 1273 default: 1274 case PMC_CPU_ARMV7_CORTEX_A8: 1275 ev = cortex_a8_event_table; 1276 count = PMC_EVENT_TABLE_SIZE(cortex_a8); 1277 break; 1278 case PMC_CPU_ARMV7_CORTEX_A9: 1279 ev = cortex_a9_event_table; 1280 count = PMC_EVENT_TABLE_SIZE(cortex_a9); 1281 break; 1282 } 1283 break; 1284 case PMC_CLASS_ARMV8: 1285 switch (cpu_info.pm_cputype) { 1286 default: 1287 case PMC_CPU_ARMV8_CORTEX_A53: 1288 ev = cortex_a53_event_table; 1289 count = PMC_EVENT_TABLE_SIZE(cortex_a53); 1290 break; 1291 case PMC_CPU_ARMV8_CORTEX_A57: 1292 ev = cortex_a57_event_table; 1293 count = PMC_EVENT_TABLE_SIZE(cortex_a57); 1294 break; 1295 case PMC_CPU_ARMV8_CORTEX_A76: 1296 ev = cortex_a76_event_table; 1297 count = PMC_EVENT_TABLE_SIZE(cortex_a76); 1298 break; 1299 } 1300 break; 1301 case PMC_CLASS_BERI: 1302 ev = beri_event_table; 1303 count = PMC_EVENT_TABLE_SIZE(beri); 1304 break; 1305 case PMC_CLASS_MIPS24K: 1306 ev = mips24k_event_table; 1307 count = PMC_EVENT_TABLE_SIZE(mips24k); 1308 break; 1309 case PMC_CLASS_MIPS74K: 1310 ev = mips74k_event_table; 1311 count = PMC_EVENT_TABLE_SIZE(mips74k); 1312 break; 1313 case PMC_CLASS_OCTEON: 1314 ev = octeon_event_table; 1315 count = PMC_EVENT_TABLE_SIZE(octeon); 1316 break; 1317 case PMC_CLASS_PPC7450: 1318 ev = ppc7450_event_table; 1319 count = PMC_EVENT_TABLE_SIZE(ppc7450); 1320 break; 1321 case PMC_CLASS_PPC970: 1322 ev = ppc970_event_table; 1323 count = PMC_EVENT_TABLE_SIZE(ppc970); 1324 break; 1325 case PMC_CLASS_POWER8: 1326 ev = power8_event_table; 1327 count = PMC_EVENT_TABLE_SIZE(power8); 1328 break; 1329 case PMC_CLASS_E500: 1330 ev = e500_event_table; 1331 count = PMC_EVENT_TABLE_SIZE(e500); 1332 break; 1333 case PMC_CLASS_SOFT: 1334 ev = soft_event_table; 1335 count = soft_event_info.pm_nevent; 1336 break; 1337 default: 1338 errno = EINVAL; 1339 return (-1); 1340 } 1341 1342 if ((names = malloc(count * sizeof(const char *))) == NULL) 1343 return (-1); 1344 1345 *eventnames = names; 1346 *nevents = count; 1347 1348 for (;count--; ev++, names++) 1349 *names = ev->pm_ev_name; 1350 1351 return (0); 1352 } 1353 1354 int 1355 pmc_flush_logfile(void) 1356 { 1357 return (PMC_CALL(FLUSHLOG,0)); 1358 } 1359 1360 int 1361 pmc_close_logfile(void) 1362 { 1363 return (PMC_CALL(CLOSELOG,0)); 1364 } 1365 1366 int 1367 pmc_get_driver_stats(struct pmc_driverstats *ds) 1368 { 1369 struct pmc_op_getdriverstats gms; 1370 1371 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 1372 return (-1); 1373 1374 /* copy out fields in the current userland<->library interface */ 1375 ds->pm_intr_ignored = gms.pm_intr_ignored; 1376 ds->pm_intr_processed = gms.pm_intr_processed; 1377 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 1378 ds->pm_syscalls = gms.pm_syscalls; 1379 ds->pm_syscall_errors = gms.pm_syscall_errors; 1380 ds->pm_buffer_requests = gms.pm_buffer_requests; 1381 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 1382 ds->pm_log_sweeps = gms.pm_log_sweeps; 1383 return (0); 1384 } 1385 1386 int 1387 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 1388 { 1389 struct pmc_op_getmsr gm; 1390 1391 gm.pm_pmcid = pmc; 1392 if (PMC_CALL(PMCGETMSR, &gm) < 0) 1393 return (-1); 1394 *msr = gm.pm_msr; 1395 return (0); 1396 } 1397 1398 int 1399 pmc_init(void) 1400 { 1401 int error, pmc_mod_id; 1402 unsigned int n; 1403 uint32_t abi_version; 1404 struct module_stat pmc_modstat; 1405 struct pmc_op_getcpuinfo op_cpu_info; 1406 #if defined(__amd64__) || defined(__i386__) 1407 int cpu_has_iaf_counters; 1408 unsigned int t; 1409 #endif 1410 1411 if (pmc_syscall != -1) /* already inited */ 1412 return (0); 1413 1414 /* retrieve the system call number from the KLD */ 1415 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 1416 return (-1); 1417 1418 pmc_modstat.version = sizeof(struct module_stat); 1419 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 1420 return (-1); 1421 1422 pmc_syscall = pmc_modstat.data.intval; 1423 1424 /* check the kernel module's ABI against our compiled-in version */ 1425 abi_version = PMC_VERSION; 1426 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 1427 return (pmc_syscall = -1); 1428 1429 /* ignore patch & minor numbers for the comparison */ 1430 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 1431 errno = EPROGMISMATCH; 1432 return (pmc_syscall = -1); 1433 } 1434 1435 bzero(&op_cpu_info, sizeof(op_cpu_info)); 1436 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 1437 return (pmc_syscall = -1); 1438 1439 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 1440 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 1441 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 1442 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 1443 for (n = 0; n < op_cpu_info.pm_nclass; n++) 1444 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n], 1445 sizeof(cpu_info.pm_classes[n])); 1446 1447 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 1448 sizeof(struct pmc_class_descr *)); 1449 1450 if (pmc_class_table == NULL) 1451 return (-1); 1452 1453 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 1454 pmc_class_table[n] = NULL; 1455 1456 /* 1457 * Get soft events list. 1458 */ 1459 soft_event_info.pm_class = PMC_CLASS_SOFT; 1460 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 1461 return (pmc_syscall = -1); 1462 1463 /* Map soft events to static list. */ 1464 for (n = 0; n < soft_event_info.pm_nevent; n++) { 1465 soft_event_table[n].pm_ev_name = 1466 soft_event_info.pm_events[n].pm_ev_name; 1467 soft_event_table[n].pm_ev_code = 1468 soft_event_info.pm_events[n].pm_ev_code; 1469 } 1470 soft_class_table_descr.pm_evc_event_table_size = \ 1471 soft_event_info.pm_nevent; 1472 soft_class_table_descr.pm_evc_event_table = \ 1473 soft_event_table; 1474 1475 /* 1476 * Fill in the class table. 1477 */ 1478 n = 0; 1479 1480 /* Fill soft events information. */ 1481 pmc_class_table[n++] = &soft_class_table_descr; 1482 #if defined(__amd64__) || defined(__i386__) 1483 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 1484 pmc_class_table[n++] = &tsc_class_table_descr; 1485 1486 /* 1487 * Check if this CPU has fixed function counters. 1488 */ 1489 cpu_has_iaf_counters = 0; 1490 for (t = 0; t < cpu_info.pm_nclass; t++) 1491 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 1492 cpu_info.pm_classes[t].pm_num > 0) 1493 cpu_has_iaf_counters = 1; 1494 #endif 1495 1496 #define PMC_MDEP_INIT(C) do { \ 1497 pmc_mdep_event_aliases = C##_aliases; \ 1498 pmc_mdep_class_list = C##_pmc_classes; \ 1499 pmc_mdep_class_list_size = \ 1500 PMC_TABLE_SIZE(C##_pmc_classes); \ 1501 } while (0) 1502 1503 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 1504 PMC_MDEP_INIT(C); \ 1505 pmc_class_table[n++] = &iaf_class_table_descr; \ 1506 if (!cpu_has_iaf_counters) \ 1507 pmc_mdep_event_aliases = \ 1508 C##_aliases_without_iaf; \ 1509 pmc_class_table[n] = &C##_class_table_descr; \ 1510 } while (0) 1511 1512 /* Configure the event name parser. */ 1513 switch (cpu_info.pm_cputype) { 1514 #if defined(__amd64__) || defined(__i386__) 1515 case PMC_CPU_AMD_K8: 1516 PMC_MDEP_INIT(k8); 1517 pmc_class_table[n] = &k8_class_table_descr; 1518 break; 1519 #endif 1520 case PMC_CPU_GENERIC: 1521 PMC_MDEP_INIT(generic); 1522 break; 1523 #if defined(__arm__) 1524 #if defined(__XSCALE__) 1525 case PMC_CPU_INTEL_XSCALE: 1526 PMC_MDEP_INIT(xscale); 1527 pmc_class_table[n] = &xscale_class_table_descr; 1528 break; 1529 #endif 1530 case PMC_CPU_ARMV7_CORTEX_A8: 1531 PMC_MDEP_INIT(cortex_a8); 1532 pmc_class_table[n] = &cortex_a8_class_table_descr; 1533 break; 1534 case PMC_CPU_ARMV7_CORTEX_A9: 1535 PMC_MDEP_INIT(cortex_a9); 1536 pmc_class_table[n] = &cortex_a9_class_table_descr; 1537 break; 1538 #endif 1539 #if defined(__aarch64__) 1540 case PMC_CPU_ARMV8_CORTEX_A53: 1541 PMC_MDEP_INIT(cortex_a53); 1542 pmc_class_table[n] = &cortex_a53_class_table_descr; 1543 break; 1544 case PMC_CPU_ARMV8_CORTEX_A57: 1545 PMC_MDEP_INIT(cortex_a57); 1546 pmc_class_table[n] = &cortex_a57_class_table_descr; 1547 break; 1548 case PMC_CPU_ARMV8_CORTEX_A76: 1549 PMC_MDEP_INIT(cortex_a76); 1550 pmc_class_table[n] = &cortex_a76_class_table_descr; 1551 break; 1552 #endif 1553 #if defined(__mips__) 1554 case PMC_CPU_MIPS_BERI: 1555 PMC_MDEP_INIT(beri); 1556 pmc_class_table[n] = &beri_class_table_descr; 1557 break; 1558 case PMC_CPU_MIPS_24K: 1559 PMC_MDEP_INIT(mips24k); 1560 pmc_class_table[n] = &mips24k_class_table_descr; 1561 break; 1562 case PMC_CPU_MIPS_74K: 1563 PMC_MDEP_INIT(mips74k); 1564 pmc_class_table[n] = &mips74k_class_table_descr; 1565 break; 1566 case PMC_CPU_MIPS_OCTEON: 1567 PMC_MDEP_INIT(octeon); 1568 pmc_class_table[n] = &octeon_class_table_descr; 1569 break; 1570 #endif /* __mips__ */ 1571 #if defined(__powerpc__) 1572 case PMC_CPU_PPC_7450: 1573 PMC_MDEP_INIT(ppc7450); 1574 pmc_class_table[n] = &ppc7450_class_table_descr; 1575 break; 1576 case PMC_CPU_PPC_970: 1577 PMC_MDEP_INIT(ppc970); 1578 pmc_class_table[n] = &ppc970_class_table_descr; 1579 break; 1580 case PMC_CPU_PPC_POWER8: 1581 PMC_MDEP_INIT(power8); 1582 pmc_class_table[n] = &power8_class_table_descr; 1583 break; 1584 case PMC_CPU_PPC_E500: 1585 PMC_MDEP_INIT(e500); 1586 pmc_class_table[n] = &e500_class_table_descr; 1587 break; 1588 #endif 1589 default: 1590 /* 1591 * Some kind of CPU this version of the library knows nothing 1592 * about. This shouldn't happen since the abi version check 1593 * should have caught this. 1594 */ 1595 #if defined(__amd64__) || defined(__i386__) 1596 break; 1597 #endif 1598 errno = ENXIO; 1599 return (pmc_syscall = -1); 1600 } 1601 1602 return (0); 1603 } 1604 1605 const char * 1606 pmc_name_of_capability(enum pmc_caps cap) 1607 { 1608 int i; 1609 1610 /* 1611 * 'cap' should have a single bit set and should be in 1612 * range. 1613 */ 1614 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 1615 cap > PMC_CAP_LAST) { 1616 errno = EINVAL; 1617 return (NULL); 1618 } 1619 1620 i = ffs(cap); 1621 return (pmc_capability_names[i - 1]); 1622 } 1623 1624 const char * 1625 pmc_name_of_class(enum pmc_class pc) 1626 { 1627 size_t n; 1628 1629 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++) 1630 if (pc == pmc_class_names[n].pm_class) 1631 return (pmc_class_names[n].pm_name); 1632 1633 errno = EINVAL; 1634 return (NULL); 1635 } 1636 1637 const char * 1638 pmc_name_of_cputype(enum pmc_cputype cp) 1639 { 1640 size_t n; 1641 1642 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 1643 if (cp == pmc_cputype_names[n].pm_cputype) 1644 return (pmc_cputype_names[n].pm_name); 1645 1646 errno = EINVAL; 1647 return (NULL); 1648 } 1649 1650 const char * 1651 pmc_name_of_disposition(enum pmc_disp pd) 1652 { 1653 if ((int) pd >= PMC_DISP_FIRST && 1654 pd <= PMC_DISP_LAST) 1655 return (pmc_disposition_names[pd]); 1656 1657 errno = EINVAL; 1658 return (NULL); 1659 } 1660 1661 const char * 1662 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 1663 { 1664 const struct pmc_event_descr *ev, *evfence; 1665 1666 ev = evfence = NULL; 1667 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 1668 ev = k8_event_table; 1669 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 1670 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 1671 ev = xscale_event_table; 1672 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 1673 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 1674 switch (cpu) { 1675 case PMC_CPU_ARMV7_CORTEX_A8: 1676 ev = cortex_a8_event_table; 1677 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8); 1678 break; 1679 case PMC_CPU_ARMV7_CORTEX_A9: 1680 ev = cortex_a9_event_table; 1681 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9); 1682 break; 1683 default: /* Unknown CPU type. */ 1684 break; 1685 } 1686 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { 1687 switch (cpu) { 1688 case PMC_CPU_ARMV8_CORTEX_A53: 1689 ev = cortex_a53_event_table; 1690 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); 1691 break; 1692 case PMC_CPU_ARMV8_CORTEX_A57: 1693 ev = cortex_a57_event_table; 1694 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); 1695 break; 1696 case PMC_CPU_ARMV8_CORTEX_A76: 1697 ev = cortex_a76_event_table; 1698 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76); 1699 break; 1700 default: /* Unknown CPU type. */ 1701 break; 1702 } 1703 } else if (pe >= PMC_EV_BERI_FIRST && pe <= PMC_EV_BERI_LAST) { 1704 ev = beri_event_table; 1705 evfence = beri_event_table + PMC_EVENT_TABLE_SIZE(beri); 1706 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 1707 ev = mips24k_event_table; 1708 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 1709 } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { 1710 ev = mips74k_event_table; 1711 evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); 1712 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 1713 ev = octeon_event_table; 1714 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 1715 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 1716 ev = ppc7450_event_table; 1717 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 1718 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 1719 ev = ppc970_event_table; 1720 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 1721 } else if (pe >= PMC_EV_POWER8_FIRST && pe <= PMC_EV_POWER8_LAST) { 1722 ev = power8_event_table; 1723 evfence = power8_event_table + PMC_EVENT_TABLE_SIZE(power8); 1724 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { 1725 ev = e500_event_table; 1726 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); 1727 } else if (pe == PMC_EV_TSC_TSC) { 1728 ev = tsc_event_table; 1729 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 1730 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 1731 ev = soft_event_table; 1732 evfence = soft_event_table + soft_event_info.pm_nevent; 1733 } 1734 1735 for (; ev != evfence; ev++) 1736 if (pe == ev->pm_ev_code) 1737 return (ev->pm_ev_name); 1738 1739 return (NULL); 1740 } 1741 1742 const char * 1743 pmc_name_of_event(enum pmc_event pe) 1744 { 1745 const char *n; 1746 1747 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 1748 return (n); 1749 1750 errno = EINVAL; 1751 return (NULL); 1752 } 1753 1754 const char * 1755 pmc_name_of_mode(enum pmc_mode pm) 1756 { 1757 if ((int) pm >= PMC_MODE_FIRST && 1758 pm <= PMC_MODE_LAST) 1759 return (pmc_mode_names[pm]); 1760 1761 errno = EINVAL; 1762 return (NULL); 1763 } 1764 1765 const char * 1766 pmc_name_of_state(enum pmc_state ps) 1767 { 1768 if ((int) ps >= PMC_STATE_FIRST && 1769 ps <= PMC_STATE_LAST) 1770 return (pmc_state_names[ps]); 1771 1772 errno = EINVAL; 1773 return (NULL); 1774 } 1775 1776 int 1777 pmc_ncpu(void) 1778 { 1779 if (pmc_syscall == -1) { 1780 errno = ENXIO; 1781 return (-1); 1782 } 1783 1784 return (cpu_info.pm_ncpu); 1785 } 1786 1787 int 1788 pmc_npmc(int cpu) 1789 { 1790 if (pmc_syscall == -1) { 1791 errno = ENXIO; 1792 return (-1); 1793 } 1794 1795 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 1796 errno = EINVAL; 1797 return (-1); 1798 } 1799 1800 return (cpu_info.pm_npmc); 1801 } 1802 1803 int 1804 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 1805 { 1806 int nbytes, npmc; 1807 struct pmc_op_getpmcinfo *pmci; 1808 1809 if ((npmc = pmc_npmc(cpu)) < 0) 1810 return (-1); 1811 1812 nbytes = sizeof(struct pmc_op_getpmcinfo) + 1813 npmc * sizeof(struct pmc_info); 1814 1815 if ((pmci = calloc(1, nbytes)) == NULL) 1816 return (-1); 1817 1818 pmci->pm_cpu = cpu; 1819 1820 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 1821 free(pmci); 1822 return (-1); 1823 } 1824 1825 /* kernel<->library, library<->userland interfaces are identical */ 1826 *ppmci = (struct pmc_pmcinfo *) pmci; 1827 return (0); 1828 } 1829 1830 int 1831 pmc_read(pmc_id_t pmc, pmc_value_t *value) 1832 { 1833 struct pmc_op_pmcrw pmc_read_op; 1834 1835 pmc_read_op.pm_pmcid = pmc; 1836 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 1837 pmc_read_op.pm_value = -1; 1838 1839 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 1840 return (-1); 1841 1842 *value = pmc_read_op.pm_value; 1843 return (0); 1844 } 1845 1846 int 1847 pmc_release(pmc_id_t pmc) 1848 { 1849 struct pmc_op_simple pmc_release_args; 1850 1851 pmc_release_args.pm_pmcid = pmc; 1852 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 1853 } 1854 1855 int 1856 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 1857 { 1858 struct pmc_op_pmcrw pmc_rw_op; 1859 1860 pmc_rw_op.pm_pmcid = pmc; 1861 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 1862 pmc_rw_op.pm_value = newvalue; 1863 1864 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 1865 return (-1); 1866 1867 *oldvaluep = pmc_rw_op.pm_value; 1868 return (0); 1869 } 1870 1871 int 1872 pmc_set(pmc_id_t pmc, pmc_value_t value) 1873 { 1874 struct pmc_op_pmcsetcount sc; 1875 1876 sc.pm_pmcid = pmc; 1877 sc.pm_count = value; 1878 1879 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 1880 return (-1); 1881 return (0); 1882 } 1883 1884 int 1885 pmc_start(pmc_id_t pmc) 1886 { 1887 struct pmc_op_simple pmc_start_args; 1888 1889 pmc_start_args.pm_pmcid = pmc; 1890 return (PMC_CALL(PMCSTART, &pmc_start_args)); 1891 } 1892 1893 int 1894 pmc_stop(pmc_id_t pmc) 1895 { 1896 struct pmc_op_simple pmc_stop_args; 1897 1898 pmc_stop_args.pm_pmcid = pmc; 1899 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 1900 } 1901 1902 int 1903 pmc_width(pmc_id_t pmcid, uint32_t *width) 1904 { 1905 unsigned int i; 1906 enum pmc_class cl; 1907 1908 cl = PMC_ID_TO_CLASS(pmcid); 1909 for (i = 0; i < cpu_info.pm_nclass; i++) 1910 if (cpu_info.pm_classes[i].pm_class == cl) { 1911 *width = cpu_info.pm_classes[i].pm_width; 1912 return (0); 1913 } 1914 errno = EINVAL; 1915 return (-1); 1916 } 1917 1918 int 1919 pmc_write(pmc_id_t pmc, pmc_value_t value) 1920 { 1921 struct pmc_op_pmcrw pmc_write_op; 1922 1923 pmc_write_op.pm_pmcid = pmc; 1924 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 1925 pmc_write_op.pm_value = value; 1926 return (PMC_CALL(PMCRW, &pmc_write_op)); 1927 } 1928 1929 int 1930 pmc_writelog(uint32_t userdata) 1931 { 1932 struct pmc_op_writelog wl; 1933 1934 wl.pm_userdata = userdata; 1935 return (PMC_CALL(WRITELOG, &wl)); 1936 } 1937