1 /*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/types.h> 31 #include <sys/module.h> 32 #include <sys/pmc.h> 33 #include <sys/syscall.h> 34 35 #include <ctype.h> 36 #include <errno.h> 37 #include <fcntl.h> 38 #include <pmc.h> 39 #include <stdio.h> 40 #include <stdlib.h> 41 #include <string.h> 42 #include <strings.h> 43 #include <unistd.h> 44 45 #include "libpmcinternal.h" 46 47 /* Function prototypes */ 48 #if defined(__i386__) 49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 50 struct pmc_op_pmcallocate *_pmc_config); 51 #endif 52 #if defined(__amd64__) || defined(__i386__) 53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 54 struct pmc_op_pmcallocate *_pmc_config); 55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 56 struct pmc_op_pmcallocate *_pmc_config); 57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 58 struct pmc_op_pmcallocate *_pmc_config); 59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 60 struct pmc_op_pmcallocate *_pmc_config); 61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 62 struct pmc_op_pmcallocate *_pmc_config); 63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65 #endif 66 #if defined(__i386__) 67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 68 struct pmc_op_pmcallocate *_pmc_config); 69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 70 struct pmc_op_pmcallocate *_pmc_config); 71 #endif 72 #if defined(__amd64__) || defined(__i386__) 73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 74 struct pmc_op_pmcallocate *_pmc_config); 75 #endif 76 #if defined(__XSCALE__) 77 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 78 struct pmc_op_pmcallocate *_pmc_config); 79 #endif 80 81 #if defined(__mips__) 82 static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84 #endif /* __mips__ */ 85 86 #if defined(__powerpc__) 87 static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec, 88 struct pmc_op_pmcallocate *_pmc_config); 89 #endif /* __powerpc__ */ 90 91 #define PMC_CALL(cmd, params) \ 92 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 93 94 /* 95 * Event aliases provide a way for the user to ask for generic events 96 * like "cache-misses", or "instructions-retired". These aliases are 97 * mapped to the appropriate canonical event descriptions using a 98 * lookup table. 99 */ 100 struct pmc_event_alias { 101 const char *pm_alias; 102 const char *pm_spec; 103 }; 104 105 static const struct pmc_event_alias *pmc_mdep_event_aliases; 106 107 /* 108 * The pmc_event_descr structure maps symbolic names known to the user 109 * to integer codes used by the PMC KLD. 110 */ 111 struct pmc_event_descr { 112 const char *pm_ev_name; 113 enum pmc_event pm_ev_code; 114 }; 115 116 /* 117 * The pmc_class_descr structure maps class name prefixes for 118 * event names to event tables and other PMC class data. 119 */ 120 struct pmc_class_descr { 121 const char *pm_evc_name; 122 size_t pm_evc_name_size; 123 enum pmc_class pm_evc_class; 124 const struct pmc_event_descr *pm_evc_event_table; 125 size_t pm_evc_event_table_size; 126 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 127 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 128 }; 129 130 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 131 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 132 133 #undef __PMC_EV 134 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 135 136 /* 137 * PMC_CLASSDEP_TABLE(NAME, CLASS) 138 * 139 * Define a table mapping event names and aliases to HWPMC event IDs. 140 */ 141 #define PMC_CLASSDEP_TABLE(N, C) \ 142 static const struct pmc_event_descr N##_event_table[] = \ 143 { \ 144 __PMC_EV_##C() \ 145 } 146 147 PMC_CLASSDEP_TABLE(iaf, IAF); 148 PMC_CLASSDEP_TABLE(k7, K7); 149 PMC_CLASSDEP_TABLE(k8, K8); 150 PMC_CLASSDEP_TABLE(p4, P4); 151 PMC_CLASSDEP_TABLE(p5, P5); 152 PMC_CLASSDEP_TABLE(p6, P6); 153 PMC_CLASSDEP_TABLE(xscale, XSCALE); 154 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 155 PMC_CLASSDEP_TABLE(ucf, UCF); 156 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 157 158 #undef __PMC_EV_ALIAS 159 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 160 161 static const struct pmc_event_descr atom_event_table[] = 162 { 163 __PMC_EV_ALIAS_ATOM() 164 }; 165 166 static const struct pmc_event_descr core_event_table[] = 167 { 168 __PMC_EV_ALIAS_CORE() 169 }; 170 171 172 static const struct pmc_event_descr core2_event_table[] = 173 { 174 __PMC_EV_ALIAS_CORE2() 175 }; 176 177 static const struct pmc_event_descr corei7_event_table[] = 178 { 179 __PMC_EV_ALIAS_COREI7() 180 }; 181 182 static const struct pmc_event_descr sandybridge_event_table[] = 183 { 184 __PMC_EV_ALIAS_SANDYBRIDGE() 185 }; 186 187 static const struct pmc_event_descr westmere_event_table[] = 188 { 189 __PMC_EV_ALIAS_WESTMERE() 190 }; 191 192 static const struct pmc_event_descr corei7uc_event_table[] = 193 { 194 __PMC_EV_ALIAS_COREI7UC() 195 }; 196 197 static const struct pmc_event_descr sandybridgeuc_event_table[] = 198 { 199 __PMC_EV_ALIAS_SANDYBRIDGEUC() 200 }; 201 202 static const struct pmc_event_descr westmereuc_event_table[] = 203 { 204 __PMC_EV_ALIAS_WESTMEREUC() 205 }; 206 207 /* 208 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 209 * 210 * Map a CPU to the PMC classes it supports. 211 */ 212 #define PMC_MDEP_TABLE(N,C,...) \ 213 static const enum pmc_class N##_pmc_classes[] = { \ 214 PMC_CLASS_##C, __VA_ARGS__ \ 215 } 216 217 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC); 218 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC); 219 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC); 220 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 221 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 222 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 223 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC); 224 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC); 225 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC); 226 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC); 227 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC); 228 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_XSCALE); 229 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_MIPS24K); 230 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_PPC7450); 231 232 static const struct pmc_event_descr tsc_event_table[] = 233 { 234 __PMC_EV_TSC() 235 }; 236 237 #undef PMC_CLASS_TABLE_DESC 238 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 239 static const struct pmc_class_descr NAME##_class_table_descr = \ 240 { \ 241 .pm_evc_name = #CLASS "-", \ 242 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 243 .pm_evc_class = PMC_CLASS_##CLASS , \ 244 .pm_evc_event_table = EVENTS##_event_table , \ 245 .pm_evc_event_table_size = \ 246 PMC_EVENT_TABLE_SIZE(EVENTS), \ 247 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 248 } 249 250 #if defined(__i386__) || defined(__amd64__) 251 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 252 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 253 PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 254 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 255 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 256 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 257 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 258 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 259 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 260 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 261 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 262 #endif 263 #if defined(__i386__) 264 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 265 #endif 266 #if defined(__i386__) || defined(__amd64__) 267 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 268 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 269 #endif 270 #if defined(__i386__) 271 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 272 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 273 #endif 274 #if defined(__i386__) || defined(__amd64__) 275 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 276 #endif 277 #if defined(__XSCALE__) 278 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 279 #endif 280 281 #if defined(__mips__) 282 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k); 283 #endif /* __mips__ */ 284 285 #if defined(__powerpc__) 286 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450); 287 #endif 288 289 #undef PMC_CLASS_TABLE_DESC 290 291 static const struct pmc_class_descr **pmc_class_table; 292 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 293 294 static const enum pmc_class *pmc_mdep_class_list; 295 static size_t pmc_mdep_class_list_size; 296 297 /* 298 * Mapping tables, mapping enumeration values to human readable 299 * strings. 300 */ 301 302 static const char * pmc_capability_names[] = { 303 #undef __PMC_CAP 304 #define __PMC_CAP(N,V,D) #N , 305 __PMC_CAPS() 306 }; 307 308 static const char * pmc_class_names[] = { 309 #undef __PMC_CLASS 310 #define __PMC_CLASS(C) #C , 311 __PMC_CLASSES() 312 }; 313 314 struct pmc_cputype_map { 315 enum pmc_cputype pm_cputype; 316 const char *pm_name; 317 }; 318 319 static const struct pmc_cputype_map pmc_cputype_names[] = { 320 #undef __PMC_CPU 321 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 322 __PMC_CPUS() 323 }; 324 325 static const char * pmc_disposition_names[] = { 326 #undef __PMC_DISP 327 #define __PMC_DISP(D) #D , 328 __PMC_DISPOSITIONS() 329 }; 330 331 static const char * pmc_mode_names[] = { 332 #undef __PMC_MODE 333 #define __PMC_MODE(M,N) #M , 334 __PMC_MODES() 335 }; 336 337 static const char * pmc_state_names[] = { 338 #undef __PMC_STATE 339 #define __PMC_STATE(S) #S , 340 __PMC_STATES() 341 }; 342 343 static int pmc_syscall = -1; /* filled in by pmc_init() */ 344 345 static struct pmc_cpuinfo cpu_info; /* filled in by pmc_init() */ 346 347 /* Event masks for events */ 348 struct pmc_masks { 349 const char *pm_name; 350 const uint32_t pm_value; 351 }; 352 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 353 #define NULLMASK { .pm_name = NULL } 354 355 #if defined(__amd64__) || defined(__i386__) 356 static int 357 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask) 358 { 359 const struct pmc_masks *pm; 360 char *q, *r; 361 int c; 362 363 if (pmask == NULL) /* no mask keywords */ 364 return (-1); 365 q = strchr(p, '='); /* skip '=' */ 366 if (*++q == '\0') /* no more data */ 367 return (-1); 368 c = 0; /* count of mask keywords seen */ 369 while ((r = strsep(&q, "+")) != NULL) { 370 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 371 pm++) 372 ; 373 if (pm->pm_name == NULL) /* not found */ 374 return (-1); 375 *evmask |= pm->pm_value; 376 c++; 377 } 378 return (c); 379 } 380 #endif 381 382 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 383 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 384 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 385 386 #if defined(__i386__) 387 388 /* 389 * AMD K7 (Athlon) CPUs. 390 */ 391 392 static struct pmc_event_alias k7_aliases[] = { 393 EV_ALIAS("branches", "k7-retired-branches"), 394 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 395 EV_ALIAS("cycles", "tsc"), 396 EV_ALIAS("dc-misses", "k7-dc-misses"), 397 EV_ALIAS("ic-misses", "k7-ic-misses"), 398 EV_ALIAS("instructions", "k7-retired-instructions"), 399 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 400 EV_ALIAS(NULL, NULL) 401 }; 402 403 #define K7_KW_COUNT "count" 404 #define K7_KW_EDGE "edge" 405 #define K7_KW_INV "inv" 406 #define K7_KW_OS "os" 407 #define K7_KW_UNITMASK "unitmask" 408 #define K7_KW_USR "usr" 409 410 static int 411 k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 412 struct pmc_op_pmcallocate *pmc_config) 413 { 414 char *e, *p, *q; 415 int c, has_unitmask; 416 uint32_t count, unitmask; 417 418 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 419 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 420 421 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 422 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 423 pe == PMC_EV_K7_DC_WRITEBACKS) { 424 has_unitmask = 1; 425 unitmask = AMD_PMC_UNITMASK_MOESI; 426 } else 427 unitmask = has_unitmask = 0; 428 429 while ((p = strsep(&ctrspec, ",")) != NULL) { 430 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 431 q = strchr(p, '='); 432 if (*++q == '\0') /* skip '=' */ 433 return (-1); 434 435 count = strtol(q, &e, 0); 436 if (e == q || *e != '\0') 437 return (-1); 438 439 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 440 pmc_config->pm_md.pm_amd.pm_amd_config |= 441 AMD_PMC_TO_COUNTER(count); 442 443 } else if (KWMATCH(p, K7_KW_EDGE)) { 444 pmc_config->pm_caps |= PMC_CAP_EDGE; 445 } else if (KWMATCH(p, K7_KW_INV)) { 446 pmc_config->pm_caps |= PMC_CAP_INVERT; 447 } else if (KWMATCH(p, K7_KW_OS)) { 448 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 449 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 450 if (has_unitmask == 0) 451 return (-1); 452 unitmask = 0; 453 q = strchr(p, '='); 454 if (*++q == '\0') /* skip '=' */ 455 return (-1); 456 457 while ((c = tolower(*q++)) != 0) 458 if (c == 'm') 459 unitmask |= AMD_PMC_UNITMASK_M; 460 else if (c == 'o') 461 unitmask |= AMD_PMC_UNITMASK_O; 462 else if (c == 'e') 463 unitmask |= AMD_PMC_UNITMASK_E; 464 else if (c == 's') 465 unitmask |= AMD_PMC_UNITMASK_S; 466 else if (c == 'i') 467 unitmask |= AMD_PMC_UNITMASK_I; 468 else if (c == '+') 469 continue; 470 else 471 return (-1); 472 473 if (unitmask == 0) 474 return (-1); 475 476 } else if (KWMATCH(p, K7_KW_USR)) { 477 pmc_config->pm_caps |= PMC_CAP_USER; 478 } else 479 return (-1); 480 } 481 482 if (has_unitmask) { 483 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 484 pmc_config->pm_md.pm_amd.pm_amd_config |= 485 AMD_PMC_TO_UNITMASK(unitmask); 486 } 487 488 return (0); 489 490 } 491 492 #endif 493 494 #if defined(__amd64__) || defined(__i386__) 495 496 /* 497 * Intel Core (Family 6, Model E) PMCs. 498 */ 499 500 static struct pmc_event_alias core_aliases[] = { 501 EV_ALIAS("branches", "iap-br-instr-ret"), 502 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 503 EV_ALIAS("cycles", "tsc-tsc"), 504 EV_ALIAS("ic-misses", "iap-icache-misses"), 505 EV_ALIAS("instructions", "iap-instr-ret"), 506 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 507 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 508 EV_ALIAS(NULL, NULL) 509 }; 510 511 /* 512 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 513 * and Atom (Family 6, model 1CH) PMCs. 514 * 515 * We map aliases to events on the fixed-function counters if these 516 * are present. Note that not all CPUs in this family contain fixed-function 517 * counters. 518 */ 519 520 static struct pmc_event_alias core2_aliases[] = { 521 EV_ALIAS("branches", "iap-br-inst-retired.any"), 522 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 523 EV_ALIAS("cycles", "tsc-tsc"), 524 EV_ALIAS("ic-misses", "iap-l1i-misses"), 525 EV_ALIAS("instructions", "iaf-instr-retired.any"), 526 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 527 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 528 EV_ALIAS(NULL, NULL) 529 }; 530 531 static struct pmc_event_alias core2_aliases_without_iaf[] = { 532 EV_ALIAS("branches", "iap-br-inst-retired.any"), 533 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 534 EV_ALIAS("cycles", "tsc-tsc"), 535 EV_ALIAS("ic-misses", "iap-l1i-misses"), 536 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 537 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 538 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 539 EV_ALIAS(NULL, NULL) 540 }; 541 542 #define atom_aliases core2_aliases 543 #define atom_aliases_without_iaf core2_aliases_without_iaf 544 #define corei7_aliases core2_aliases 545 #define corei7_aliases_without_iaf core2_aliases_without_iaf 546 #define sandybridge_aliases core2_aliases 547 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf 548 #define westmere_aliases core2_aliases 549 #define westmere_aliases_without_iaf core2_aliases_without_iaf 550 551 #define IAF_KW_OS "os" 552 #define IAF_KW_USR "usr" 553 #define IAF_KW_ANYTHREAD "anythread" 554 555 /* 556 * Parse an event specifier for Intel fixed function counters. 557 */ 558 static int 559 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 560 struct pmc_op_pmcallocate *pmc_config) 561 { 562 char *p; 563 564 (void) pe; 565 566 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 567 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 568 569 while ((p = strsep(&ctrspec, ",")) != NULL) { 570 if (KWMATCH(p, IAF_KW_OS)) 571 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 572 else if (KWMATCH(p, IAF_KW_USR)) 573 pmc_config->pm_caps |= PMC_CAP_USER; 574 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 575 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 576 else 577 return (-1); 578 } 579 580 return (0); 581 } 582 583 /* 584 * Core/Core2 support. 585 */ 586 587 #define IAP_KW_AGENT "agent" 588 #define IAP_KW_ANYTHREAD "anythread" 589 #define IAP_KW_CACHESTATE "cachestate" 590 #define IAP_KW_CMASK "cmask" 591 #define IAP_KW_CORE "core" 592 #define IAP_KW_EDGE "edge" 593 #define IAP_KW_INV "inv" 594 #define IAP_KW_OS "os" 595 #define IAP_KW_PREFETCH "prefetch" 596 #define IAP_KW_SNOOPRESPONSE "snoopresponse" 597 #define IAP_KW_SNOOPTYPE "snooptype" 598 #define IAP_KW_TRANSITION "trans" 599 #define IAP_KW_USR "usr" 600 #define IAP_KW_RSP "rsp" 601 602 static struct pmc_masks iap_core_mask[] = { 603 PMCMASK(all, (0x3 << 14)), 604 PMCMASK(this, (0x1 << 14)), 605 NULLMASK 606 }; 607 608 static struct pmc_masks iap_agent_mask[] = { 609 PMCMASK(this, 0), 610 PMCMASK(any, (0x1 << 13)), 611 NULLMASK 612 }; 613 614 static struct pmc_masks iap_prefetch_mask[] = { 615 PMCMASK(both, (0x3 << 12)), 616 PMCMASK(only, (0x1 << 12)), 617 PMCMASK(exclude, 0), 618 NULLMASK 619 }; 620 621 static struct pmc_masks iap_cachestate_mask[] = { 622 PMCMASK(i, (1 << 8)), 623 PMCMASK(s, (1 << 9)), 624 PMCMASK(e, (1 << 10)), 625 PMCMASK(m, (1 << 11)), 626 NULLMASK 627 }; 628 629 static struct pmc_masks iap_snoopresponse_mask[] = { 630 PMCMASK(clean, (1 << 8)), 631 PMCMASK(hit, (1 << 9)), 632 PMCMASK(hitm, (1 << 11)), 633 NULLMASK 634 }; 635 636 static struct pmc_masks iap_snooptype_mask[] = { 637 PMCMASK(cmp2s, (1 << 8)), 638 PMCMASK(cmp2i, (1 << 9)), 639 NULLMASK 640 }; 641 642 static struct pmc_masks iap_transition_mask[] = { 643 PMCMASK(any, 0x00), 644 PMCMASK(frequency, 0x10), 645 NULLMASK 646 }; 647 648 static struct pmc_masks iap_rsp_mask[] = { 649 PMCMASK(DMND_DATA_RD, (1 << 0)), 650 PMCMASK(DMND_RFO, (1 << 1)), 651 PMCMASK(DMND_IFETCH, (1 << 2)), 652 PMCMASK(WB, (1 << 3)), 653 PMCMASK(PF_DATA_RD, (1 << 4)), 654 PMCMASK(PF_RFO, (1 << 5)), 655 PMCMASK(PF_IFETCH, (1 << 6)), 656 PMCMASK(OTHER, (1 << 7)), 657 PMCMASK(UNCORE_HIT, (1 << 8)), 658 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 659 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 660 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 661 PMCMASK(REMOTE_DRAM, (1 << 13)), 662 PMCMASK(LOCAL_DRAM, (1 << 14)), 663 PMCMASK(NON_DRAM, (1 << 15)), 664 NULLMASK 665 }; 666 667 static int 668 iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 669 struct pmc_op_pmcallocate *pmc_config) 670 { 671 char *e, *p, *q; 672 uint32_t cachestate, evmask, rsp; 673 int count, n; 674 675 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 676 PMC_CAP_QUALIFIER); 677 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 678 679 cachestate = evmask = rsp = 0; 680 681 /* Parse additional modifiers if present */ 682 while ((p = strsep(&ctrspec, ",")) != NULL) { 683 684 n = 0; 685 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 686 q = strchr(p, '='); 687 if (*++q == '\0') /* skip '=' */ 688 return (-1); 689 count = strtol(q, &e, 0); 690 if (e == q || *e != '\0') 691 return (-1); 692 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 693 pmc_config->pm_md.pm_iap.pm_iap_config |= 694 IAP_CMASK(count); 695 } else if (KWMATCH(p, IAP_KW_EDGE)) { 696 pmc_config->pm_caps |= PMC_CAP_EDGE; 697 } else if (KWMATCH(p, IAP_KW_INV)) { 698 pmc_config->pm_caps |= PMC_CAP_INVERT; 699 } else if (KWMATCH(p, IAP_KW_OS)) { 700 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 701 } else if (KWMATCH(p, IAP_KW_USR)) { 702 pmc_config->pm_caps |= PMC_CAP_USER; 703 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 704 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 705 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 706 n = pmc_parse_mask(iap_core_mask, p, &evmask); 707 if (n != 1) 708 return (-1); 709 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 710 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 711 if (n != 1) 712 return (-1); 713 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 714 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 715 if (n != 1) 716 return (-1); 717 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 718 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 719 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 720 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 721 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 722 if (n != 1) 723 return (-1); 724 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 725 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 726 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 727 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 728 n = pmc_parse_mask(iap_snoopresponse_mask, p, 729 &evmask); 730 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 731 n = pmc_parse_mask(iap_snooptype_mask, p, 732 &evmask); 733 } else 734 return (-1); 735 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 736 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { 737 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 738 n = pmc_parse_mask(iap_rsp_mask, p, &rsp); 739 } else 740 return (-1); 741 } else 742 return (-1); 743 744 if (n < 0) /* Parsing failed. */ 745 return (-1); 746 } 747 748 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 749 750 /* 751 * If the event requires a 'cachestate' qualifier but was not 752 * specified by the user, use a sensible default. 753 */ 754 switch (pe) { 755 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 756 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 757 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 758 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 759 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 760 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 761 case PMC_EV_IAP_EVENT_32H: /* Core */ 762 case PMC_EV_IAP_EVENT_40H: /* Core */ 763 case PMC_EV_IAP_EVENT_41H: /* Core */ 764 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 765 if (cachestate == 0) 766 cachestate = (0xF << 8); 767 break; 768 case PMC_EV_IAP_EVENT_77H: /* Atom */ 769 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 770 * Atom processor 771 */ 772 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 773 cachestate = (0xF << 8); 774 break; 775 default: 776 break; 777 } 778 779 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 780 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 781 782 return (0); 783 } 784 785 /* 786 * Intel Uncore. 787 */ 788 789 static int 790 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 791 struct pmc_op_pmcallocate *pmc_config) 792 { 793 (void) pe; 794 (void) ctrspec; 795 796 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 797 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 798 799 return (0); 800 } 801 802 #define UCP_KW_CMASK "cmask" 803 #define UCP_KW_EDGE "edge" 804 #define UCP_KW_INV "inv" 805 806 static int 807 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 808 struct pmc_op_pmcallocate *pmc_config) 809 { 810 char *e, *p, *q; 811 int count, n; 812 813 (void) pe; 814 815 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 816 PMC_CAP_QUALIFIER); 817 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 818 819 /* Parse additional modifiers if present */ 820 while ((p = strsep(&ctrspec, ",")) != NULL) { 821 822 n = 0; 823 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 824 q = strchr(p, '='); 825 if (*++q == '\0') /* skip '=' */ 826 return (-1); 827 count = strtol(q, &e, 0); 828 if (e == q || *e != '\0') 829 return (-1); 830 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 831 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 832 UCP_CMASK(count); 833 } else if (KWMATCH(p, UCP_KW_EDGE)) { 834 pmc_config->pm_caps |= PMC_CAP_EDGE; 835 } else if (KWMATCH(p, UCP_KW_INV)) { 836 pmc_config->pm_caps |= PMC_CAP_INVERT; 837 } else 838 return (-1); 839 840 if (n < 0) /* Parsing failed. */ 841 return (-1); 842 } 843 844 return (0); 845 } 846 847 /* 848 * AMD K8 PMCs. 849 * 850 * These are very similar to AMD K7 PMCs, but support more kinds of 851 * events. 852 */ 853 854 static struct pmc_event_alias k8_aliases[] = { 855 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 856 EV_ALIAS("branch-mispredicts", 857 "k8-fr-retired-taken-branches-mispredicted"), 858 EV_ALIAS("cycles", "tsc"), 859 EV_ALIAS("dc-misses", "k8-dc-miss"), 860 EV_ALIAS("ic-misses", "k8-ic-miss"), 861 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 862 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 863 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 864 EV_ALIAS(NULL, NULL) 865 }; 866 867 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 868 869 /* 870 * Parsing tables 871 */ 872 873 /* fp dispatched fpu ops */ 874 static const struct pmc_masks k8_mask_fdfo[] = { 875 __K8MASK(add-pipe-excluding-junk-ops, 0), 876 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 877 __K8MASK(store-pipe-excluding-junk-ops, 2), 878 __K8MASK(add-pipe-junk-ops, 3), 879 __K8MASK(multiply-pipe-junk-ops, 4), 880 __K8MASK(store-pipe-junk-ops, 5), 881 NULLMASK 882 }; 883 884 /* ls segment register loads */ 885 static const struct pmc_masks k8_mask_lsrl[] = { 886 __K8MASK(es, 0), 887 __K8MASK(cs, 1), 888 __K8MASK(ss, 2), 889 __K8MASK(ds, 3), 890 __K8MASK(fs, 4), 891 __K8MASK(gs, 5), 892 __K8MASK(hs, 6), 893 NULLMASK 894 }; 895 896 /* ls locked operation */ 897 static const struct pmc_masks k8_mask_llo[] = { 898 __K8MASK(locked-instructions, 0), 899 __K8MASK(cycles-in-request, 1), 900 __K8MASK(cycles-to-complete, 2), 901 NULLMASK 902 }; 903 904 /* dc refill from {l2,system} and dc copyback */ 905 static const struct pmc_masks k8_mask_dc[] = { 906 __K8MASK(invalid, 0), 907 __K8MASK(shared, 1), 908 __K8MASK(exclusive, 2), 909 __K8MASK(owner, 3), 910 __K8MASK(modified, 4), 911 NULLMASK 912 }; 913 914 /* dc one bit ecc error */ 915 static const struct pmc_masks k8_mask_dobee[] = { 916 __K8MASK(scrubber, 0), 917 __K8MASK(piggyback, 1), 918 NULLMASK 919 }; 920 921 /* dc dispatched prefetch instructions */ 922 static const struct pmc_masks k8_mask_ddpi[] = { 923 __K8MASK(load, 0), 924 __K8MASK(store, 1), 925 __K8MASK(nta, 2), 926 NULLMASK 927 }; 928 929 /* dc dcache accesses by locks */ 930 static const struct pmc_masks k8_mask_dabl[] = { 931 __K8MASK(accesses, 0), 932 __K8MASK(misses, 1), 933 NULLMASK 934 }; 935 936 /* bu internal l2 request */ 937 static const struct pmc_masks k8_mask_bilr[] = { 938 __K8MASK(ic-fill, 0), 939 __K8MASK(dc-fill, 1), 940 __K8MASK(tlb-reload, 2), 941 __K8MASK(tag-snoop, 3), 942 __K8MASK(cancelled, 4), 943 NULLMASK 944 }; 945 946 /* bu fill request l2 miss */ 947 static const struct pmc_masks k8_mask_bfrlm[] = { 948 __K8MASK(ic-fill, 0), 949 __K8MASK(dc-fill, 1), 950 __K8MASK(tlb-reload, 2), 951 NULLMASK 952 }; 953 954 /* bu fill into l2 */ 955 static const struct pmc_masks k8_mask_bfil[] = { 956 __K8MASK(dirty-l2-victim, 0), 957 __K8MASK(victim-from-l2, 1), 958 NULLMASK 959 }; 960 961 /* fr retired fpu instructions */ 962 static const struct pmc_masks k8_mask_frfi[] = { 963 __K8MASK(x87, 0), 964 __K8MASK(mmx-3dnow, 1), 965 __K8MASK(packed-sse-sse2, 2), 966 __K8MASK(scalar-sse-sse2, 3), 967 NULLMASK 968 }; 969 970 /* fr retired fastpath double op instructions */ 971 static const struct pmc_masks k8_mask_frfdoi[] = { 972 __K8MASK(low-op-pos-0, 0), 973 __K8MASK(low-op-pos-1, 1), 974 __K8MASK(low-op-pos-2, 2), 975 NULLMASK 976 }; 977 978 /* fr fpu exceptions */ 979 static const struct pmc_masks k8_mask_ffe[] = { 980 __K8MASK(x87-reclass-microfaults, 0), 981 __K8MASK(sse-retype-microfaults, 1), 982 __K8MASK(sse-reclass-microfaults, 2), 983 __K8MASK(sse-and-x87-microtraps, 3), 984 NULLMASK 985 }; 986 987 /* nb memory controller page access event */ 988 static const struct pmc_masks k8_mask_nmcpae[] = { 989 __K8MASK(page-hit, 0), 990 __K8MASK(page-miss, 1), 991 __K8MASK(page-conflict, 2), 992 NULLMASK 993 }; 994 995 /* nb memory controller turnaround */ 996 static const struct pmc_masks k8_mask_nmct[] = { 997 __K8MASK(dimm-turnaround, 0), 998 __K8MASK(read-to-write-turnaround, 1), 999 __K8MASK(write-to-read-turnaround, 2), 1000 NULLMASK 1001 }; 1002 1003 /* nb memory controller bypass saturation */ 1004 static const struct pmc_masks k8_mask_nmcbs[] = { 1005 __K8MASK(memory-controller-hi-pri-bypass, 0), 1006 __K8MASK(memory-controller-lo-pri-bypass, 1), 1007 __K8MASK(dram-controller-interface-bypass, 2), 1008 __K8MASK(dram-controller-queue-bypass, 3), 1009 NULLMASK 1010 }; 1011 1012 /* nb sized commands */ 1013 static const struct pmc_masks k8_mask_nsc[] = { 1014 __K8MASK(nonpostwrszbyte, 0), 1015 __K8MASK(nonpostwrszdword, 1), 1016 __K8MASK(postwrszbyte, 2), 1017 __K8MASK(postwrszdword, 3), 1018 __K8MASK(rdszbyte, 4), 1019 __K8MASK(rdszdword, 5), 1020 __K8MASK(rdmodwr, 6), 1021 NULLMASK 1022 }; 1023 1024 /* nb probe result */ 1025 static const struct pmc_masks k8_mask_npr[] = { 1026 __K8MASK(probe-miss, 0), 1027 __K8MASK(probe-hit, 1), 1028 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1029 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1030 NULLMASK 1031 }; 1032 1033 /* nb hypertransport bus bandwidth */ 1034 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1035 __K8MASK(command, 0), 1036 __K8MASK(data, 1), 1037 __K8MASK(buffer-release, 2), 1038 __K8MASK(nop, 3), 1039 NULLMASK 1040 }; 1041 1042 #undef __K8MASK 1043 1044 #define K8_KW_COUNT "count" 1045 #define K8_KW_EDGE "edge" 1046 #define K8_KW_INV "inv" 1047 #define K8_KW_MASK "mask" 1048 #define K8_KW_OS "os" 1049 #define K8_KW_USR "usr" 1050 1051 static int 1052 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1053 struct pmc_op_pmcallocate *pmc_config) 1054 { 1055 char *e, *p, *q; 1056 int n; 1057 uint32_t count, evmask; 1058 const struct pmc_masks *pm, *pmask; 1059 1060 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1061 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1062 1063 pmask = NULL; 1064 evmask = 0; 1065 1066 #define __K8SETMASK(M) pmask = k8_mask_##M 1067 1068 /* setup parsing tables */ 1069 switch (pe) { 1070 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1071 __K8SETMASK(fdfo); 1072 break; 1073 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1074 __K8SETMASK(lsrl); 1075 break; 1076 case PMC_EV_K8_LS_LOCKED_OPERATION: 1077 __K8SETMASK(llo); 1078 break; 1079 case PMC_EV_K8_DC_REFILL_FROM_L2: 1080 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1081 case PMC_EV_K8_DC_COPYBACK: 1082 __K8SETMASK(dc); 1083 break; 1084 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1085 __K8SETMASK(dobee); 1086 break; 1087 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1088 __K8SETMASK(ddpi); 1089 break; 1090 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1091 __K8SETMASK(dabl); 1092 break; 1093 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1094 __K8SETMASK(bilr); 1095 break; 1096 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1097 __K8SETMASK(bfrlm); 1098 break; 1099 case PMC_EV_K8_BU_FILL_INTO_L2: 1100 __K8SETMASK(bfil); 1101 break; 1102 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1103 __K8SETMASK(frfi); 1104 break; 1105 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1106 __K8SETMASK(frfdoi); 1107 break; 1108 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1109 __K8SETMASK(ffe); 1110 break; 1111 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1112 __K8SETMASK(nmcpae); 1113 break; 1114 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1115 __K8SETMASK(nmct); 1116 break; 1117 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1118 __K8SETMASK(nmcbs); 1119 break; 1120 case PMC_EV_K8_NB_SIZED_COMMANDS: 1121 __K8SETMASK(nsc); 1122 break; 1123 case PMC_EV_K8_NB_PROBE_RESULT: 1124 __K8SETMASK(npr); 1125 break; 1126 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1127 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1128 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1129 __K8SETMASK(nhbb); 1130 break; 1131 1132 default: 1133 break; /* no options defined */ 1134 } 1135 1136 while ((p = strsep(&ctrspec, ",")) != NULL) { 1137 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1138 q = strchr(p, '='); 1139 if (*++q == '\0') /* skip '=' */ 1140 return (-1); 1141 1142 count = strtol(q, &e, 0); 1143 if (e == q || *e != '\0') 1144 return (-1); 1145 1146 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1147 pmc_config->pm_md.pm_amd.pm_amd_config |= 1148 AMD_PMC_TO_COUNTER(count); 1149 1150 } else if (KWMATCH(p, K8_KW_EDGE)) { 1151 pmc_config->pm_caps |= PMC_CAP_EDGE; 1152 } else if (KWMATCH(p, K8_KW_INV)) { 1153 pmc_config->pm_caps |= PMC_CAP_INVERT; 1154 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1155 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1156 return (-1); 1157 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1158 } else if (KWMATCH(p, K8_KW_OS)) { 1159 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1160 } else if (KWMATCH(p, K8_KW_USR)) { 1161 pmc_config->pm_caps |= PMC_CAP_USER; 1162 } else 1163 return (-1); 1164 } 1165 1166 /* other post processing */ 1167 switch (pe) { 1168 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1169 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1170 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1171 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1172 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1173 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1174 /* XXX only available in rev B and later */ 1175 break; 1176 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1177 /* XXX only available in rev C and later */ 1178 break; 1179 case PMC_EV_K8_LS_LOCKED_OPERATION: 1180 /* XXX CPU Rev A,B evmask is to be zero */ 1181 if (evmask & (evmask - 1)) /* > 1 bit set */ 1182 return (-1); 1183 if (evmask == 0) { 1184 evmask = 0x01; /* Rev C and later: #instrs */ 1185 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1186 } 1187 break; 1188 default: 1189 if (evmask == 0 && pmask != NULL) { 1190 for (pm = pmask; pm->pm_name; pm++) 1191 evmask |= pm->pm_value; 1192 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1193 } 1194 } 1195 1196 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1197 pmc_config->pm_md.pm_amd.pm_amd_config = 1198 AMD_PMC_TO_UNITMASK(evmask); 1199 1200 return (0); 1201 } 1202 1203 #endif 1204 1205 #if defined(__amd64__) || defined(__i386__) 1206 1207 /* 1208 * Intel P4 PMCs 1209 */ 1210 1211 static struct pmc_event_alias p4_aliases[] = { 1212 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1213 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1214 EV_ALIAS("cycles", "tsc"), 1215 EV_ALIAS("instructions", 1216 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1217 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1218 EV_ALIAS(NULL, NULL) 1219 }; 1220 1221 #define P4_KW_ACTIVE "active" 1222 #define P4_KW_ACTIVE_ANY "any" 1223 #define P4_KW_ACTIVE_BOTH "both" 1224 #define P4_KW_ACTIVE_NONE "none" 1225 #define P4_KW_ACTIVE_SINGLE "single" 1226 #define P4_KW_BUSREQTYPE "busreqtype" 1227 #define P4_KW_CASCADE "cascade" 1228 #define P4_KW_EDGE "edge" 1229 #define P4_KW_INV "complement" 1230 #define P4_KW_OS "os" 1231 #define P4_KW_MASK "mask" 1232 #define P4_KW_PRECISE "precise" 1233 #define P4_KW_TAG "tag" 1234 #define P4_KW_THRESHOLD "threshold" 1235 #define P4_KW_USR "usr" 1236 1237 #define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1238 1239 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1240 __P4MASK(dd, 0), 1241 __P4MASK(db, 1), 1242 __P4MASK(di, 2), 1243 __P4MASK(bd, 3), 1244 __P4MASK(bb, 4), 1245 __P4MASK(bi, 5), 1246 __P4MASK(id, 6), 1247 __P4MASK(ib, 7), 1248 NULLMASK 1249 }; 1250 1251 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1252 __P4MASK(tcmiss, 0), 1253 NULLMASK, 1254 }; 1255 1256 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1257 __P4MASK(hit, 0), 1258 __P4MASK(miss, 1), 1259 __P4MASK(hit-uc, 2), 1260 NULLMASK 1261 }; 1262 1263 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1264 __P4MASK(st-rb-full, 2), 1265 __P4MASK(64k-conf, 3), 1266 NULLMASK 1267 }; 1268 1269 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1270 __P4MASK(lsc, 0), 1271 __P4MASK(ssc, 1), 1272 NULLMASK 1273 }; 1274 1275 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1276 __P4MASK(split-ld, 1), 1277 NULLMASK 1278 }; 1279 1280 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1281 __P4MASK(split-st, 1), 1282 NULLMASK 1283 }; 1284 1285 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1286 __P4MASK(no-sta, 1), 1287 __P4MASK(no-std, 3), 1288 __P4MASK(partial-data, 4), 1289 __P4MASK(unalgn-addr, 5), 1290 NULLMASK 1291 }; 1292 1293 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1294 __P4MASK(dtmiss, 0), 1295 __P4MASK(itmiss, 1), 1296 NULLMASK 1297 }; 1298 1299 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1300 __P4MASK(rd-2ndl-hits, 0), 1301 __P4MASK(rd-2ndl-hite, 1), 1302 __P4MASK(rd-2ndl-hitm, 2), 1303 __P4MASK(rd-3rdl-hits, 3), 1304 __P4MASK(rd-3rdl-hite, 4), 1305 __P4MASK(rd-3rdl-hitm, 5), 1306 __P4MASK(rd-2ndl-miss, 8), 1307 __P4MASK(rd-3rdl-miss, 9), 1308 __P4MASK(wr-2ndl-miss, 10), 1309 NULLMASK 1310 }; 1311 1312 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1313 __P4MASK(all-read, 5), 1314 __P4MASK(all-write, 6), 1315 __P4MASK(mem-uc, 7), 1316 __P4MASK(mem-wc, 8), 1317 __P4MASK(mem-wt, 9), 1318 __P4MASK(mem-wp, 10), 1319 __P4MASK(mem-wb, 11), 1320 __P4MASK(own, 13), 1321 __P4MASK(other, 14), 1322 __P4MASK(prefetch, 15), 1323 NULLMASK 1324 }; 1325 1326 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1327 __P4MASK(all-read, 5), 1328 __P4MASK(all-write, 6), 1329 __P4MASK(mem-uc, 7), 1330 __P4MASK(mem-wc, 8), 1331 __P4MASK(mem-wt, 9), 1332 __P4MASK(mem-wp, 10), 1333 __P4MASK(mem-wb, 11), 1334 __P4MASK(own, 13), 1335 __P4MASK(other, 14), 1336 __P4MASK(prefetch, 15), 1337 NULLMASK 1338 }; 1339 1340 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1341 __P4MASK(drdy-drv, 0), 1342 __P4MASK(drdy-own, 1), 1343 __P4MASK(drdy-other, 2), 1344 __P4MASK(dbsy-drv, 3), 1345 __P4MASK(dbsy-own, 4), 1346 __P4MASK(dbsy-other, 5), 1347 NULLMASK 1348 }; 1349 1350 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1351 __P4MASK(req-type0, 0), 1352 __P4MASK(req-type1, 1), 1353 __P4MASK(req-len0, 2), 1354 __P4MASK(req-len1, 3), 1355 __P4MASK(req-io-type, 5), 1356 __P4MASK(req-lock-type, 6), 1357 __P4MASK(req-cache-type, 7), 1358 __P4MASK(req-split-type, 8), 1359 __P4MASK(req-dem-type, 9), 1360 __P4MASK(req-ord-type, 10), 1361 __P4MASK(mem-type0, 11), 1362 __P4MASK(mem-type1, 12), 1363 __P4MASK(mem-type2, 13), 1364 NULLMASK 1365 }; 1366 1367 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1368 __P4MASK(all, 15), 1369 NULLMASK 1370 }; 1371 1372 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1373 __P4MASK(all, 15), 1374 NULLMASK 1375 }; 1376 1377 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1378 __P4MASK(all, 15), 1379 NULLMASK 1380 }; 1381 1382 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1383 __P4MASK(all, 15), 1384 NULLMASK 1385 }; 1386 1387 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1388 __P4MASK(all, 15), 1389 NULLMASK 1390 }; 1391 1392 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1393 __P4MASK(all, 15), 1394 NULLMASK 1395 }; 1396 1397 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1398 __P4MASK(all, 15), 1399 NULLMASK 1400 }; 1401 1402 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1403 __P4MASK(all, 15), 1404 NULLMASK 1405 }; 1406 1407 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1408 __P4MASK(allp0, 3), 1409 __P4MASK(allp2, 4), 1410 NULLMASK 1411 }; 1412 1413 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1414 __P4MASK(running, 0), 1415 NULLMASK 1416 }; 1417 1418 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1419 __P4MASK(cisc, 0), 1420 NULLMASK 1421 }; 1422 1423 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1424 __P4MASK(from-tc-build, 0), 1425 __P4MASK(from-tc-deliver, 1), 1426 __P4MASK(from-rom, 2), 1427 NULLMASK 1428 }; 1429 1430 static const struct pmc_masks p4_mask_rmbt[] = { 1431 /* retired mispred branch type */ 1432 __P4MASK(conditional, 1), 1433 __P4MASK(call, 2), 1434 __P4MASK(return, 3), 1435 __P4MASK(indirect, 4), 1436 NULLMASK 1437 }; 1438 1439 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1440 __P4MASK(conditional, 1), 1441 __P4MASK(call, 2), 1442 __P4MASK(retired, 3), 1443 __P4MASK(indirect, 4), 1444 NULLMASK 1445 }; 1446 1447 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1448 __P4MASK(sbfull, 5), 1449 NULLMASK 1450 }; 1451 1452 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1453 __P4MASK(wcb-evicts, 0), 1454 __P4MASK(wcb-full-evict, 1), 1455 NULLMASK 1456 }; 1457 1458 static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1459 __P4MASK(nbogus, 0), 1460 __P4MASK(bogus, 1), 1461 NULLMASK 1462 }; 1463 1464 static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1465 __P4MASK(nbogus0, 0), 1466 __P4MASK(nbogus1, 1), 1467 __P4MASK(nbogus2, 2), 1468 __P4MASK(nbogus3, 3), 1469 __P4MASK(bogus0, 4), 1470 __P4MASK(bogus1, 5), 1471 __P4MASK(bogus2, 6), 1472 __P4MASK(bogus3, 7), 1473 NULLMASK 1474 }; 1475 1476 static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1477 __P4MASK(nbogus, 0), 1478 __P4MASK(bogus, 1), 1479 NULLMASK 1480 }; 1481 1482 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1483 __P4MASK(nbogusntag, 0), 1484 __P4MASK(nbogustag, 1), 1485 __P4MASK(bogusntag, 2), 1486 __P4MASK(bogustag, 3), 1487 NULLMASK 1488 }; 1489 1490 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1491 __P4MASK(nbogus, 0), 1492 __P4MASK(bogus, 1), 1493 NULLMASK 1494 }; 1495 1496 static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1497 __P4MASK(tagloads, 1), 1498 __P4MASK(tagstores, 2), 1499 NULLMASK 1500 }; 1501 1502 static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1503 __P4MASK(mmnp, 0), 1504 __P4MASK(mmnm, 1), 1505 __P4MASK(mmtp, 2), 1506 __P4MASK(mmtm, 3), 1507 NULLMASK 1508 }; 1509 1510 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1511 __P4MASK(nbogus, 0), 1512 NULLMASK 1513 }; 1514 1515 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1516 __P4MASK(fpsu, 0), 1517 __P4MASK(fpso, 1), 1518 __P4MASK(poao, 2), 1519 __P4MASK(poau, 3), 1520 __P4MASK(prea, 4), 1521 NULLMASK 1522 }; 1523 1524 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1525 __P4MASK(clear, 0), 1526 __P4MASK(moclear, 2), 1527 __P4MASK(smclear, 3), 1528 NULLMASK 1529 }; 1530 1531 /* P4 event parser */ 1532 static int 1533 p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1534 struct pmc_op_pmcallocate *pmc_config) 1535 { 1536 1537 char *e, *p, *q; 1538 int count, has_tag, has_busreqtype, n; 1539 uint32_t evmask, cccractivemask; 1540 const struct pmc_masks *pm, *pmask; 1541 1542 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1543 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1544 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1545 1546 pmask = NULL; 1547 evmask = 0; 1548 cccractivemask = 0x3; 1549 has_tag = has_busreqtype = 0; 1550 1551 #define __P4SETMASK(M) do { \ 1552 pmask = p4_mask_##M; \ 1553 } while (0) 1554 1555 switch (pe) { 1556 case PMC_EV_P4_TC_DELIVER_MODE: 1557 __P4SETMASK(tcdm); 1558 break; 1559 case PMC_EV_P4_BPU_FETCH_REQUEST: 1560 __P4SETMASK(bfr); 1561 break; 1562 case PMC_EV_P4_ITLB_REFERENCE: 1563 __P4SETMASK(ir); 1564 break; 1565 case PMC_EV_P4_MEMORY_CANCEL: 1566 __P4SETMASK(memcan); 1567 break; 1568 case PMC_EV_P4_MEMORY_COMPLETE: 1569 __P4SETMASK(memcomp); 1570 break; 1571 case PMC_EV_P4_LOAD_PORT_REPLAY: 1572 __P4SETMASK(lpr); 1573 break; 1574 case PMC_EV_P4_STORE_PORT_REPLAY: 1575 __P4SETMASK(spr); 1576 break; 1577 case PMC_EV_P4_MOB_LOAD_REPLAY: 1578 __P4SETMASK(mlr); 1579 break; 1580 case PMC_EV_P4_PAGE_WALK_TYPE: 1581 __P4SETMASK(pwt); 1582 break; 1583 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1584 __P4SETMASK(bcr); 1585 break; 1586 case PMC_EV_P4_IOQ_ALLOCATION: 1587 __P4SETMASK(ia); 1588 has_busreqtype = 1; 1589 break; 1590 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1591 __P4SETMASK(iae); 1592 has_busreqtype = 1; 1593 break; 1594 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1595 __P4SETMASK(fda); 1596 break; 1597 case PMC_EV_P4_BSQ_ALLOCATION: 1598 __P4SETMASK(ba); 1599 break; 1600 case PMC_EV_P4_SSE_INPUT_ASSIST: 1601 __P4SETMASK(sia); 1602 break; 1603 case PMC_EV_P4_PACKED_SP_UOP: 1604 __P4SETMASK(psu); 1605 break; 1606 case PMC_EV_P4_PACKED_DP_UOP: 1607 __P4SETMASK(pdu); 1608 break; 1609 case PMC_EV_P4_SCALAR_SP_UOP: 1610 __P4SETMASK(ssu); 1611 break; 1612 case PMC_EV_P4_SCALAR_DP_UOP: 1613 __P4SETMASK(sdu); 1614 break; 1615 case PMC_EV_P4_64BIT_MMX_UOP: 1616 __P4SETMASK(64bmu); 1617 break; 1618 case PMC_EV_P4_128BIT_MMX_UOP: 1619 __P4SETMASK(128bmu); 1620 break; 1621 case PMC_EV_P4_X87_FP_UOP: 1622 __P4SETMASK(xfu); 1623 break; 1624 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1625 __P4SETMASK(xsmu); 1626 break; 1627 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1628 __P4SETMASK(gpe); 1629 break; 1630 case PMC_EV_P4_TC_MS_XFER: 1631 __P4SETMASK(tmx); 1632 break; 1633 case PMC_EV_P4_UOP_QUEUE_WRITES: 1634 __P4SETMASK(uqw); 1635 break; 1636 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1637 __P4SETMASK(rmbt); 1638 break; 1639 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1640 __P4SETMASK(rbt); 1641 break; 1642 case PMC_EV_P4_RESOURCE_STALL: 1643 __P4SETMASK(rs); 1644 break; 1645 case PMC_EV_P4_WC_BUFFER: 1646 __P4SETMASK(wb); 1647 break; 1648 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1649 case PMC_EV_P4_B2B_CYCLES: 1650 case PMC_EV_P4_BNR: 1651 case PMC_EV_P4_SNOOP: 1652 case PMC_EV_P4_RESPONSE: 1653 break; 1654 case PMC_EV_P4_FRONT_END_EVENT: 1655 __P4SETMASK(fee); 1656 break; 1657 case PMC_EV_P4_EXECUTION_EVENT: 1658 __P4SETMASK(ee); 1659 break; 1660 case PMC_EV_P4_REPLAY_EVENT: 1661 __P4SETMASK(re); 1662 break; 1663 case PMC_EV_P4_INSTR_RETIRED: 1664 __P4SETMASK(insret); 1665 break; 1666 case PMC_EV_P4_UOPS_RETIRED: 1667 __P4SETMASK(ur); 1668 break; 1669 case PMC_EV_P4_UOP_TYPE: 1670 __P4SETMASK(ut); 1671 break; 1672 case PMC_EV_P4_BRANCH_RETIRED: 1673 __P4SETMASK(br); 1674 break; 1675 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1676 __P4SETMASK(mbr); 1677 break; 1678 case PMC_EV_P4_X87_ASSIST: 1679 __P4SETMASK(xa); 1680 break; 1681 case PMC_EV_P4_MACHINE_CLEAR: 1682 __P4SETMASK(machclr); 1683 break; 1684 default: 1685 return (-1); 1686 } 1687 1688 /* process additional flags */ 1689 while ((p = strsep(&ctrspec, ",")) != NULL) { 1690 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1691 q = strchr(p, '='); 1692 if (*++q == '\0') /* skip '=' */ 1693 return (-1); 1694 1695 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1696 cccractivemask = 0x0; 1697 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1698 cccractivemask = 0x1; 1699 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1700 cccractivemask = 0x2; 1701 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1702 cccractivemask = 0x3; 1703 else 1704 return (-1); 1705 1706 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1707 if (has_busreqtype == 0) 1708 return (-1); 1709 1710 q = strchr(p, '='); 1711 if (*++q == '\0') /* skip '=' */ 1712 return (-1); 1713 1714 count = strtol(q, &e, 0); 1715 if (e == q || *e != '\0') 1716 return (-1); 1717 evmask = (evmask & ~0x1F) | (count & 0x1F); 1718 } else if (KWMATCH(p, P4_KW_CASCADE)) 1719 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1720 else if (KWMATCH(p, P4_KW_EDGE)) 1721 pmc_config->pm_caps |= PMC_CAP_EDGE; 1722 else if (KWMATCH(p, P4_KW_INV)) 1723 pmc_config->pm_caps |= PMC_CAP_INVERT; 1724 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1725 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1726 return (-1); 1727 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1728 } else if (KWMATCH(p, P4_KW_OS)) 1729 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1730 else if (KWMATCH(p, P4_KW_PRECISE)) 1731 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1732 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1733 if (has_tag == 0) 1734 return (-1); 1735 1736 q = strchr(p, '='); 1737 if (*++q == '\0') /* skip '=' */ 1738 return (-1); 1739 1740 count = strtol(q, &e, 0); 1741 if (e == q || *e != '\0') 1742 return (-1); 1743 1744 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1745 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1746 P4_ESCR_TO_TAG_VALUE(count); 1747 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1748 q = strchr(p, '='); 1749 if (*++q == '\0') /* skip '=' */ 1750 return (-1); 1751 1752 count = strtol(q, &e, 0); 1753 if (e == q || *e != '\0') 1754 return (-1); 1755 1756 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1757 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1758 ~P4_CCCR_THRESHOLD_MASK; 1759 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1760 P4_CCCR_TO_THRESHOLD(count); 1761 } else if (KWMATCH(p, P4_KW_USR)) 1762 pmc_config->pm_caps |= PMC_CAP_USER; 1763 else 1764 return (-1); 1765 } 1766 1767 /* other post processing */ 1768 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1769 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1770 pe == PMC_EV_P4_BSQ_ALLOCATION) 1771 pmc_config->pm_caps |= PMC_CAP_EDGE; 1772 1773 /* fill in thread activity mask */ 1774 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1775 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1776 1777 if (evmask) 1778 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1779 1780 switch (pe) { 1781 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1782 if ((evmask & 0x06) == 0x06 || 1783 (evmask & 0x18) == 0x18) 1784 return (-1); /* can't have own+other bits together */ 1785 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1786 evmask = 0x1D; 1787 break; 1788 case PMC_EV_P4_MACHINE_CLEAR: 1789 /* only one bit is allowed to be set */ 1790 if ((evmask & (evmask - 1)) != 0) 1791 return (-1); 1792 if (evmask == 0) { 1793 evmask = 0x1; /* 'CLEAR' */ 1794 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1795 } 1796 break; 1797 default: 1798 if (evmask == 0 && pmask) { 1799 for (pm = pmask; pm->pm_name; pm++) 1800 evmask |= pm->pm_value; 1801 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1802 } 1803 } 1804 1805 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1806 P4_ESCR_TO_EVENT_MASK(evmask); 1807 1808 return (0); 1809 } 1810 1811 #endif 1812 1813 #if defined(__i386__) 1814 1815 /* 1816 * Pentium style PMCs 1817 */ 1818 1819 static struct pmc_event_alias p5_aliases[] = { 1820 EV_ALIAS("branches", "p5-taken-branches"), 1821 EV_ALIAS("cycles", "tsc"), 1822 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 1823 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 1824 EV_ALIAS("instructions", "p5-instructions-executed"), 1825 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 1826 EV_ALIAS("unhalted-cycles", 1827 "p5-number-of-cycles-not-in-halt-state"), 1828 EV_ALIAS(NULL, NULL) 1829 }; 1830 1831 static int 1832 p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 1833 struct pmc_op_pmcallocate *pmc_config) 1834 { 1835 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 1836 } 1837 1838 /* 1839 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 1840 * and Pentium M CPUs. 1841 */ 1842 1843 static struct pmc_event_alias p6_aliases[] = { 1844 EV_ALIAS("branches", "p6-br-inst-retired"), 1845 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 1846 EV_ALIAS("cycles", "tsc"), 1847 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 1848 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 1849 EV_ALIAS("instructions", "p6-inst-retired"), 1850 EV_ALIAS("interrupts", "p6-hw-int-rx"), 1851 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 1852 EV_ALIAS(NULL, NULL) 1853 }; 1854 1855 #define P6_KW_CMASK "cmask" 1856 #define P6_KW_EDGE "edge" 1857 #define P6_KW_INV "inv" 1858 #define P6_KW_OS "os" 1859 #define P6_KW_UMASK "umask" 1860 #define P6_KW_USR "usr" 1861 1862 static struct pmc_masks p6_mask_mesi[] = { 1863 PMCMASK(m, 0x01), 1864 PMCMASK(e, 0x02), 1865 PMCMASK(s, 0x04), 1866 PMCMASK(i, 0x08), 1867 NULLMASK 1868 }; 1869 1870 static struct pmc_masks p6_mask_mesihw[] = { 1871 PMCMASK(m, 0x01), 1872 PMCMASK(e, 0x02), 1873 PMCMASK(s, 0x04), 1874 PMCMASK(i, 0x08), 1875 PMCMASK(nonhw, 0x00), 1876 PMCMASK(hw, 0x10), 1877 PMCMASK(both, 0x30), 1878 NULLMASK 1879 }; 1880 1881 static struct pmc_masks p6_mask_hw[] = { 1882 PMCMASK(nonhw, 0x00), 1883 PMCMASK(hw, 0x10), 1884 PMCMASK(both, 0x30), 1885 NULLMASK 1886 }; 1887 1888 static struct pmc_masks p6_mask_any[] = { 1889 PMCMASK(self, 0x00), 1890 PMCMASK(any, 0x20), 1891 NULLMASK 1892 }; 1893 1894 static struct pmc_masks p6_mask_ekp[] = { 1895 PMCMASK(nta, 0x00), 1896 PMCMASK(t1, 0x01), 1897 PMCMASK(t2, 0x02), 1898 PMCMASK(wos, 0x03), 1899 NULLMASK 1900 }; 1901 1902 static struct pmc_masks p6_mask_pps[] = { 1903 PMCMASK(packed-and-scalar, 0x00), 1904 PMCMASK(scalar, 0x01), 1905 NULLMASK 1906 }; 1907 1908 static struct pmc_masks p6_mask_mite[] = { 1909 PMCMASK(packed-multiply, 0x01), 1910 PMCMASK(packed-shift, 0x02), 1911 PMCMASK(pack, 0x04), 1912 PMCMASK(unpack, 0x08), 1913 PMCMASK(packed-logical, 0x10), 1914 PMCMASK(packed-arithmetic, 0x20), 1915 NULLMASK 1916 }; 1917 1918 static struct pmc_masks p6_mask_fmt[] = { 1919 PMCMASK(mmxtofp, 0x00), 1920 PMCMASK(fptommx, 0x01), 1921 NULLMASK 1922 }; 1923 1924 static struct pmc_masks p6_mask_sr[] = { 1925 PMCMASK(es, 0x01), 1926 PMCMASK(ds, 0x02), 1927 PMCMASK(fs, 0x04), 1928 PMCMASK(gs, 0x08), 1929 NULLMASK 1930 }; 1931 1932 static struct pmc_masks p6_mask_eet[] = { 1933 PMCMASK(all, 0x00), 1934 PMCMASK(freq, 0x02), 1935 NULLMASK 1936 }; 1937 1938 static struct pmc_masks p6_mask_efur[] = { 1939 PMCMASK(all, 0x00), 1940 PMCMASK(loadop, 0x01), 1941 PMCMASK(stdsta, 0x02), 1942 NULLMASK 1943 }; 1944 1945 static struct pmc_masks p6_mask_essir[] = { 1946 PMCMASK(sse-packed-single, 0x00), 1947 PMCMASK(sse-packed-single-scalar-single, 0x01), 1948 PMCMASK(sse2-packed-double, 0x02), 1949 PMCMASK(sse2-scalar-double, 0x03), 1950 NULLMASK 1951 }; 1952 1953 static struct pmc_masks p6_mask_esscir[] = { 1954 PMCMASK(sse-packed-single, 0x00), 1955 PMCMASK(sse-scalar-single, 0x01), 1956 PMCMASK(sse2-packed-double, 0x02), 1957 PMCMASK(sse2-scalar-double, 0x03), 1958 NULLMASK 1959 }; 1960 1961 /* P6 event parser */ 1962 static int 1963 p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 1964 struct pmc_op_pmcallocate *pmc_config) 1965 { 1966 char *e, *p, *q; 1967 uint32_t evmask; 1968 int count, n; 1969 const struct pmc_masks *pm, *pmask; 1970 1971 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1972 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 1973 1974 evmask = 0; 1975 1976 #define P6MASKSET(M) pmask = p6_mask_ ## M 1977 1978 switch(pe) { 1979 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 1980 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 1981 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 1982 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 1983 case PMC_EV_P6_BUS_DRDY_CLOCKS: 1984 case PMC_EV_P6_BUS_LOCK_CLOCKS: 1985 case PMC_EV_P6_BUS_TRAN_BRD: 1986 case PMC_EV_P6_BUS_TRAN_RFO: 1987 case PMC_EV_P6_BUS_TRANS_WB: 1988 case PMC_EV_P6_BUS_TRAN_IFETCH: 1989 case PMC_EV_P6_BUS_TRAN_INVAL: 1990 case PMC_EV_P6_BUS_TRAN_PWR: 1991 case PMC_EV_P6_BUS_TRANS_P: 1992 case PMC_EV_P6_BUS_TRANS_IO: 1993 case PMC_EV_P6_BUS_TRAN_DEF: 1994 case PMC_EV_P6_BUS_TRAN_BURST: 1995 case PMC_EV_P6_BUS_TRAN_ANY: 1996 case PMC_EV_P6_BUS_TRAN_MEM: 1997 P6MASKSET(any); break; 1998 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 1999 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2000 P6MASKSET(ekp); break; 2001 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2002 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2003 P6MASKSET(pps); break; 2004 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2005 P6MASKSET(mite); break; 2006 case PMC_EV_P6_FP_MMX_TRANS: 2007 P6MASKSET(fmt); break; 2008 case PMC_EV_P6_SEG_RENAME_STALLS: 2009 case PMC_EV_P6_SEG_REG_RENAMES: 2010 P6MASKSET(sr); break; 2011 case PMC_EV_P6_EMON_EST_TRANS: 2012 P6MASKSET(eet); break; 2013 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2014 P6MASKSET(efur); break; 2015 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2016 P6MASKSET(essir); break; 2017 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2018 P6MASKSET(esscir); break; 2019 default: 2020 pmask = NULL; 2021 break; 2022 } 2023 2024 /* Pentium M PMCs have a few events with different semantics */ 2025 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2026 if (pe == PMC_EV_P6_L2_LD || 2027 pe == PMC_EV_P6_L2_LINES_IN || 2028 pe == PMC_EV_P6_L2_LINES_OUT) 2029 P6MASKSET(mesihw); 2030 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2031 P6MASKSET(hw); 2032 } 2033 2034 /* Parse additional modifiers if present */ 2035 while ((p = strsep(&ctrspec, ",")) != NULL) { 2036 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2037 q = strchr(p, '='); 2038 if (*++q == '\0') /* skip '=' */ 2039 return (-1); 2040 count = strtol(q, &e, 0); 2041 if (e == q || *e != '\0') 2042 return (-1); 2043 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2044 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2045 P6_EVSEL_TO_CMASK(count); 2046 } else if (KWMATCH(p, P6_KW_EDGE)) { 2047 pmc_config->pm_caps |= PMC_CAP_EDGE; 2048 } else if (KWMATCH(p, P6_KW_INV)) { 2049 pmc_config->pm_caps |= PMC_CAP_INVERT; 2050 } else if (KWMATCH(p, P6_KW_OS)) { 2051 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2052 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2053 evmask = 0; 2054 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2055 return (-1); 2056 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2057 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2058 pe == PMC_EV_P6_BUS_TRAN_BRD || 2059 pe == PMC_EV_P6_BUS_TRAN_RFO || 2060 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2061 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2062 pe == PMC_EV_P6_BUS_TRAN_PWR || 2063 pe == PMC_EV_P6_BUS_TRAN_DEF || 2064 pe == PMC_EV_P6_BUS_TRAN_BURST || 2065 pe == PMC_EV_P6_BUS_TRAN_ANY || 2066 pe == PMC_EV_P6_BUS_TRAN_MEM || 2067 pe == PMC_EV_P6_BUS_TRANS_IO || 2068 pe == PMC_EV_P6_BUS_TRANS_P || 2069 pe == PMC_EV_P6_BUS_TRANS_WB || 2070 pe == PMC_EV_P6_EMON_EST_TRANS || 2071 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2072 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2073 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2074 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2075 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2076 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2077 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2078 pe == PMC_EV_P6_FP_MMX_TRANS) 2079 && (n > 1)) /* Only one mask keyword is allowed. */ 2080 return (-1); 2081 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2082 } else if (KWMATCH(p, P6_KW_USR)) { 2083 pmc_config->pm_caps |= PMC_CAP_USER; 2084 } else 2085 return (-1); 2086 } 2087 2088 /* post processing */ 2089 switch (pe) { 2090 2091 /* 2092 * The following events default to an evmask of 0 2093 */ 2094 2095 /* default => 'self' */ 2096 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2097 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2098 case PMC_EV_P6_BUS_TRAN_BRD: 2099 case PMC_EV_P6_BUS_TRAN_RFO: 2100 case PMC_EV_P6_BUS_TRANS_WB: 2101 case PMC_EV_P6_BUS_TRAN_IFETCH: 2102 case PMC_EV_P6_BUS_TRAN_INVAL: 2103 case PMC_EV_P6_BUS_TRAN_PWR: 2104 case PMC_EV_P6_BUS_TRANS_P: 2105 case PMC_EV_P6_BUS_TRANS_IO: 2106 case PMC_EV_P6_BUS_TRAN_DEF: 2107 case PMC_EV_P6_BUS_TRAN_BURST: 2108 case PMC_EV_P6_BUS_TRAN_ANY: 2109 case PMC_EV_P6_BUS_TRAN_MEM: 2110 2111 /* default => 'nta' */ 2112 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2113 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2114 2115 /* default => 'packed and scalar' */ 2116 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2117 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2118 2119 /* default => 'mmx to fp transitions' */ 2120 case PMC_EV_P6_FP_MMX_TRANS: 2121 2122 /* default => 'SSE Packed Single' */ 2123 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2124 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2125 2126 /* default => 'all fused micro-ops' */ 2127 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2128 2129 /* default => 'all transitions' */ 2130 case PMC_EV_P6_EMON_EST_TRANS: 2131 break; 2132 2133 case PMC_EV_P6_MMX_UOPS_EXEC: 2134 evmask = 0x0F; /* only value allowed */ 2135 break; 2136 2137 default: 2138 /* 2139 * For all other events, set the default event mask 2140 * to a logical OR of all the allowed event mask bits. 2141 */ 2142 if (evmask == 0 && pmask) { 2143 for (pm = pmask; pm->pm_name; pm++) 2144 evmask |= pm->pm_value; 2145 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2146 } 2147 2148 break; 2149 } 2150 2151 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2152 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2153 P6_EVSEL_TO_UMASK(evmask); 2154 2155 return (0); 2156 } 2157 2158 #endif 2159 2160 #if defined(__i386__) || defined(__amd64__) 2161 static int 2162 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2163 struct pmc_op_pmcallocate *pmc_config) 2164 { 2165 if (pe != PMC_EV_TSC_TSC) 2166 return (-1); 2167 2168 /* TSC events must be unqualified. */ 2169 if (ctrspec && *ctrspec != '\0') 2170 return (-1); 2171 2172 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2173 pmc_config->pm_caps |= PMC_CAP_READ; 2174 2175 return (0); 2176 } 2177 #endif 2178 2179 #if defined(__XSCALE__) 2180 2181 static struct pmc_event_alias xscale_aliases[] = { 2182 EV_ALIAS("branches", "BRANCH_RETIRED"), 2183 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2184 EV_ALIAS("dc-misses", "DC_MISS"), 2185 EV_ALIAS("ic-misses", "IC_MISS"), 2186 EV_ALIAS("instructions", "INSTR_RETIRED"), 2187 EV_ALIAS(NULL, NULL) 2188 }; 2189 static int 2190 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2191 struct pmc_op_pmcallocate *pmc_config __unused) 2192 { 2193 switch (pe) { 2194 default: 2195 break; 2196 } 2197 2198 return (0); 2199 } 2200 #endif 2201 2202 #if defined(__mips__) 2203 2204 static struct pmc_event_alias mips24k_aliases[] = { 2205 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2206 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2207 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2208 EV_ALIAS(NULL, NULL) 2209 }; 2210 2211 #define MIPS24K_KW_OS "os" 2212 #define MIPS24K_KW_USR "usr" 2213 #define MIPS24K_KW_ANYTHREAD "anythread" 2214 2215 static int 2216 mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2217 struct pmc_op_pmcallocate *pmc_config __unused) 2218 { 2219 char *p; 2220 2221 (void) pe; 2222 2223 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2224 2225 while ((p = strsep(&ctrspec, ",")) != NULL) { 2226 if (KWMATCH(p, MIPS24K_KW_OS)) 2227 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2228 else if (KWMATCH(p, MIPS24K_KW_USR)) 2229 pmc_config->pm_caps |= PMC_CAP_USER; 2230 else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD)) 2231 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2232 else 2233 return (-1); 2234 } 2235 2236 return (0); 2237 } 2238 #endif /* __mips__ */ 2239 2240 #if defined(__powerpc__) 2241 2242 static struct pmc_event_alias ppc7450_aliases[] = { 2243 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2244 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2245 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2246 EV_ALIAS(NULL, NULL) 2247 }; 2248 2249 #define PPC7450_KW_OS "os" 2250 #define PPC7450_KW_USR "usr" 2251 #define PPC7450_KW_ANYTHREAD "anythread" 2252 2253 static int 2254 ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2255 struct pmc_op_pmcallocate *pmc_config __unused) 2256 { 2257 char *p; 2258 2259 (void) pe; 2260 2261 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2262 2263 while ((p = strsep(&ctrspec, ",")) != NULL) { 2264 if (KWMATCH(p, PPC7450_KW_OS)) 2265 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2266 else if (KWMATCH(p, PPC7450_KW_USR)) 2267 pmc_config->pm_caps |= PMC_CAP_USER; 2268 else if (KWMATCH(p, PPC7450_KW_ANYTHREAD)) 2269 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2270 else 2271 return (-1); 2272 } 2273 2274 return (0); 2275 } 2276 #endif /* __powerpc__ */ 2277 2278 2279 /* 2280 * Match an event name `name' with its canonical form. 2281 * 2282 * Matches are case insensitive and spaces, periods, underscores and 2283 * hyphen characters are considered to match each other. 2284 * 2285 * Returns 1 for a match, 0 otherwise. 2286 */ 2287 2288 static int 2289 pmc_match_event_name(const char *name, const char *canonicalname) 2290 { 2291 int cc, nc; 2292 const unsigned char *c, *n; 2293 2294 c = (const unsigned char *) canonicalname; 2295 n = (const unsigned char *) name; 2296 2297 for (; (nc = *n) && (cc = *c); n++, c++) { 2298 2299 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2300 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2301 continue; 2302 2303 if (toupper(nc) == toupper(cc)) 2304 continue; 2305 2306 2307 return (0); 2308 } 2309 2310 if (*n == '\0' && *c == '\0') 2311 return (1); 2312 2313 return (0); 2314 } 2315 2316 /* 2317 * Match an event name against all the event named supported by a 2318 * PMC class. 2319 * 2320 * Returns an event descriptor pointer on match or NULL otherwise. 2321 */ 2322 static const struct pmc_event_descr * 2323 pmc_match_event_class(const char *name, 2324 const struct pmc_class_descr *pcd) 2325 { 2326 size_t n; 2327 const struct pmc_event_descr *ev; 2328 2329 ev = pcd->pm_evc_event_table; 2330 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2331 if (pmc_match_event_name(name, ev->pm_ev_name)) 2332 return (ev); 2333 2334 return (NULL); 2335 } 2336 2337 static int 2338 pmc_mdep_is_compatible_class(enum pmc_class pc) 2339 { 2340 size_t n; 2341 2342 for (n = 0; n < pmc_mdep_class_list_size; n++) 2343 if (pmc_mdep_class_list[n] == pc) 2344 return (1); 2345 return (0); 2346 } 2347 2348 /* 2349 * API entry points 2350 */ 2351 2352 int 2353 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2354 uint32_t flags, int cpu, pmc_id_t *pmcid) 2355 { 2356 size_t n; 2357 int retval; 2358 char *r, *spec_copy; 2359 const char *ctrname; 2360 const struct pmc_event_descr *ev; 2361 const struct pmc_event_alias *alias; 2362 struct pmc_op_pmcallocate pmc_config; 2363 const struct pmc_class_descr *pcd; 2364 2365 spec_copy = NULL; 2366 retval = -1; 2367 2368 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2369 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2370 errno = EINVAL; 2371 goto out; 2372 } 2373 2374 /* replace an event alias with the canonical event specifier */ 2375 if (pmc_mdep_event_aliases) 2376 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2377 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2378 spec_copy = strdup(alias->pm_spec); 2379 break; 2380 } 2381 2382 if (spec_copy == NULL) 2383 spec_copy = strdup(ctrspec); 2384 2385 r = spec_copy; 2386 ctrname = strsep(&r, ","); 2387 2388 /* 2389 * If a explicit class prefix was given by the user, restrict the 2390 * search for the event to the specified PMC class. 2391 */ 2392 ev = NULL; 2393 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2394 pcd = pmc_class_table[n]; 2395 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2396 strncasecmp(ctrname, pcd->pm_evc_name, 2397 pcd->pm_evc_name_size) == 0) { 2398 if ((ev = pmc_match_event_class(ctrname + 2399 pcd->pm_evc_name_size, pcd)) == NULL) { 2400 errno = EINVAL; 2401 goto out; 2402 } 2403 break; 2404 } 2405 } 2406 2407 /* 2408 * Otherwise, search for this event in all compatible PMC 2409 * classes. 2410 */ 2411 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2412 pcd = pmc_class_table[n]; 2413 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2414 ev = pmc_match_event_class(ctrname, pcd); 2415 } 2416 2417 if (ev == NULL) { 2418 errno = EINVAL; 2419 goto out; 2420 } 2421 2422 bzero(&pmc_config, sizeof(pmc_config)); 2423 pmc_config.pm_ev = ev->pm_ev_code; 2424 pmc_config.pm_class = pcd->pm_evc_class; 2425 pmc_config.pm_cpu = cpu; 2426 pmc_config.pm_mode = mode; 2427 pmc_config.pm_flags = flags; 2428 2429 if (PMC_IS_SAMPLING_MODE(mode)) 2430 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2431 2432 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2433 errno = EINVAL; 2434 goto out; 2435 } 2436 2437 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2438 goto out; 2439 2440 *pmcid = pmc_config.pm_pmcid; 2441 2442 retval = 0; 2443 2444 out: 2445 if (spec_copy) 2446 free(spec_copy); 2447 2448 return (retval); 2449 } 2450 2451 int 2452 pmc_attach(pmc_id_t pmc, pid_t pid) 2453 { 2454 struct pmc_op_pmcattach pmc_attach_args; 2455 2456 pmc_attach_args.pm_pmc = pmc; 2457 pmc_attach_args.pm_pid = pid; 2458 2459 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2460 } 2461 2462 int 2463 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2464 { 2465 unsigned int i; 2466 enum pmc_class cl; 2467 2468 cl = PMC_ID_TO_CLASS(pmcid); 2469 for (i = 0; i < cpu_info.pm_nclass; i++) 2470 if (cpu_info.pm_classes[i].pm_class == cl) { 2471 *caps = cpu_info.pm_classes[i].pm_caps; 2472 return (0); 2473 } 2474 errno = EINVAL; 2475 return (-1); 2476 } 2477 2478 int 2479 pmc_configure_logfile(int fd) 2480 { 2481 struct pmc_op_configurelog cla; 2482 2483 cla.pm_logfd = fd; 2484 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2485 return (-1); 2486 return (0); 2487 } 2488 2489 int 2490 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2491 { 2492 if (pmc_syscall == -1) { 2493 errno = ENXIO; 2494 return (-1); 2495 } 2496 2497 *pci = &cpu_info; 2498 return (0); 2499 } 2500 2501 int 2502 pmc_detach(pmc_id_t pmc, pid_t pid) 2503 { 2504 struct pmc_op_pmcattach pmc_detach_args; 2505 2506 pmc_detach_args.pm_pmc = pmc; 2507 pmc_detach_args.pm_pid = pid; 2508 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2509 } 2510 2511 int 2512 pmc_disable(int cpu, int pmc) 2513 { 2514 struct pmc_op_pmcadmin ssa; 2515 2516 ssa.pm_cpu = cpu; 2517 ssa.pm_pmc = pmc; 2518 ssa.pm_state = PMC_STATE_DISABLED; 2519 return (PMC_CALL(PMCADMIN, &ssa)); 2520 } 2521 2522 int 2523 pmc_enable(int cpu, int pmc) 2524 { 2525 struct pmc_op_pmcadmin ssa; 2526 2527 ssa.pm_cpu = cpu; 2528 ssa.pm_pmc = pmc; 2529 ssa.pm_state = PMC_STATE_FREE; 2530 return (PMC_CALL(PMCADMIN, &ssa)); 2531 } 2532 2533 /* 2534 * Return a list of events known to a given PMC class. 'cl' is the 2535 * PMC class identifier, 'eventnames' is the returned list of 'const 2536 * char *' pointers pointing to the names of the events. 'nevents' is 2537 * the number of event name pointers returned. 2538 * 2539 * The space for 'eventnames' is allocated using malloc(3). The caller 2540 * is responsible for freeing this space when done. 2541 */ 2542 int 2543 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2544 int *nevents) 2545 { 2546 int count; 2547 const char **names; 2548 const struct pmc_event_descr *ev; 2549 2550 switch (cl) 2551 { 2552 case PMC_CLASS_IAF: 2553 ev = iaf_event_table; 2554 count = PMC_EVENT_TABLE_SIZE(iaf); 2555 break; 2556 case PMC_CLASS_IAP: 2557 /* 2558 * Return the most appropriate set of event name 2559 * spellings for the current CPU. 2560 */ 2561 switch (cpu_info.pm_cputype) { 2562 default: 2563 case PMC_CPU_INTEL_ATOM: 2564 ev = atom_event_table; 2565 count = PMC_EVENT_TABLE_SIZE(atom); 2566 break; 2567 case PMC_CPU_INTEL_CORE: 2568 ev = core_event_table; 2569 count = PMC_EVENT_TABLE_SIZE(core); 2570 break; 2571 case PMC_CPU_INTEL_CORE2: 2572 case PMC_CPU_INTEL_CORE2EXTREME: 2573 ev = core2_event_table; 2574 count = PMC_EVENT_TABLE_SIZE(core2); 2575 break; 2576 case PMC_CPU_INTEL_COREI7: 2577 ev = corei7_event_table; 2578 count = PMC_EVENT_TABLE_SIZE(corei7); 2579 break; 2580 case PMC_CPU_INTEL_SANDYBRIDGE: 2581 ev = sandybridge_event_table; 2582 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2583 break; 2584 case PMC_CPU_INTEL_WESTMERE: 2585 ev = westmere_event_table; 2586 count = PMC_EVENT_TABLE_SIZE(westmere); 2587 break; 2588 } 2589 break; 2590 case PMC_CLASS_UCF: 2591 ev = ucf_event_table; 2592 count = PMC_EVENT_TABLE_SIZE(ucf); 2593 break; 2594 case PMC_CLASS_UCP: 2595 /* 2596 * Return the most appropriate set of event name 2597 * spellings for the current CPU. 2598 */ 2599 switch (cpu_info.pm_cputype) { 2600 default: 2601 case PMC_CPU_INTEL_COREI7: 2602 ev = corei7uc_event_table; 2603 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2604 break; 2605 case PMC_CPU_INTEL_SANDYBRIDGE: 2606 ev = sandybridgeuc_event_table; 2607 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2608 break; 2609 case PMC_CPU_INTEL_WESTMERE: 2610 ev = westmereuc_event_table; 2611 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2612 break; 2613 } 2614 break; 2615 case PMC_CLASS_TSC: 2616 ev = tsc_event_table; 2617 count = PMC_EVENT_TABLE_SIZE(tsc); 2618 break; 2619 case PMC_CLASS_K7: 2620 ev = k7_event_table; 2621 count = PMC_EVENT_TABLE_SIZE(k7); 2622 break; 2623 case PMC_CLASS_K8: 2624 ev = k8_event_table; 2625 count = PMC_EVENT_TABLE_SIZE(k8); 2626 break; 2627 case PMC_CLASS_P4: 2628 ev = p4_event_table; 2629 count = PMC_EVENT_TABLE_SIZE(p4); 2630 break; 2631 case PMC_CLASS_P5: 2632 ev = p5_event_table; 2633 count = PMC_EVENT_TABLE_SIZE(p5); 2634 break; 2635 case PMC_CLASS_P6: 2636 ev = p6_event_table; 2637 count = PMC_EVENT_TABLE_SIZE(p6); 2638 break; 2639 case PMC_CLASS_XSCALE: 2640 ev = xscale_event_table; 2641 count = PMC_EVENT_TABLE_SIZE(xscale); 2642 break; 2643 case PMC_CLASS_MIPS24K: 2644 ev = mips24k_event_table; 2645 count = PMC_EVENT_TABLE_SIZE(mips24k); 2646 break; 2647 case PMC_CLASS_PPC7450: 2648 ev = ppc7450_event_table; 2649 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2650 break; 2651 default: 2652 errno = EINVAL; 2653 return (-1); 2654 } 2655 2656 if ((names = malloc(count * sizeof(const char *))) == NULL) 2657 return (-1); 2658 2659 *eventnames = names; 2660 *nevents = count; 2661 2662 for (;count--; ev++, names++) 2663 *names = ev->pm_ev_name; 2664 return (0); 2665 } 2666 2667 int 2668 pmc_flush_logfile(void) 2669 { 2670 return (PMC_CALL(FLUSHLOG,0)); 2671 } 2672 2673 int 2674 pmc_close_logfile(void) 2675 { 2676 return (PMC_CALL(CLOSELOG,0)); 2677 } 2678 2679 int 2680 pmc_get_driver_stats(struct pmc_driverstats *ds) 2681 { 2682 struct pmc_op_getdriverstats gms; 2683 2684 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2685 return (-1); 2686 2687 /* copy out fields in the current userland<->library interface */ 2688 ds->pm_intr_ignored = gms.pm_intr_ignored; 2689 ds->pm_intr_processed = gms.pm_intr_processed; 2690 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2691 ds->pm_syscalls = gms.pm_syscalls; 2692 ds->pm_syscall_errors = gms.pm_syscall_errors; 2693 ds->pm_buffer_requests = gms.pm_buffer_requests; 2694 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 2695 ds->pm_log_sweeps = gms.pm_log_sweeps; 2696 return (0); 2697 } 2698 2699 int 2700 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 2701 { 2702 struct pmc_op_getmsr gm; 2703 2704 gm.pm_pmcid = pmc; 2705 if (PMC_CALL(PMCGETMSR, &gm) < 0) 2706 return (-1); 2707 *msr = gm.pm_msr; 2708 return (0); 2709 } 2710 2711 int 2712 pmc_init(void) 2713 { 2714 int error, pmc_mod_id; 2715 unsigned int n; 2716 uint32_t abi_version; 2717 struct module_stat pmc_modstat; 2718 struct pmc_op_getcpuinfo op_cpu_info; 2719 #if defined(__amd64__) || defined(__i386__) 2720 int cpu_has_iaf_counters; 2721 unsigned int t; 2722 #endif 2723 2724 if (pmc_syscall != -1) /* already inited */ 2725 return (0); 2726 2727 /* retrieve the system call number from the KLD */ 2728 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 2729 return (-1); 2730 2731 pmc_modstat.version = sizeof(struct module_stat); 2732 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 2733 return (-1); 2734 2735 pmc_syscall = pmc_modstat.data.intval; 2736 2737 /* check the kernel module's ABI against our compiled-in version */ 2738 abi_version = PMC_VERSION; 2739 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 2740 return (pmc_syscall = -1); 2741 2742 /* ignore patch & minor numbers for the comparision */ 2743 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 2744 errno = EPROGMISMATCH; 2745 return (pmc_syscall = -1); 2746 } 2747 2748 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 2749 return (pmc_syscall = -1); 2750 2751 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 2752 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 2753 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 2754 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 2755 for (n = 0; n < cpu_info.pm_nclass; n++) 2756 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 2757 2758 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 2759 sizeof(struct pmc_class_descr *)); 2760 2761 if (pmc_class_table == NULL) 2762 return (-1); 2763 2764 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 2765 pmc_class_table[n] = NULL; 2766 2767 /* 2768 * Fill in the class table. 2769 */ 2770 n = 0; 2771 #if defined(__amd64__) || defined(__i386__) 2772 pmc_class_table[n++] = &tsc_class_table_descr; 2773 2774 /* 2775 * Check if this CPU has fixed function counters. 2776 */ 2777 cpu_has_iaf_counters = 0; 2778 for (t = 0; t < cpu_info.pm_nclass; t++) 2779 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 2780 cpu_info.pm_classes[t].pm_num > 0) 2781 cpu_has_iaf_counters = 1; 2782 #endif 2783 2784 #define PMC_MDEP_INIT(C) do { \ 2785 pmc_mdep_event_aliases = C##_aliases; \ 2786 pmc_mdep_class_list = C##_pmc_classes; \ 2787 pmc_mdep_class_list_size = \ 2788 PMC_TABLE_SIZE(C##_pmc_classes); \ 2789 } while (0) 2790 2791 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 2792 PMC_MDEP_INIT(C); \ 2793 pmc_class_table[n++] = &iaf_class_table_descr; \ 2794 if (!cpu_has_iaf_counters) \ 2795 pmc_mdep_event_aliases = \ 2796 C##_aliases_without_iaf; \ 2797 pmc_class_table[n] = &C##_class_table_descr; \ 2798 } while (0) 2799 2800 /* Configure the event name parser. */ 2801 switch (cpu_info.pm_cputype) { 2802 #if defined(__i386__) 2803 case PMC_CPU_AMD_K7: 2804 PMC_MDEP_INIT(k7); 2805 pmc_class_table[n] = &k7_class_table_descr; 2806 break; 2807 case PMC_CPU_INTEL_P5: 2808 PMC_MDEP_INIT(p5); 2809 pmc_class_table[n] = &p5_class_table_descr; 2810 break; 2811 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 2812 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 2813 case PMC_CPU_INTEL_PIII: 2814 case PMC_CPU_INTEL_PM: 2815 PMC_MDEP_INIT(p6); 2816 pmc_class_table[n] = &p6_class_table_descr; 2817 break; 2818 #endif 2819 #if defined(__amd64__) || defined(__i386__) 2820 case PMC_CPU_AMD_K8: 2821 PMC_MDEP_INIT(k8); 2822 pmc_class_table[n] = &k8_class_table_descr; 2823 break; 2824 case PMC_CPU_INTEL_ATOM: 2825 PMC_MDEP_INIT_INTEL_V2(atom); 2826 break; 2827 case PMC_CPU_INTEL_CORE: 2828 PMC_MDEP_INIT(core); 2829 pmc_class_table[n] = &core_class_table_descr; 2830 break; 2831 case PMC_CPU_INTEL_CORE2: 2832 case PMC_CPU_INTEL_CORE2EXTREME: 2833 PMC_MDEP_INIT_INTEL_V2(core2); 2834 break; 2835 case PMC_CPU_INTEL_COREI7: 2836 pmc_class_table[n++] = &ucf_class_table_descr; 2837 pmc_class_table[n++] = &corei7uc_class_table_descr; 2838 PMC_MDEP_INIT_INTEL_V2(corei7); 2839 break; 2840 case PMC_CPU_INTEL_SANDYBRIDGE: 2841 pmc_class_table[n++] = &ucf_class_table_descr; 2842 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 2843 PMC_MDEP_INIT_INTEL_V2(sandybridge); 2844 break; 2845 case PMC_CPU_INTEL_WESTMERE: 2846 pmc_class_table[n++] = &ucf_class_table_descr; 2847 pmc_class_table[n++] = &westmereuc_class_table_descr; 2848 PMC_MDEP_INIT_INTEL_V2(westmere); 2849 break; 2850 case PMC_CPU_INTEL_PIV: 2851 PMC_MDEP_INIT(p4); 2852 pmc_class_table[n] = &p4_class_table_descr; 2853 break; 2854 #endif 2855 #if defined(__XSCALE__) 2856 case PMC_CPU_INTEL_XSCALE: 2857 PMC_MDEP_INIT(xscale); 2858 pmc_class_table[n] = &xscale_class_table_descr; 2859 break; 2860 #endif 2861 #if defined(__mips__) 2862 case PMC_CPU_MIPS_24K: 2863 PMC_MDEP_INIT(mips24k); 2864 pmc_class_table[n] = &mips24k_class_table_descr; 2865 break; 2866 #endif /* __mips__ */ 2867 #if defined(__powerpc__) 2868 case PMC_CPU_PPC_7450: 2869 PMC_MDEP_INIT(ppc7450); 2870 pmc_class_table[n] = &ppc7450_class_table_descr; 2871 break; 2872 #endif 2873 default: 2874 /* 2875 * Some kind of CPU this version of the library knows nothing 2876 * about. This shouldn't happen since the abi version check 2877 * should have caught this. 2878 */ 2879 errno = ENXIO; 2880 return (pmc_syscall = -1); 2881 } 2882 2883 return (0); 2884 } 2885 2886 const char * 2887 pmc_name_of_capability(enum pmc_caps cap) 2888 { 2889 int i; 2890 2891 /* 2892 * 'cap' should have a single bit set and should be in 2893 * range. 2894 */ 2895 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 2896 cap > PMC_CAP_LAST) { 2897 errno = EINVAL; 2898 return (NULL); 2899 } 2900 2901 i = ffs(cap); 2902 return (pmc_capability_names[i - 1]); 2903 } 2904 2905 const char * 2906 pmc_name_of_class(enum pmc_class pc) 2907 { 2908 if ((int) pc >= PMC_CLASS_FIRST && 2909 pc <= PMC_CLASS_LAST) 2910 return (pmc_class_names[pc]); 2911 2912 errno = EINVAL; 2913 return (NULL); 2914 } 2915 2916 const char * 2917 pmc_name_of_cputype(enum pmc_cputype cp) 2918 { 2919 size_t n; 2920 2921 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 2922 if (cp == pmc_cputype_names[n].pm_cputype) 2923 return (pmc_cputype_names[n].pm_name); 2924 2925 errno = EINVAL; 2926 return (NULL); 2927 } 2928 2929 const char * 2930 pmc_name_of_disposition(enum pmc_disp pd) 2931 { 2932 if ((int) pd >= PMC_DISP_FIRST && 2933 pd <= PMC_DISP_LAST) 2934 return (pmc_disposition_names[pd]); 2935 2936 errno = EINVAL; 2937 return (NULL); 2938 } 2939 2940 const char * 2941 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 2942 { 2943 const struct pmc_event_descr *ev, *evfence; 2944 2945 ev = evfence = NULL; 2946 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 2947 ev = iaf_event_table; 2948 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 2949 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 2950 switch (cpu) { 2951 case PMC_CPU_INTEL_ATOM: 2952 ev = atom_event_table; 2953 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 2954 break; 2955 case PMC_CPU_INTEL_CORE: 2956 ev = core_event_table; 2957 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 2958 break; 2959 case PMC_CPU_INTEL_CORE2: 2960 case PMC_CPU_INTEL_CORE2EXTREME: 2961 ev = core2_event_table; 2962 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 2963 break; 2964 case PMC_CPU_INTEL_COREI7: 2965 ev = corei7_event_table; 2966 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 2967 break; 2968 case PMC_CPU_INTEL_SANDYBRIDGE: 2969 ev = sandybridge_event_table; 2970 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 2971 break; 2972 case PMC_CPU_INTEL_WESTMERE: 2973 ev = westmere_event_table; 2974 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 2975 break; 2976 default: /* Unknown CPU type. */ 2977 break; 2978 } 2979 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 2980 ev = ucf_event_table; 2981 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 2982 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 2983 switch (cpu) { 2984 case PMC_CPU_INTEL_COREI7: 2985 ev = corei7uc_event_table; 2986 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 2987 break; 2988 case PMC_CPU_INTEL_SANDYBRIDGE: 2989 ev = sandybridgeuc_event_table; 2990 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2991 break; 2992 case PMC_CPU_INTEL_WESTMERE: 2993 ev = westmereuc_event_table; 2994 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 2995 break; 2996 default: /* Unknown CPU type. */ 2997 break; 2998 } 2999 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3000 ev = k7_event_table; 3001 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3002 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3003 ev = k8_event_table; 3004 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3005 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3006 ev = p4_event_table; 3007 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3008 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3009 ev = p5_event_table; 3010 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3011 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3012 ev = p6_event_table; 3013 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3014 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3015 ev = xscale_event_table; 3016 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3017 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3018 ev = mips24k_event_table; 3019 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k 3020 ); 3021 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3022 ev = ppc7450_event_table; 3023 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450 3024 ); 3025 } else if (pe == PMC_EV_TSC_TSC) { 3026 ev = tsc_event_table; 3027 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3028 } 3029 3030 for (; ev != evfence; ev++) 3031 if (pe == ev->pm_ev_code) 3032 return (ev->pm_ev_name); 3033 3034 return (NULL); 3035 } 3036 3037 const char * 3038 pmc_name_of_event(enum pmc_event pe) 3039 { 3040 const char *n; 3041 3042 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3043 return (n); 3044 3045 errno = EINVAL; 3046 return (NULL); 3047 } 3048 3049 const char * 3050 pmc_name_of_mode(enum pmc_mode pm) 3051 { 3052 if ((int) pm >= PMC_MODE_FIRST && 3053 pm <= PMC_MODE_LAST) 3054 return (pmc_mode_names[pm]); 3055 3056 errno = EINVAL; 3057 return (NULL); 3058 } 3059 3060 const char * 3061 pmc_name_of_state(enum pmc_state ps) 3062 { 3063 if ((int) ps >= PMC_STATE_FIRST && 3064 ps <= PMC_STATE_LAST) 3065 return (pmc_state_names[ps]); 3066 3067 errno = EINVAL; 3068 return (NULL); 3069 } 3070 3071 int 3072 pmc_ncpu(void) 3073 { 3074 if (pmc_syscall == -1) { 3075 errno = ENXIO; 3076 return (-1); 3077 } 3078 3079 return (cpu_info.pm_ncpu); 3080 } 3081 3082 int 3083 pmc_npmc(int cpu) 3084 { 3085 if (pmc_syscall == -1) { 3086 errno = ENXIO; 3087 return (-1); 3088 } 3089 3090 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3091 errno = EINVAL; 3092 return (-1); 3093 } 3094 3095 return (cpu_info.pm_npmc); 3096 } 3097 3098 int 3099 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3100 { 3101 int nbytes, npmc; 3102 struct pmc_op_getpmcinfo *pmci; 3103 3104 if ((npmc = pmc_npmc(cpu)) < 0) 3105 return (-1); 3106 3107 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3108 npmc * sizeof(struct pmc_info); 3109 3110 if ((pmci = calloc(1, nbytes)) == NULL) 3111 return (-1); 3112 3113 pmci->pm_cpu = cpu; 3114 3115 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3116 free(pmci); 3117 return (-1); 3118 } 3119 3120 /* kernel<->library, library<->userland interfaces are identical */ 3121 *ppmci = (struct pmc_pmcinfo *) pmci; 3122 return (0); 3123 } 3124 3125 int 3126 pmc_read(pmc_id_t pmc, pmc_value_t *value) 3127 { 3128 struct pmc_op_pmcrw pmc_read_op; 3129 3130 pmc_read_op.pm_pmcid = pmc; 3131 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3132 pmc_read_op.pm_value = -1; 3133 3134 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3135 return (-1); 3136 3137 *value = pmc_read_op.pm_value; 3138 return (0); 3139 } 3140 3141 int 3142 pmc_release(pmc_id_t pmc) 3143 { 3144 struct pmc_op_simple pmc_release_args; 3145 3146 pmc_release_args.pm_pmcid = pmc; 3147 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3148 } 3149 3150 int 3151 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3152 { 3153 struct pmc_op_pmcrw pmc_rw_op; 3154 3155 pmc_rw_op.pm_pmcid = pmc; 3156 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3157 pmc_rw_op.pm_value = newvalue; 3158 3159 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3160 return (-1); 3161 3162 *oldvaluep = pmc_rw_op.pm_value; 3163 return (0); 3164 } 3165 3166 int 3167 pmc_set(pmc_id_t pmc, pmc_value_t value) 3168 { 3169 struct pmc_op_pmcsetcount sc; 3170 3171 sc.pm_pmcid = pmc; 3172 sc.pm_count = value; 3173 3174 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3175 return (-1); 3176 return (0); 3177 } 3178 3179 int 3180 pmc_start(pmc_id_t pmc) 3181 { 3182 struct pmc_op_simple pmc_start_args; 3183 3184 pmc_start_args.pm_pmcid = pmc; 3185 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3186 } 3187 3188 int 3189 pmc_stop(pmc_id_t pmc) 3190 { 3191 struct pmc_op_simple pmc_stop_args; 3192 3193 pmc_stop_args.pm_pmcid = pmc; 3194 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3195 } 3196 3197 int 3198 pmc_width(pmc_id_t pmcid, uint32_t *width) 3199 { 3200 unsigned int i; 3201 enum pmc_class cl; 3202 3203 cl = PMC_ID_TO_CLASS(pmcid); 3204 for (i = 0; i < cpu_info.pm_nclass; i++) 3205 if (cpu_info.pm_classes[i].pm_class == cl) { 3206 *width = cpu_info.pm_classes[i].pm_width; 3207 return (0); 3208 } 3209 errno = EINVAL; 3210 return (-1); 3211 } 3212 3213 int 3214 pmc_write(pmc_id_t pmc, pmc_value_t value) 3215 { 3216 struct pmc_op_pmcrw pmc_write_op; 3217 3218 pmc_write_op.pm_pmcid = pmc; 3219 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3220 pmc_write_op.pm_value = value; 3221 return (PMC_CALL(PMCRW, &pmc_write_op)); 3222 } 3223 3224 int 3225 pmc_writelog(uint32_t userdata) 3226 { 3227 struct pmc_op_writelog wl; 3228 3229 wl.pm_userdata = userdata; 3230 return (PMC_CALL(WRITELOG, &wl)); 3231 } 3232