1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/module.h> 35 #include <sys/pmc.h> 36 #include <sys/syscall.h> 37 38 #include <ctype.h> 39 #include <errno.h> 40 #include <err.h> 41 #include <fcntl.h> 42 #include <pmc.h> 43 #include <stdio.h> 44 #include <stdlib.h> 45 #include <string.h> 46 #include <strings.h> 47 #include <sysexits.h> 48 #include <unistd.h> 49 50 #include "libpmcinternal.h" 51 52 /* Function prototypes */ 53 #if defined(__amd64__) || defined(__i386__) 54 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56 #endif 57 #if defined(__amd64__) || defined(__i386__) 58 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60 #endif 61 #if defined(__arm__) 62 #if defined(__XSCALE__) 63 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65 #endif 66 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 67 struct pmc_op_pmcallocate *_pmc_config); 68 #endif 69 #if defined(__aarch64__) 70 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72 #endif 73 #if defined(__mips__) 74 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 #endif /* __mips__ */ 77 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 78 struct pmc_op_pmcallocate *_pmc_config); 79 80 #if defined(__powerpc__) 81 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 82 struct pmc_op_pmcallocate *_pmc_config); 83 #endif /* __powerpc__ */ 84 85 #define PMC_CALL(cmd, params) \ 86 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 87 88 /* 89 * Event aliases provide a way for the user to ask for generic events 90 * like "cache-misses", or "instructions-retired". These aliases are 91 * mapped to the appropriate canonical event descriptions using a 92 * lookup table. 93 */ 94 struct pmc_event_alias { 95 const char *pm_alias; 96 const char *pm_spec; 97 }; 98 99 static const struct pmc_event_alias *pmc_mdep_event_aliases; 100 101 /* 102 * The pmc_event_descr structure maps symbolic names known to the user 103 * to integer codes used by the PMC KLD. 104 */ 105 struct pmc_event_descr { 106 const char *pm_ev_name; 107 enum pmc_event pm_ev_code; 108 }; 109 110 /* 111 * The pmc_class_descr structure maps class name prefixes for 112 * event names to event tables and other PMC class data. 113 */ 114 struct pmc_class_descr { 115 const char *pm_evc_name; 116 size_t pm_evc_name_size; 117 enum pmc_class pm_evc_class; 118 const struct pmc_event_descr *pm_evc_event_table; 119 size_t pm_evc_event_table_size; 120 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 121 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 122 }; 123 124 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 125 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 126 127 #undef __PMC_EV 128 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 129 130 /* 131 * PMC_CLASSDEP_TABLE(NAME, CLASS) 132 * 133 * Define a table mapping event names and aliases to HWPMC event IDs. 134 */ 135 #define PMC_CLASSDEP_TABLE(N, C) \ 136 static const struct pmc_event_descr N##_event_table[] = \ 137 { \ 138 __PMC_EV_##C() \ 139 } 140 141 PMC_CLASSDEP_TABLE(iaf, IAF); 142 PMC_CLASSDEP_TABLE(k8, K8); 143 PMC_CLASSDEP_TABLE(xscale, XSCALE); 144 PMC_CLASSDEP_TABLE(armv7, ARMV7); 145 PMC_CLASSDEP_TABLE(armv8, ARMV8); 146 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 147 PMC_CLASSDEP_TABLE(mips74k, MIPS74K); 148 PMC_CLASSDEP_TABLE(octeon, OCTEON); 149 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 150 PMC_CLASSDEP_TABLE(ppc970, PPC970); 151 PMC_CLASSDEP_TABLE(e500, E500); 152 153 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 154 155 #undef __PMC_EV_ALIAS 156 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 157 158 static const struct pmc_event_descr cortex_a8_event_table[] = 159 { 160 __PMC_EV_ALIAS_ARMV7_CORTEX_A8() 161 }; 162 163 static const struct pmc_event_descr cortex_a9_event_table[] = 164 { 165 __PMC_EV_ALIAS_ARMV7_CORTEX_A9() 166 }; 167 168 static const struct pmc_event_descr cortex_a53_event_table[] = 169 { 170 __PMC_EV_ALIAS_ARMV8_CORTEX_A53() 171 }; 172 173 static const struct pmc_event_descr cortex_a57_event_table[] = 174 { 175 __PMC_EV_ALIAS_ARMV8_CORTEX_A57() 176 }; 177 178 /* 179 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 180 * 181 * Map a CPU to the PMC classes it supports. 182 */ 183 #define PMC_MDEP_TABLE(N,C,...) \ 184 static const enum pmc_class N##_pmc_classes[] = { \ 185 PMC_CLASS_##C, __VA_ARGS__ \ 186 } 187 188 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 189 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 190 PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 191 PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 192 PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); 193 PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); 194 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 195 PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); 196 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 197 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450, PMC_CLASS_TSC); 198 PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970, PMC_CLASS_TSC); 199 PMC_MDEP_TABLE(e500, E500, PMC_CLASS_SOFT, PMC_CLASS_E500, PMC_CLASS_TSC); 200 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 201 202 static const struct pmc_event_descr tsc_event_table[] = 203 { 204 __PMC_EV_TSC() 205 }; 206 207 #undef PMC_CLASS_TABLE_DESC 208 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 209 static const struct pmc_class_descr NAME##_class_table_descr = \ 210 { \ 211 .pm_evc_name = #CLASS "-", \ 212 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 213 .pm_evc_class = PMC_CLASS_##CLASS , \ 214 .pm_evc_event_table = EVENTS##_event_table , \ 215 .pm_evc_event_table_size = \ 216 PMC_EVENT_TABLE_SIZE(EVENTS), \ 217 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 218 } 219 220 #if defined(__i386__) || defined(__amd64__) 221 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 222 #endif 223 #if defined(__i386__) || defined(__amd64__) 224 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 225 #endif 226 #if defined(__arm__) 227 #if defined(__XSCALE__) 228 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 229 #endif 230 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7); 231 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); 232 #endif 233 #if defined(__aarch64__) 234 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); 235 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); 236 #endif 237 #if defined(__mips__) 238 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 239 PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); 240 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 241 #endif /* __mips__ */ 242 #if defined(__powerpc__) 243 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 244 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 245 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); 246 #endif 247 248 static struct pmc_class_descr soft_class_table_descr = 249 { 250 .pm_evc_name = "SOFT-", 251 .pm_evc_name_size = sizeof("SOFT-") - 1, 252 .pm_evc_class = PMC_CLASS_SOFT, 253 .pm_evc_event_table = NULL, 254 .pm_evc_event_table_size = 0, 255 .pm_evc_allocate_pmc = soft_allocate_pmc 256 }; 257 258 #undef PMC_CLASS_TABLE_DESC 259 260 static const struct pmc_class_descr **pmc_class_table; 261 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 262 263 static const enum pmc_class *pmc_mdep_class_list; 264 static size_t pmc_mdep_class_list_size; 265 266 /* 267 * Mapping tables, mapping enumeration values to human readable 268 * strings. 269 */ 270 271 static const char * pmc_capability_names[] = { 272 #undef __PMC_CAP 273 #define __PMC_CAP(N,V,D) #N , 274 __PMC_CAPS() 275 }; 276 277 struct pmc_class_map { 278 enum pmc_class pm_class; 279 const char *pm_name; 280 }; 281 282 static const struct pmc_class_map pmc_class_names[] = { 283 #undef __PMC_CLASS 284 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } , 285 __PMC_CLASSES() 286 }; 287 288 struct pmc_cputype_map { 289 enum pmc_cputype pm_cputype; 290 const char *pm_name; 291 }; 292 293 static const struct pmc_cputype_map pmc_cputype_names[] = { 294 #undef __PMC_CPU 295 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 296 __PMC_CPUS() 297 }; 298 299 static const char * pmc_disposition_names[] = { 300 #undef __PMC_DISP 301 #define __PMC_DISP(D) #D , 302 __PMC_DISPOSITIONS() 303 }; 304 305 static const char * pmc_mode_names[] = { 306 #undef __PMC_MODE 307 #define __PMC_MODE(M,N) #M , 308 __PMC_MODES() 309 }; 310 311 static const char * pmc_state_names[] = { 312 #undef __PMC_STATE 313 #define __PMC_STATE(S) #S , 314 __PMC_STATES() 315 }; 316 317 /* 318 * Filled in by pmc_init(). 319 */ 320 static int pmc_syscall = -1; 321 static struct pmc_cpuinfo cpu_info; 322 static struct pmc_op_getdyneventinfo soft_event_info; 323 324 /* Event masks for events */ 325 struct pmc_masks { 326 const char *pm_name; 327 const uint64_t pm_value; 328 }; 329 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 330 #define NULLMASK { .pm_name = NULL } 331 332 #if defined(__amd64__) || defined(__i386__) 333 static int 334 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 335 { 336 const struct pmc_masks *pm; 337 char *q, *r; 338 int c; 339 340 if (pmask == NULL) /* no mask keywords */ 341 return (-1); 342 q = strchr(p, '='); /* skip '=' */ 343 if (*++q == '\0') /* no more data */ 344 return (-1); 345 c = 0; /* count of mask keywords seen */ 346 while ((r = strsep(&q, "+")) != NULL) { 347 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 348 pm++) 349 ; 350 if (pm->pm_name == NULL) /* not found */ 351 return (-1); 352 *evmask |= pm->pm_value; 353 c++; 354 } 355 return (c); 356 } 357 #endif 358 359 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 360 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 361 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 362 363 #if defined(__amd64__) || defined(__i386__) 364 /* 365 * AMD K8 PMCs. 366 * 367 */ 368 369 static struct pmc_event_alias k8_aliases[] = { 370 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 371 EV_ALIAS("branch-mispredicts", 372 "k8-fr-retired-taken-branches-mispredicted"), 373 EV_ALIAS("cycles", "tsc"), 374 EV_ALIAS("dc-misses", "k8-dc-miss"), 375 EV_ALIAS("ic-misses", "k8-ic-miss"), 376 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 377 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 378 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 379 EV_ALIAS(NULL, NULL) 380 }; 381 382 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 383 384 /* 385 * Parsing tables 386 */ 387 388 /* fp dispatched fpu ops */ 389 static const struct pmc_masks k8_mask_fdfo[] = { 390 __K8MASK(add-pipe-excluding-junk-ops, 0), 391 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 392 __K8MASK(store-pipe-excluding-junk-ops, 2), 393 __K8MASK(add-pipe-junk-ops, 3), 394 __K8MASK(multiply-pipe-junk-ops, 4), 395 __K8MASK(store-pipe-junk-ops, 5), 396 NULLMASK 397 }; 398 399 /* ls segment register loads */ 400 static const struct pmc_masks k8_mask_lsrl[] = { 401 __K8MASK(es, 0), 402 __K8MASK(cs, 1), 403 __K8MASK(ss, 2), 404 __K8MASK(ds, 3), 405 __K8MASK(fs, 4), 406 __K8MASK(gs, 5), 407 __K8MASK(hs, 6), 408 NULLMASK 409 }; 410 411 /* ls locked operation */ 412 static const struct pmc_masks k8_mask_llo[] = { 413 __K8MASK(locked-instructions, 0), 414 __K8MASK(cycles-in-request, 1), 415 __K8MASK(cycles-to-complete, 2), 416 NULLMASK 417 }; 418 419 /* dc refill from {l2,system} and dc copyback */ 420 static const struct pmc_masks k8_mask_dc[] = { 421 __K8MASK(invalid, 0), 422 __K8MASK(shared, 1), 423 __K8MASK(exclusive, 2), 424 __K8MASK(owner, 3), 425 __K8MASK(modified, 4), 426 NULLMASK 427 }; 428 429 /* dc one bit ecc error */ 430 static const struct pmc_masks k8_mask_dobee[] = { 431 __K8MASK(scrubber, 0), 432 __K8MASK(piggyback, 1), 433 NULLMASK 434 }; 435 436 /* dc dispatched prefetch instructions */ 437 static const struct pmc_masks k8_mask_ddpi[] = { 438 __K8MASK(load, 0), 439 __K8MASK(store, 1), 440 __K8MASK(nta, 2), 441 NULLMASK 442 }; 443 444 /* dc dcache accesses by locks */ 445 static const struct pmc_masks k8_mask_dabl[] = { 446 __K8MASK(accesses, 0), 447 __K8MASK(misses, 1), 448 NULLMASK 449 }; 450 451 /* bu internal l2 request */ 452 static const struct pmc_masks k8_mask_bilr[] = { 453 __K8MASK(ic-fill, 0), 454 __K8MASK(dc-fill, 1), 455 __K8MASK(tlb-reload, 2), 456 __K8MASK(tag-snoop, 3), 457 __K8MASK(cancelled, 4), 458 NULLMASK 459 }; 460 461 /* bu fill request l2 miss */ 462 static const struct pmc_masks k8_mask_bfrlm[] = { 463 __K8MASK(ic-fill, 0), 464 __K8MASK(dc-fill, 1), 465 __K8MASK(tlb-reload, 2), 466 NULLMASK 467 }; 468 469 /* bu fill into l2 */ 470 static const struct pmc_masks k8_mask_bfil[] = { 471 __K8MASK(dirty-l2-victim, 0), 472 __K8MASK(victim-from-l2, 1), 473 NULLMASK 474 }; 475 476 /* fr retired fpu instructions */ 477 static const struct pmc_masks k8_mask_frfi[] = { 478 __K8MASK(x87, 0), 479 __K8MASK(mmx-3dnow, 1), 480 __K8MASK(packed-sse-sse2, 2), 481 __K8MASK(scalar-sse-sse2, 3), 482 NULLMASK 483 }; 484 485 /* fr retired fastpath double op instructions */ 486 static const struct pmc_masks k8_mask_frfdoi[] = { 487 __K8MASK(low-op-pos-0, 0), 488 __K8MASK(low-op-pos-1, 1), 489 __K8MASK(low-op-pos-2, 2), 490 NULLMASK 491 }; 492 493 /* fr fpu exceptions */ 494 static const struct pmc_masks k8_mask_ffe[] = { 495 __K8MASK(x87-reclass-microfaults, 0), 496 __K8MASK(sse-retype-microfaults, 1), 497 __K8MASK(sse-reclass-microfaults, 2), 498 __K8MASK(sse-and-x87-microtraps, 3), 499 NULLMASK 500 }; 501 502 /* nb memory controller page access event */ 503 static const struct pmc_masks k8_mask_nmcpae[] = { 504 __K8MASK(page-hit, 0), 505 __K8MASK(page-miss, 1), 506 __K8MASK(page-conflict, 2), 507 NULLMASK 508 }; 509 510 /* nb memory controller turnaround */ 511 static const struct pmc_masks k8_mask_nmct[] = { 512 __K8MASK(dimm-turnaround, 0), 513 __K8MASK(read-to-write-turnaround, 1), 514 __K8MASK(write-to-read-turnaround, 2), 515 NULLMASK 516 }; 517 518 /* nb memory controller bypass saturation */ 519 static const struct pmc_masks k8_mask_nmcbs[] = { 520 __K8MASK(memory-controller-hi-pri-bypass, 0), 521 __K8MASK(memory-controller-lo-pri-bypass, 1), 522 __K8MASK(dram-controller-interface-bypass, 2), 523 __K8MASK(dram-controller-queue-bypass, 3), 524 NULLMASK 525 }; 526 527 /* nb sized commands */ 528 static const struct pmc_masks k8_mask_nsc[] = { 529 __K8MASK(nonpostwrszbyte, 0), 530 __K8MASK(nonpostwrszdword, 1), 531 __K8MASK(postwrszbyte, 2), 532 __K8MASK(postwrszdword, 3), 533 __K8MASK(rdszbyte, 4), 534 __K8MASK(rdszdword, 5), 535 __K8MASK(rdmodwr, 6), 536 NULLMASK 537 }; 538 539 /* nb probe result */ 540 static const struct pmc_masks k8_mask_npr[] = { 541 __K8MASK(probe-miss, 0), 542 __K8MASK(probe-hit, 1), 543 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 544 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 545 NULLMASK 546 }; 547 548 /* nb hypertransport bus bandwidth */ 549 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 550 __K8MASK(command, 0), 551 __K8MASK(data, 1), 552 __K8MASK(buffer-release, 2), 553 __K8MASK(nop, 3), 554 NULLMASK 555 }; 556 557 #undef __K8MASK 558 559 #define K8_KW_COUNT "count" 560 #define K8_KW_EDGE "edge" 561 #define K8_KW_INV "inv" 562 #define K8_KW_MASK "mask" 563 #define K8_KW_OS "os" 564 #define K8_KW_USR "usr" 565 566 static int 567 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 568 struct pmc_op_pmcallocate *pmc_config) 569 { 570 char *e, *p, *q; 571 int n; 572 uint32_t count; 573 uint64_t evmask; 574 const struct pmc_masks *pm, *pmask; 575 576 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 577 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 578 579 pmask = NULL; 580 evmask = 0; 581 582 #define __K8SETMASK(M) pmask = k8_mask_##M 583 584 /* setup parsing tables */ 585 switch (pe) { 586 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 587 __K8SETMASK(fdfo); 588 break; 589 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 590 __K8SETMASK(lsrl); 591 break; 592 case PMC_EV_K8_LS_LOCKED_OPERATION: 593 __K8SETMASK(llo); 594 break; 595 case PMC_EV_K8_DC_REFILL_FROM_L2: 596 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 597 case PMC_EV_K8_DC_COPYBACK: 598 __K8SETMASK(dc); 599 break; 600 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 601 __K8SETMASK(dobee); 602 break; 603 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 604 __K8SETMASK(ddpi); 605 break; 606 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 607 __K8SETMASK(dabl); 608 break; 609 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 610 __K8SETMASK(bilr); 611 break; 612 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 613 __K8SETMASK(bfrlm); 614 break; 615 case PMC_EV_K8_BU_FILL_INTO_L2: 616 __K8SETMASK(bfil); 617 break; 618 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 619 __K8SETMASK(frfi); 620 break; 621 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 622 __K8SETMASK(frfdoi); 623 break; 624 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 625 __K8SETMASK(ffe); 626 break; 627 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 628 __K8SETMASK(nmcpae); 629 break; 630 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 631 __K8SETMASK(nmct); 632 break; 633 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 634 __K8SETMASK(nmcbs); 635 break; 636 case PMC_EV_K8_NB_SIZED_COMMANDS: 637 __K8SETMASK(nsc); 638 break; 639 case PMC_EV_K8_NB_PROBE_RESULT: 640 __K8SETMASK(npr); 641 break; 642 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 643 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 644 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 645 __K8SETMASK(nhbb); 646 break; 647 648 default: 649 break; /* no options defined */ 650 } 651 652 while ((p = strsep(&ctrspec, ",")) != NULL) { 653 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 654 q = strchr(p, '='); 655 if (*++q == '\0') /* skip '=' */ 656 return (-1); 657 658 count = strtol(q, &e, 0); 659 if (e == q || *e != '\0') 660 return (-1); 661 662 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 663 pmc_config->pm_md.pm_amd.pm_amd_config |= 664 AMD_PMC_TO_COUNTER(count); 665 666 } else if (KWMATCH(p, K8_KW_EDGE)) { 667 pmc_config->pm_caps |= PMC_CAP_EDGE; 668 } else if (KWMATCH(p, K8_KW_INV)) { 669 pmc_config->pm_caps |= PMC_CAP_INVERT; 670 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 671 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 672 return (-1); 673 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 674 } else if (KWMATCH(p, K8_KW_OS)) { 675 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 676 } else if (KWMATCH(p, K8_KW_USR)) { 677 pmc_config->pm_caps |= PMC_CAP_USER; 678 } else 679 return (-1); 680 } 681 682 /* other post processing */ 683 switch (pe) { 684 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 685 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 686 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 687 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 688 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 689 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 690 /* XXX only available in rev B and later */ 691 break; 692 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 693 /* XXX only available in rev C and later */ 694 break; 695 case PMC_EV_K8_LS_LOCKED_OPERATION: 696 /* XXX CPU Rev A,B evmask is to be zero */ 697 if (evmask & (evmask - 1)) /* > 1 bit set */ 698 return (-1); 699 if (evmask == 0) { 700 evmask = 0x01; /* Rev C and later: #instrs */ 701 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 702 } 703 break; 704 default: 705 if (evmask == 0 && pmask != NULL) { 706 for (pm = pmask; pm->pm_name; pm++) 707 evmask |= pm->pm_value; 708 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 709 } 710 } 711 712 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 713 pmc_config->pm_md.pm_amd.pm_amd_config = 714 AMD_PMC_TO_UNITMASK(evmask); 715 716 return (0); 717 } 718 719 #endif 720 721 #if defined(__i386__) || defined(__amd64__) 722 static int 723 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 724 struct pmc_op_pmcallocate *pmc_config) 725 { 726 if (pe != PMC_EV_TSC_TSC) 727 return (-1); 728 729 /* TSC events must be unqualified. */ 730 if (ctrspec && *ctrspec != '\0') 731 return (-1); 732 733 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 734 pmc_config->pm_caps |= PMC_CAP_READ; 735 736 return (0); 737 } 738 #endif 739 740 static struct pmc_event_alias generic_aliases[] = { 741 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 742 EV_ALIAS(NULL, NULL) 743 }; 744 745 static int 746 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 747 struct pmc_op_pmcallocate *pmc_config) 748 { 749 (void)ctrspec; 750 (void)pmc_config; 751 752 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 753 return (-1); 754 755 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 756 return (0); 757 } 758 759 #if defined(__arm__) 760 #if defined(__XSCALE__) 761 762 static struct pmc_event_alias xscale_aliases[] = { 763 EV_ALIAS("branches", "BRANCH_RETIRED"), 764 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 765 EV_ALIAS("dc-misses", "DC_MISS"), 766 EV_ALIAS("ic-misses", "IC_MISS"), 767 EV_ALIAS("instructions", "INSTR_RETIRED"), 768 EV_ALIAS(NULL, NULL) 769 }; 770 static int 771 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 772 struct pmc_op_pmcallocate *pmc_config __unused) 773 { 774 switch (pe) { 775 default: 776 break; 777 } 778 779 return (0); 780 } 781 #endif 782 783 static struct pmc_event_alias cortex_a8_aliases[] = { 784 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 785 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 786 EV_ALIAS("instructions", "INSTR_EXECUTED"), 787 EV_ALIAS(NULL, NULL) 788 }; 789 790 static struct pmc_event_alias cortex_a9_aliases[] = { 791 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 792 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 793 EV_ALIAS("instructions", "INSTR_EXECUTED"), 794 EV_ALIAS(NULL, NULL) 795 }; 796 797 static int 798 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 799 struct pmc_op_pmcallocate *pmc_config __unused) 800 { 801 switch (pe) { 802 default: 803 break; 804 } 805 806 return (0); 807 } 808 #endif 809 810 #if defined(__aarch64__) 811 static struct pmc_event_alias cortex_a53_aliases[] = { 812 EV_ALIAS(NULL, NULL) 813 }; 814 static struct pmc_event_alias cortex_a57_aliases[] = { 815 EV_ALIAS(NULL, NULL) 816 }; 817 static int 818 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 819 struct pmc_op_pmcallocate *pmc_config __unused) 820 { 821 switch (pe) { 822 default: 823 break; 824 } 825 826 return (0); 827 } 828 #endif 829 830 #if defined(__mips__) 831 832 static struct pmc_event_alias mips24k_aliases[] = { 833 EV_ALIAS("instructions", "INSTR_EXECUTED"), 834 EV_ALIAS("branches", "BRANCH_COMPLETED"), 835 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 836 EV_ALIAS(NULL, NULL) 837 }; 838 839 static struct pmc_event_alias mips74k_aliases[] = { 840 EV_ALIAS("instructions", "INSTR_EXECUTED"), 841 EV_ALIAS("branches", "BRANCH_INSNS"), 842 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"), 843 EV_ALIAS(NULL, NULL) 844 }; 845 846 static struct pmc_event_alias octeon_aliases[] = { 847 EV_ALIAS("instructions", "RET"), 848 EV_ALIAS("branches", "BR"), 849 EV_ALIAS("branch-mispredicts", "BRMIS"), 850 EV_ALIAS(NULL, NULL) 851 }; 852 853 #define MIPS_KW_OS "os" 854 #define MIPS_KW_USR "usr" 855 #define MIPS_KW_ANYTHREAD "anythread" 856 857 static int 858 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 859 struct pmc_op_pmcallocate *pmc_config __unused) 860 { 861 char *p; 862 863 (void) pe; 864 865 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 866 867 while ((p = strsep(&ctrspec, ",")) != NULL) { 868 if (KWMATCH(p, MIPS_KW_OS)) 869 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 870 else if (KWMATCH(p, MIPS_KW_USR)) 871 pmc_config->pm_caps |= PMC_CAP_USER; 872 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 873 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 874 else 875 return (-1); 876 } 877 878 return (0); 879 } 880 881 #endif /* __mips__ */ 882 883 #if defined(__powerpc__) 884 885 static struct pmc_event_alias ppc7450_aliases[] = { 886 EV_ALIAS("instructions", "INSTR_COMPLETED"), 887 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 888 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 889 EV_ALIAS(NULL, NULL) 890 }; 891 892 static struct pmc_event_alias ppc970_aliases[] = { 893 EV_ALIAS("instructions", "INSTR_COMPLETED"), 894 EV_ALIAS("cycles", "CYCLES"), 895 EV_ALIAS(NULL, NULL) 896 }; 897 898 static struct pmc_event_alias e500_aliases[] = { 899 EV_ALIAS("instructions", "INSTR_COMPLETED"), 900 EV_ALIAS("cycles", "CYCLES"), 901 EV_ALIAS(NULL, NULL) 902 }; 903 904 #define POWERPC_KW_OS "os" 905 #define POWERPC_KW_USR "usr" 906 #define POWERPC_KW_ANYTHREAD "anythread" 907 908 static int 909 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 910 struct pmc_op_pmcallocate *pmc_config __unused) 911 { 912 char *p; 913 914 (void) pe; 915 916 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 917 918 while ((p = strsep(&ctrspec, ",")) != NULL) { 919 if (KWMATCH(p, POWERPC_KW_OS)) 920 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 921 else if (KWMATCH(p, POWERPC_KW_USR)) 922 pmc_config->pm_caps |= PMC_CAP_USER; 923 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 924 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 925 else 926 return (-1); 927 } 928 929 return (0); 930 } 931 932 #endif /* __powerpc__ */ 933 934 935 /* 936 * Match an event name `name' with its canonical form. 937 * 938 * Matches are case insensitive and spaces, periods, underscores and 939 * hyphen characters are considered to match each other. 940 * 941 * Returns 1 for a match, 0 otherwise. 942 */ 943 944 static int 945 pmc_match_event_name(const char *name, const char *canonicalname) 946 { 947 int cc, nc; 948 const unsigned char *c, *n; 949 950 c = (const unsigned char *) canonicalname; 951 n = (const unsigned char *) name; 952 953 for (; (nc = *n) && (cc = *c); n++, c++) { 954 955 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 956 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 957 continue; 958 959 if (toupper(nc) == toupper(cc)) 960 continue; 961 962 963 return (0); 964 } 965 966 if (*n == '\0' && *c == '\0') 967 return (1); 968 969 return (0); 970 } 971 972 /* 973 * Match an event name against all the event named supported by a 974 * PMC class. 975 * 976 * Returns an event descriptor pointer on match or NULL otherwise. 977 */ 978 static const struct pmc_event_descr * 979 pmc_match_event_class(const char *name, 980 const struct pmc_class_descr *pcd) 981 { 982 size_t n; 983 const struct pmc_event_descr *ev; 984 985 ev = pcd->pm_evc_event_table; 986 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 987 if (pmc_match_event_name(name, ev->pm_ev_name)) 988 return (ev); 989 990 return (NULL); 991 } 992 993 static int 994 pmc_mdep_is_compatible_class(enum pmc_class pc) 995 { 996 size_t n; 997 998 for (n = 0; n < pmc_mdep_class_list_size; n++) 999 if (pmc_mdep_class_list[n] == pc) 1000 return (1); 1001 return (0); 1002 } 1003 1004 /* 1005 * API entry points 1006 */ 1007 1008 int 1009 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 1010 uint32_t flags, int cpu, pmc_id_t *pmcid) 1011 { 1012 size_t n; 1013 int retval; 1014 char *r, *spec_copy; 1015 const char *ctrname; 1016 const struct pmc_event_descr *ev; 1017 const struct pmc_event_alias *alias; 1018 struct pmc_op_pmcallocate pmc_config; 1019 const struct pmc_class_descr *pcd; 1020 1021 spec_copy = NULL; 1022 retval = -1; 1023 1024 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 1025 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 1026 errno = EINVAL; 1027 goto out; 1028 } 1029 bzero(&pmc_config, sizeof(pmc_config)); 1030 pmc_config.pm_cpu = cpu; 1031 pmc_config.pm_mode = mode; 1032 pmc_config.pm_flags = flags; 1033 if (PMC_IS_SAMPLING_MODE(mode)) 1034 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 1035 /* 1036 * Can we pull this straight from the pmu table? 1037 */ 1038 r = spec_copy = strdup(ctrspec); 1039 ctrname = strsep(&r, ","); 1040 if (pmc_pmu_enabled()) { 1041 if (pmc_pmu_pmcallocate(ctrname, &pmc_config) == 0) { 1042 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) { 1043 goto out; 1044 } 1045 retval = 0; 1046 *pmcid = pmc_config.pm_pmcid; 1047 goto out; 1048 } 1049 errx(EX_USAGE, "ERROR: pmc_pmu_allocate failed, check for ctrname %s\n", ctrname); 1050 } else { 1051 free(spec_copy); 1052 spec_copy = NULL; 1053 } 1054 1055 /* replace an event alias with the canonical event specifier */ 1056 if (pmc_mdep_event_aliases) 1057 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 1058 if (!strcasecmp(ctrspec, alias->pm_alias)) { 1059 spec_copy = strdup(alias->pm_spec); 1060 break; 1061 } 1062 1063 if (spec_copy == NULL) 1064 spec_copy = strdup(ctrspec); 1065 1066 r = spec_copy; 1067 ctrname = strsep(&r, ","); 1068 1069 /* 1070 * If a explicit class prefix was given by the user, restrict the 1071 * search for the event to the specified PMC class. 1072 */ 1073 ev = NULL; 1074 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 1075 pcd = pmc_class_table[n]; 1076 if (pcd && pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 1077 strncasecmp(ctrname, pcd->pm_evc_name, 1078 pcd->pm_evc_name_size) == 0) { 1079 if ((ev = pmc_match_event_class(ctrname + 1080 pcd->pm_evc_name_size, pcd)) == NULL) { 1081 errno = EINVAL; 1082 goto out; 1083 } 1084 break; 1085 } 1086 } 1087 1088 /* 1089 * Otherwise, search for this event in all compatible PMC 1090 * classes. 1091 */ 1092 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 1093 pcd = pmc_class_table[n]; 1094 if (pcd && pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 1095 ev = pmc_match_event_class(ctrname, pcd); 1096 } 1097 1098 if (ev == NULL) { 1099 errno = EINVAL; 1100 goto out; 1101 } 1102 1103 pmc_config.pm_ev = ev->pm_ev_code; 1104 pmc_config.pm_class = pcd->pm_evc_class; 1105 1106 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 1107 errno = EINVAL; 1108 goto out; 1109 } 1110 1111 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 1112 goto out; 1113 1114 *pmcid = pmc_config.pm_pmcid; 1115 1116 retval = 0; 1117 1118 out: 1119 if (spec_copy) 1120 free(spec_copy); 1121 1122 return (retval); 1123 } 1124 1125 int 1126 pmc_attach(pmc_id_t pmc, pid_t pid) 1127 { 1128 struct pmc_op_pmcattach pmc_attach_args; 1129 1130 pmc_attach_args.pm_pmc = pmc; 1131 pmc_attach_args.pm_pid = pid; 1132 1133 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 1134 } 1135 1136 int 1137 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 1138 { 1139 unsigned int i; 1140 enum pmc_class cl; 1141 1142 cl = PMC_ID_TO_CLASS(pmcid); 1143 for (i = 0; i < cpu_info.pm_nclass; i++) 1144 if (cpu_info.pm_classes[i].pm_class == cl) { 1145 *caps = cpu_info.pm_classes[i].pm_caps; 1146 return (0); 1147 } 1148 errno = EINVAL; 1149 return (-1); 1150 } 1151 1152 int 1153 pmc_configure_logfile(int fd) 1154 { 1155 struct pmc_op_configurelog cla; 1156 1157 cla.pm_logfd = fd; 1158 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 1159 return (-1); 1160 return (0); 1161 } 1162 1163 int 1164 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 1165 { 1166 if (pmc_syscall == -1) { 1167 errno = ENXIO; 1168 return (-1); 1169 } 1170 1171 *pci = &cpu_info; 1172 return (0); 1173 } 1174 1175 int 1176 pmc_detach(pmc_id_t pmc, pid_t pid) 1177 { 1178 struct pmc_op_pmcattach pmc_detach_args; 1179 1180 pmc_detach_args.pm_pmc = pmc; 1181 pmc_detach_args.pm_pid = pid; 1182 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 1183 } 1184 1185 int 1186 pmc_disable(int cpu, int pmc) 1187 { 1188 struct pmc_op_pmcadmin ssa; 1189 1190 ssa.pm_cpu = cpu; 1191 ssa.pm_pmc = pmc; 1192 ssa.pm_state = PMC_STATE_DISABLED; 1193 return (PMC_CALL(PMCADMIN, &ssa)); 1194 } 1195 1196 int 1197 pmc_enable(int cpu, int pmc) 1198 { 1199 struct pmc_op_pmcadmin ssa; 1200 1201 ssa.pm_cpu = cpu; 1202 ssa.pm_pmc = pmc; 1203 ssa.pm_state = PMC_STATE_FREE; 1204 return (PMC_CALL(PMCADMIN, &ssa)); 1205 } 1206 1207 /* 1208 * Return a list of events known to a given PMC class. 'cl' is the 1209 * PMC class identifier, 'eventnames' is the returned list of 'const 1210 * char *' pointers pointing to the names of the events. 'nevents' is 1211 * the number of event name pointers returned. 1212 * 1213 * The space for 'eventnames' is allocated using malloc(3). The caller 1214 * is responsible for freeing this space when done. 1215 */ 1216 int 1217 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 1218 int *nevents) 1219 { 1220 int count; 1221 const char **names; 1222 const struct pmc_event_descr *ev; 1223 1224 switch (cl) 1225 { 1226 case PMC_CLASS_IAF: 1227 ev = iaf_event_table; 1228 count = PMC_EVENT_TABLE_SIZE(iaf); 1229 break; 1230 case PMC_CLASS_TSC: 1231 ev = tsc_event_table; 1232 count = PMC_EVENT_TABLE_SIZE(tsc); 1233 break; 1234 case PMC_CLASS_K8: 1235 ev = k8_event_table; 1236 count = PMC_EVENT_TABLE_SIZE(k8); 1237 break; 1238 case PMC_CLASS_XSCALE: 1239 ev = xscale_event_table; 1240 count = PMC_EVENT_TABLE_SIZE(xscale); 1241 break; 1242 case PMC_CLASS_ARMV7: 1243 switch (cpu_info.pm_cputype) { 1244 default: 1245 case PMC_CPU_ARMV7_CORTEX_A8: 1246 ev = cortex_a8_event_table; 1247 count = PMC_EVENT_TABLE_SIZE(cortex_a8); 1248 break; 1249 case PMC_CPU_ARMV7_CORTEX_A9: 1250 ev = cortex_a9_event_table; 1251 count = PMC_EVENT_TABLE_SIZE(cortex_a9); 1252 break; 1253 } 1254 break; 1255 case PMC_CLASS_ARMV8: 1256 switch (cpu_info.pm_cputype) { 1257 default: 1258 case PMC_CPU_ARMV8_CORTEX_A53: 1259 ev = cortex_a53_event_table; 1260 count = PMC_EVENT_TABLE_SIZE(cortex_a53); 1261 break; 1262 case PMC_CPU_ARMV8_CORTEX_A57: 1263 ev = cortex_a57_event_table; 1264 count = PMC_EVENT_TABLE_SIZE(cortex_a57); 1265 break; 1266 } 1267 break; 1268 case PMC_CLASS_MIPS24K: 1269 ev = mips24k_event_table; 1270 count = PMC_EVENT_TABLE_SIZE(mips24k); 1271 break; 1272 case PMC_CLASS_MIPS74K: 1273 ev = mips74k_event_table; 1274 count = PMC_EVENT_TABLE_SIZE(mips74k); 1275 break; 1276 case PMC_CLASS_OCTEON: 1277 ev = octeon_event_table; 1278 count = PMC_EVENT_TABLE_SIZE(octeon); 1279 break; 1280 case PMC_CLASS_PPC7450: 1281 ev = ppc7450_event_table; 1282 count = PMC_EVENT_TABLE_SIZE(ppc7450); 1283 break; 1284 case PMC_CLASS_PPC970: 1285 ev = ppc970_event_table; 1286 count = PMC_EVENT_TABLE_SIZE(ppc970); 1287 break; 1288 case PMC_CLASS_E500: 1289 ev = e500_event_table; 1290 count = PMC_EVENT_TABLE_SIZE(e500); 1291 break; 1292 case PMC_CLASS_SOFT: 1293 ev = soft_event_table; 1294 count = soft_event_info.pm_nevent; 1295 break; 1296 default: 1297 errno = EINVAL; 1298 return (-1); 1299 } 1300 1301 if ((names = malloc(count * sizeof(const char *))) == NULL) 1302 return (-1); 1303 1304 *eventnames = names; 1305 *nevents = count; 1306 1307 for (;count--; ev++, names++) 1308 *names = ev->pm_ev_name; 1309 1310 return (0); 1311 } 1312 1313 int 1314 pmc_flush_logfile(void) 1315 { 1316 return (PMC_CALL(FLUSHLOG,0)); 1317 } 1318 1319 int 1320 pmc_close_logfile(void) 1321 { 1322 return (PMC_CALL(CLOSELOG,0)); 1323 } 1324 1325 int 1326 pmc_get_driver_stats(struct pmc_driverstats *ds) 1327 { 1328 struct pmc_op_getdriverstats gms; 1329 1330 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 1331 return (-1); 1332 1333 /* copy out fields in the current userland<->library interface */ 1334 ds->pm_intr_ignored = gms.pm_intr_ignored; 1335 ds->pm_intr_processed = gms.pm_intr_processed; 1336 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 1337 ds->pm_syscalls = gms.pm_syscalls; 1338 ds->pm_syscall_errors = gms.pm_syscall_errors; 1339 ds->pm_buffer_requests = gms.pm_buffer_requests; 1340 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 1341 ds->pm_log_sweeps = gms.pm_log_sweeps; 1342 return (0); 1343 } 1344 1345 int 1346 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 1347 { 1348 struct pmc_op_getmsr gm; 1349 1350 gm.pm_pmcid = pmc; 1351 if (PMC_CALL(PMCGETMSR, &gm) < 0) 1352 return (-1); 1353 *msr = gm.pm_msr; 1354 return (0); 1355 } 1356 1357 int 1358 pmc_init(void) 1359 { 1360 int error, pmc_mod_id; 1361 unsigned int n; 1362 uint32_t abi_version; 1363 struct module_stat pmc_modstat; 1364 struct pmc_op_getcpuinfo op_cpu_info; 1365 #if defined(__amd64__) || defined(__i386__) 1366 int cpu_has_iaf_counters; 1367 unsigned int t; 1368 #endif 1369 1370 if (pmc_syscall != -1) /* already inited */ 1371 return (0); 1372 1373 /* retrieve the system call number from the KLD */ 1374 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 1375 return (-1); 1376 1377 pmc_modstat.version = sizeof(struct module_stat); 1378 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 1379 return (-1); 1380 1381 pmc_syscall = pmc_modstat.data.intval; 1382 1383 /* check the kernel module's ABI against our compiled-in version */ 1384 abi_version = PMC_VERSION; 1385 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 1386 return (pmc_syscall = -1); 1387 1388 /* ignore patch & minor numbers for the comparison */ 1389 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 1390 errno = EPROGMISMATCH; 1391 return (pmc_syscall = -1); 1392 } 1393 1394 bzero(&op_cpu_info, sizeof(op_cpu_info)); 1395 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 1396 return (pmc_syscall = -1); 1397 1398 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 1399 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 1400 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 1401 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 1402 for (n = 0; n < op_cpu_info.pm_nclass; n++) 1403 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n], 1404 sizeof(cpu_info.pm_classes[n])); 1405 1406 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 1407 sizeof(struct pmc_class_descr *)); 1408 1409 if (pmc_class_table == NULL) 1410 return (-1); 1411 1412 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 1413 pmc_class_table[n] = NULL; 1414 1415 /* 1416 * Get soft events list. 1417 */ 1418 soft_event_info.pm_class = PMC_CLASS_SOFT; 1419 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 1420 return (pmc_syscall = -1); 1421 1422 /* Map soft events to static list. */ 1423 for (n = 0; n < soft_event_info.pm_nevent; n++) { 1424 soft_event_table[n].pm_ev_name = 1425 soft_event_info.pm_events[n].pm_ev_name; 1426 soft_event_table[n].pm_ev_code = 1427 soft_event_info.pm_events[n].pm_ev_code; 1428 } 1429 soft_class_table_descr.pm_evc_event_table_size = \ 1430 soft_event_info.pm_nevent; 1431 soft_class_table_descr.pm_evc_event_table = \ 1432 soft_event_table; 1433 1434 /* 1435 * Fill in the class table. 1436 */ 1437 n = 0; 1438 1439 /* Fill soft events information. */ 1440 pmc_class_table[n++] = &soft_class_table_descr; 1441 #if defined(__amd64__) || defined(__i386__) 1442 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 1443 pmc_class_table[n++] = &tsc_class_table_descr; 1444 1445 /* 1446 * Check if this CPU has fixed function counters. 1447 */ 1448 cpu_has_iaf_counters = 0; 1449 for (t = 0; t < cpu_info.pm_nclass; t++) 1450 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 1451 cpu_info.pm_classes[t].pm_num > 0) 1452 cpu_has_iaf_counters = 1; 1453 #endif 1454 1455 #define PMC_MDEP_INIT(C) do { \ 1456 pmc_mdep_event_aliases = C##_aliases; \ 1457 pmc_mdep_class_list = C##_pmc_classes; \ 1458 pmc_mdep_class_list_size = \ 1459 PMC_TABLE_SIZE(C##_pmc_classes); \ 1460 } while (0) 1461 1462 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 1463 PMC_MDEP_INIT(C); \ 1464 pmc_class_table[n++] = &iaf_class_table_descr; \ 1465 if (!cpu_has_iaf_counters) \ 1466 pmc_mdep_event_aliases = \ 1467 C##_aliases_without_iaf; \ 1468 pmc_class_table[n] = &C##_class_table_descr; \ 1469 } while (0) 1470 1471 /* Configure the event name parser. */ 1472 switch (cpu_info.pm_cputype) { 1473 #if defined(__amd64__) || defined(__i386__) 1474 case PMC_CPU_AMD_K8: 1475 PMC_MDEP_INIT(k8); 1476 pmc_class_table[n] = &k8_class_table_descr; 1477 break; 1478 #endif 1479 case PMC_CPU_GENERIC: 1480 PMC_MDEP_INIT(generic); 1481 break; 1482 #if defined(__arm__) 1483 #if defined(__XSCALE__) 1484 case PMC_CPU_INTEL_XSCALE: 1485 PMC_MDEP_INIT(xscale); 1486 pmc_class_table[n] = &xscale_class_table_descr; 1487 break; 1488 #endif 1489 case PMC_CPU_ARMV7_CORTEX_A8: 1490 PMC_MDEP_INIT(cortex_a8); 1491 pmc_class_table[n] = &cortex_a8_class_table_descr; 1492 break; 1493 case PMC_CPU_ARMV7_CORTEX_A9: 1494 PMC_MDEP_INIT(cortex_a9); 1495 pmc_class_table[n] = &cortex_a9_class_table_descr; 1496 break; 1497 #endif 1498 #if defined(__aarch64__) 1499 case PMC_CPU_ARMV8_CORTEX_A53: 1500 PMC_MDEP_INIT(cortex_a53); 1501 pmc_class_table[n] = &cortex_a53_class_table_descr; 1502 break; 1503 case PMC_CPU_ARMV8_CORTEX_A57: 1504 PMC_MDEP_INIT(cortex_a57); 1505 pmc_class_table[n] = &cortex_a57_class_table_descr; 1506 break; 1507 #endif 1508 #if defined(__mips__) 1509 case PMC_CPU_MIPS_24K: 1510 PMC_MDEP_INIT(mips24k); 1511 pmc_class_table[n] = &mips24k_class_table_descr; 1512 break; 1513 case PMC_CPU_MIPS_74K: 1514 PMC_MDEP_INIT(mips74k); 1515 pmc_class_table[n] = &mips74k_class_table_descr; 1516 break; 1517 case PMC_CPU_MIPS_OCTEON: 1518 PMC_MDEP_INIT(octeon); 1519 pmc_class_table[n] = &octeon_class_table_descr; 1520 break; 1521 #endif /* __mips__ */ 1522 #if defined(__powerpc__) 1523 case PMC_CPU_PPC_7450: 1524 PMC_MDEP_INIT(ppc7450); 1525 pmc_class_table[n] = &ppc7450_class_table_descr; 1526 break; 1527 case PMC_CPU_PPC_970: 1528 PMC_MDEP_INIT(ppc970); 1529 pmc_class_table[n] = &ppc970_class_table_descr; 1530 break; 1531 case PMC_CPU_PPC_E500: 1532 PMC_MDEP_INIT(e500); 1533 pmc_class_table[n] = &e500_class_table_descr; 1534 break; 1535 #endif 1536 default: 1537 /* 1538 * Some kind of CPU this version of the library knows nothing 1539 * about. This shouldn't happen since the abi version check 1540 * should have caught this. 1541 */ 1542 #if defined(__amd64__) || defined(__i386__) 1543 break; 1544 #endif 1545 errno = ENXIO; 1546 return (pmc_syscall = -1); 1547 } 1548 1549 return (0); 1550 } 1551 1552 const char * 1553 pmc_name_of_capability(enum pmc_caps cap) 1554 { 1555 int i; 1556 1557 /* 1558 * 'cap' should have a single bit set and should be in 1559 * range. 1560 */ 1561 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 1562 cap > PMC_CAP_LAST) { 1563 errno = EINVAL; 1564 return (NULL); 1565 } 1566 1567 i = ffs(cap); 1568 return (pmc_capability_names[i - 1]); 1569 } 1570 1571 const char * 1572 pmc_name_of_class(enum pmc_class pc) 1573 { 1574 size_t n; 1575 1576 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++) 1577 if (pc == pmc_class_names[n].pm_class) 1578 return (pmc_class_names[n].pm_name); 1579 1580 errno = EINVAL; 1581 return (NULL); 1582 } 1583 1584 const char * 1585 pmc_name_of_cputype(enum pmc_cputype cp) 1586 { 1587 size_t n; 1588 1589 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 1590 if (cp == pmc_cputype_names[n].pm_cputype) 1591 return (pmc_cputype_names[n].pm_name); 1592 1593 errno = EINVAL; 1594 return (NULL); 1595 } 1596 1597 const char * 1598 pmc_name_of_disposition(enum pmc_disp pd) 1599 { 1600 if ((int) pd >= PMC_DISP_FIRST && 1601 pd <= PMC_DISP_LAST) 1602 return (pmc_disposition_names[pd]); 1603 1604 errno = EINVAL; 1605 return (NULL); 1606 } 1607 1608 const char * 1609 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 1610 { 1611 const struct pmc_event_descr *ev, *evfence; 1612 1613 ev = evfence = NULL; 1614 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 1615 ev = k8_event_table; 1616 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 1617 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 1618 ev = xscale_event_table; 1619 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 1620 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 1621 switch (cpu) { 1622 case PMC_CPU_ARMV7_CORTEX_A8: 1623 ev = cortex_a8_event_table; 1624 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8); 1625 break; 1626 case PMC_CPU_ARMV7_CORTEX_A9: 1627 ev = cortex_a9_event_table; 1628 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9); 1629 break; 1630 default: /* Unknown CPU type. */ 1631 break; 1632 } 1633 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { 1634 switch (cpu) { 1635 case PMC_CPU_ARMV8_CORTEX_A53: 1636 ev = cortex_a53_event_table; 1637 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); 1638 break; 1639 case PMC_CPU_ARMV8_CORTEX_A57: 1640 ev = cortex_a57_event_table; 1641 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); 1642 break; 1643 default: /* Unknown CPU type. */ 1644 break; 1645 } 1646 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 1647 ev = mips24k_event_table; 1648 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 1649 } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { 1650 ev = mips74k_event_table; 1651 evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); 1652 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 1653 ev = octeon_event_table; 1654 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 1655 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 1656 ev = ppc7450_event_table; 1657 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 1658 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 1659 ev = ppc970_event_table; 1660 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 1661 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { 1662 ev = e500_event_table; 1663 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); 1664 } else if (pe == PMC_EV_TSC_TSC) { 1665 ev = tsc_event_table; 1666 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 1667 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 1668 ev = soft_event_table; 1669 evfence = soft_event_table + soft_event_info.pm_nevent; 1670 } 1671 1672 for (; ev != evfence; ev++) 1673 if (pe == ev->pm_ev_code) 1674 return (ev->pm_ev_name); 1675 1676 return (NULL); 1677 } 1678 1679 const char * 1680 pmc_name_of_event(enum pmc_event pe) 1681 { 1682 const char *n; 1683 1684 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 1685 return (n); 1686 1687 errno = EINVAL; 1688 return (NULL); 1689 } 1690 1691 const char * 1692 pmc_name_of_mode(enum pmc_mode pm) 1693 { 1694 if ((int) pm >= PMC_MODE_FIRST && 1695 pm <= PMC_MODE_LAST) 1696 return (pmc_mode_names[pm]); 1697 1698 errno = EINVAL; 1699 return (NULL); 1700 } 1701 1702 const char * 1703 pmc_name_of_state(enum pmc_state ps) 1704 { 1705 if ((int) ps >= PMC_STATE_FIRST && 1706 ps <= PMC_STATE_LAST) 1707 return (pmc_state_names[ps]); 1708 1709 errno = EINVAL; 1710 return (NULL); 1711 } 1712 1713 int 1714 pmc_ncpu(void) 1715 { 1716 if (pmc_syscall == -1) { 1717 errno = ENXIO; 1718 return (-1); 1719 } 1720 1721 return (cpu_info.pm_ncpu); 1722 } 1723 1724 int 1725 pmc_npmc(int cpu) 1726 { 1727 if (pmc_syscall == -1) { 1728 errno = ENXIO; 1729 return (-1); 1730 } 1731 1732 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 1733 errno = EINVAL; 1734 return (-1); 1735 } 1736 1737 return (cpu_info.pm_npmc); 1738 } 1739 1740 int 1741 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 1742 { 1743 int nbytes, npmc; 1744 struct pmc_op_getpmcinfo *pmci; 1745 1746 if ((npmc = pmc_npmc(cpu)) < 0) 1747 return (-1); 1748 1749 nbytes = sizeof(struct pmc_op_getpmcinfo) + 1750 npmc * sizeof(struct pmc_info); 1751 1752 if ((pmci = calloc(1, nbytes)) == NULL) 1753 return (-1); 1754 1755 pmci->pm_cpu = cpu; 1756 1757 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 1758 free(pmci); 1759 return (-1); 1760 } 1761 1762 /* kernel<->library, library<->userland interfaces are identical */ 1763 *ppmci = (struct pmc_pmcinfo *) pmci; 1764 return (0); 1765 } 1766 1767 int 1768 pmc_read(pmc_id_t pmc, pmc_value_t *value) 1769 { 1770 struct pmc_op_pmcrw pmc_read_op; 1771 1772 pmc_read_op.pm_pmcid = pmc; 1773 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 1774 pmc_read_op.pm_value = -1; 1775 1776 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 1777 return (-1); 1778 1779 *value = pmc_read_op.pm_value; 1780 return (0); 1781 } 1782 1783 int 1784 pmc_release(pmc_id_t pmc) 1785 { 1786 struct pmc_op_simple pmc_release_args; 1787 1788 pmc_release_args.pm_pmcid = pmc; 1789 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 1790 } 1791 1792 int 1793 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 1794 { 1795 struct pmc_op_pmcrw pmc_rw_op; 1796 1797 pmc_rw_op.pm_pmcid = pmc; 1798 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 1799 pmc_rw_op.pm_value = newvalue; 1800 1801 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 1802 return (-1); 1803 1804 *oldvaluep = pmc_rw_op.pm_value; 1805 return (0); 1806 } 1807 1808 int 1809 pmc_set(pmc_id_t pmc, pmc_value_t value) 1810 { 1811 struct pmc_op_pmcsetcount sc; 1812 1813 sc.pm_pmcid = pmc; 1814 sc.pm_count = value; 1815 1816 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 1817 return (-1); 1818 return (0); 1819 } 1820 1821 int 1822 pmc_start(pmc_id_t pmc) 1823 { 1824 struct pmc_op_simple pmc_start_args; 1825 1826 pmc_start_args.pm_pmcid = pmc; 1827 return (PMC_CALL(PMCSTART, &pmc_start_args)); 1828 } 1829 1830 int 1831 pmc_stop(pmc_id_t pmc) 1832 { 1833 struct pmc_op_simple pmc_stop_args; 1834 1835 pmc_stop_args.pm_pmcid = pmc; 1836 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 1837 } 1838 1839 int 1840 pmc_width(pmc_id_t pmcid, uint32_t *width) 1841 { 1842 unsigned int i; 1843 enum pmc_class cl; 1844 1845 cl = PMC_ID_TO_CLASS(pmcid); 1846 for (i = 0; i < cpu_info.pm_nclass; i++) 1847 if (cpu_info.pm_classes[i].pm_class == cl) { 1848 *width = cpu_info.pm_classes[i].pm_width; 1849 return (0); 1850 } 1851 errno = EINVAL; 1852 return (-1); 1853 } 1854 1855 int 1856 pmc_write(pmc_id_t pmc, pmc_value_t value) 1857 { 1858 struct pmc_op_pmcrw pmc_write_op; 1859 1860 pmc_write_op.pm_pmcid = pmc; 1861 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 1862 pmc_write_op.pm_value = value; 1863 return (PMC_CALL(PMCRW, &pmc_write_op)); 1864 } 1865 1866 int 1867 pmc_writelog(uint32_t userdata) 1868 { 1869 struct pmc_op_writelog wl; 1870 1871 wl.pm_userdata = userdata; 1872 return (PMC_CALL(WRITELOG, &wl)); 1873 } 1874