1 /*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/types.h> 31 #include <sys/module.h> 32 #include <sys/pmc.h> 33 #include <sys/syscall.h> 34 35 #include <ctype.h> 36 #include <errno.h> 37 #include <fcntl.h> 38 #include <pmc.h> 39 #include <stdio.h> 40 #include <stdlib.h> 41 #include <string.h> 42 #include <strings.h> 43 #include <unistd.h> 44 45 #include "libpmcinternal.h" 46 47 /* Function prototypes */ 48 #if defined(__i386__) 49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 50 struct pmc_op_pmcallocate *_pmc_config); 51 #endif 52 #if defined(__amd64__) || defined(__i386__) 53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 54 struct pmc_op_pmcallocate *_pmc_config); 55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 56 struct pmc_op_pmcallocate *_pmc_config); 57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 58 struct pmc_op_pmcallocate *_pmc_config); 59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 60 struct pmc_op_pmcallocate *_pmc_config); 61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 62 struct pmc_op_pmcallocate *_pmc_config); 63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65 #endif 66 #if defined(__i386__) 67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 68 struct pmc_op_pmcallocate *_pmc_config); 69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 70 struct pmc_op_pmcallocate *_pmc_config); 71 #endif 72 #if defined(__amd64__) || defined(__i386__) 73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 74 struct pmc_op_pmcallocate *_pmc_config); 75 #endif 76 #if defined(__XSCALE__) 77 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 78 struct pmc_op_pmcallocate *_pmc_config); 79 #endif 80 81 #if defined(__mips__) 82 static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84 #endif /* __mips__ */ 85 86 87 #define PMC_CALL(cmd, params) \ 88 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 89 90 /* 91 * Event aliases provide a way for the user to ask for generic events 92 * like "cache-misses", or "instructions-retired". These aliases are 93 * mapped to the appropriate canonical event descriptions using a 94 * lookup table. 95 */ 96 struct pmc_event_alias { 97 const char *pm_alias; 98 const char *pm_spec; 99 }; 100 101 static const struct pmc_event_alias *pmc_mdep_event_aliases; 102 103 /* 104 * The pmc_event_descr structure maps symbolic names known to the user 105 * to integer codes used by the PMC KLD. 106 */ 107 struct pmc_event_descr { 108 const char *pm_ev_name; 109 enum pmc_event pm_ev_code; 110 }; 111 112 /* 113 * The pmc_class_descr structure maps class name prefixes for 114 * event names to event tables and other PMC class data. 115 */ 116 struct pmc_class_descr { 117 const char *pm_evc_name; 118 size_t pm_evc_name_size; 119 enum pmc_class pm_evc_class; 120 const struct pmc_event_descr *pm_evc_event_table; 121 size_t pm_evc_event_table_size; 122 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 123 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 124 }; 125 126 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 127 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 128 129 #undef __PMC_EV 130 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 131 132 /* 133 * PMC_CLASSDEP_TABLE(NAME, CLASS) 134 * 135 * Define a table mapping event names and aliases to HWPMC event IDs. 136 */ 137 #define PMC_CLASSDEP_TABLE(N, C) \ 138 static const struct pmc_event_descr N##_event_table[] = \ 139 { \ 140 __PMC_EV_##C() \ 141 } 142 143 PMC_CLASSDEP_TABLE(iaf, IAF); 144 PMC_CLASSDEP_TABLE(k7, K7); 145 PMC_CLASSDEP_TABLE(k8, K8); 146 PMC_CLASSDEP_TABLE(p4, P4); 147 PMC_CLASSDEP_TABLE(p5, P5); 148 PMC_CLASSDEP_TABLE(p6, P6); 149 PMC_CLASSDEP_TABLE(xscale, XSCALE); 150 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 151 PMC_CLASSDEP_TABLE(ucf, UCF); 152 153 #undef __PMC_EV_ALIAS 154 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 155 156 static const struct pmc_event_descr atom_event_table[] = 157 { 158 __PMC_EV_ALIAS_ATOM() 159 }; 160 161 static const struct pmc_event_descr core_event_table[] = 162 { 163 __PMC_EV_ALIAS_CORE() 164 }; 165 166 167 static const struct pmc_event_descr core2_event_table[] = 168 { 169 __PMC_EV_ALIAS_CORE2() 170 }; 171 172 static const struct pmc_event_descr corei7_event_table[] = 173 { 174 __PMC_EV_ALIAS_COREI7() 175 }; 176 177 static const struct pmc_event_descr westmere_event_table[] = 178 { 179 __PMC_EV_ALIAS_WESTMERE() 180 }; 181 182 static const struct pmc_event_descr corei7uc_event_table[] = 183 { 184 __PMC_EV_ALIAS_COREI7UC() 185 }; 186 187 static const struct pmc_event_descr westmereuc_event_table[] = 188 { 189 __PMC_EV_ALIAS_WESTMEREUC() 190 }; 191 192 /* 193 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 194 * 195 * Map a CPU to the PMC classes it supports. 196 */ 197 #define PMC_MDEP_TABLE(N,C,...) \ 198 static const enum pmc_class N##_pmc_classes[] = { \ 199 PMC_CLASS_##C, __VA_ARGS__ \ 200 } 201 202 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC); 203 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC); 204 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC); 205 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 206 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 207 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC); 208 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC); 209 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC); 210 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC); 211 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC); 212 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_XSCALE); 213 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_MIPS24K); 214 215 static const struct pmc_event_descr tsc_event_table[] = 216 { 217 __PMC_EV_TSC() 218 }; 219 220 #undef PMC_CLASS_TABLE_DESC 221 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 222 static const struct pmc_class_descr NAME##_class_table_descr = \ 223 { \ 224 .pm_evc_name = #CLASS "-", \ 225 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 226 .pm_evc_class = PMC_CLASS_##CLASS , \ 227 .pm_evc_event_table = EVENTS##_event_table , \ 228 .pm_evc_event_table_size = \ 229 PMC_EVENT_TABLE_SIZE(EVENTS), \ 230 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 231 } 232 233 #if defined(__i386__) || defined(__amd64__) 234 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 235 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 236 PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 237 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 238 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 239 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 240 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 241 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 242 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 243 #endif 244 #if defined(__i386__) 245 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 246 #endif 247 #if defined(__i386__) || defined(__amd64__) 248 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 249 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 250 #endif 251 #if defined(__i386__) 252 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 253 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 254 #endif 255 #if defined(__i386__) || defined(__amd64__) 256 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 257 #endif 258 #if defined(__XSCALE__) 259 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 260 #endif 261 262 #if defined(__mips__) 263 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k); 264 #endif /* __mips__ */ 265 266 #undef PMC_CLASS_TABLE_DESC 267 268 static const struct pmc_class_descr **pmc_class_table; 269 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 270 271 static const enum pmc_class *pmc_mdep_class_list; 272 static size_t pmc_mdep_class_list_size; 273 274 /* 275 * Mapping tables, mapping enumeration values to human readable 276 * strings. 277 */ 278 279 static const char * pmc_capability_names[] = { 280 #undef __PMC_CAP 281 #define __PMC_CAP(N,V,D) #N , 282 __PMC_CAPS() 283 }; 284 285 static const char * pmc_class_names[] = { 286 #undef __PMC_CLASS 287 #define __PMC_CLASS(C) #C , 288 __PMC_CLASSES() 289 }; 290 291 struct pmc_cputype_map { 292 enum pmc_class pm_cputype; 293 const char *pm_name; 294 }; 295 296 static const struct pmc_cputype_map pmc_cputype_names[] = { 297 #undef __PMC_CPU 298 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 299 __PMC_CPUS() 300 }; 301 302 static const char * pmc_disposition_names[] = { 303 #undef __PMC_DISP 304 #define __PMC_DISP(D) #D , 305 __PMC_DISPOSITIONS() 306 }; 307 308 static const char * pmc_mode_names[] = { 309 #undef __PMC_MODE 310 #define __PMC_MODE(M,N) #M , 311 __PMC_MODES() 312 }; 313 314 static const char * pmc_state_names[] = { 315 #undef __PMC_STATE 316 #define __PMC_STATE(S) #S , 317 __PMC_STATES() 318 }; 319 320 static int pmc_syscall = -1; /* filled in by pmc_init() */ 321 322 static struct pmc_cpuinfo cpu_info; /* filled in by pmc_init() */ 323 324 /* Event masks for events */ 325 struct pmc_masks { 326 const char *pm_name; 327 const uint32_t pm_value; 328 }; 329 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 330 #define NULLMASK { .pm_name = NULL } 331 332 #if defined(__amd64__) || defined(__i386__) 333 static int 334 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask) 335 { 336 const struct pmc_masks *pm; 337 char *q, *r; 338 int c; 339 340 if (pmask == NULL) /* no mask keywords */ 341 return (-1); 342 q = strchr(p, '='); /* skip '=' */ 343 if (*++q == '\0') /* no more data */ 344 return (-1); 345 c = 0; /* count of mask keywords seen */ 346 while ((r = strsep(&q, "+")) != NULL) { 347 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 348 pm++) 349 ; 350 if (pm->pm_name == NULL) /* not found */ 351 return (-1); 352 *evmask |= pm->pm_value; 353 c++; 354 } 355 return (c); 356 } 357 #endif 358 359 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 360 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 361 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 362 363 #if defined(__i386__) 364 365 /* 366 * AMD K7 (Athlon) CPUs. 367 */ 368 369 static struct pmc_event_alias k7_aliases[] = { 370 EV_ALIAS("branches", "k7-retired-branches"), 371 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 372 EV_ALIAS("cycles", "tsc"), 373 EV_ALIAS("dc-misses", "k7-dc-misses"), 374 EV_ALIAS("ic-misses", "k7-ic-misses"), 375 EV_ALIAS("instructions", "k7-retired-instructions"), 376 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 377 EV_ALIAS(NULL, NULL) 378 }; 379 380 #define K7_KW_COUNT "count" 381 #define K7_KW_EDGE "edge" 382 #define K7_KW_INV "inv" 383 #define K7_KW_OS "os" 384 #define K7_KW_UNITMASK "unitmask" 385 #define K7_KW_USR "usr" 386 387 static int 388 k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 389 struct pmc_op_pmcallocate *pmc_config) 390 { 391 char *e, *p, *q; 392 int c, has_unitmask; 393 uint32_t count, unitmask; 394 395 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 396 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 397 398 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 399 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 400 pe == PMC_EV_K7_DC_WRITEBACKS) { 401 has_unitmask = 1; 402 unitmask = AMD_PMC_UNITMASK_MOESI; 403 } else 404 unitmask = has_unitmask = 0; 405 406 while ((p = strsep(&ctrspec, ",")) != NULL) { 407 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 408 q = strchr(p, '='); 409 if (*++q == '\0') /* skip '=' */ 410 return (-1); 411 412 count = strtol(q, &e, 0); 413 if (e == q || *e != '\0') 414 return (-1); 415 416 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 417 pmc_config->pm_md.pm_amd.pm_amd_config |= 418 AMD_PMC_TO_COUNTER(count); 419 420 } else if (KWMATCH(p, K7_KW_EDGE)) { 421 pmc_config->pm_caps |= PMC_CAP_EDGE; 422 } else if (KWMATCH(p, K7_KW_INV)) { 423 pmc_config->pm_caps |= PMC_CAP_INVERT; 424 } else if (KWMATCH(p, K7_KW_OS)) { 425 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 426 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 427 if (has_unitmask == 0) 428 return (-1); 429 unitmask = 0; 430 q = strchr(p, '='); 431 if (*++q == '\0') /* skip '=' */ 432 return (-1); 433 434 while ((c = tolower(*q++)) != 0) 435 if (c == 'm') 436 unitmask |= AMD_PMC_UNITMASK_M; 437 else if (c == 'o') 438 unitmask |= AMD_PMC_UNITMASK_O; 439 else if (c == 'e') 440 unitmask |= AMD_PMC_UNITMASK_E; 441 else if (c == 's') 442 unitmask |= AMD_PMC_UNITMASK_S; 443 else if (c == 'i') 444 unitmask |= AMD_PMC_UNITMASK_I; 445 else if (c == '+') 446 continue; 447 else 448 return (-1); 449 450 if (unitmask == 0) 451 return (-1); 452 453 } else if (KWMATCH(p, K7_KW_USR)) { 454 pmc_config->pm_caps |= PMC_CAP_USER; 455 } else 456 return (-1); 457 } 458 459 if (has_unitmask) { 460 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 461 pmc_config->pm_md.pm_amd.pm_amd_config |= 462 AMD_PMC_TO_UNITMASK(unitmask); 463 } 464 465 return (0); 466 467 } 468 469 #endif 470 471 #if defined(__amd64__) || defined(__i386__) 472 473 /* 474 * Intel Core (Family 6, Model E) PMCs. 475 */ 476 477 static struct pmc_event_alias core_aliases[] = { 478 EV_ALIAS("branches", "iap-br-instr-ret"), 479 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 480 EV_ALIAS("cycles", "tsc-tsc"), 481 EV_ALIAS("ic-misses", "iap-icache-misses"), 482 EV_ALIAS("instructions", "iap-instr-ret"), 483 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 484 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 485 EV_ALIAS(NULL, NULL) 486 }; 487 488 /* 489 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 490 * and Atom (Family 6, model 1CH) PMCs. 491 * 492 * We map aliases to events on the fixed-function counters if these 493 * are present. Note that not all CPUs in this family contain fixed-function 494 * counters. 495 */ 496 497 static struct pmc_event_alias core2_aliases[] = { 498 EV_ALIAS("branches", "iap-br-inst-retired.any"), 499 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 500 EV_ALIAS("cycles", "tsc-tsc"), 501 EV_ALIAS("ic-misses", "iap-l1i-misses"), 502 EV_ALIAS("instructions", "iaf-instr-retired.any"), 503 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 504 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 505 EV_ALIAS(NULL, NULL) 506 }; 507 508 static struct pmc_event_alias core2_aliases_without_iaf[] = { 509 EV_ALIAS("branches", "iap-br-inst-retired.any"), 510 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 511 EV_ALIAS("cycles", "tsc-tsc"), 512 EV_ALIAS("ic-misses", "iap-l1i-misses"), 513 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 514 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 515 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 516 EV_ALIAS(NULL, NULL) 517 }; 518 519 #define atom_aliases core2_aliases 520 #define atom_aliases_without_iaf core2_aliases_without_iaf 521 #define corei7_aliases core2_aliases 522 #define corei7_aliases_without_iaf core2_aliases_without_iaf 523 #define westmere_aliases core2_aliases 524 #define westmere_aliases_without_iaf core2_aliases_without_iaf 525 526 #define IAF_KW_OS "os" 527 #define IAF_KW_USR "usr" 528 #define IAF_KW_ANYTHREAD "anythread" 529 530 /* 531 * Parse an event specifier for Intel fixed function counters. 532 */ 533 static int 534 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 535 struct pmc_op_pmcallocate *pmc_config) 536 { 537 char *p; 538 539 (void) pe; 540 541 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 542 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 543 544 while ((p = strsep(&ctrspec, ",")) != NULL) { 545 if (KWMATCH(p, IAF_KW_OS)) 546 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 547 else if (KWMATCH(p, IAF_KW_USR)) 548 pmc_config->pm_caps |= PMC_CAP_USER; 549 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 550 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 551 else 552 return (-1); 553 } 554 555 return (0); 556 } 557 558 /* 559 * Core/Core2 support. 560 */ 561 562 #define IAP_KW_AGENT "agent" 563 #define IAP_KW_ANYTHREAD "anythread" 564 #define IAP_KW_CACHESTATE "cachestate" 565 #define IAP_KW_CMASK "cmask" 566 #define IAP_KW_CORE "core" 567 #define IAP_KW_EDGE "edge" 568 #define IAP_KW_INV "inv" 569 #define IAP_KW_OS "os" 570 #define IAP_KW_PREFETCH "prefetch" 571 #define IAP_KW_SNOOPRESPONSE "snoopresponse" 572 #define IAP_KW_SNOOPTYPE "snooptype" 573 #define IAP_KW_TRANSITION "trans" 574 #define IAP_KW_USR "usr" 575 #define IAP_KW_RSP "rsp" 576 577 static struct pmc_masks iap_core_mask[] = { 578 PMCMASK(all, (0x3 << 14)), 579 PMCMASK(this, (0x1 << 14)), 580 NULLMASK 581 }; 582 583 static struct pmc_masks iap_agent_mask[] = { 584 PMCMASK(this, 0), 585 PMCMASK(any, (0x1 << 13)), 586 NULLMASK 587 }; 588 589 static struct pmc_masks iap_prefetch_mask[] = { 590 PMCMASK(both, (0x3 << 12)), 591 PMCMASK(only, (0x1 << 12)), 592 PMCMASK(exclude, 0), 593 NULLMASK 594 }; 595 596 static struct pmc_masks iap_cachestate_mask[] = { 597 PMCMASK(i, (1 << 8)), 598 PMCMASK(s, (1 << 9)), 599 PMCMASK(e, (1 << 10)), 600 PMCMASK(m, (1 << 11)), 601 NULLMASK 602 }; 603 604 static struct pmc_masks iap_snoopresponse_mask[] = { 605 PMCMASK(clean, (1 << 8)), 606 PMCMASK(hit, (1 << 9)), 607 PMCMASK(hitm, (1 << 11)), 608 NULLMASK 609 }; 610 611 static struct pmc_masks iap_snooptype_mask[] = { 612 PMCMASK(cmp2s, (1 << 8)), 613 PMCMASK(cmp2i, (1 << 9)), 614 NULLMASK 615 }; 616 617 static struct pmc_masks iap_transition_mask[] = { 618 PMCMASK(any, 0x00), 619 PMCMASK(frequency, 0x10), 620 NULLMASK 621 }; 622 623 static struct pmc_masks iap_rsp_mask[] = { 624 PMCMASK(DMND_DATA_RD, (1 << 0)), 625 PMCMASK(DMND_RFO, (1 << 1)), 626 PMCMASK(DMND_IFETCH, (1 << 2)), 627 PMCMASK(WB, (1 << 3)), 628 PMCMASK(PF_DATA_RD, (1 << 4)), 629 PMCMASK(PF_RFO, (1 << 5)), 630 PMCMASK(PF_IFETCH, (1 << 6)), 631 PMCMASK(OTHER, (1 << 7)), 632 PMCMASK(UNCORE_HIT, (1 << 8)), 633 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 634 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 635 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 636 PMCMASK(REMOTE_DRAM, (1 << 13)), 637 PMCMASK(LOCAL_DRAM, (1 << 14)), 638 PMCMASK(NON_DRAM, (1 << 15)), 639 NULLMASK 640 }; 641 642 static int 643 iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 644 struct pmc_op_pmcallocate *pmc_config) 645 { 646 char *e, *p, *q; 647 uint32_t cachestate, evmask, rsp; 648 int count, n; 649 650 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 651 PMC_CAP_QUALIFIER); 652 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 653 654 cachestate = evmask = rsp = 0; 655 656 /* Parse additional modifiers if present */ 657 while ((p = strsep(&ctrspec, ",")) != NULL) { 658 659 n = 0; 660 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 661 q = strchr(p, '='); 662 if (*++q == '\0') /* skip '=' */ 663 return (-1); 664 count = strtol(q, &e, 0); 665 if (e == q || *e != '\0') 666 return (-1); 667 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 668 pmc_config->pm_md.pm_iap.pm_iap_config |= 669 IAP_CMASK(count); 670 } else if (KWMATCH(p, IAP_KW_EDGE)) { 671 pmc_config->pm_caps |= PMC_CAP_EDGE; 672 } else if (KWMATCH(p, IAP_KW_INV)) { 673 pmc_config->pm_caps |= PMC_CAP_INVERT; 674 } else if (KWMATCH(p, IAP_KW_OS)) { 675 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 676 } else if (KWMATCH(p, IAP_KW_USR)) { 677 pmc_config->pm_caps |= PMC_CAP_USER; 678 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 679 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 680 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 681 n = pmc_parse_mask(iap_core_mask, p, &evmask); 682 if (n != 1) 683 return (-1); 684 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 685 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 686 if (n != 1) 687 return (-1); 688 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 689 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 690 if (n != 1) 691 return (-1); 692 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 693 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 694 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 695 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 696 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 697 if (n != 1) 698 return (-1); 699 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 700 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 701 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 702 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 703 n = pmc_parse_mask(iap_snoopresponse_mask, p, 704 &evmask); 705 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 706 n = pmc_parse_mask(iap_snooptype_mask, p, 707 &evmask); 708 } else 709 return (-1); 710 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 711 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { 712 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 713 n = pmc_parse_mask(iap_rsp_mask, p, &rsp); 714 } else 715 return (-1); 716 } else 717 return (-1); 718 719 if (n < 0) /* Parsing failed. */ 720 return (-1); 721 } 722 723 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 724 725 /* 726 * If the event requires a 'cachestate' qualifier but was not 727 * specified by the user, use a sensible default. 728 */ 729 switch (pe) { 730 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 731 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 732 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 733 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 734 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 735 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 736 case PMC_EV_IAP_EVENT_32H: /* Core */ 737 case PMC_EV_IAP_EVENT_40H: /* Core */ 738 case PMC_EV_IAP_EVENT_41H: /* Core */ 739 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 740 if (cachestate == 0) 741 cachestate = (0xF << 8); 742 break; 743 case PMC_EV_IAP_EVENT_77H: /* Atom */ 744 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 745 * Atom processor 746 */ 747 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 748 cachestate = (0xF << 8); 749 break; 750 default: 751 break; 752 } 753 754 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 755 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 756 757 return (0); 758 } 759 760 /* 761 * Intel Uncore. 762 */ 763 764 static int 765 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 766 struct pmc_op_pmcallocate *pmc_config) 767 { 768 (void) pe; 769 (void) ctrspec; 770 771 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 772 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 773 774 return (0); 775 } 776 777 #define UCP_KW_CMASK "cmask" 778 #define UCP_KW_EDGE "edge" 779 #define UCP_KW_INV "inv" 780 781 static int 782 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 783 struct pmc_op_pmcallocate *pmc_config) 784 { 785 char *e, *p, *q; 786 int count, n; 787 788 (void) pe; 789 790 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 791 PMC_CAP_QUALIFIER); 792 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 793 794 /* Parse additional modifiers if present */ 795 while ((p = strsep(&ctrspec, ",")) != NULL) { 796 797 n = 0; 798 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 799 q = strchr(p, '='); 800 if (*++q == '\0') /* skip '=' */ 801 return (-1); 802 count = strtol(q, &e, 0); 803 if (e == q || *e != '\0') 804 return (-1); 805 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 806 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 807 UCP_CMASK(count); 808 } else if (KWMATCH(p, UCP_KW_EDGE)) { 809 pmc_config->pm_caps |= PMC_CAP_EDGE; 810 } else if (KWMATCH(p, UCP_KW_INV)) { 811 pmc_config->pm_caps |= PMC_CAP_INVERT; 812 } else 813 return (-1); 814 815 if (n < 0) /* Parsing failed. */ 816 return (-1); 817 } 818 819 return (0); 820 } 821 822 /* 823 * AMD K8 PMCs. 824 * 825 * These are very similar to AMD K7 PMCs, but support more kinds of 826 * events. 827 */ 828 829 static struct pmc_event_alias k8_aliases[] = { 830 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 831 EV_ALIAS("branch-mispredicts", 832 "k8-fr-retired-taken-branches-mispredicted"), 833 EV_ALIAS("cycles", "tsc"), 834 EV_ALIAS("dc-misses", "k8-dc-miss"), 835 EV_ALIAS("ic-misses", "k8-ic-miss"), 836 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 837 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 838 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 839 EV_ALIAS(NULL, NULL) 840 }; 841 842 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 843 844 /* 845 * Parsing tables 846 */ 847 848 /* fp dispatched fpu ops */ 849 static const struct pmc_masks k8_mask_fdfo[] = { 850 __K8MASK(add-pipe-excluding-junk-ops, 0), 851 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 852 __K8MASK(store-pipe-excluding-junk-ops, 2), 853 __K8MASK(add-pipe-junk-ops, 3), 854 __K8MASK(multiply-pipe-junk-ops, 4), 855 __K8MASK(store-pipe-junk-ops, 5), 856 NULLMASK 857 }; 858 859 /* ls segment register loads */ 860 static const struct pmc_masks k8_mask_lsrl[] = { 861 __K8MASK(es, 0), 862 __K8MASK(cs, 1), 863 __K8MASK(ss, 2), 864 __K8MASK(ds, 3), 865 __K8MASK(fs, 4), 866 __K8MASK(gs, 5), 867 __K8MASK(hs, 6), 868 NULLMASK 869 }; 870 871 /* ls locked operation */ 872 static const struct pmc_masks k8_mask_llo[] = { 873 __K8MASK(locked-instructions, 0), 874 __K8MASK(cycles-in-request, 1), 875 __K8MASK(cycles-to-complete, 2), 876 NULLMASK 877 }; 878 879 /* dc refill from {l2,system} and dc copyback */ 880 static const struct pmc_masks k8_mask_dc[] = { 881 __K8MASK(invalid, 0), 882 __K8MASK(shared, 1), 883 __K8MASK(exclusive, 2), 884 __K8MASK(owner, 3), 885 __K8MASK(modified, 4), 886 NULLMASK 887 }; 888 889 /* dc one bit ecc error */ 890 static const struct pmc_masks k8_mask_dobee[] = { 891 __K8MASK(scrubber, 0), 892 __K8MASK(piggyback, 1), 893 NULLMASK 894 }; 895 896 /* dc dispatched prefetch instructions */ 897 static const struct pmc_masks k8_mask_ddpi[] = { 898 __K8MASK(load, 0), 899 __K8MASK(store, 1), 900 __K8MASK(nta, 2), 901 NULLMASK 902 }; 903 904 /* dc dcache accesses by locks */ 905 static const struct pmc_masks k8_mask_dabl[] = { 906 __K8MASK(accesses, 0), 907 __K8MASK(misses, 1), 908 NULLMASK 909 }; 910 911 /* bu internal l2 request */ 912 static const struct pmc_masks k8_mask_bilr[] = { 913 __K8MASK(ic-fill, 0), 914 __K8MASK(dc-fill, 1), 915 __K8MASK(tlb-reload, 2), 916 __K8MASK(tag-snoop, 3), 917 __K8MASK(cancelled, 4), 918 NULLMASK 919 }; 920 921 /* bu fill request l2 miss */ 922 static const struct pmc_masks k8_mask_bfrlm[] = { 923 __K8MASK(ic-fill, 0), 924 __K8MASK(dc-fill, 1), 925 __K8MASK(tlb-reload, 2), 926 NULLMASK 927 }; 928 929 /* bu fill into l2 */ 930 static const struct pmc_masks k8_mask_bfil[] = { 931 __K8MASK(dirty-l2-victim, 0), 932 __K8MASK(victim-from-l2, 1), 933 NULLMASK 934 }; 935 936 /* fr retired fpu instructions */ 937 static const struct pmc_masks k8_mask_frfi[] = { 938 __K8MASK(x87, 0), 939 __K8MASK(mmx-3dnow, 1), 940 __K8MASK(packed-sse-sse2, 2), 941 __K8MASK(scalar-sse-sse2, 3), 942 NULLMASK 943 }; 944 945 /* fr retired fastpath double op instructions */ 946 static const struct pmc_masks k8_mask_frfdoi[] = { 947 __K8MASK(low-op-pos-0, 0), 948 __K8MASK(low-op-pos-1, 1), 949 __K8MASK(low-op-pos-2, 2), 950 NULLMASK 951 }; 952 953 /* fr fpu exceptions */ 954 static const struct pmc_masks k8_mask_ffe[] = { 955 __K8MASK(x87-reclass-microfaults, 0), 956 __K8MASK(sse-retype-microfaults, 1), 957 __K8MASK(sse-reclass-microfaults, 2), 958 __K8MASK(sse-and-x87-microtraps, 3), 959 NULLMASK 960 }; 961 962 /* nb memory controller page access event */ 963 static const struct pmc_masks k8_mask_nmcpae[] = { 964 __K8MASK(page-hit, 0), 965 __K8MASK(page-miss, 1), 966 __K8MASK(page-conflict, 2), 967 NULLMASK 968 }; 969 970 /* nb memory controller turnaround */ 971 static const struct pmc_masks k8_mask_nmct[] = { 972 __K8MASK(dimm-turnaround, 0), 973 __K8MASK(read-to-write-turnaround, 1), 974 __K8MASK(write-to-read-turnaround, 2), 975 NULLMASK 976 }; 977 978 /* nb memory controller bypass saturation */ 979 static const struct pmc_masks k8_mask_nmcbs[] = { 980 __K8MASK(memory-controller-hi-pri-bypass, 0), 981 __K8MASK(memory-controller-lo-pri-bypass, 1), 982 __K8MASK(dram-controller-interface-bypass, 2), 983 __K8MASK(dram-controller-queue-bypass, 3), 984 NULLMASK 985 }; 986 987 /* nb sized commands */ 988 static const struct pmc_masks k8_mask_nsc[] = { 989 __K8MASK(nonpostwrszbyte, 0), 990 __K8MASK(nonpostwrszdword, 1), 991 __K8MASK(postwrszbyte, 2), 992 __K8MASK(postwrszdword, 3), 993 __K8MASK(rdszbyte, 4), 994 __K8MASK(rdszdword, 5), 995 __K8MASK(rdmodwr, 6), 996 NULLMASK 997 }; 998 999 /* nb probe result */ 1000 static const struct pmc_masks k8_mask_npr[] = { 1001 __K8MASK(probe-miss, 0), 1002 __K8MASK(probe-hit, 1), 1003 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1004 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1005 NULLMASK 1006 }; 1007 1008 /* nb hypertransport bus bandwidth */ 1009 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1010 __K8MASK(command, 0), 1011 __K8MASK(data, 1), 1012 __K8MASK(buffer-release, 2), 1013 __K8MASK(nop, 3), 1014 NULLMASK 1015 }; 1016 1017 #undef __K8MASK 1018 1019 #define K8_KW_COUNT "count" 1020 #define K8_KW_EDGE "edge" 1021 #define K8_KW_INV "inv" 1022 #define K8_KW_MASK "mask" 1023 #define K8_KW_OS "os" 1024 #define K8_KW_USR "usr" 1025 1026 static int 1027 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1028 struct pmc_op_pmcallocate *pmc_config) 1029 { 1030 char *e, *p, *q; 1031 int n; 1032 uint32_t count, evmask; 1033 const struct pmc_masks *pm, *pmask; 1034 1035 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1036 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1037 1038 pmask = NULL; 1039 evmask = 0; 1040 1041 #define __K8SETMASK(M) pmask = k8_mask_##M 1042 1043 /* setup parsing tables */ 1044 switch (pe) { 1045 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1046 __K8SETMASK(fdfo); 1047 break; 1048 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1049 __K8SETMASK(lsrl); 1050 break; 1051 case PMC_EV_K8_LS_LOCKED_OPERATION: 1052 __K8SETMASK(llo); 1053 break; 1054 case PMC_EV_K8_DC_REFILL_FROM_L2: 1055 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1056 case PMC_EV_K8_DC_COPYBACK: 1057 __K8SETMASK(dc); 1058 break; 1059 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1060 __K8SETMASK(dobee); 1061 break; 1062 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1063 __K8SETMASK(ddpi); 1064 break; 1065 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1066 __K8SETMASK(dabl); 1067 break; 1068 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1069 __K8SETMASK(bilr); 1070 break; 1071 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1072 __K8SETMASK(bfrlm); 1073 break; 1074 case PMC_EV_K8_BU_FILL_INTO_L2: 1075 __K8SETMASK(bfil); 1076 break; 1077 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1078 __K8SETMASK(frfi); 1079 break; 1080 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1081 __K8SETMASK(frfdoi); 1082 break; 1083 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1084 __K8SETMASK(ffe); 1085 break; 1086 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1087 __K8SETMASK(nmcpae); 1088 break; 1089 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1090 __K8SETMASK(nmct); 1091 break; 1092 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1093 __K8SETMASK(nmcbs); 1094 break; 1095 case PMC_EV_K8_NB_SIZED_COMMANDS: 1096 __K8SETMASK(nsc); 1097 break; 1098 case PMC_EV_K8_NB_PROBE_RESULT: 1099 __K8SETMASK(npr); 1100 break; 1101 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1102 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1103 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1104 __K8SETMASK(nhbb); 1105 break; 1106 1107 default: 1108 break; /* no options defined */ 1109 } 1110 1111 while ((p = strsep(&ctrspec, ",")) != NULL) { 1112 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1113 q = strchr(p, '='); 1114 if (*++q == '\0') /* skip '=' */ 1115 return (-1); 1116 1117 count = strtol(q, &e, 0); 1118 if (e == q || *e != '\0') 1119 return (-1); 1120 1121 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1122 pmc_config->pm_md.pm_amd.pm_amd_config |= 1123 AMD_PMC_TO_COUNTER(count); 1124 1125 } else if (KWMATCH(p, K8_KW_EDGE)) { 1126 pmc_config->pm_caps |= PMC_CAP_EDGE; 1127 } else if (KWMATCH(p, K8_KW_INV)) { 1128 pmc_config->pm_caps |= PMC_CAP_INVERT; 1129 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1130 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1131 return (-1); 1132 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1133 } else if (KWMATCH(p, K8_KW_OS)) { 1134 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1135 } else if (KWMATCH(p, K8_KW_USR)) { 1136 pmc_config->pm_caps |= PMC_CAP_USER; 1137 } else 1138 return (-1); 1139 } 1140 1141 /* other post processing */ 1142 switch (pe) { 1143 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1144 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1145 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1146 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1147 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1148 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1149 /* XXX only available in rev B and later */ 1150 break; 1151 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1152 /* XXX only available in rev C and later */ 1153 break; 1154 case PMC_EV_K8_LS_LOCKED_OPERATION: 1155 /* XXX CPU Rev A,B evmask is to be zero */ 1156 if (evmask & (evmask - 1)) /* > 1 bit set */ 1157 return (-1); 1158 if (evmask == 0) { 1159 evmask = 0x01; /* Rev C and later: #instrs */ 1160 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1161 } 1162 break; 1163 default: 1164 if (evmask == 0 && pmask != NULL) { 1165 for (pm = pmask; pm->pm_name; pm++) 1166 evmask |= pm->pm_value; 1167 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1168 } 1169 } 1170 1171 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1172 pmc_config->pm_md.pm_amd.pm_amd_config = 1173 AMD_PMC_TO_UNITMASK(evmask); 1174 1175 return (0); 1176 } 1177 1178 #endif 1179 1180 #if defined(__amd64__) || defined(__i386__) 1181 1182 /* 1183 * Intel P4 PMCs 1184 */ 1185 1186 static struct pmc_event_alias p4_aliases[] = { 1187 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1188 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1189 EV_ALIAS("cycles", "tsc"), 1190 EV_ALIAS("instructions", 1191 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1192 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1193 EV_ALIAS(NULL, NULL) 1194 }; 1195 1196 #define P4_KW_ACTIVE "active" 1197 #define P4_KW_ACTIVE_ANY "any" 1198 #define P4_KW_ACTIVE_BOTH "both" 1199 #define P4_KW_ACTIVE_NONE "none" 1200 #define P4_KW_ACTIVE_SINGLE "single" 1201 #define P4_KW_BUSREQTYPE "busreqtype" 1202 #define P4_KW_CASCADE "cascade" 1203 #define P4_KW_EDGE "edge" 1204 #define P4_KW_INV "complement" 1205 #define P4_KW_OS "os" 1206 #define P4_KW_MASK "mask" 1207 #define P4_KW_PRECISE "precise" 1208 #define P4_KW_TAG "tag" 1209 #define P4_KW_THRESHOLD "threshold" 1210 #define P4_KW_USR "usr" 1211 1212 #define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1213 1214 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1215 __P4MASK(dd, 0), 1216 __P4MASK(db, 1), 1217 __P4MASK(di, 2), 1218 __P4MASK(bd, 3), 1219 __P4MASK(bb, 4), 1220 __P4MASK(bi, 5), 1221 __P4MASK(id, 6), 1222 __P4MASK(ib, 7), 1223 NULLMASK 1224 }; 1225 1226 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1227 __P4MASK(tcmiss, 0), 1228 NULLMASK, 1229 }; 1230 1231 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1232 __P4MASK(hit, 0), 1233 __P4MASK(miss, 1), 1234 __P4MASK(hit-uc, 2), 1235 NULLMASK 1236 }; 1237 1238 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1239 __P4MASK(st-rb-full, 2), 1240 __P4MASK(64k-conf, 3), 1241 NULLMASK 1242 }; 1243 1244 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1245 __P4MASK(lsc, 0), 1246 __P4MASK(ssc, 1), 1247 NULLMASK 1248 }; 1249 1250 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1251 __P4MASK(split-ld, 1), 1252 NULLMASK 1253 }; 1254 1255 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1256 __P4MASK(split-st, 1), 1257 NULLMASK 1258 }; 1259 1260 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1261 __P4MASK(no-sta, 1), 1262 __P4MASK(no-std, 3), 1263 __P4MASK(partial-data, 4), 1264 __P4MASK(unalgn-addr, 5), 1265 NULLMASK 1266 }; 1267 1268 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1269 __P4MASK(dtmiss, 0), 1270 __P4MASK(itmiss, 1), 1271 NULLMASK 1272 }; 1273 1274 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1275 __P4MASK(rd-2ndl-hits, 0), 1276 __P4MASK(rd-2ndl-hite, 1), 1277 __P4MASK(rd-2ndl-hitm, 2), 1278 __P4MASK(rd-3rdl-hits, 3), 1279 __P4MASK(rd-3rdl-hite, 4), 1280 __P4MASK(rd-3rdl-hitm, 5), 1281 __P4MASK(rd-2ndl-miss, 8), 1282 __P4MASK(rd-3rdl-miss, 9), 1283 __P4MASK(wr-2ndl-miss, 10), 1284 NULLMASK 1285 }; 1286 1287 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1288 __P4MASK(all-read, 5), 1289 __P4MASK(all-write, 6), 1290 __P4MASK(mem-uc, 7), 1291 __P4MASK(mem-wc, 8), 1292 __P4MASK(mem-wt, 9), 1293 __P4MASK(mem-wp, 10), 1294 __P4MASK(mem-wb, 11), 1295 __P4MASK(own, 13), 1296 __P4MASK(other, 14), 1297 __P4MASK(prefetch, 15), 1298 NULLMASK 1299 }; 1300 1301 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1302 __P4MASK(all-read, 5), 1303 __P4MASK(all-write, 6), 1304 __P4MASK(mem-uc, 7), 1305 __P4MASK(mem-wc, 8), 1306 __P4MASK(mem-wt, 9), 1307 __P4MASK(mem-wp, 10), 1308 __P4MASK(mem-wb, 11), 1309 __P4MASK(own, 13), 1310 __P4MASK(other, 14), 1311 __P4MASK(prefetch, 15), 1312 NULLMASK 1313 }; 1314 1315 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1316 __P4MASK(drdy-drv, 0), 1317 __P4MASK(drdy-own, 1), 1318 __P4MASK(drdy-other, 2), 1319 __P4MASK(dbsy-drv, 3), 1320 __P4MASK(dbsy-own, 4), 1321 __P4MASK(dbsy-other, 5), 1322 NULLMASK 1323 }; 1324 1325 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1326 __P4MASK(req-type0, 0), 1327 __P4MASK(req-type1, 1), 1328 __P4MASK(req-len0, 2), 1329 __P4MASK(req-len1, 3), 1330 __P4MASK(req-io-type, 5), 1331 __P4MASK(req-lock-type, 6), 1332 __P4MASK(req-cache-type, 7), 1333 __P4MASK(req-split-type, 8), 1334 __P4MASK(req-dem-type, 9), 1335 __P4MASK(req-ord-type, 10), 1336 __P4MASK(mem-type0, 11), 1337 __P4MASK(mem-type1, 12), 1338 __P4MASK(mem-type2, 13), 1339 NULLMASK 1340 }; 1341 1342 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1343 __P4MASK(all, 15), 1344 NULLMASK 1345 }; 1346 1347 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1348 __P4MASK(all, 15), 1349 NULLMASK 1350 }; 1351 1352 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1353 __P4MASK(all, 15), 1354 NULLMASK 1355 }; 1356 1357 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1358 __P4MASK(all, 15), 1359 NULLMASK 1360 }; 1361 1362 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1363 __P4MASK(all, 15), 1364 NULLMASK 1365 }; 1366 1367 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1368 __P4MASK(all, 15), 1369 NULLMASK 1370 }; 1371 1372 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1373 __P4MASK(all, 15), 1374 NULLMASK 1375 }; 1376 1377 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1378 __P4MASK(all, 15), 1379 NULLMASK 1380 }; 1381 1382 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1383 __P4MASK(allp0, 3), 1384 __P4MASK(allp2, 4), 1385 NULLMASK 1386 }; 1387 1388 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1389 __P4MASK(running, 0), 1390 NULLMASK 1391 }; 1392 1393 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1394 __P4MASK(cisc, 0), 1395 NULLMASK 1396 }; 1397 1398 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1399 __P4MASK(from-tc-build, 0), 1400 __P4MASK(from-tc-deliver, 1), 1401 __P4MASK(from-rom, 2), 1402 NULLMASK 1403 }; 1404 1405 static const struct pmc_masks p4_mask_rmbt[] = { 1406 /* retired mispred branch type */ 1407 __P4MASK(conditional, 1), 1408 __P4MASK(call, 2), 1409 __P4MASK(return, 3), 1410 __P4MASK(indirect, 4), 1411 NULLMASK 1412 }; 1413 1414 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1415 __P4MASK(conditional, 1), 1416 __P4MASK(call, 2), 1417 __P4MASK(retired, 3), 1418 __P4MASK(indirect, 4), 1419 NULLMASK 1420 }; 1421 1422 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1423 __P4MASK(sbfull, 5), 1424 NULLMASK 1425 }; 1426 1427 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1428 __P4MASK(wcb-evicts, 0), 1429 __P4MASK(wcb-full-evict, 1), 1430 NULLMASK 1431 }; 1432 1433 static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1434 __P4MASK(nbogus, 0), 1435 __P4MASK(bogus, 1), 1436 NULLMASK 1437 }; 1438 1439 static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1440 __P4MASK(nbogus0, 0), 1441 __P4MASK(nbogus1, 1), 1442 __P4MASK(nbogus2, 2), 1443 __P4MASK(nbogus3, 3), 1444 __P4MASK(bogus0, 4), 1445 __P4MASK(bogus1, 5), 1446 __P4MASK(bogus2, 6), 1447 __P4MASK(bogus3, 7), 1448 NULLMASK 1449 }; 1450 1451 static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1452 __P4MASK(nbogus, 0), 1453 __P4MASK(bogus, 1), 1454 NULLMASK 1455 }; 1456 1457 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1458 __P4MASK(nbogusntag, 0), 1459 __P4MASK(nbogustag, 1), 1460 __P4MASK(bogusntag, 2), 1461 __P4MASK(bogustag, 3), 1462 NULLMASK 1463 }; 1464 1465 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1466 __P4MASK(nbogus, 0), 1467 __P4MASK(bogus, 1), 1468 NULLMASK 1469 }; 1470 1471 static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1472 __P4MASK(tagloads, 1), 1473 __P4MASK(tagstores, 2), 1474 NULLMASK 1475 }; 1476 1477 static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1478 __P4MASK(mmnp, 0), 1479 __P4MASK(mmnm, 1), 1480 __P4MASK(mmtp, 2), 1481 __P4MASK(mmtm, 3), 1482 NULLMASK 1483 }; 1484 1485 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1486 __P4MASK(nbogus, 0), 1487 NULLMASK 1488 }; 1489 1490 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1491 __P4MASK(fpsu, 0), 1492 __P4MASK(fpso, 1), 1493 __P4MASK(poao, 2), 1494 __P4MASK(poau, 3), 1495 __P4MASK(prea, 4), 1496 NULLMASK 1497 }; 1498 1499 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1500 __P4MASK(clear, 0), 1501 __P4MASK(moclear, 2), 1502 __P4MASK(smclear, 3), 1503 NULLMASK 1504 }; 1505 1506 /* P4 event parser */ 1507 static int 1508 p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1509 struct pmc_op_pmcallocate *pmc_config) 1510 { 1511 1512 char *e, *p, *q; 1513 int count, has_tag, has_busreqtype, n; 1514 uint32_t evmask, cccractivemask; 1515 const struct pmc_masks *pm, *pmask; 1516 1517 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1518 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1519 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1520 1521 pmask = NULL; 1522 evmask = 0; 1523 cccractivemask = 0x3; 1524 has_tag = has_busreqtype = 0; 1525 1526 #define __P4SETMASK(M) do { \ 1527 pmask = p4_mask_##M; \ 1528 } while (0) 1529 1530 switch (pe) { 1531 case PMC_EV_P4_TC_DELIVER_MODE: 1532 __P4SETMASK(tcdm); 1533 break; 1534 case PMC_EV_P4_BPU_FETCH_REQUEST: 1535 __P4SETMASK(bfr); 1536 break; 1537 case PMC_EV_P4_ITLB_REFERENCE: 1538 __P4SETMASK(ir); 1539 break; 1540 case PMC_EV_P4_MEMORY_CANCEL: 1541 __P4SETMASK(memcan); 1542 break; 1543 case PMC_EV_P4_MEMORY_COMPLETE: 1544 __P4SETMASK(memcomp); 1545 break; 1546 case PMC_EV_P4_LOAD_PORT_REPLAY: 1547 __P4SETMASK(lpr); 1548 break; 1549 case PMC_EV_P4_STORE_PORT_REPLAY: 1550 __P4SETMASK(spr); 1551 break; 1552 case PMC_EV_P4_MOB_LOAD_REPLAY: 1553 __P4SETMASK(mlr); 1554 break; 1555 case PMC_EV_P4_PAGE_WALK_TYPE: 1556 __P4SETMASK(pwt); 1557 break; 1558 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1559 __P4SETMASK(bcr); 1560 break; 1561 case PMC_EV_P4_IOQ_ALLOCATION: 1562 __P4SETMASK(ia); 1563 has_busreqtype = 1; 1564 break; 1565 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1566 __P4SETMASK(iae); 1567 has_busreqtype = 1; 1568 break; 1569 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1570 __P4SETMASK(fda); 1571 break; 1572 case PMC_EV_P4_BSQ_ALLOCATION: 1573 __P4SETMASK(ba); 1574 break; 1575 case PMC_EV_P4_SSE_INPUT_ASSIST: 1576 __P4SETMASK(sia); 1577 break; 1578 case PMC_EV_P4_PACKED_SP_UOP: 1579 __P4SETMASK(psu); 1580 break; 1581 case PMC_EV_P4_PACKED_DP_UOP: 1582 __P4SETMASK(pdu); 1583 break; 1584 case PMC_EV_P4_SCALAR_SP_UOP: 1585 __P4SETMASK(ssu); 1586 break; 1587 case PMC_EV_P4_SCALAR_DP_UOP: 1588 __P4SETMASK(sdu); 1589 break; 1590 case PMC_EV_P4_64BIT_MMX_UOP: 1591 __P4SETMASK(64bmu); 1592 break; 1593 case PMC_EV_P4_128BIT_MMX_UOP: 1594 __P4SETMASK(128bmu); 1595 break; 1596 case PMC_EV_P4_X87_FP_UOP: 1597 __P4SETMASK(xfu); 1598 break; 1599 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1600 __P4SETMASK(xsmu); 1601 break; 1602 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1603 __P4SETMASK(gpe); 1604 break; 1605 case PMC_EV_P4_TC_MS_XFER: 1606 __P4SETMASK(tmx); 1607 break; 1608 case PMC_EV_P4_UOP_QUEUE_WRITES: 1609 __P4SETMASK(uqw); 1610 break; 1611 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1612 __P4SETMASK(rmbt); 1613 break; 1614 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1615 __P4SETMASK(rbt); 1616 break; 1617 case PMC_EV_P4_RESOURCE_STALL: 1618 __P4SETMASK(rs); 1619 break; 1620 case PMC_EV_P4_WC_BUFFER: 1621 __P4SETMASK(wb); 1622 break; 1623 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1624 case PMC_EV_P4_B2B_CYCLES: 1625 case PMC_EV_P4_BNR: 1626 case PMC_EV_P4_SNOOP: 1627 case PMC_EV_P4_RESPONSE: 1628 break; 1629 case PMC_EV_P4_FRONT_END_EVENT: 1630 __P4SETMASK(fee); 1631 break; 1632 case PMC_EV_P4_EXECUTION_EVENT: 1633 __P4SETMASK(ee); 1634 break; 1635 case PMC_EV_P4_REPLAY_EVENT: 1636 __P4SETMASK(re); 1637 break; 1638 case PMC_EV_P4_INSTR_RETIRED: 1639 __P4SETMASK(insret); 1640 break; 1641 case PMC_EV_P4_UOPS_RETIRED: 1642 __P4SETMASK(ur); 1643 break; 1644 case PMC_EV_P4_UOP_TYPE: 1645 __P4SETMASK(ut); 1646 break; 1647 case PMC_EV_P4_BRANCH_RETIRED: 1648 __P4SETMASK(br); 1649 break; 1650 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1651 __P4SETMASK(mbr); 1652 break; 1653 case PMC_EV_P4_X87_ASSIST: 1654 __P4SETMASK(xa); 1655 break; 1656 case PMC_EV_P4_MACHINE_CLEAR: 1657 __P4SETMASK(machclr); 1658 break; 1659 default: 1660 return (-1); 1661 } 1662 1663 /* process additional flags */ 1664 while ((p = strsep(&ctrspec, ",")) != NULL) { 1665 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1666 q = strchr(p, '='); 1667 if (*++q == '\0') /* skip '=' */ 1668 return (-1); 1669 1670 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1671 cccractivemask = 0x0; 1672 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1673 cccractivemask = 0x1; 1674 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1675 cccractivemask = 0x2; 1676 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1677 cccractivemask = 0x3; 1678 else 1679 return (-1); 1680 1681 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1682 if (has_busreqtype == 0) 1683 return (-1); 1684 1685 q = strchr(p, '='); 1686 if (*++q == '\0') /* skip '=' */ 1687 return (-1); 1688 1689 count = strtol(q, &e, 0); 1690 if (e == q || *e != '\0') 1691 return (-1); 1692 evmask = (evmask & ~0x1F) | (count & 0x1F); 1693 } else if (KWMATCH(p, P4_KW_CASCADE)) 1694 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1695 else if (KWMATCH(p, P4_KW_EDGE)) 1696 pmc_config->pm_caps |= PMC_CAP_EDGE; 1697 else if (KWMATCH(p, P4_KW_INV)) 1698 pmc_config->pm_caps |= PMC_CAP_INVERT; 1699 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1700 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1701 return (-1); 1702 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1703 } else if (KWMATCH(p, P4_KW_OS)) 1704 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1705 else if (KWMATCH(p, P4_KW_PRECISE)) 1706 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1707 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1708 if (has_tag == 0) 1709 return (-1); 1710 1711 q = strchr(p, '='); 1712 if (*++q == '\0') /* skip '=' */ 1713 return (-1); 1714 1715 count = strtol(q, &e, 0); 1716 if (e == q || *e != '\0') 1717 return (-1); 1718 1719 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1720 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1721 P4_ESCR_TO_TAG_VALUE(count); 1722 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1723 q = strchr(p, '='); 1724 if (*++q == '\0') /* skip '=' */ 1725 return (-1); 1726 1727 count = strtol(q, &e, 0); 1728 if (e == q || *e != '\0') 1729 return (-1); 1730 1731 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1732 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1733 ~P4_CCCR_THRESHOLD_MASK; 1734 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1735 P4_CCCR_TO_THRESHOLD(count); 1736 } else if (KWMATCH(p, P4_KW_USR)) 1737 pmc_config->pm_caps |= PMC_CAP_USER; 1738 else 1739 return (-1); 1740 } 1741 1742 /* other post processing */ 1743 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1744 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1745 pe == PMC_EV_P4_BSQ_ALLOCATION) 1746 pmc_config->pm_caps |= PMC_CAP_EDGE; 1747 1748 /* fill in thread activity mask */ 1749 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1750 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1751 1752 if (evmask) 1753 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1754 1755 switch (pe) { 1756 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1757 if ((evmask & 0x06) == 0x06 || 1758 (evmask & 0x18) == 0x18) 1759 return (-1); /* can't have own+other bits together */ 1760 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1761 evmask = 0x1D; 1762 break; 1763 case PMC_EV_P4_MACHINE_CLEAR: 1764 /* only one bit is allowed to be set */ 1765 if ((evmask & (evmask - 1)) != 0) 1766 return (-1); 1767 if (evmask == 0) { 1768 evmask = 0x1; /* 'CLEAR' */ 1769 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1770 } 1771 break; 1772 default: 1773 if (evmask == 0 && pmask) { 1774 for (pm = pmask; pm->pm_name; pm++) 1775 evmask |= pm->pm_value; 1776 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1777 } 1778 } 1779 1780 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1781 P4_ESCR_TO_EVENT_MASK(evmask); 1782 1783 return (0); 1784 } 1785 1786 #endif 1787 1788 #if defined(__i386__) 1789 1790 /* 1791 * Pentium style PMCs 1792 */ 1793 1794 static struct pmc_event_alias p5_aliases[] = { 1795 EV_ALIAS("branches", "p5-taken-branches"), 1796 EV_ALIAS("cycles", "tsc"), 1797 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 1798 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 1799 EV_ALIAS("instructions", "p5-instructions-executed"), 1800 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 1801 EV_ALIAS("unhalted-cycles", 1802 "p5-number-of-cycles-not-in-halt-state"), 1803 EV_ALIAS(NULL, NULL) 1804 }; 1805 1806 static int 1807 p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 1808 struct pmc_op_pmcallocate *pmc_config) 1809 { 1810 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 1811 } 1812 1813 /* 1814 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 1815 * and Pentium M CPUs. 1816 */ 1817 1818 static struct pmc_event_alias p6_aliases[] = { 1819 EV_ALIAS("branches", "p6-br-inst-retired"), 1820 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 1821 EV_ALIAS("cycles", "tsc"), 1822 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 1823 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 1824 EV_ALIAS("instructions", "p6-inst-retired"), 1825 EV_ALIAS("interrupts", "p6-hw-int-rx"), 1826 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 1827 EV_ALIAS(NULL, NULL) 1828 }; 1829 1830 #define P6_KW_CMASK "cmask" 1831 #define P6_KW_EDGE "edge" 1832 #define P6_KW_INV "inv" 1833 #define P6_KW_OS "os" 1834 #define P6_KW_UMASK "umask" 1835 #define P6_KW_USR "usr" 1836 1837 static struct pmc_masks p6_mask_mesi[] = { 1838 PMCMASK(m, 0x01), 1839 PMCMASK(e, 0x02), 1840 PMCMASK(s, 0x04), 1841 PMCMASK(i, 0x08), 1842 NULLMASK 1843 }; 1844 1845 static struct pmc_masks p6_mask_mesihw[] = { 1846 PMCMASK(m, 0x01), 1847 PMCMASK(e, 0x02), 1848 PMCMASK(s, 0x04), 1849 PMCMASK(i, 0x08), 1850 PMCMASK(nonhw, 0x00), 1851 PMCMASK(hw, 0x10), 1852 PMCMASK(both, 0x30), 1853 NULLMASK 1854 }; 1855 1856 static struct pmc_masks p6_mask_hw[] = { 1857 PMCMASK(nonhw, 0x00), 1858 PMCMASK(hw, 0x10), 1859 PMCMASK(both, 0x30), 1860 NULLMASK 1861 }; 1862 1863 static struct pmc_masks p6_mask_any[] = { 1864 PMCMASK(self, 0x00), 1865 PMCMASK(any, 0x20), 1866 NULLMASK 1867 }; 1868 1869 static struct pmc_masks p6_mask_ekp[] = { 1870 PMCMASK(nta, 0x00), 1871 PMCMASK(t1, 0x01), 1872 PMCMASK(t2, 0x02), 1873 PMCMASK(wos, 0x03), 1874 NULLMASK 1875 }; 1876 1877 static struct pmc_masks p6_mask_pps[] = { 1878 PMCMASK(packed-and-scalar, 0x00), 1879 PMCMASK(scalar, 0x01), 1880 NULLMASK 1881 }; 1882 1883 static struct pmc_masks p6_mask_mite[] = { 1884 PMCMASK(packed-multiply, 0x01), 1885 PMCMASK(packed-shift, 0x02), 1886 PMCMASK(pack, 0x04), 1887 PMCMASK(unpack, 0x08), 1888 PMCMASK(packed-logical, 0x10), 1889 PMCMASK(packed-arithmetic, 0x20), 1890 NULLMASK 1891 }; 1892 1893 static struct pmc_masks p6_mask_fmt[] = { 1894 PMCMASK(mmxtofp, 0x00), 1895 PMCMASK(fptommx, 0x01), 1896 NULLMASK 1897 }; 1898 1899 static struct pmc_masks p6_mask_sr[] = { 1900 PMCMASK(es, 0x01), 1901 PMCMASK(ds, 0x02), 1902 PMCMASK(fs, 0x04), 1903 PMCMASK(gs, 0x08), 1904 NULLMASK 1905 }; 1906 1907 static struct pmc_masks p6_mask_eet[] = { 1908 PMCMASK(all, 0x00), 1909 PMCMASK(freq, 0x02), 1910 NULLMASK 1911 }; 1912 1913 static struct pmc_masks p6_mask_efur[] = { 1914 PMCMASK(all, 0x00), 1915 PMCMASK(loadop, 0x01), 1916 PMCMASK(stdsta, 0x02), 1917 NULLMASK 1918 }; 1919 1920 static struct pmc_masks p6_mask_essir[] = { 1921 PMCMASK(sse-packed-single, 0x00), 1922 PMCMASK(sse-packed-single-scalar-single, 0x01), 1923 PMCMASK(sse2-packed-double, 0x02), 1924 PMCMASK(sse2-scalar-double, 0x03), 1925 NULLMASK 1926 }; 1927 1928 static struct pmc_masks p6_mask_esscir[] = { 1929 PMCMASK(sse-packed-single, 0x00), 1930 PMCMASK(sse-scalar-single, 0x01), 1931 PMCMASK(sse2-packed-double, 0x02), 1932 PMCMASK(sse2-scalar-double, 0x03), 1933 NULLMASK 1934 }; 1935 1936 /* P6 event parser */ 1937 static int 1938 p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 1939 struct pmc_op_pmcallocate *pmc_config) 1940 { 1941 char *e, *p, *q; 1942 uint32_t evmask; 1943 int count, n; 1944 const struct pmc_masks *pm, *pmask; 1945 1946 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1947 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 1948 1949 evmask = 0; 1950 1951 #define P6MASKSET(M) pmask = p6_mask_ ## M 1952 1953 switch(pe) { 1954 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 1955 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 1956 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 1957 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 1958 case PMC_EV_P6_BUS_DRDY_CLOCKS: 1959 case PMC_EV_P6_BUS_LOCK_CLOCKS: 1960 case PMC_EV_P6_BUS_TRAN_BRD: 1961 case PMC_EV_P6_BUS_TRAN_RFO: 1962 case PMC_EV_P6_BUS_TRANS_WB: 1963 case PMC_EV_P6_BUS_TRAN_IFETCH: 1964 case PMC_EV_P6_BUS_TRAN_INVAL: 1965 case PMC_EV_P6_BUS_TRAN_PWR: 1966 case PMC_EV_P6_BUS_TRANS_P: 1967 case PMC_EV_P6_BUS_TRANS_IO: 1968 case PMC_EV_P6_BUS_TRAN_DEF: 1969 case PMC_EV_P6_BUS_TRAN_BURST: 1970 case PMC_EV_P6_BUS_TRAN_ANY: 1971 case PMC_EV_P6_BUS_TRAN_MEM: 1972 P6MASKSET(any); break; 1973 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 1974 case PMC_EV_P6_EMON_KNI_PREF_MISS: 1975 P6MASKSET(ekp); break; 1976 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 1977 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 1978 P6MASKSET(pps); break; 1979 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 1980 P6MASKSET(mite); break; 1981 case PMC_EV_P6_FP_MMX_TRANS: 1982 P6MASKSET(fmt); break; 1983 case PMC_EV_P6_SEG_RENAME_STALLS: 1984 case PMC_EV_P6_SEG_REG_RENAMES: 1985 P6MASKSET(sr); break; 1986 case PMC_EV_P6_EMON_EST_TRANS: 1987 P6MASKSET(eet); break; 1988 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 1989 P6MASKSET(efur); break; 1990 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 1991 P6MASKSET(essir); break; 1992 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 1993 P6MASKSET(esscir); break; 1994 default: 1995 pmask = NULL; 1996 break; 1997 } 1998 1999 /* Pentium M PMCs have a few events with different semantics */ 2000 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2001 if (pe == PMC_EV_P6_L2_LD || 2002 pe == PMC_EV_P6_L2_LINES_IN || 2003 pe == PMC_EV_P6_L2_LINES_OUT) 2004 P6MASKSET(mesihw); 2005 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2006 P6MASKSET(hw); 2007 } 2008 2009 /* Parse additional modifiers if present */ 2010 while ((p = strsep(&ctrspec, ",")) != NULL) { 2011 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2012 q = strchr(p, '='); 2013 if (*++q == '\0') /* skip '=' */ 2014 return (-1); 2015 count = strtol(q, &e, 0); 2016 if (e == q || *e != '\0') 2017 return (-1); 2018 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2019 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2020 P6_EVSEL_TO_CMASK(count); 2021 } else if (KWMATCH(p, P6_KW_EDGE)) { 2022 pmc_config->pm_caps |= PMC_CAP_EDGE; 2023 } else if (KWMATCH(p, P6_KW_INV)) { 2024 pmc_config->pm_caps |= PMC_CAP_INVERT; 2025 } else if (KWMATCH(p, P6_KW_OS)) { 2026 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2027 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2028 evmask = 0; 2029 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2030 return (-1); 2031 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2032 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2033 pe == PMC_EV_P6_BUS_TRAN_BRD || 2034 pe == PMC_EV_P6_BUS_TRAN_RFO || 2035 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2036 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2037 pe == PMC_EV_P6_BUS_TRAN_PWR || 2038 pe == PMC_EV_P6_BUS_TRAN_DEF || 2039 pe == PMC_EV_P6_BUS_TRAN_BURST || 2040 pe == PMC_EV_P6_BUS_TRAN_ANY || 2041 pe == PMC_EV_P6_BUS_TRAN_MEM || 2042 pe == PMC_EV_P6_BUS_TRANS_IO || 2043 pe == PMC_EV_P6_BUS_TRANS_P || 2044 pe == PMC_EV_P6_BUS_TRANS_WB || 2045 pe == PMC_EV_P6_EMON_EST_TRANS || 2046 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2047 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2048 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2049 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2050 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2051 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2052 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2053 pe == PMC_EV_P6_FP_MMX_TRANS) 2054 && (n > 1)) /* Only one mask keyword is allowed. */ 2055 return (-1); 2056 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2057 } else if (KWMATCH(p, P6_KW_USR)) { 2058 pmc_config->pm_caps |= PMC_CAP_USER; 2059 } else 2060 return (-1); 2061 } 2062 2063 /* post processing */ 2064 switch (pe) { 2065 2066 /* 2067 * The following events default to an evmask of 0 2068 */ 2069 2070 /* default => 'self' */ 2071 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2072 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2073 case PMC_EV_P6_BUS_TRAN_BRD: 2074 case PMC_EV_P6_BUS_TRAN_RFO: 2075 case PMC_EV_P6_BUS_TRANS_WB: 2076 case PMC_EV_P6_BUS_TRAN_IFETCH: 2077 case PMC_EV_P6_BUS_TRAN_INVAL: 2078 case PMC_EV_P6_BUS_TRAN_PWR: 2079 case PMC_EV_P6_BUS_TRANS_P: 2080 case PMC_EV_P6_BUS_TRANS_IO: 2081 case PMC_EV_P6_BUS_TRAN_DEF: 2082 case PMC_EV_P6_BUS_TRAN_BURST: 2083 case PMC_EV_P6_BUS_TRAN_ANY: 2084 case PMC_EV_P6_BUS_TRAN_MEM: 2085 2086 /* default => 'nta' */ 2087 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2088 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2089 2090 /* default => 'packed and scalar' */ 2091 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2092 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2093 2094 /* default => 'mmx to fp transitions' */ 2095 case PMC_EV_P6_FP_MMX_TRANS: 2096 2097 /* default => 'SSE Packed Single' */ 2098 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2099 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2100 2101 /* default => 'all fused micro-ops' */ 2102 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2103 2104 /* default => 'all transitions' */ 2105 case PMC_EV_P6_EMON_EST_TRANS: 2106 break; 2107 2108 case PMC_EV_P6_MMX_UOPS_EXEC: 2109 evmask = 0x0F; /* only value allowed */ 2110 break; 2111 2112 default: 2113 /* 2114 * For all other events, set the default event mask 2115 * to a logical OR of all the allowed event mask bits. 2116 */ 2117 if (evmask == 0 && pmask) { 2118 for (pm = pmask; pm->pm_name; pm++) 2119 evmask |= pm->pm_value; 2120 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2121 } 2122 2123 break; 2124 } 2125 2126 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2127 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2128 P6_EVSEL_TO_UMASK(evmask); 2129 2130 return (0); 2131 } 2132 2133 #endif 2134 2135 #if defined(__i386__) || defined(__amd64__) 2136 static int 2137 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2138 struct pmc_op_pmcallocate *pmc_config) 2139 { 2140 if (pe != PMC_EV_TSC_TSC) 2141 return (-1); 2142 2143 /* TSC events must be unqualified. */ 2144 if (ctrspec && *ctrspec != '\0') 2145 return (-1); 2146 2147 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2148 pmc_config->pm_caps |= PMC_CAP_READ; 2149 2150 return (0); 2151 } 2152 #endif 2153 2154 #if defined(__XSCALE__) 2155 2156 static struct pmc_event_alias xscale_aliases[] = { 2157 EV_ALIAS("branches", "BRANCH_RETIRED"), 2158 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2159 EV_ALIAS("dc-misses", "DC_MISS"), 2160 EV_ALIAS("ic-misses", "IC_MISS"), 2161 EV_ALIAS("instructions", "INSTR_RETIRED"), 2162 EV_ALIAS(NULL, NULL) 2163 }; 2164 static int 2165 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2166 struct pmc_op_pmcallocate *pmc_config __unused) 2167 { 2168 switch (pe) { 2169 default: 2170 break; 2171 } 2172 2173 return (0); 2174 } 2175 #endif 2176 2177 #if defined(__mips__) 2178 2179 static struct pmc_event_alias mips24k_aliases[] = { 2180 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2181 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2182 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2183 EV_ALIAS(NULL, NULL) 2184 }; 2185 2186 #define MIPS24K_KW_OS "os" 2187 #define MIPS24K_KW_USR "usr" 2188 #define MIPS24K_KW_ANYTHREAD "anythread" 2189 2190 static int 2191 mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2192 struct pmc_op_pmcallocate *pmc_config __unused) 2193 { 2194 char *p; 2195 2196 (void) pe; 2197 2198 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2199 2200 while ((p = strsep(&ctrspec, ",")) != NULL) { 2201 if (KWMATCH(p, MIPS24K_KW_OS)) 2202 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2203 else if (KWMATCH(p, MIPS24K_KW_USR)) 2204 pmc_config->pm_caps |= PMC_CAP_USER; 2205 else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD)) 2206 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2207 else 2208 return (-1); 2209 } 2210 2211 return (0); 2212 } 2213 #endif /* __mips__ */ 2214 2215 2216 /* 2217 * Match an event name `name' with its canonical form. 2218 * 2219 * Matches are case insensitive and spaces, periods, underscores and 2220 * hyphen characters are considered to match each other. 2221 * 2222 * Returns 1 for a match, 0 otherwise. 2223 */ 2224 2225 static int 2226 pmc_match_event_name(const char *name, const char *canonicalname) 2227 { 2228 int cc, nc; 2229 const unsigned char *c, *n; 2230 2231 c = (const unsigned char *) canonicalname; 2232 n = (const unsigned char *) name; 2233 2234 for (; (nc = *n) && (cc = *c); n++, c++) { 2235 2236 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2237 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2238 continue; 2239 2240 if (toupper(nc) == toupper(cc)) 2241 continue; 2242 2243 2244 return (0); 2245 } 2246 2247 if (*n == '\0' && *c == '\0') 2248 return (1); 2249 2250 return (0); 2251 } 2252 2253 /* 2254 * Match an event name against all the event named supported by a 2255 * PMC class. 2256 * 2257 * Returns an event descriptor pointer on match or NULL otherwise. 2258 */ 2259 static const struct pmc_event_descr * 2260 pmc_match_event_class(const char *name, 2261 const struct pmc_class_descr *pcd) 2262 { 2263 size_t n; 2264 const struct pmc_event_descr *ev; 2265 2266 ev = pcd->pm_evc_event_table; 2267 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2268 if (pmc_match_event_name(name, ev->pm_ev_name)) 2269 return (ev); 2270 2271 return (NULL); 2272 } 2273 2274 static int 2275 pmc_mdep_is_compatible_class(enum pmc_class pc) 2276 { 2277 size_t n; 2278 2279 for (n = 0; n < pmc_mdep_class_list_size; n++) 2280 if (pmc_mdep_class_list[n] == pc) 2281 return (1); 2282 return (0); 2283 } 2284 2285 /* 2286 * API entry points 2287 */ 2288 2289 int 2290 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2291 uint32_t flags, int cpu, pmc_id_t *pmcid) 2292 { 2293 size_t n; 2294 int retval; 2295 char *r, *spec_copy; 2296 const char *ctrname; 2297 const struct pmc_event_descr *ev; 2298 const struct pmc_event_alias *alias; 2299 struct pmc_op_pmcallocate pmc_config; 2300 const struct pmc_class_descr *pcd; 2301 2302 spec_copy = NULL; 2303 retval = -1; 2304 2305 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2306 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2307 errno = EINVAL; 2308 goto out; 2309 } 2310 2311 /* replace an event alias with the canonical event specifier */ 2312 if (pmc_mdep_event_aliases) 2313 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2314 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2315 spec_copy = strdup(alias->pm_spec); 2316 break; 2317 } 2318 2319 if (spec_copy == NULL) 2320 spec_copy = strdup(ctrspec); 2321 2322 r = spec_copy; 2323 ctrname = strsep(&r, ","); 2324 2325 /* 2326 * If a explicit class prefix was given by the user, restrict the 2327 * search for the event to the specified PMC class. 2328 */ 2329 ev = NULL; 2330 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2331 pcd = pmc_class_table[n]; 2332 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2333 strncasecmp(ctrname, pcd->pm_evc_name, 2334 pcd->pm_evc_name_size) == 0) { 2335 if ((ev = pmc_match_event_class(ctrname + 2336 pcd->pm_evc_name_size, pcd)) == NULL) { 2337 errno = EINVAL; 2338 goto out; 2339 } 2340 break; 2341 } 2342 } 2343 2344 /* 2345 * Otherwise, search for this event in all compatible PMC 2346 * classes. 2347 */ 2348 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2349 pcd = pmc_class_table[n]; 2350 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2351 ev = pmc_match_event_class(ctrname, pcd); 2352 } 2353 2354 if (ev == NULL) { 2355 errno = EINVAL; 2356 goto out; 2357 } 2358 2359 bzero(&pmc_config, sizeof(pmc_config)); 2360 pmc_config.pm_ev = ev->pm_ev_code; 2361 pmc_config.pm_class = pcd->pm_evc_class; 2362 pmc_config.pm_cpu = cpu; 2363 pmc_config.pm_mode = mode; 2364 pmc_config.pm_flags = flags; 2365 2366 if (PMC_IS_SAMPLING_MODE(mode)) 2367 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2368 2369 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2370 errno = EINVAL; 2371 goto out; 2372 } 2373 2374 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2375 goto out; 2376 2377 *pmcid = pmc_config.pm_pmcid; 2378 2379 retval = 0; 2380 2381 out: 2382 if (spec_copy) 2383 free(spec_copy); 2384 2385 return (retval); 2386 } 2387 2388 int 2389 pmc_attach(pmc_id_t pmc, pid_t pid) 2390 { 2391 struct pmc_op_pmcattach pmc_attach_args; 2392 2393 pmc_attach_args.pm_pmc = pmc; 2394 pmc_attach_args.pm_pid = pid; 2395 2396 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2397 } 2398 2399 int 2400 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2401 { 2402 unsigned int i; 2403 enum pmc_class cl; 2404 2405 cl = PMC_ID_TO_CLASS(pmcid); 2406 for (i = 0; i < cpu_info.pm_nclass; i++) 2407 if (cpu_info.pm_classes[i].pm_class == cl) { 2408 *caps = cpu_info.pm_classes[i].pm_caps; 2409 return (0); 2410 } 2411 errno = EINVAL; 2412 return (-1); 2413 } 2414 2415 int 2416 pmc_configure_logfile(int fd) 2417 { 2418 struct pmc_op_configurelog cla; 2419 2420 cla.pm_logfd = fd; 2421 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2422 return (-1); 2423 return (0); 2424 } 2425 2426 int 2427 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2428 { 2429 if (pmc_syscall == -1) { 2430 errno = ENXIO; 2431 return (-1); 2432 } 2433 2434 *pci = &cpu_info; 2435 return (0); 2436 } 2437 2438 int 2439 pmc_detach(pmc_id_t pmc, pid_t pid) 2440 { 2441 struct pmc_op_pmcattach pmc_detach_args; 2442 2443 pmc_detach_args.pm_pmc = pmc; 2444 pmc_detach_args.pm_pid = pid; 2445 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2446 } 2447 2448 int 2449 pmc_disable(int cpu, int pmc) 2450 { 2451 struct pmc_op_pmcadmin ssa; 2452 2453 ssa.pm_cpu = cpu; 2454 ssa.pm_pmc = pmc; 2455 ssa.pm_state = PMC_STATE_DISABLED; 2456 return (PMC_CALL(PMCADMIN, &ssa)); 2457 } 2458 2459 int 2460 pmc_enable(int cpu, int pmc) 2461 { 2462 struct pmc_op_pmcadmin ssa; 2463 2464 ssa.pm_cpu = cpu; 2465 ssa.pm_pmc = pmc; 2466 ssa.pm_state = PMC_STATE_FREE; 2467 return (PMC_CALL(PMCADMIN, &ssa)); 2468 } 2469 2470 /* 2471 * Return a list of events known to a given PMC class. 'cl' is the 2472 * PMC class identifier, 'eventnames' is the returned list of 'const 2473 * char *' pointers pointing to the names of the events. 'nevents' is 2474 * the number of event name pointers returned. 2475 * 2476 * The space for 'eventnames' is allocated using malloc(3). The caller 2477 * is responsible for freeing this space when done. 2478 */ 2479 int 2480 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2481 int *nevents) 2482 { 2483 int count; 2484 const char **names; 2485 const struct pmc_event_descr *ev; 2486 2487 switch (cl) 2488 { 2489 case PMC_CLASS_IAF: 2490 ev = iaf_event_table; 2491 count = PMC_EVENT_TABLE_SIZE(iaf); 2492 break; 2493 case PMC_CLASS_IAP: 2494 /* 2495 * Return the most appropriate set of event name 2496 * spellings for the current CPU. 2497 */ 2498 switch (cpu_info.pm_cputype) { 2499 default: 2500 case PMC_CPU_INTEL_ATOM: 2501 ev = atom_event_table; 2502 count = PMC_EVENT_TABLE_SIZE(atom); 2503 break; 2504 case PMC_CPU_INTEL_CORE: 2505 ev = core_event_table; 2506 count = PMC_EVENT_TABLE_SIZE(core); 2507 break; 2508 case PMC_CPU_INTEL_CORE2: 2509 case PMC_CPU_INTEL_CORE2EXTREME: 2510 ev = core2_event_table; 2511 count = PMC_EVENT_TABLE_SIZE(core2); 2512 break; 2513 case PMC_CPU_INTEL_COREI7: 2514 ev = corei7_event_table; 2515 count = PMC_EVENT_TABLE_SIZE(corei7); 2516 break; 2517 case PMC_CPU_INTEL_WESTMERE: 2518 ev = westmere_event_table; 2519 count = PMC_EVENT_TABLE_SIZE(westmere); 2520 break; 2521 } 2522 break; 2523 case PMC_CLASS_UCF: 2524 ev = ucf_event_table; 2525 count = PMC_EVENT_TABLE_SIZE(ucf); 2526 break; 2527 case PMC_CLASS_UCP: 2528 /* 2529 * Return the most appropriate set of event name 2530 * spellings for the current CPU. 2531 */ 2532 switch (cpu_info.pm_cputype) { 2533 default: 2534 case PMC_CPU_INTEL_COREI7: 2535 ev = corei7uc_event_table; 2536 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2537 break; 2538 case PMC_CPU_INTEL_WESTMERE: 2539 ev = westmereuc_event_table; 2540 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2541 break; 2542 } 2543 break; 2544 case PMC_CLASS_TSC: 2545 ev = tsc_event_table; 2546 count = PMC_EVENT_TABLE_SIZE(tsc); 2547 break; 2548 case PMC_CLASS_K7: 2549 ev = k7_event_table; 2550 count = PMC_EVENT_TABLE_SIZE(k7); 2551 break; 2552 case PMC_CLASS_K8: 2553 ev = k8_event_table; 2554 count = PMC_EVENT_TABLE_SIZE(k8); 2555 break; 2556 case PMC_CLASS_P4: 2557 ev = p4_event_table; 2558 count = PMC_EVENT_TABLE_SIZE(p4); 2559 break; 2560 case PMC_CLASS_P5: 2561 ev = p5_event_table; 2562 count = PMC_EVENT_TABLE_SIZE(p5); 2563 break; 2564 case PMC_CLASS_P6: 2565 ev = p6_event_table; 2566 count = PMC_EVENT_TABLE_SIZE(p6); 2567 break; 2568 case PMC_CLASS_XSCALE: 2569 ev = xscale_event_table; 2570 count = PMC_EVENT_TABLE_SIZE(xscale); 2571 break; 2572 case PMC_CLASS_MIPS24K: 2573 ev = mips24k_event_table; 2574 count = PMC_EVENT_TABLE_SIZE(mips24k); 2575 break; 2576 default: 2577 errno = EINVAL; 2578 return (-1); 2579 } 2580 2581 if ((names = malloc(count * sizeof(const char *))) == NULL) 2582 return (-1); 2583 2584 *eventnames = names; 2585 *nevents = count; 2586 2587 for (;count--; ev++, names++) 2588 *names = ev->pm_ev_name; 2589 return (0); 2590 } 2591 2592 int 2593 pmc_flush_logfile(void) 2594 { 2595 return (PMC_CALL(FLUSHLOG,0)); 2596 } 2597 2598 int 2599 pmc_get_driver_stats(struct pmc_driverstats *ds) 2600 { 2601 struct pmc_op_getdriverstats gms; 2602 2603 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2604 return (-1); 2605 2606 /* copy out fields in the current userland<->library interface */ 2607 ds->pm_intr_ignored = gms.pm_intr_ignored; 2608 ds->pm_intr_processed = gms.pm_intr_processed; 2609 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2610 ds->pm_syscalls = gms.pm_syscalls; 2611 ds->pm_syscall_errors = gms.pm_syscall_errors; 2612 ds->pm_buffer_requests = gms.pm_buffer_requests; 2613 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 2614 ds->pm_log_sweeps = gms.pm_log_sweeps; 2615 return (0); 2616 } 2617 2618 int 2619 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 2620 { 2621 struct pmc_op_getmsr gm; 2622 2623 gm.pm_pmcid = pmc; 2624 if (PMC_CALL(PMCGETMSR, &gm) < 0) 2625 return (-1); 2626 *msr = gm.pm_msr; 2627 return (0); 2628 } 2629 2630 int 2631 pmc_init(void) 2632 { 2633 int error, pmc_mod_id; 2634 unsigned int n; 2635 uint32_t abi_version; 2636 struct module_stat pmc_modstat; 2637 struct pmc_op_getcpuinfo op_cpu_info; 2638 #if defined(__amd64__) || defined(__i386__) 2639 int cpu_has_iaf_counters; 2640 unsigned int t; 2641 #endif 2642 2643 if (pmc_syscall != -1) /* already inited */ 2644 return (0); 2645 2646 /* retrieve the system call number from the KLD */ 2647 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 2648 return (-1); 2649 2650 pmc_modstat.version = sizeof(struct module_stat); 2651 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 2652 return (-1); 2653 2654 pmc_syscall = pmc_modstat.data.intval; 2655 2656 /* check the kernel module's ABI against our compiled-in version */ 2657 abi_version = PMC_VERSION; 2658 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 2659 return (pmc_syscall = -1); 2660 2661 /* ignore patch & minor numbers for the comparision */ 2662 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 2663 errno = EPROGMISMATCH; 2664 return (pmc_syscall = -1); 2665 } 2666 2667 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 2668 return (pmc_syscall = -1); 2669 2670 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 2671 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 2672 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 2673 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 2674 for (n = 0; n < cpu_info.pm_nclass; n++) 2675 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 2676 2677 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 2678 sizeof(struct pmc_class_descr *)); 2679 2680 if (pmc_class_table == NULL) 2681 return (-1); 2682 2683 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 2684 pmc_class_table[n] = NULL; 2685 2686 /* 2687 * Fill in the class table. 2688 */ 2689 n = 0; 2690 #if defined(__amd64__) || defined(__i386__) 2691 pmc_class_table[n++] = &tsc_class_table_descr; 2692 2693 /* 2694 * Check if this CPU has fixed function counters. 2695 */ 2696 cpu_has_iaf_counters = 0; 2697 for (t = 0; t < cpu_info.pm_nclass; t++) 2698 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF) 2699 cpu_has_iaf_counters = 1; 2700 #endif 2701 2702 #define PMC_MDEP_INIT(C) do { \ 2703 pmc_mdep_event_aliases = C##_aliases; \ 2704 pmc_mdep_class_list = C##_pmc_classes; \ 2705 pmc_mdep_class_list_size = \ 2706 PMC_TABLE_SIZE(C##_pmc_classes); \ 2707 } while (0) 2708 2709 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 2710 PMC_MDEP_INIT(C); \ 2711 if (cpu_has_iaf_counters) \ 2712 pmc_class_table[n++] = &iaf_class_table_descr; \ 2713 else \ 2714 pmc_mdep_event_aliases = \ 2715 C##_aliases_without_iaf; \ 2716 pmc_class_table[n] = &C##_class_table_descr; \ 2717 } while (0) 2718 2719 /* Configure the event name parser. */ 2720 switch (cpu_info.pm_cputype) { 2721 #if defined(__i386__) 2722 case PMC_CPU_AMD_K7: 2723 PMC_MDEP_INIT(k7); 2724 pmc_class_table[n] = &k7_class_table_descr; 2725 break; 2726 case PMC_CPU_INTEL_P5: 2727 PMC_MDEP_INIT(p5); 2728 pmc_class_table[n] = &p5_class_table_descr; 2729 break; 2730 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 2731 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 2732 case PMC_CPU_INTEL_PIII: 2733 case PMC_CPU_INTEL_PM: 2734 PMC_MDEP_INIT(p6); 2735 pmc_class_table[n] = &p6_class_table_descr; 2736 break; 2737 #endif 2738 #if defined(__amd64__) || defined(__i386__) 2739 case PMC_CPU_AMD_K8: 2740 PMC_MDEP_INIT(k8); 2741 pmc_class_table[n] = &k8_class_table_descr; 2742 break; 2743 case PMC_CPU_INTEL_ATOM: 2744 PMC_MDEP_INIT_INTEL_V2(atom); 2745 break; 2746 case PMC_CPU_INTEL_CORE: 2747 PMC_MDEP_INIT(core); 2748 pmc_class_table[n] = &core_class_table_descr; 2749 break; 2750 case PMC_CPU_INTEL_CORE2: 2751 case PMC_CPU_INTEL_CORE2EXTREME: 2752 PMC_MDEP_INIT_INTEL_V2(core2); 2753 break; 2754 case PMC_CPU_INTEL_COREI7: 2755 pmc_class_table[n++] = &ucf_class_table_descr; 2756 pmc_class_table[n++] = &corei7uc_class_table_descr; 2757 PMC_MDEP_INIT_INTEL_V2(corei7); 2758 break; 2759 case PMC_CPU_INTEL_WESTMERE: 2760 pmc_class_table[n++] = &ucf_class_table_descr; 2761 pmc_class_table[n++] = &westmereuc_class_table_descr; 2762 PMC_MDEP_INIT_INTEL_V2(westmere); 2763 break; 2764 case PMC_CPU_INTEL_PIV: 2765 PMC_MDEP_INIT(p4); 2766 pmc_class_table[n] = &p4_class_table_descr; 2767 break; 2768 #endif 2769 #if defined(__XSCALE__) 2770 case PMC_CPU_INTEL_XSCALE: 2771 PMC_MDEP_INIT(xscale); 2772 pmc_class_table[n] = &xscale_class_table_descr; 2773 break; 2774 #endif 2775 #if defined(__mips__) 2776 case PMC_CPU_MIPS_24K: 2777 PMC_MDEP_INIT(mips24k); 2778 pmc_class_table[n] = &mips24k_class_table_descr; 2779 break; 2780 #endif /* __mips__ */ 2781 default: 2782 /* 2783 * Some kind of CPU this version of the library knows nothing 2784 * about. This shouldn't happen since the abi version check 2785 * should have caught this. 2786 */ 2787 errno = ENXIO; 2788 return (pmc_syscall = -1); 2789 } 2790 2791 return (0); 2792 } 2793 2794 const char * 2795 pmc_name_of_capability(enum pmc_caps cap) 2796 { 2797 int i; 2798 2799 /* 2800 * 'cap' should have a single bit set and should be in 2801 * range. 2802 */ 2803 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 2804 cap > PMC_CAP_LAST) { 2805 errno = EINVAL; 2806 return (NULL); 2807 } 2808 2809 i = ffs(cap); 2810 return (pmc_capability_names[i - 1]); 2811 } 2812 2813 const char * 2814 pmc_name_of_class(enum pmc_class pc) 2815 { 2816 if ((int) pc >= PMC_CLASS_FIRST && 2817 pc <= PMC_CLASS_LAST) 2818 return (pmc_class_names[pc]); 2819 2820 errno = EINVAL; 2821 return (NULL); 2822 } 2823 2824 const char * 2825 pmc_name_of_cputype(enum pmc_cputype cp) 2826 { 2827 size_t n; 2828 2829 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 2830 if (cp == pmc_cputype_names[n].pm_cputype) 2831 return (pmc_cputype_names[n].pm_name); 2832 2833 errno = EINVAL; 2834 return (NULL); 2835 } 2836 2837 const char * 2838 pmc_name_of_disposition(enum pmc_disp pd) 2839 { 2840 if ((int) pd >= PMC_DISP_FIRST && 2841 pd <= PMC_DISP_LAST) 2842 return (pmc_disposition_names[pd]); 2843 2844 errno = EINVAL; 2845 return (NULL); 2846 } 2847 2848 const char * 2849 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 2850 { 2851 const struct pmc_event_descr *ev, *evfence; 2852 2853 ev = evfence = NULL; 2854 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 2855 ev = iaf_event_table; 2856 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 2857 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 2858 switch (cpu) { 2859 case PMC_CPU_INTEL_ATOM: 2860 ev = atom_event_table; 2861 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 2862 break; 2863 case PMC_CPU_INTEL_CORE: 2864 ev = core_event_table; 2865 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 2866 break; 2867 case PMC_CPU_INTEL_CORE2: 2868 case PMC_CPU_INTEL_CORE2EXTREME: 2869 ev = core2_event_table; 2870 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 2871 break; 2872 case PMC_CPU_INTEL_COREI7: 2873 ev = corei7_event_table; 2874 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 2875 break; 2876 case PMC_CPU_INTEL_WESTMERE: 2877 ev = westmere_event_table; 2878 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 2879 break; 2880 default: /* Unknown CPU type. */ 2881 break; 2882 } 2883 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 2884 ev = ucf_event_table; 2885 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 2886 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 2887 switch (cpu) { 2888 case PMC_CPU_INTEL_COREI7: 2889 ev = corei7uc_event_table; 2890 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 2891 break; 2892 case PMC_CPU_INTEL_WESTMERE: 2893 ev = westmereuc_event_table; 2894 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 2895 break; 2896 default: /* Unknown CPU type. */ 2897 break; 2898 } 2899 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 2900 ev = k7_event_table; 2901 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 2902 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 2903 ev = k8_event_table; 2904 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 2905 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 2906 ev = p4_event_table; 2907 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 2908 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 2909 ev = p5_event_table; 2910 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 2911 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 2912 ev = p6_event_table; 2913 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 2914 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 2915 ev = xscale_event_table; 2916 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 2917 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 2918 ev = mips24k_event_table; 2919 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k 2920 ); 2921 } else if (pe == PMC_EV_TSC_TSC) { 2922 ev = tsc_event_table; 2923 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 2924 } 2925 2926 for (; ev != evfence; ev++) 2927 if (pe == ev->pm_ev_code) 2928 return (ev->pm_ev_name); 2929 2930 return (NULL); 2931 } 2932 2933 const char * 2934 pmc_name_of_event(enum pmc_event pe) 2935 { 2936 const char *n; 2937 2938 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 2939 return (n); 2940 2941 errno = EINVAL; 2942 return (NULL); 2943 } 2944 2945 const char * 2946 pmc_name_of_mode(enum pmc_mode pm) 2947 { 2948 if ((int) pm >= PMC_MODE_FIRST && 2949 pm <= PMC_MODE_LAST) 2950 return (pmc_mode_names[pm]); 2951 2952 errno = EINVAL; 2953 return (NULL); 2954 } 2955 2956 const char * 2957 pmc_name_of_state(enum pmc_state ps) 2958 { 2959 if ((int) ps >= PMC_STATE_FIRST && 2960 ps <= PMC_STATE_LAST) 2961 return (pmc_state_names[ps]); 2962 2963 errno = EINVAL; 2964 return (NULL); 2965 } 2966 2967 int 2968 pmc_ncpu(void) 2969 { 2970 if (pmc_syscall == -1) { 2971 errno = ENXIO; 2972 return (-1); 2973 } 2974 2975 return (cpu_info.pm_ncpu); 2976 } 2977 2978 int 2979 pmc_npmc(int cpu) 2980 { 2981 if (pmc_syscall == -1) { 2982 errno = ENXIO; 2983 return (-1); 2984 } 2985 2986 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 2987 errno = EINVAL; 2988 return (-1); 2989 } 2990 2991 return (cpu_info.pm_npmc); 2992 } 2993 2994 int 2995 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 2996 { 2997 int nbytes, npmc; 2998 struct pmc_op_getpmcinfo *pmci; 2999 3000 if ((npmc = pmc_npmc(cpu)) < 0) 3001 return (-1); 3002 3003 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3004 npmc * sizeof(struct pmc_info); 3005 3006 if ((pmci = calloc(1, nbytes)) == NULL) 3007 return (-1); 3008 3009 pmci->pm_cpu = cpu; 3010 3011 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3012 free(pmci); 3013 return (-1); 3014 } 3015 3016 /* kernel<->library, library<->userland interfaces are identical */ 3017 *ppmci = (struct pmc_pmcinfo *) pmci; 3018 return (0); 3019 } 3020 3021 int 3022 pmc_read(pmc_id_t pmc, pmc_value_t *value) 3023 { 3024 struct pmc_op_pmcrw pmc_read_op; 3025 3026 pmc_read_op.pm_pmcid = pmc; 3027 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3028 pmc_read_op.pm_value = -1; 3029 3030 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3031 return (-1); 3032 3033 *value = pmc_read_op.pm_value; 3034 return (0); 3035 } 3036 3037 int 3038 pmc_release(pmc_id_t pmc) 3039 { 3040 struct pmc_op_simple pmc_release_args; 3041 3042 pmc_release_args.pm_pmcid = pmc; 3043 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3044 } 3045 3046 int 3047 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3048 { 3049 struct pmc_op_pmcrw pmc_rw_op; 3050 3051 pmc_rw_op.pm_pmcid = pmc; 3052 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3053 pmc_rw_op.pm_value = newvalue; 3054 3055 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3056 return (-1); 3057 3058 *oldvaluep = pmc_rw_op.pm_value; 3059 return (0); 3060 } 3061 3062 int 3063 pmc_set(pmc_id_t pmc, pmc_value_t value) 3064 { 3065 struct pmc_op_pmcsetcount sc; 3066 3067 sc.pm_pmcid = pmc; 3068 sc.pm_count = value; 3069 3070 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3071 return (-1); 3072 return (0); 3073 } 3074 3075 int 3076 pmc_start(pmc_id_t pmc) 3077 { 3078 struct pmc_op_simple pmc_start_args; 3079 3080 pmc_start_args.pm_pmcid = pmc; 3081 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3082 } 3083 3084 int 3085 pmc_stop(pmc_id_t pmc) 3086 { 3087 struct pmc_op_simple pmc_stop_args; 3088 3089 pmc_stop_args.pm_pmcid = pmc; 3090 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3091 } 3092 3093 int 3094 pmc_width(pmc_id_t pmcid, uint32_t *width) 3095 { 3096 unsigned int i; 3097 enum pmc_class cl; 3098 3099 cl = PMC_ID_TO_CLASS(pmcid); 3100 for (i = 0; i < cpu_info.pm_nclass; i++) 3101 if (cpu_info.pm_classes[i].pm_class == cl) { 3102 *width = cpu_info.pm_classes[i].pm_width; 3103 return (0); 3104 } 3105 errno = EINVAL; 3106 return (-1); 3107 } 3108 3109 int 3110 pmc_write(pmc_id_t pmc, pmc_value_t value) 3111 { 3112 struct pmc_op_pmcrw pmc_write_op; 3113 3114 pmc_write_op.pm_pmcid = pmc; 3115 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3116 pmc_write_op.pm_value = value; 3117 return (PMC_CALL(PMCRW, &pmc_write_op)); 3118 } 3119 3120 int 3121 pmc_writelog(uint32_t userdata) 3122 { 3123 struct pmc_op_writelog wl; 3124 3125 wl.pm_userdata = userdata; 3126 return (PMC_CALL(WRITELOG, &wl)); 3127 } 3128