1 /*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/pmc.h> 34 #include <sys/syscall.h> 35 36 #include <ctype.h> 37 #include <errno.h> 38 #include <fcntl.h> 39 #include <pmc.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <unistd.h> 45 46 #include "libpmcinternal.h" 47 48 /* Function prototypes */ 49 #if defined(__i386__) 50 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 51 struct pmc_op_pmcallocate *_pmc_config); 52 #endif 53 #if defined(__amd64__) || defined(__i386__) 54 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 57 struct pmc_op_pmcallocate *_pmc_config); 58 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 61 struct pmc_op_pmcallocate *_pmc_config); 62 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 63 struct pmc_op_pmcallocate *_pmc_config); 64 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 65 struct pmc_op_pmcallocate *_pmc_config); 66 #endif 67 #if defined(__i386__) 68 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 69 struct pmc_op_pmcallocate *_pmc_config); 70 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72 #endif 73 #if defined(__amd64__) || defined(__i386__) 74 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 #endif 77 #if defined(__arm__) 78 #if defined(__XSCALE__) 79 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 80 struct pmc_op_pmcallocate *_pmc_config); 81 #endif 82 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84 #endif 85 #if defined(__mips__) 86 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 87 struct pmc_op_pmcallocate *_pmc_config); 88 #endif /* __mips__ */ 89 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 90 struct pmc_op_pmcallocate *_pmc_config); 91 92 #if defined(__powerpc__) 93 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 94 struct pmc_op_pmcallocate *_pmc_config); 95 #endif /* __powerpc__ */ 96 97 #define PMC_CALL(cmd, params) \ 98 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 99 100 /* 101 * Event aliases provide a way for the user to ask for generic events 102 * like "cache-misses", or "instructions-retired". These aliases are 103 * mapped to the appropriate canonical event descriptions using a 104 * lookup table. 105 */ 106 struct pmc_event_alias { 107 const char *pm_alias; 108 const char *pm_spec; 109 }; 110 111 static const struct pmc_event_alias *pmc_mdep_event_aliases; 112 113 /* 114 * The pmc_event_descr structure maps symbolic names known to the user 115 * to integer codes used by the PMC KLD. 116 */ 117 struct pmc_event_descr { 118 const char *pm_ev_name; 119 enum pmc_event pm_ev_code; 120 }; 121 122 /* 123 * The pmc_class_descr structure maps class name prefixes for 124 * event names to event tables and other PMC class data. 125 */ 126 struct pmc_class_descr { 127 const char *pm_evc_name; 128 size_t pm_evc_name_size; 129 enum pmc_class pm_evc_class; 130 const struct pmc_event_descr *pm_evc_event_table; 131 size_t pm_evc_event_table_size; 132 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 133 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 134 }; 135 136 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 137 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 138 139 #undef __PMC_EV 140 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 141 142 /* 143 * PMC_CLASSDEP_TABLE(NAME, CLASS) 144 * 145 * Define a table mapping event names and aliases to HWPMC event IDs. 146 */ 147 #define PMC_CLASSDEP_TABLE(N, C) \ 148 static const struct pmc_event_descr N##_event_table[] = \ 149 { \ 150 __PMC_EV_##C() \ 151 } 152 153 PMC_CLASSDEP_TABLE(iaf, IAF); 154 PMC_CLASSDEP_TABLE(k7, K7); 155 PMC_CLASSDEP_TABLE(k8, K8); 156 PMC_CLASSDEP_TABLE(p4, P4); 157 PMC_CLASSDEP_TABLE(p5, P5); 158 PMC_CLASSDEP_TABLE(p6, P6); 159 PMC_CLASSDEP_TABLE(xscale, XSCALE); 160 PMC_CLASSDEP_TABLE(armv7, ARMV7); 161 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 162 PMC_CLASSDEP_TABLE(mips74k, MIPS74K); 163 PMC_CLASSDEP_TABLE(octeon, OCTEON); 164 PMC_CLASSDEP_TABLE(ucf, UCF); 165 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 166 PMC_CLASSDEP_TABLE(ppc970, PPC970); 167 PMC_CLASSDEP_TABLE(e500, E500); 168 169 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 170 171 #undef __PMC_EV_ALIAS 172 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 173 174 static const struct pmc_event_descr atom_event_table[] = 175 { 176 __PMC_EV_ALIAS_ATOM() 177 }; 178 179 static const struct pmc_event_descr atom_silvermont_event_table[] = 180 { 181 __PMC_EV_ALIAS_ATOM_SILVERMONT() 182 }; 183 184 static const struct pmc_event_descr core_event_table[] = 185 { 186 __PMC_EV_ALIAS_CORE() 187 }; 188 189 190 static const struct pmc_event_descr core2_event_table[] = 191 { 192 __PMC_EV_ALIAS_CORE2() 193 }; 194 195 static const struct pmc_event_descr corei7_event_table[] = 196 { 197 __PMC_EV_ALIAS_COREI7() 198 }; 199 200 static const struct pmc_event_descr nehalem_ex_event_table[] = 201 { 202 __PMC_EV_ALIAS_COREI7() 203 }; 204 205 static const struct pmc_event_descr haswell_event_table[] = 206 { 207 __PMC_EV_ALIAS_HASWELL() 208 }; 209 210 static const struct pmc_event_descr haswell_xeon_event_table[] = 211 { 212 __PMC_EV_ALIAS_HASWELL_XEON() 213 }; 214 215 216 static const struct pmc_event_descr ivybridge_event_table[] = 217 { 218 __PMC_EV_ALIAS_IVYBRIDGE() 219 }; 220 221 static const struct pmc_event_descr ivybridge_xeon_event_table[] = 222 { 223 __PMC_EV_ALIAS_IVYBRIDGE_XEON() 224 }; 225 226 static const struct pmc_event_descr sandybridge_event_table[] = 227 { 228 __PMC_EV_ALIAS_SANDYBRIDGE() 229 }; 230 231 static const struct pmc_event_descr sandybridge_xeon_event_table[] = 232 { 233 __PMC_EV_ALIAS_SANDYBRIDGE_XEON() 234 }; 235 236 static const struct pmc_event_descr westmere_event_table[] = 237 { 238 __PMC_EV_ALIAS_WESTMERE() 239 }; 240 241 static const struct pmc_event_descr westmere_ex_event_table[] = 242 { 243 __PMC_EV_ALIAS_WESTMERE() 244 }; 245 246 static const struct pmc_event_descr corei7uc_event_table[] = 247 { 248 __PMC_EV_ALIAS_COREI7UC() 249 }; 250 251 static const struct pmc_event_descr haswelluc_event_table[] = 252 { 253 __PMC_EV_ALIAS_HASWELLUC() 254 }; 255 256 static const struct pmc_event_descr sandybridgeuc_event_table[] = 257 { 258 __PMC_EV_ALIAS_SANDYBRIDGEUC() 259 }; 260 261 static const struct pmc_event_descr westmereuc_event_table[] = 262 { 263 __PMC_EV_ALIAS_WESTMEREUC() 264 }; 265 266 /* 267 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 268 * 269 * Map a CPU to the PMC classes it supports. 270 */ 271 #define PMC_MDEP_TABLE(N,C,...) \ 272 static const enum pmc_class N##_pmc_classes[] = { \ 273 PMC_CLASS_##C, __VA_ARGS__ \ 274 } 275 276 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 277 PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 278 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); 279 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 280 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 281 PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 282 PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 283 PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 284 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 285 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 286 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 287 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 288 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 289 PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 290 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); 291 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 292 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); 293 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); 294 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); 295 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 296 PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 297 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 298 PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); 299 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 300 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450, PMC_CLASS_TSC); 301 PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970, PMC_CLASS_TSC); 302 PMC_MDEP_TABLE(e500, E500, PMC_CLASS_SOFT, PMC_CLASS_E500, PMC_CLASS_TSC); 303 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 304 305 static const struct pmc_event_descr tsc_event_table[] = 306 { 307 __PMC_EV_TSC() 308 }; 309 310 #undef PMC_CLASS_TABLE_DESC 311 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 312 static const struct pmc_class_descr NAME##_class_table_descr = \ 313 { \ 314 .pm_evc_name = #CLASS "-", \ 315 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 316 .pm_evc_class = PMC_CLASS_##CLASS , \ 317 .pm_evc_event_table = EVENTS##_event_table , \ 318 .pm_evc_event_table_size = \ 319 PMC_EVENT_TABLE_SIZE(EVENTS), \ 320 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 321 } 322 323 #if defined(__i386__) || defined(__amd64__) 324 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 325 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 326 PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); 327 PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 328 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 329 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 330 PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); 331 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); 332 PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap); 333 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); 334 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); 335 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 336 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); 337 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 338 PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); 339 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 340 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 341 PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); 342 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 343 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 344 #endif 345 #if defined(__i386__) 346 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 347 #endif 348 #if defined(__i386__) || defined(__amd64__) 349 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 350 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 351 #endif 352 #if defined(__i386__) 353 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 354 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 355 #endif 356 #if defined(__i386__) || defined(__amd64__) 357 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 358 #endif 359 #if defined(__arm__) 360 #if defined(__XSCALE__) 361 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 362 #endif 363 PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7); 364 #endif 365 #if defined(__mips__) 366 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 367 PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); 368 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 369 #endif /* __mips__ */ 370 #if defined(__powerpc__) 371 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 372 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 373 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); 374 #endif 375 376 static struct pmc_class_descr soft_class_table_descr = 377 { 378 .pm_evc_name = "SOFT-", 379 .pm_evc_name_size = sizeof("SOFT-") - 1, 380 .pm_evc_class = PMC_CLASS_SOFT, 381 .pm_evc_event_table = NULL, 382 .pm_evc_event_table_size = 0, 383 .pm_evc_allocate_pmc = soft_allocate_pmc 384 }; 385 386 #undef PMC_CLASS_TABLE_DESC 387 388 static const struct pmc_class_descr **pmc_class_table; 389 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 390 391 static const enum pmc_class *pmc_mdep_class_list; 392 static size_t pmc_mdep_class_list_size; 393 394 /* 395 * Mapping tables, mapping enumeration values to human readable 396 * strings. 397 */ 398 399 static const char * pmc_capability_names[] = { 400 #undef __PMC_CAP 401 #define __PMC_CAP(N,V,D) #N , 402 __PMC_CAPS() 403 }; 404 405 static const char * pmc_class_names[] = { 406 #undef __PMC_CLASS 407 #define __PMC_CLASS(C) #C , 408 __PMC_CLASSES() 409 }; 410 411 struct pmc_cputype_map { 412 enum pmc_cputype pm_cputype; 413 const char *pm_name; 414 }; 415 416 static const struct pmc_cputype_map pmc_cputype_names[] = { 417 #undef __PMC_CPU 418 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 419 __PMC_CPUS() 420 }; 421 422 static const char * pmc_disposition_names[] = { 423 #undef __PMC_DISP 424 #define __PMC_DISP(D) #D , 425 __PMC_DISPOSITIONS() 426 }; 427 428 static const char * pmc_mode_names[] = { 429 #undef __PMC_MODE 430 #define __PMC_MODE(M,N) #M , 431 __PMC_MODES() 432 }; 433 434 static const char * pmc_state_names[] = { 435 #undef __PMC_STATE 436 #define __PMC_STATE(S) #S , 437 __PMC_STATES() 438 }; 439 440 /* 441 * Filled in by pmc_init(). 442 */ 443 static int pmc_syscall = -1; 444 static struct pmc_cpuinfo cpu_info; 445 static struct pmc_op_getdyneventinfo soft_event_info; 446 447 /* Event masks for events */ 448 struct pmc_masks { 449 const char *pm_name; 450 const uint64_t pm_value; 451 }; 452 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 453 #define NULLMASK { .pm_name = NULL } 454 455 #if defined(__amd64__) || defined(__i386__) 456 static int 457 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 458 { 459 const struct pmc_masks *pm; 460 char *q, *r; 461 int c; 462 463 if (pmask == NULL) /* no mask keywords */ 464 return (-1); 465 q = strchr(p, '='); /* skip '=' */ 466 if (*++q == '\0') /* no more data */ 467 return (-1); 468 c = 0; /* count of mask keywords seen */ 469 while ((r = strsep(&q, "+")) != NULL) { 470 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 471 pm++) 472 ; 473 if (pm->pm_name == NULL) /* not found */ 474 return (-1); 475 *evmask |= pm->pm_value; 476 c++; 477 } 478 return (c); 479 } 480 #endif 481 482 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 483 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 484 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 485 486 #if defined(__i386__) 487 488 /* 489 * AMD K7 (Athlon) CPUs. 490 */ 491 492 static struct pmc_event_alias k7_aliases[] = { 493 EV_ALIAS("branches", "k7-retired-branches"), 494 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 495 EV_ALIAS("cycles", "tsc"), 496 EV_ALIAS("dc-misses", "k7-dc-misses"), 497 EV_ALIAS("ic-misses", "k7-ic-misses"), 498 EV_ALIAS("instructions", "k7-retired-instructions"), 499 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 500 EV_ALIAS(NULL, NULL) 501 }; 502 503 #define K7_KW_COUNT "count" 504 #define K7_KW_EDGE "edge" 505 #define K7_KW_INV "inv" 506 #define K7_KW_OS "os" 507 #define K7_KW_UNITMASK "unitmask" 508 #define K7_KW_USR "usr" 509 510 static int 511 k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 512 struct pmc_op_pmcallocate *pmc_config) 513 { 514 char *e, *p, *q; 515 int c, has_unitmask; 516 uint32_t count, unitmask; 517 518 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 519 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 520 521 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 522 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 523 pe == PMC_EV_K7_DC_WRITEBACKS) { 524 has_unitmask = 1; 525 unitmask = AMD_PMC_UNITMASK_MOESI; 526 } else 527 unitmask = has_unitmask = 0; 528 529 while ((p = strsep(&ctrspec, ",")) != NULL) { 530 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 531 q = strchr(p, '='); 532 if (*++q == '\0') /* skip '=' */ 533 return (-1); 534 535 count = strtol(q, &e, 0); 536 if (e == q || *e != '\0') 537 return (-1); 538 539 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 540 pmc_config->pm_md.pm_amd.pm_amd_config |= 541 AMD_PMC_TO_COUNTER(count); 542 543 } else if (KWMATCH(p, K7_KW_EDGE)) { 544 pmc_config->pm_caps |= PMC_CAP_EDGE; 545 } else if (KWMATCH(p, K7_KW_INV)) { 546 pmc_config->pm_caps |= PMC_CAP_INVERT; 547 } else if (KWMATCH(p, K7_KW_OS)) { 548 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 549 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 550 if (has_unitmask == 0) 551 return (-1); 552 unitmask = 0; 553 q = strchr(p, '='); 554 if (*++q == '\0') /* skip '=' */ 555 return (-1); 556 557 while ((c = tolower(*q++)) != 0) 558 if (c == 'm') 559 unitmask |= AMD_PMC_UNITMASK_M; 560 else if (c == 'o') 561 unitmask |= AMD_PMC_UNITMASK_O; 562 else if (c == 'e') 563 unitmask |= AMD_PMC_UNITMASK_E; 564 else if (c == 's') 565 unitmask |= AMD_PMC_UNITMASK_S; 566 else if (c == 'i') 567 unitmask |= AMD_PMC_UNITMASK_I; 568 else if (c == '+') 569 continue; 570 else 571 return (-1); 572 573 if (unitmask == 0) 574 return (-1); 575 576 } else if (KWMATCH(p, K7_KW_USR)) { 577 pmc_config->pm_caps |= PMC_CAP_USER; 578 } else 579 return (-1); 580 } 581 582 if (has_unitmask) { 583 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 584 pmc_config->pm_md.pm_amd.pm_amd_config |= 585 AMD_PMC_TO_UNITMASK(unitmask); 586 } 587 588 return (0); 589 590 } 591 592 #endif 593 594 #if defined(__amd64__) || defined(__i386__) 595 596 /* 597 * Intel Core (Family 6, Model E) PMCs. 598 */ 599 600 static struct pmc_event_alias core_aliases[] = { 601 EV_ALIAS("branches", "iap-br-instr-ret"), 602 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 603 EV_ALIAS("cycles", "tsc-tsc"), 604 EV_ALIAS("ic-misses", "iap-icache-misses"), 605 EV_ALIAS("instructions", "iap-instr-ret"), 606 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 607 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 608 EV_ALIAS(NULL, NULL) 609 }; 610 611 /* 612 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 613 * and Atom (Family 6, model 1CH) PMCs. 614 * 615 * We map aliases to events on the fixed-function counters if these 616 * are present. Note that not all CPUs in this family contain fixed-function 617 * counters. 618 */ 619 620 static struct pmc_event_alias core2_aliases[] = { 621 EV_ALIAS("branches", "iap-br-inst-retired.any"), 622 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 623 EV_ALIAS("cycles", "tsc-tsc"), 624 EV_ALIAS("ic-misses", "iap-l1i-misses"), 625 EV_ALIAS("instructions", "iaf-instr-retired.any"), 626 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 627 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 628 EV_ALIAS(NULL, NULL) 629 }; 630 631 static struct pmc_event_alias core2_aliases_without_iaf[] = { 632 EV_ALIAS("branches", "iap-br-inst-retired.any"), 633 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 634 EV_ALIAS("cycles", "tsc-tsc"), 635 EV_ALIAS("ic-misses", "iap-l1i-misses"), 636 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 637 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 638 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 639 EV_ALIAS(NULL, NULL) 640 }; 641 642 #define atom_aliases core2_aliases 643 #define atom_aliases_without_iaf core2_aliases_without_iaf 644 #define atom_silvermont_aliases core2_aliases 645 #define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf 646 #define corei7_aliases core2_aliases 647 #define corei7_aliases_without_iaf core2_aliases_without_iaf 648 #define nehalem_ex_aliases core2_aliases 649 #define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf 650 #define haswell_aliases core2_aliases 651 #define haswell_aliases_without_iaf core2_aliases_without_iaf 652 #define haswell_xeon_aliases core2_aliases 653 #define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf 654 #define ivybridge_aliases core2_aliases 655 #define ivybridge_aliases_without_iaf core2_aliases_without_iaf 656 #define ivybridge_xeon_aliases core2_aliases 657 #define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 658 #define sandybridge_aliases core2_aliases 659 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf 660 #define sandybridge_xeon_aliases core2_aliases 661 #define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 662 #define westmere_aliases core2_aliases 663 #define westmere_aliases_without_iaf core2_aliases_without_iaf 664 #define westmere_ex_aliases core2_aliases 665 #define westmere_ex_aliases_without_iaf core2_aliases_without_iaf 666 667 #define IAF_KW_OS "os" 668 #define IAF_KW_USR "usr" 669 #define IAF_KW_ANYTHREAD "anythread" 670 671 /* 672 * Parse an event specifier for Intel fixed function counters. 673 */ 674 static int 675 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 676 struct pmc_op_pmcallocate *pmc_config) 677 { 678 char *p; 679 680 (void) pe; 681 682 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 683 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 684 685 while ((p = strsep(&ctrspec, ",")) != NULL) { 686 if (KWMATCH(p, IAF_KW_OS)) 687 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 688 else if (KWMATCH(p, IAF_KW_USR)) 689 pmc_config->pm_caps |= PMC_CAP_USER; 690 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 691 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 692 else 693 return (-1); 694 } 695 696 return (0); 697 } 698 699 /* 700 * Core/Core2 support. 701 */ 702 703 #define IAP_KW_AGENT "agent" 704 #define IAP_KW_ANYTHREAD "anythread" 705 #define IAP_KW_CACHESTATE "cachestate" 706 #define IAP_KW_CMASK "cmask" 707 #define IAP_KW_CORE "core" 708 #define IAP_KW_EDGE "edge" 709 #define IAP_KW_INV "inv" 710 #define IAP_KW_OS "os" 711 #define IAP_KW_PREFETCH "prefetch" 712 #define IAP_KW_SNOOPRESPONSE "snoopresponse" 713 #define IAP_KW_SNOOPTYPE "snooptype" 714 #define IAP_KW_TRANSITION "trans" 715 #define IAP_KW_USR "usr" 716 #define IAP_KW_RSP "rsp" 717 718 static struct pmc_masks iap_core_mask[] = { 719 PMCMASK(all, (0x3 << 14)), 720 PMCMASK(this, (0x1 << 14)), 721 NULLMASK 722 }; 723 724 static struct pmc_masks iap_agent_mask[] = { 725 PMCMASK(this, 0), 726 PMCMASK(any, (0x1 << 13)), 727 NULLMASK 728 }; 729 730 static struct pmc_masks iap_prefetch_mask[] = { 731 PMCMASK(both, (0x3 << 12)), 732 PMCMASK(only, (0x1 << 12)), 733 PMCMASK(exclude, 0), 734 NULLMASK 735 }; 736 737 static struct pmc_masks iap_cachestate_mask[] = { 738 PMCMASK(i, (1 << 8)), 739 PMCMASK(s, (1 << 9)), 740 PMCMASK(e, (1 << 10)), 741 PMCMASK(m, (1 << 11)), 742 NULLMASK 743 }; 744 745 static struct pmc_masks iap_snoopresponse_mask[] = { 746 PMCMASK(clean, (1 << 8)), 747 PMCMASK(hit, (1 << 9)), 748 PMCMASK(hitm, (1 << 11)), 749 NULLMASK 750 }; 751 752 static struct pmc_masks iap_snooptype_mask[] = { 753 PMCMASK(cmp2s, (1 << 8)), 754 PMCMASK(cmp2i, (1 << 9)), 755 NULLMASK 756 }; 757 758 static struct pmc_masks iap_transition_mask[] = { 759 PMCMASK(any, 0x00), 760 PMCMASK(frequency, 0x10), 761 NULLMASK 762 }; 763 764 static struct pmc_masks iap_rsp_mask_i7_wm[] = { 765 PMCMASK(DMND_DATA_RD, (1 << 0)), 766 PMCMASK(DMND_RFO, (1 << 1)), 767 PMCMASK(DMND_IFETCH, (1 << 2)), 768 PMCMASK(WB, (1 << 3)), 769 PMCMASK(PF_DATA_RD, (1 << 4)), 770 PMCMASK(PF_RFO, (1 << 5)), 771 PMCMASK(PF_IFETCH, (1 << 6)), 772 PMCMASK(OTHER, (1 << 7)), 773 PMCMASK(UNCORE_HIT, (1 << 8)), 774 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 775 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 776 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 777 PMCMASK(REMOTE_DRAM, (1 << 13)), 778 PMCMASK(LOCAL_DRAM, (1 << 14)), 779 PMCMASK(NON_DRAM, (1 << 15)), 780 NULLMASK 781 }; 782 783 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { 784 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 785 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 786 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 787 PMCMASK(REQ_WB, (1ULL << 3)), 788 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 789 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 790 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 791 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), 792 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), 793 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), 794 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), 795 PMCMASK(REQ_STRM_ST, (1ULL << 11)), 796 PMCMASK(REQ_OTHER, (1ULL << 15)), 797 PMCMASK(RES_ANY, (1ULL << 16)), 798 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 799 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 800 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 801 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 802 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 803 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 804 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 805 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 806 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 807 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 808 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 809 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 810 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 811 NULLMASK 812 }; 813 814 static struct pmc_masks iap_rsp_mask_haswell[] = { 815 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 816 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 817 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 818 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 819 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 820 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 821 PMCMASK(REQ_OTHER, (1ULL << 15)), 822 PMCMASK(RES_ANY, (1ULL << 16)), 823 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 824 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 825 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 826 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 827 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 828 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 829 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 830 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 831 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 832 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 833 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 834 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 835 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 836 NULLMASK 837 }; 838 839 static int 840 iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 841 struct pmc_op_pmcallocate *pmc_config) 842 { 843 char *e, *p, *q; 844 uint64_t cachestate, evmask, rsp; 845 int count, n; 846 847 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 848 PMC_CAP_QUALIFIER); 849 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 850 851 cachestate = evmask = rsp = 0; 852 853 /* Parse additional modifiers if present */ 854 while ((p = strsep(&ctrspec, ",")) != NULL) { 855 856 n = 0; 857 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 858 q = strchr(p, '='); 859 if (*++q == '\0') /* skip '=' */ 860 return (-1); 861 count = strtol(q, &e, 0); 862 if (e == q || *e != '\0') 863 return (-1); 864 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 865 pmc_config->pm_md.pm_iap.pm_iap_config |= 866 IAP_CMASK(count); 867 } else if (KWMATCH(p, IAP_KW_EDGE)) { 868 pmc_config->pm_caps |= PMC_CAP_EDGE; 869 } else if (KWMATCH(p, IAP_KW_INV)) { 870 pmc_config->pm_caps |= PMC_CAP_INVERT; 871 } else if (KWMATCH(p, IAP_KW_OS)) { 872 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 873 } else if (KWMATCH(p, IAP_KW_USR)) { 874 pmc_config->pm_caps |= PMC_CAP_USER; 875 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 876 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 877 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 878 n = pmc_parse_mask(iap_core_mask, p, &evmask); 879 if (n != 1) 880 return (-1); 881 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 882 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 883 if (n != 1) 884 return (-1); 885 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 886 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 887 if (n != 1) 888 return (-1); 889 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 890 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 891 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 892 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 893 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 894 if (n != 1) 895 return (-1); 896 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 897 cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 898 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 899 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 900 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 901 n = pmc_parse_mask(iap_snoopresponse_mask, p, 902 &evmask); 903 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 904 n = pmc_parse_mask(iap_snooptype_mask, p, 905 &evmask); 906 } else 907 return (-1); 908 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 909 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || 910 cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || 911 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { 912 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 913 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); 914 } else 915 return (-1); 916 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 917 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 918 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || 919 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { 920 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 921 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); 922 } else 923 return (-1); 924 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL || 925 cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) { 926 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 927 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); 928 } else 929 return (-1); 930 } else 931 return (-1); 932 933 if (n < 0) /* Parsing failed. */ 934 return (-1); 935 } 936 937 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 938 939 /* 940 * If the event requires a 'cachestate' qualifier but was not 941 * specified by the user, use a sensible default. 942 */ 943 switch (pe) { 944 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 945 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 946 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 947 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 948 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 949 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 950 case PMC_EV_IAP_EVENT_32H: /* Core */ 951 case PMC_EV_IAP_EVENT_40H: /* Core */ 952 case PMC_EV_IAP_EVENT_41H: /* Core */ 953 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 954 if (cachestate == 0) 955 cachestate = (0xF << 8); 956 break; 957 case PMC_EV_IAP_EVENT_77H: /* Atom */ 958 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 959 * Atom processor 960 */ 961 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 962 cachestate = (0xF << 8); 963 break; 964 default: 965 break; 966 } 967 968 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 969 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 970 971 return (0); 972 } 973 974 /* 975 * Intel Uncore. 976 */ 977 978 static int 979 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 980 struct pmc_op_pmcallocate *pmc_config) 981 { 982 (void) pe; 983 (void) ctrspec; 984 985 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 986 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 987 988 return (0); 989 } 990 991 #define UCP_KW_CMASK "cmask" 992 #define UCP_KW_EDGE "edge" 993 #define UCP_KW_INV "inv" 994 995 static int 996 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 997 struct pmc_op_pmcallocate *pmc_config) 998 { 999 char *e, *p, *q; 1000 int count, n; 1001 1002 (void) pe; 1003 1004 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 1005 PMC_CAP_QUALIFIER); 1006 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 1007 1008 /* Parse additional modifiers if present */ 1009 while ((p = strsep(&ctrspec, ",")) != NULL) { 1010 1011 n = 0; 1012 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 1013 q = strchr(p, '='); 1014 if (*++q == '\0') /* skip '=' */ 1015 return (-1); 1016 count = strtol(q, &e, 0); 1017 if (e == q || *e != '\0') 1018 return (-1); 1019 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1020 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 1021 UCP_CMASK(count); 1022 } else if (KWMATCH(p, UCP_KW_EDGE)) { 1023 pmc_config->pm_caps |= PMC_CAP_EDGE; 1024 } else if (KWMATCH(p, UCP_KW_INV)) { 1025 pmc_config->pm_caps |= PMC_CAP_INVERT; 1026 } else 1027 return (-1); 1028 1029 if (n < 0) /* Parsing failed. */ 1030 return (-1); 1031 } 1032 1033 return (0); 1034 } 1035 1036 /* 1037 * AMD K8 PMCs. 1038 * 1039 * These are very similar to AMD K7 PMCs, but support more kinds of 1040 * events. 1041 */ 1042 1043 static struct pmc_event_alias k8_aliases[] = { 1044 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 1045 EV_ALIAS("branch-mispredicts", 1046 "k8-fr-retired-taken-branches-mispredicted"), 1047 EV_ALIAS("cycles", "tsc"), 1048 EV_ALIAS("dc-misses", "k8-dc-miss"), 1049 EV_ALIAS("ic-misses", "k8-ic-miss"), 1050 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 1051 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 1052 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 1053 EV_ALIAS(NULL, NULL) 1054 }; 1055 1056 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 1057 1058 /* 1059 * Parsing tables 1060 */ 1061 1062 /* fp dispatched fpu ops */ 1063 static const struct pmc_masks k8_mask_fdfo[] = { 1064 __K8MASK(add-pipe-excluding-junk-ops, 0), 1065 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 1066 __K8MASK(store-pipe-excluding-junk-ops, 2), 1067 __K8MASK(add-pipe-junk-ops, 3), 1068 __K8MASK(multiply-pipe-junk-ops, 4), 1069 __K8MASK(store-pipe-junk-ops, 5), 1070 NULLMASK 1071 }; 1072 1073 /* ls segment register loads */ 1074 static const struct pmc_masks k8_mask_lsrl[] = { 1075 __K8MASK(es, 0), 1076 __K8MASK(cs, 1), 1077 __K8MASK(ss, 2), 1078 __K8MASK(ds, 3), 1079 __K8MASK(fs, 4), 1080 __K8MASK(gs, 5), 1081 __K8MASK(hs, 6), 1082 NULLMASK 1083 }; 1084 1085 /* ls locked operation */ 1086 static const struct pmc_masks k8_mask_llo[] = { 1087 __K8MASK(locked-instructions, 0), 1088 __K8MASK(cycles-in-request, 1), 1089 __K8MASK(cycles-to-complete, 2), 1090 NULLMASK 1091 }; 1092 1093 /* dc refill from {l2,system} and dc copyback */ 1094 static const struct pmc_masks k8_mask_dc[] = { 1095 __K8MASK(invalid, 0), 1096 __K8MASK(shared, 1), 1097 __K8MASK(exclusive, 2), 1098 __K8MASK(owner, 3), 1099 __K8MASK(modified, 4), 1100 NULLMASK 1101 }; 1102 1103 /* dc one bit ecc error */ 1104 static const struct pmc_masks k8_mask_dobee[] = { 1105 __K8MASK(scrubber, 0), 1106 __K8MASK(piggyback, 1), 1107 NULLMASK 1108 }; 1109 1110 /* dc dispatched prefetch instructions */ 1111 static const struct pmc_masks k8_mask_ddpi[] = { 1112 __K8MASK(load, 0), 1113 __K8MASK(store, 1), 1114 __K8MASK(nta, 2), 1115 NULLMASK 1116 }; 1117 1118 /* dc dcache accesses by locks */ 1119 static const struct pmc_masks k8_mask_dabl[] = { 1120 __K8MASK(accesses, 0), 1121 __K8MASK(misses, 1), 1122 NULLMASK 1123 }; 1124 1125 /* bu internal l2 request */ 1126 static const struct pmc_masks k8_mask_bilr[] = { 1127 __K8MASK(ic-fill, 0), 1128 __K8MASK(dc-fill, 1), 1129 __K8MASK(tlb-reload, 2), 1130 __K8MASK(tag-snoop, 3), 1131 __K8MASK(cancelled, 4), 1132 NULLMASK 1133 }; 1134 1135 /* bu fill request l2 miss */ 1136 static const struct pmc_masks k8_mask_bfrlm[] = { 1137 __K8MASK(ic-fill, 0), 1138 __K8MASK(dc-fill, 1), 1139 __K8MASK(tlb-reload, 2), 1140 NULLMASK 1141 }; 1142 1143 /* bu fill into l2 */ 1144 static const struct pmc_masks k8_mask_bfil[] = { 1145 __K8MASK(dirty-l2-victim, 0), 1146 __K8MASK(victim-from-l2, 1), 1147 NULLMASK 1148 }; 1149 1150 /* fr retired fpu instructions */ 1151 static const struct pmc_masks k8_mask_frfi[] = { 1152 __K8MASK(x87, 0), 1153 __K8MASK(mmx-3dnow, 1), 1154 __K8MASK(packed-sse-sse2, 2), 1155 __K8MASK(scalar-sse-sse2, 3), 1156 NULLMASK 1157 }; 1158 1159 /* fr retired fastpath double op instructions */ 1160 static const struct pmc_masks k8_mask_frfdoi[] = { 1161 __K8MASK(low-op-pos-0, 0), 1162 __K8MASK(low-op-pos-1, 1), 1163 __K8MASK(low-op-pos-2, 2), 1164 NULLMASK 1165 }; 1166 1167 /* fr fpu exceptions */ 1168 static const struct pmc_masks k8_mask_ffe[] = { 1169 __K8MASK(x87-reclass-microfaults, 0), 1170 __K8MASK(sse-retype-microfaults, 1), 1171 __K8MASK(sse-reclass-microfaults, 2), 1172 __K8MASK(sse-and-x87-microtraps, 3), 1173 NULLMASK 1174 }; 1175 1176 /* nb memory controller page access event */ 1177 static const struct pmc_masks k8_mask_nmcpae[] = { 1178 __K8MASK(page-hit, 0), 1179 __K8MASK(page-miss, 1), 1180 __K8MASK(page-conflict, 2), 1181 NULLMASK 1182 }; 1183 1184 /* nb memory controller turnaround */ 1185 static const struct pmc_masks k8_mask_nmct[] = { 1186 __K8MASK(dimm-turnaround, 0), 1187 __K8MASK(read-to-write-turnaround, 1), 1188 __K8MASK(write-to-read-turnaround, 2), 1189 NULLMASK 1190 }; 1191 1192 /* nb memory controller bypass saturation */ 1193 static const struct pmc_masks k8_mask_nmcbs[] = { 1194 __K8MASK(memory-controller-hi-pri-bypass, 0), 1195 __K8MASK(memory-controller-lo-pri-bypass, 1), 1196 __K8MASK(dram-controller-interface-bypass, 2), 1197 __K8MASK(dram-controller-queue-bypass, 3), 1198 NULLMASK 1199 }; 1200 1201 /* nb sized commands */ 1202 static const struct pmc_masks k8_mask_nsc[] = { 1203 __K8MASK(nonpostwrszbyte, 0), 1204 __K8MASK(nonpostwrszdword, 1), 1205 __K8MASK(postwrszbyte, 2), 1206 __K8MASK(postwrszdword, 3), 1207 __K8MASK(rdszbyte, 4), 1208 __K8MASK(rdszdword, 5), 1209 __K8MASK(rdmodwr, 6), 1210 NULLMASK 1211 }; 1212 1213 /* nb probe result */ 1214 static const struct pmc_masks k8_mask_npr[] = { 1215 __K8MASK(probe-miss, 0), 1216 __K8MASK(probe-hit, 1), 1217 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1218 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1219 NULLMASK 1220 }; 1221 1222 /* nb hypertransport bus bandwidth */ 1223 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1224 __K8MASK(command, 0), 1225 __K8MASK(data, 1), 1226 __K8MASK(buffer-release, 2), 1227 __K8MASK(nop, 3), 1228 NULLMASK 1229 }; 1230 1231 #undef __K8MASK 1232 1233 #define K8_KW_COUNT "count" 1234 #define K8_KW_EDGE "edge" 1235 #define K8_KW_INV "inv" 1236 #define K8_KW_MASK "mask" 1237 #define K8_KW_OS "os" 1238 #define K8_KW_USR "usr" 1239 1240 static int 1241 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1242 struct pmc_op_pmcallocate *pmc_config) 1243 { 1244 char *e, *p, *q; 1245 int n; 1246 uint32_t count; 1247 uint64_t evmask; 1248 const struct pmc_masks *pm, *pmask; 1249 1250 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1251 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1252 1253 pmask = NULL; 1254 evmask = 0; 1255 1256 #define __K8SETMASK(M) pmask = k8_mask_##M 1257 1258 /* setup parsing tables */ 1259 switch (pe) { 1260 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1261 __K8SETMASK(fdfo); 1262 break; 1263 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1264 __K8SETMASK(lsrl); 1265 break; 1266 case PMC_EV_K8_LS_LOCKED_OPERATION: 1267 __K8SETMASK(llo); 1268 break; 1269 case PMC_EV_K8_DC_REFILL_FROM_L2: 1270 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1271 case PMC_EV_K8_DC_COPYBACK: 1272 __K8SETMASK(dc); 1273 break; 1274 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1275 __K8SETMASK(dobee); 1276 break; 1277 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1278 __K8SETMASK(ddpi); 1279 break; 1280 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1281 __K8SETMASK(dabl); 1282 break; 1283 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1284 __K8SETMASK(bilr); 1285 break; 1286 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1287 __K8SETMASK(bfrlm); 1288 break; 1289 case PMC_EV_K8_BU_FILL_INTO_L2: 1290 __K8SETMASK(bfil); 1291 break; 1292 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1293 __K8SETMASK(frfi); 1294 break; 1295 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1296 __K8SETMASK(frfdoi); 1297 break; 1298 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1299 __K8SETMASK(ffe); 1300 break; 1301 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1302 __K8SETMASK(nmcpae); 1303 break; 1304 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1305 __K8SETMASK(nmct); 1306 break; 1307 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1308 __K8SETMASK(nmcbs); 1309 break; 1310 case PMC_EV_K8_NB_SIZED_COMMANDS: 1311 __K8SETMASK(nsc); 1312 break; 1313 case PMC_EV_K8_NB_PROBE_RESULT: 1314 __K8SETMASK(npr); 1315 break; 1316 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1317 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1318 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1319 __K8SETMASK(nhbb); 1320 break; 1321 1322 default: 1323 break; /* no options defined */ 1324 } 1325 1326 while ((p = strsep(&ctrspec, ",")) != NULL) { 1327 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1328 q = strchr(p, '='); 1329 if (*++q == '\0') /* skip '=' */ 1330 return (-1); 1331 1332 count = strtol(q, &e, 0); 1333 if (e == q || *e != '\0') 1334 return (-1); 1335 1336 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1337 pmc_config->pm_md.pm_amd.pm_amd_config |= 1338 AMD_PMC_TO_COUNTER(count); 1339 1340 } else if (KWMATCH(p, K8_KW_EDGE)) { 1341 pmc_config->pm_caps |= PMC_CAP_EDGE; 1342 } else if (KWMATCH(p, K8_KW_INV)) { 1343 pmc_config->pm_caps |= PMC_CAP_INVERT; 1344 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1345 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1346 return (-1); 1347 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1348 } else if (KWMATCH(p, K8_KW_OS)) { 1349 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1350 } else if (KWMATCH(p, K8_KW_USR)) { 1351 pmc_config->pm_caps |= PMC_CAP_USER; 1352 } else 1353 return (-1); 1354 } 1355 1356 /* other post processing */ 1357 switch (pe) { 1358 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1359 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1360 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1361 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1362 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1363 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1364 /* XXX only available in rev B and later */ 1365 break; 1366 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1367 /* XXX only available in rev C and later */ 1368 break; 1369 case PMC_EV_K8_LS_LOCKED_OPERATION: 1370 /* XXX CPU Rev A,B evmask is to be zero */ 1371 if (evmask & (evmask - 1)) /* > 1 bit set */ 1372 return (-1); 1373 if (evmask == 0) { 1374 evmask = 0x01; /* Rev C and later: #instrs */ 1375 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1376 } 1377 break; 1378 default: 1379 if (evmask == 0 && pmask != NULL) { 1380 for (pm = pmask; pm->pm_name; pm++) 1381 evmask |= pm->pm_value; 1382 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1383 } 1384 } 1385 1386 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1387 pmc_config->pm_md.pm_amd.pm_amd_config = 1388 AMD_PMC_TO_UNITMASK(evmask); 1389 1390 return (0); 1391 } 1392 1393 #endif 1394 1395 #if defined(__amd64__) || defined(__i386__) 1396 1397 /* 1398 * Intel P4 PMCs 1399 */ 1400 1401 static struct pmc_event_alias p4_aliases[] = { 1402 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1403 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1404 EV_ALIAS("cycles", "tsc"), 1405 EV_ALIAS("instructions", 1406 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1407 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1408 EV_ALIAS(NULL, NULL) 1409 }; 1410 1411 #define P4_KW_ACTIVE "active" 1412 #define P4_KW_ACTIVE_ANY "any" 1413 #define P4_KW_ACTIVE_BOTH "both" 1414 #define P4_KW_ACTIVE_NONE "none" 1415 #define P4_KW_ACTIVE_SINGLE "single" 1416 #define P4_KW_BUSREQTYPE "busreqtype" 1417 #define P4_KW_CASCADE "cascade" 1418 #define P4_KW_EDGE "edge" 1419 #define P4_KW_INV "complement" 1420 #define P4_KW_OS "os" 1421 #define P4_KW_MASK "mask" 1422 #define P4_KW_PRECISE "precise" 1423 #define P4_KW_TAG "tag" 1424 #define P4_KW_THRESHOLD "threshold" 1425 #define P4_KW_USR "usr" 1426 1427 #define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1428 1429 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1430 __P4MASK(dd, 0), 1431 __P4MASK(db, 1), 1432 __P4MASK(di, 2), 1433 __P4MASK(bd, 3), 1434 __P4MASK(bb, 4), 1435 __P4MASK(bi, 5), 1436 __P4MASK(id, 6), 1437 __P4MASK(ib, 7), 1438 NULLMASK 1439 }; 1440 1441 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1442 __P4MASK(tcmiss, 0), 1443 NULLMASK, 1444 }; 1445 1446 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1447 __P4MASK(hit, 0), 1448 __P4MASK(miss, 1), 1449 __P4MASK(hit-uc, 2), 1450 NULLMASK 1451 }; 1452 1453 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1454 __P4MASK(st-rb-full, 2), 1455 __P4MASK(64k-conf, 3), 1456 NULLMASK 1457 }; 1458 1459 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1460 __P4MASK(lsc, 0), 1461 __P4MASK(ssc, 1), 1462 NULLMASK 1463 }; 1464 1465 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1466 __P4MASK(split-ld, 1), 1467 NULLMASK 1468 }; 1469 1470 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1471 __P4MASK(split-st, 1), 1472 NULLMASK 1473 }; 1474 1475 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1476 __P4MASK(no-sta, 1), 1477 __P4MASK(no-std, 3), 1478 __P4MASK(partial-data, 4), 1479 __P4MASK(unalgn-addr, 5), 1480 NULLMASK 1481 }; 1482 1483 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1484 __P4MASK(dtmiss, 0), 1485 __P4MASK(itmiss, 1), 1486 NULLMASK 1487 }; 1488 1489 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1490 __P4MASK(rd-2ndl-hits, 0), 1491 __P4MASK(rd-2ndl-hite, 1), 1492 __P4MASK(rd-2ndl-hitm, 2), 1493 __P4MASK(rd-3rdl-hits, 3), 1494 __P4MASK(rd-3rdl-hite, 4), 1495 __P4MASK(rd-3rdl-hitm, 5), 1496 __P4MASK(rd-2ndl-miss, 8), 1497 __P4MASK(rd-3rdl-miss, 9), 1498 __P4MASK(wr-2ndl-miss, 10), 1499 NULLMASK 1500 }; 1501 1502 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1503 __P4MASK(all-read, 5), 1504 __P4MASK(all-write, 6), 1505 __P4MASK(mem-uc, 7), 1506 __P4MASK(mem-wc, 8), 1507 __P4MASK(mem-wt, 9), 1508 __P4MASK(mem-wp, 10), 1509 __P4MASK(mem-wb, 11), 1510 __P4MASK(own, 13), 1511 __P4MASK(other, 14), 1512 __P4MASK(prefetch, 15), 1513 NULLMASK 1514 }; 1515 1516 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1517 __P4MASK(all-read, 5), 1518 __P4MASK(all-write, 6), 1519 __P4MASK(mem-uc, 7), 1520 __P4MASK(mem-wc, 8), 1521 __P4MASK(mem-wt, 9), 1522 __P4MASK(mem-wp, 10), 1523 __P4MASK(mem-wb, 11), 1524 __P4MASK(own, 13), 1525 __P4MASK(other, 14), 1526 __P4MASK(prefetch, 15), 1527 NULLMASK 1528 }; 1529 1530 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1531 __P4MASK(drdy-drv, 0), 1532 __P4MASK(drdy-own, 1), 1533 __P4MASK(drdy-other, 2), 1534 __P4MASK(dbsy-drv, 3), 1535 __P4MASK(dbsy-own, 4), 1536 __P4MASK(dbsy-other, 5), 1537 NULLMASK 1538 }; 1539 1540 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1541 __P4MASK(req-type0, 0), 1542 __P4MASK(req-type1, 1), 1543 __P4MASK(req-len0, 2), 1544 __P4MASK(req-len1, 3), 1545 __P4MASK(req-io-type, 5), 1546 __P4MASK(req-lock-type, 6), 1547 __P4MASK(req-cache-type, 7), 1548 __P4MASK(req-split-type, 8), 1549 __P4MASK(req-dem-type, 9), 1550 __P4MASK(req-ord-type, 10), 1551 __P4MASK(mem-type0, 11), 1552 __P4MASK(mem-type1, 12), 1553 __P4MASK(mem-type2, 13), 1554 NULLMASK 1555 }; 1556 1557 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1558 __P4MASK(all, 15), 1559 NULLMASK 1560 }; 1561 1562 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1563 __P4MASK(all, 15), 1564 NULLMASK 1565 }; 1566 1567 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1568 __P4MASK(all, 15), 1569 NULLMASK 1570 }; 1571 1572 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1573 __P4MASK(all, 15), 1574 NULLMASK 1575 }; 1576 1577 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1578 __P4MASK(all, 15), 1579 NULLMASK 1580 }; 1581 1582 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1583 __P4MASK(all, 15), 1584 NULLMASK 1585 }; 1586 1587 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1588 __P4MASK(all, 15), 1589 NULLMASK 1590 }; 1591 1592 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1593 __P4MASK(all, 15), 1594 NULLMASK 1595 }; 1596 1597 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1598 __P4MASK(allp0, 3), 1599 __P4MASK(allp2, 4), 1600 NULLMASK 1601 }; 1602 1603 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1604 __P4MASK(running, 0), 1605 NULLMASK 1606 }; 1607 1608 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1609 __P4MASK(cisc, 0), 1610 NULLMASK 1611 }; 1612 1613 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1614 __P4MASK(from-tc-build, 0), 1615 __P4MASK(from-tc-deliver, 1), 1616 __P4MASK(from-rom, 2), 1617 NULLMASK 1618 }; 1619 1620 static const struct pmc_masks p4_mask_rmbt[] = { 1621 /* retired mispred branch type */ 1622 __P4MASK(conditional, 1), 1623 __P4MASK(call, 2), 1624 __P4MASK(return, 3), 1625 __P4MASK(indirect, 4), 1626 NULLMASK 1627 }; 1628 1629 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1630 __P4MASK(conditional, 1), 1631 __P4MASK(call, 2), 1632 __P4MASK(retired, 3), 1633 __P4MASK(indirect, 4), 1634 NULLMASK 1635 }; 1636 1637 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1638 __P4MASK(sbfull, 5), 1639 NULLMASK 1640 }; 1641 1642 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1643 __P4MASK(wcb-evicts, 0), 1644 __P4MASK(wcb-full-evict, 1), 1645 NULLMASK 1646 }; 1647 1648 static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1649 __P4MASK(nbogus, 0), 1650 __P4MASK(bogus, 1), 1651 NULLMASK 1652 }; 1653 1654 static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1655 __P4MASK(nbogus0, 0), 1656 __P4MASK(nbogus1, 1), 1657 __P4MASK(nbogus2, 2), 1658 __P4MASK(nbogus3, 3), 1659 __P4MASK(bogus0, 4), 1660 __P4MASK(bogus1, 5), 1661 __P4MASK(bogus2, 6), 1662 __P4MASK(bogus3, 7), 1663 NULLMASK 1664 }; 1665 1666 static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1667 __P4MASK(nbogus, 0), 1668 __P4MASK(bogus, 1), 1669 NULLMASK 1670 }; 1671 1672 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1673 __P4MASK(nbogusntag, 0), 1674 __P4MASK(nbogustag, 1), 1675 __P4MASK(bogusntag, 2), 1676 __P4MASK(bogustag, 3), 1677 NULLMASK 1678 }; 1679 1680 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1681 __P4MASK(nbogus, 0), 1682 __P4MASK(bogus, 1), 1683 NULLMASK 1684 }; 1685 1686 static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1687 __P4MASK(tagloads, 1), 1688 __P4MASK(tagstores, 2), 1689 NULLMASK 1690 }; 1691 1692 static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1693 __P4MASK(mmnp, 0), 1694 __P4MASK(mmnm, 1), 1695 __P4MASK(mmtp, 2), 1696 __P4MASK(mmtm, 3), 1697 NULLMASK 1698 }; 1699 1700 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1701 __P4MASK(nbogus, 0), 1702 NULLMASK 1703 }; 1704 1705 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1706 __P4MASK(fpsu, 0), 1707 __P4MASK(fpso, 1), 1708 __P4MASK(poao, 2), 1709 __P4MASK(poau, 3), 1710 __P4MASK(prea, 4), 1711 NULLMASK 1712 }; 1713 1714 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1715 __P4MASK(clear, 0), 1716 __P4MASK(moclear, 2), 1717 __P4MASK(smclear, 3), 1718 NULLMASK 1719 }; 1720 1721 /* P4 event parser */ 1722 static int 1723 p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1724 struct pmc_op_pmcallocate *pmc_config) 1725 { 1726 1727 char *e, *p, *q; 1728 int count, has_tag, has_busreqtype, n; 1729 uint32_t cccractivemask; 1730 uint64_t evmask; 1731 const struct pmc_masks *pm, *pmask; 1732 1733 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1734 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1735 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1736 1737 pmask = NULL; 1738 evmask = 0; 1739 cccractivemask = 0x3; 1740 has_tag = has_busreqtype = 0; 1741 1742 #define __P4SETMASK(M) do { \ 1743 pmask = p4_mask_##M; \ 1744 } while (0) 1745 1746 switch (pe) { 1747 case PMC_EV_P4_TC_DELIVER_MODE: 1748 __P4SETMASK(tcdm); 1749 break; 1750 case PMC_EV_P4_BPU_FETCH_REQUEST: 1751 __P4SETMASK(bfr); 1752 break; 1753 case PMC_EV_P4_ITLB_REFERENCE: 1754 __P4SETMASK(ir); 1755 break; 1756 case PMC_EV_P4_MEMORY_CANCEL: 1757 __P4SETMASK(memcan); 1758 break; 1759 case PMC_EV_P4_MEMORY_COMPLETE: 1760 __P4SETMASK(memcomp); 1761 break; 1762 case PMC_EV_P4_LOAD_PORT_REPLAY: 1763 __P4SETMASK(lpr); 1764 break; 1765 case PMC_EV_P4_STORE_PORT_REPLAY: 1766 __P4SETMASK(spr); 1767 break; 1768 case PMC_EV_P4_MOB_LOAD_REPLAY: 1769 __P4SETMASK(mlr); 1770 break; 1771 case PMC_EV_P4_PAGE_WALK_TYPE: 1772 __P4SETMASK(pwt); 1773 break; 1774 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1775 __P4SETMASK(bcr); 1776 break; 1777 case PMC_EV_P4_IOQ_ALLOCATION: 1778 __P4SETMASK(ia); 1779 has_busreqtype = 1; 1780 break; 1781 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1782 __P4SETMASK(iae); 1783 has_busreqtype = 1; 1784 break; 1785 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1786 __P4SETMASK(fda); 1787 break; 1788 case PMC_EV_P4_BSQ_ALLOCATION: 1789 __P4SETMASK(ba); 1790 break; 1791 case PMC_EV_P4_SSE_INPUT_ASSIST: 1792 __P4SETMASK(sia); 1793 break; 1794 case PMC_EV_P4_PACKED_SP_UOP: 1795 __P4SETMASK(psu); 1796 break; 1797 case PMC_EV_P4_PACKED_DP_UOP: 1798 __P4SETMASK(pdu); 1799 break; 1800 case PMC_EV_P4_SCALAR_SP_UOP: 1801 __P4SETMASK(ssu); 1802 break; 1803 case PMC_EV_P4_SCALAR_DP_UOP: 1804 __P4SETMASK(sdu); 1805 break; 1806 case PMC_EV_P4_64BIT_MMX_UOP: 1807 __P4SETMASK(64bmu); 1808 break; 1809 case PMC_EV_P4_128BIT_MMX_UOP: 1810 __P4SETMASK(128bmu); 1811 break; 1812 case PMC_EV_P4_X87_FP_UOP: 1813 __P4SETMASK(xfu); 1814 break; 1815 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1816 __P4SETMASK(xsmu); 1817 break; 1818 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1819 __P4SETMASK(gpe); 1820 break; 1821 case PMC_EV_P4_TC_MS_XFER: 1822 __P4SETMASK(tmx); 1823 break; 1824 case PMC_EV_P4_UOP_QUEUE_WRITES: 1825 __P4SETMASK(uqw); 1826 break; 1827 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1828 __P4SETMASK(rmbt); 1829 break; 1830 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1831 __P4SETMASK(rbt); 1832 break; 1833 case PMC_EV_P4_RESOURCE_STALL: 1834 __P4SETMASK(rs); 1835 break; 1836 case PMC_EV_P4_WC_BUFFER: 1837 __P4SETMASK(wb); 1838 break; 1839 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1840 case PMC_EV_P4_B2B_CYCLES: 1841 case PMC_EV_P4_BNR: 1842 case PMC_EV_P4_SNOOP: 1843 case PMC_EV_P4_RESPONSE: 1844 break; 1845 case PMC_EV_P4_FRONT_END_EVENT: 1846 __P4SETMASK(fee); 1847 break; 1848 case PMC_EV_P4_EXECUTION_EVENT: 1849 __P4SETMASK(ee); 1850 break; 1851 case PMC_EV_P4_REPLAY_EVENT: 1852 __P4SETMASK(re); 1853 break; 1854 case PMC_EV_P4_INSTR_RETIRED: 1855 __P4SETMASK(insret); 1856 break; 1857 case PMC_EV_P4_UOPS_RETIRED: 1858 __P4SETMASK(ur); 1859 break; 1860 case PMC_EV_P4_UOP_TYPE: 1861 __P4SETMASK(ut); 1862 break; 1863 case PMC_EV_P4_BRANCH_RETIRED: 1864 __P4SETMASK(br); 1865 break; 1866 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1867 __P4SETMASK(mbr); 1868 break; 1869 case PMC_EV_P4_X87_ASSIST: 1870 __P4SETMASK(xa); 1871 break; 1872 case PMC_EV_P4_MACHINE_CLEAR: 1873 __P4SETMASK(machclr); 1874 break; 1875 default: 1876 return (-1); 1877 } 1878 1879 /* process additional flags */ 1880 while ((p = strsep(&ctrspec, ",")) != NULL) { 1881 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1882 q = strchr(p, '='); 1883 if (*++q == '\0') /* skip '=' */ 1884 return (-1); 1885 1886 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1887 cccractivemask = 0x0; 1888 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1889 cccractivemask = 0x1; 1890 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1891 cccractivemask = 0x2; 1892 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1893 cccractivemask = 0x3; 1894 else 1895 return (-1); 1896 1897 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1898 if (has_busreqtype == 0) 1899 return (-1); 1900 1901 q = strchr(p, '='); 1902 if (*++q == '\0') /* skip '=' */ 1903 return (-1); 1904 1905 count = strtol(q, &e, 0); 1906 if (e == q || *e != '\0') 1907 return (-1); 1908 evmask = (evmask & ~0x1F) | (count & 0x1F); 1909 } else if (KWMATCH(p, P4_KW_CASCADE)) 1910 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1911 else if (KWMATCH(p, P4_KW_EDGE)) 1912 pmc_config->pm_caps |= PMC_CAP_EDGE; 1913 else if (KWMATCH(p, P4_KW_INV)) 1914 pmc_config->pm_caps |= PMC_CAP_INVERT; 1915 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1916 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1917 return (-1); 1918 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1919 } else if (KWMATCH(p, P4_KW_OS)) 1920 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1921 else if (KWMATCH(p, P4_KW_PRECISE)) 1922 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1923 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1924 if (has_tag == 0) 1925 return (-1); 1926 1927 q = strchr(p, '='); 1928 if (*++q == '\0') /* skip '=' */ 1929 return (-1); 1930 1931 count = strtol(q, &e, 0); 1932 if (e == q || *e != '\0') 1933 return (-1); 1934 1935 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1936 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1937 P4_ESCR_TO_TAG_VALUE(count); 1938 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1939 q = strchr(p, '='); 1940 if (*++q == '\0') /* skip '=' */ 1941 return (-1); 1942 1943 count = strtol(q, &e, 0); 1944 if (e == q || *e != '\0') 1945 return (-1); 1946 1947 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1948 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1949 ~P4_CCCR_THRESHOLD_MASK; 1950 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1951 P4_CCCR_TO_THRESHOLD(count); 1952 } else if (KWMATCH(p, P4_KW_USR)) 1953 pmc_config->pm_caps |= PMC_CAP_USER; 1954 else 1955 return (-1); 1956 } 1957 1958 /* other post processing */ 1959 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1960 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1961 pe == PMC_EV_P4_BSQ_ALLOCATION) 1962 pmc_config->pm_caps |= PMC_CAP_EDGE; 1963 1964 /* fill in thread activity mask */ 1965 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1966 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1967 1968 if (evmask) 1969 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1970 1971 switch (pe) { 1972 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1973 if ((evmask & 0x06) == 0x06 || 1974 (evmask & 0x18) == 0x18) 1975 return (-1); /* can't have own+other bits together */ 1976 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1977 evmask = 0x1D; 1978 break; 1979 case PMC_EV_P4_MACHINE_CLEAR: 1980 /* only one bit is allowed to be set */ 1981 if ((evmask & (evmask - 1)) != 0) 1982 return (-1); 1983 if (evmask == 0) { 1984 evmask = 0x1; /* 'CLEAR' */ 1985 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1986 } 1987 break; 1988 default: 1989 if (evmask == 0 && pmask) { 1990 for (pm = pmask; pm->pm_name; pm++) 1991 evmask |= pm->pm_value; 1992 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1993 } 1994 } 1995 1996 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1997 P4_ESCR_TO_EVENT_MASK(evmask); 1998 1999 return (0); 2000 } 2001 2002 #endif 2003 2004 #if defined(__i386__) 2005 2006 /* 2007 * Pentium style PMCs 2008 */ 2009 2010 static struct pmc_event_alias p5_aliases[] = { 2011 EV_ALIAS("branches", "p5-taken-branches"), 2012 EV_ALIAS("cycles", "tsc"), 2013 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 2014 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 2015 EV_ALIAS("instructions", "p5-instructions-executed"), 2016 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 2017 EV_ALIAS("unhalted-cycles", 2018 "p5-number-of-cycles-not-in-halt-state"), 2019 EV_ALIAS(NULL, NULL) 2020 }; 2021 2022 static int 2023 p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 2024 struct pmc_op_pmcallocate *pmc_config) 2025 { 2026 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 2027 } 2028 2029 /* 2030 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 2031 * and Pentium M CPUs. 2032 */ 2033 2034 static struct pmc_event_alias p6_aliases[] = { 2035 EV_ALIAS("branches", "p6-br-inst-retired"), 2036 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 2037 EV_ALIAS("cycles", "tsc"), 2038 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 2039 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 2040 EV_ALIAS("instructions", "p6-inst-retired"), 2041 EV_ALIAS("interrupts", "p6-hw-int-rx"), 2042 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 2043 EV_ALIAS(NULL, NULL) 2044 }; 2045 2046 #define P6_KW_CMASK "cmask" 2047 #define P6_KW_EDGE "edge" 2048 #define P6_KW_INV "inv" 2049 #define P6_KW_OS "os" 2050 #define P6_KW_UMASK "umask" 2051 #define P6_KW_USR "usr" 2052 2053 static struct pmc_masks p6_mask_mesi[] = { 2054 PMCMASK(m, 0x01), 2055 PMCMASK(e, 0x02), 2056 PMCMASK(s, 0x04), 2057 PMCMASK(i, 0x08), 2058 NULLMASK 2059 }; 2060 2061 static struct pmc_masks p6_mask_mesihw[] = { 2062 PMCMASK(m, 0x01), 2063 PMCMASK(e, 0x02), 2064 PMCMASK(s, 0x04), 2065 PMCMASK(i, 0x08), 2066 PMCMASK(nonhw, 0x00), 2067 PMCMASK(hw, 0x10), 2068 PMCMASK(both, 0x30), 2069 NULLMASK 2070 }; 2071 2072 static struct pmc_masks p6_mask_hw[] = { 2073 PMCMASK(nonhw, 0x00), 2074 PMCMASK(hw, 0x10), 2075 PMCMASK(both, 0x30), 2076 NULLMASK 2077 }; 2078 2079 static struct pmc_masks p6_mask_any[] = { 2080 PMCMASK(self, 0x00), 2081 PMCMASK(any, 0x20), 2082 NULLMASK 2083 }; 2084 2085 static struct pmc_masks p6_mask_ekp[] = { 2086 PMCMASK(nta, 0x00), 2087 PMCMASK(t1, 0x01), 2088 PMCMASK(t2, 0x02), 2089 PMCMASK(wos, 0x03), 2090 NULLMASK 2091 }; 2092 2093 static struct pmc_masks p6_mask_pps[] = { 2094 PMCMASK(packed-and-scalar, 0x00), 2095 PMCMASK(scalar, 0x01), 2096 NULLMASK 2097 }; 2098 2099 static struct pmc_masks p6_mask_mite[] = { 2100 PMCMASK(packed-multiply, 0x01), 2101 PMCMASK(packed-shift, 0x02), 2102 PMCMASK(pack, 0x04), 2103 PMCMASK(unpack, 0x08), 2104 PMCMASK(packed-logical, 0x10), 2105 PMCMASK(packed-arithmetic, 0x20), 2106 NULLMASK 2107 }; 2108 2109 static struct pmc_masks p6_mask_fmt[] = { 2110 PMCMASK(mmxtofp, 0x00), 2111 PMCMASK(fptommx, 0x01), 2112 NULLMASK 2113 }; 2114 2115 static struct pmc_masks p6_mask_sr[] = { 2116 PMCMASK(es, 0x01), 2117 PMCMASK(ds, 0x02), 2118 PMCMASK(fs, 0x04), 2119 PMCMASK(gs, 0x08), 2120 NULLMASK 2121 }; 2122 2123 static struct pmc_masks p6_mask_eet[] = { 2124 PMCMASK(all, 0x00), 2125 PMCMASK(freq, 0x02), 2126 NULLMASK 2127 }; 2128 2129 static struct pmc_masks p6_mask_efur[] = { 2130 PMCMASK(all, 0x00), 2131 PMCMASK(loadop, 0x01), 2132 PMCMASK(stdsta, 0x02), 2133 NULLMASK 2134 }; 2135 2136 static struct pmc_masks p6_mask_essir[] = { 2137 PMCMASK(sse-packed-single, 0x00), 2138 PMCMASK(sse-packed-single-scalar-single, 0x01), 2139 PMCMASK(sse2-packed-double, 0x02), 2140 PMCMASK(sse2-scalar-double, 0x03), 2141 NULLMASK 2142 }; 2143 2144 static struct pmc_masks p6_mask_esscir[] = { 2145 PMCMASK(sse-packed-single, 0x00), 2146 PMCMASK(sse-scalar-single, 0x01), 2147 PMCMASK(sse2-packed-double, 0x02), 2148 PMCMASK(sse2-scalar-double, 0x03), 2149 NULLMASK 2150 }; 2151 2152 /* P6 event parser */ 2153 static int 2154 p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 2155 struct pmc_op_pmcallocate *pmc_config) 2156 { 2157 char *e, *p, *q; 2158 uint64_t evmask; 2159 int count, n; 2160 const struct pmc_masks *pm, *pmask; 2161 2162 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2163 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 2164 2165 evmask = 0; 2166 2167 #define P6MASKSET(M) pmask = p6_mask_ ## M 2168 2169 switch(pe) { 2170 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 2171 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 2172 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 2173 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 2174 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2175 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2176 case PMC_EV_P6_BUS_TRAN_BRD: 2177 case PMC_EV_P6_BUS_TRAN_RFO: 2178 case PMC_EV_P6_BUS_TRANS_WB: 2179 case PMC_EV_P6_BUS_TRAN_IFETCH: 2180 case PMC_EV_P6_BUS_TRAN_INVAL: 2181 case PMC_EV_P6_BUS_TRAN_PWR: 2182 case PMC_EV_P6_BUS_TRANS_P: 2183 case PMC_EV_P6_BUS_TRANS_IO: 2184 case PMC_EV_P6_BUS_TRAN_DEF: 2185 case PMC_EV_P6_BUS_TRAN_BURST: 2186 case PMC_EV_P6_BUS_TRAN_ANY: 2187 case PMC_EV_P6_BUS_TRAN_MEM: 2188 P6MASKSET(any); break; 2189 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2190 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2191 P6MASKSET(ekp); break; 2192 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2193 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2194 P6MASKSET(pps); break; 2195 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2196 P6MASKSET(mite); break; 2197 case PMC_EV_P6_FP_MMX_TRANS: 2198 P6MASKSET(fmt); break; 2199 case PMC_EV_P6_SEG_RENAME_STALLS: 2200 case PMC_EV_P6_SEG_REG_RENAMES: 2201 P6MASKSET(sr); break; 2202 case PMC_EV_P6_EMON_EST_TRANS: 2203 P6MASKSET(eet); break; 2204 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2205 P6MASKSET(efur); break; 2206 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2207 P6MASKSET(essir); break; 2208 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2209 P6MASKSET(esscir); break; 2210 default: 2211 pmask = NULL; 2212 break; 2213 } 2214 2215 /* Pentium M PMCs have a few events with different semantics */ 2216 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2217 if (pe == PMC_EV_P6_L2_LD || 2218 pe == PMC_EV_P6_L2_LINES_IN || 2219 pe == PMC_EV_P6_L2_LINES_OUT) 2220 P6MASKSET(mesihw); 2221 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2222 P6MASKSET(hw); 2223 } 2224 2225 /* Parse additional modifiers if present */ 2226 while ((p = strsep(&ctrspec, ",")) != NULL) { 2227 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2228 q = strchr(p, '='); 2229 if (*++q == '\0') /* skip '=' */ 2230 return (-1); 2231 count = strtol(q, &e, 0); 2232 if (e == q || *e != '\0') 2233 return (-1); 2234 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2235 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2236 P6_EVSEL_TO_CMASK(count); 2237 } else if (KWMATCH(p, P6_KW_EDGE)) { 2238 pmc_config->pm_caps |= PMC_CAP_EDGE; 2239 } else if (KWMATCH(p, P6_KW_INV)) { 2240 pmc_config->pm_caps |= PMC_CAP_INVERT; 2241 } else if (KWMATCH(p, P6_KW_OS)) { 2242 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2243 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2244 evmask = 0; 2245 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2246 return (-1); 2247 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2248 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2249 pe == PMC_EV_P6_BUS_TRAN_BRD || 2250 pe == PMC_EV_P6_BUS_TRAN_RFO || 2251 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2252 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2253 pe == PMC_EV_P6_BUS_TRAN_PWR || 2254 pe == PMC_EV_P6_BUS_TRAN_DEF || 2255 pe == PMC_EV_P6_BUS_TRAN_BURST || 2256 pe == PMC_EV_P6_BUS_TRAN_ANY || 2257 pe == PMC_EV_P6_BUS_TRAN_MEM || 2258 pe == PMC_EV_P6_BUS_TRANS_IO || 2259 pe == PMC_EV_P6_BUS_TRANS_P || 2260 pe == PMC_EV_P6_BUS_TRANS_WB || 2261 pe == PMC_EV_P6_EMON_EST_TRANS || 2262 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2263 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2264 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2265 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2266 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2267 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2268 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2269 pe == PMC_EV_P6_FP_MMX_TRANS) 2270 && (n > 1)) /* Only one mask keyword is allowed. */ 2271 return (-1); 2272 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2273 } else if (KWMATCH(p, P6_KW_USR)) { 2274 pmc_config->pm_caps |= PMC_CAP_USER; 2275 } else 2276 return (-1); 2277 } 2278 2279 /* post processing */ 2280 switch (pe) { 2281 2282 /* 2283 * The following events default to an evmask of 0 2284 */ 2285 2286 /* default => 'self' */ 2287 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2288 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2289 case PMC_EV_P6_BUS_TRAN_BRD: 2290 case PMC_EV_P6_BUS_TRAN_RFO: 2291 case PMC_EV_P6_BUS_TRANS_WB: 2292 case PMC_EV_P6_BUS_TRAN_IFETCH: 2293 case PMC_EV_P6_BUS_TRAN_INVAL: 2294 case PMC_EV_P6_BUS_TRAN_PWR: 2295 case PMC_EV_P6_BUS_TRANS_P: 2296 case PMC_EV_P6_BUS_TRANS_IO: 2297 case PMC_EV_P6_BUS_TRAN_DEF: 2298 case PMC_EV_P6_BUS_TRAN_BURST: 2299 case PMC_EV_P6_BUS_TRAN_ANY: 2300 case PMC_EV_P6_BUS_TRAN_MEM: 2301 2302 /* default => 'nta' */ 2303 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2304 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2305 2306 /* default => 'packed and scalar' */ 2307 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2308 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2309 2310 /* default => 'mmx to fp transitions' */ 2311 case PMC_EV_P6_FP_MMX_TRANS: 2312 2313 /* default => 'SSE Packed Single' */ 2314 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2315 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2316 2317 /* default => 'all fused micro-ops' */ 2318 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2319 2320 /* default => 'all transitions' */ 2321 case PMC_EV_P6_EMON_EST_TRANS: 2322 break; 2323 2324 case PMC_EV_P6_MMX_UOPS_EXEC: 2325 evmask = 0x0F; /* only value allowed */ 2326 break; 2327 2328 default: 2329 /* 2330 * For all other events, set the default event mask 2331 * to a logical OR of all the allowed event mask bits. 2332 */ 2333 if (evmask == 0 && pmask) { 2334 for (pm = pmask; pm->pm_name; pm++) 2335 evmask |= pm->pm_value; 2336 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2337 } 2338 2339 break; 2340 } 2341 2342 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2343 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2344 P6_EVSEL_TO_UMASK(evmask); 2345 2346 return (0); 2347 } 2348 2349 #endif 2350 2351 #if defined(__i386__) || defined(__amd64__) 2352 static int 2353 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2354 struct pmc_op_pmcallocate *pmc_config) 2355 { 2356 if (pe != PMC_EV_TSC_TSC) 2357 return (-1); 2358 2359 /* TSC events must be unqualified. */ 2360 if (ctrspec && *ctrspec != '\0') 2361 return (-1); 2362 2363 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2364 pmc_config->pm_caps |= PMC_CAP_READ; 2365 2366 return (0); 2367 } 2368 #endif 2369 2370 static struct pmc_event_alias generic_aliases[] = { 2371 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 2372 EV_ALIAS(NULL, NULL) 2373 }; 2374 2375 static int 2376 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 2377 struct pmc_op_pmcallocate *pmc_config) 2378 { 2379 (void)ctrspec; 2380 (void)pmc_config; 2381 2382 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 2383 return (-1); 2384 2385 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2386 return (0); 2387 } 2388 2389 #if defined(__arm__) 2390 #if defined(__XSCALE__) 2391 2392 static struct pmc_event_alias xscale_aliases[] = { 2393 EV_ALIAS("branches", "BRANCH_RETIRED"), 2394 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2395 EV_ALIAS("dc-misses", "DC_MISS"), 2396 EV_ALIAS("ic-misses", "IC_MISS"), 2397 EV_ALIAS("instructions", "INSTR_RETIRED"), 2398 EV_ALIAS(NULL, NULL) 2399 }; 2400 static int 2401 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2402 struct pmc_op_pmcallocate *pmc_config __unused) 2403 { 2404 switch (pe) { 2405 default: 2406 break; 2407 } 2408 2409 return (0); 2410 } 2411 #endif 2412 2413 static struct pmc_event_alias armv7_aliases[] = { 2414 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 2415 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 2416 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2417 EV_ALIAS(NULL, NULL) 2418 }; 2419 static int 2420 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2421 struct pmc_op_pmcallocate *pmc_config __unused) 2422 { 2423 switch (pe) { 2424 default: 2425 break; 2426 } 2427 2428 return (0); 2429 } 2430 #endif 2431 2432 #if defined(__mips__) 2433 2434 static struct pmc_event_alias mips24k_aliases[] = { 2435 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2436 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2437 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2438 EV_ALIAS(NULL, NULL) 2439 }; 2440 2441 static struct pmc_event_alias mips74k_aliases[] = { 2442 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2443 EV_ALIAS("branches", "BRANCH_INSNS"), 2444 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"), 2445 EV_ALIAS(NULL, NULL) 2446 }; 2447 2448 static struct pmc_event_alias octeon_aliases[] = { 2449 EV_ALIAS("instructions", "RET"), 2450 EV_ALIAS("branches", "BR"), 2451 EV_ALIAS("branch-mispredicts", "BRMIS"), 2452 EV_ALIAS(NULL, NULL) 2453 }; 2454 2455 #define MIPS_KW_OS "os" 2456 #define MIPS_KW_USR "usr" 2457 #define MIPS_KW_ANYTHREAD "anythread" 2458 2459 static int 2460 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2461 struct pmc_op_pmcallocate *pmc_config __unused) 2462 { 2463 char *p; 2464 2465 (void) pe; 2466 2467 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2468 2469 while ((p = strsep(&ctrspec, ",")) != NULL) { 2470 if (KWMATCH(p, MIPS_KW_OS)) 2471 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2472 else if (KWMATCH(p, MIPS_KW_USR)) 2473 pmc_config->pm_caps |= PMC_CAP_USER; 2474 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 2475 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2476 else 2477 return (-1); 2478 } 2479 2480 return (0); 2481 } 2482 2483 #endif /* __mips__ */ 2484 2485 #if defined(__powerpc__) 2486 2487 static struct pmc_event_alias ppc7450_aliases[] = { 2488 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2489 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2490 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2491 EV_ALIAS(NULL, NULL) 2492 }; 2493 2494 static struct pmc_event_alias ppc970_aliases[] = { 2495 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2496 EV_ALIAS("cycles", "CYCLES"), 2497 EV_ALIAS(NULL, NULL) 2498 }; 2499 2500 static struct pmc_event_alias e500_aliases[] = { 2501 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2502 EV_ALIAS("cycles", "CYCLES"), 2503 EV_ALIAS(NULL, NULL) 2504 }; 2505 2506 #define POWERPC_KW_OS "os" 2507 #define POWERPC_KW_USR "usr" 2508 #define POWERPC_KW_ANYTHREAD "anythread" 2509 2510 static int 2511 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2512 struct pmc_op_pmcallocate *pmc_config __unused) 2513 { 2514 char *p; 2515 2516 (void) pe; 2517 2518 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2519 2520 while ((p = strsep(&ctrspec, ",")) != NULL) { 2521 if (KWMATCH(p, POWERPC_KW_OS)) 2522 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2523 else if (KWMATCH(p, POWERPC_KW_USR)) 2524 pmc_config->pm_caps |= PMC_CAP_USER; 2525 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 2526 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2527 else 2528 return (-1); 2529 } 2530 2531 return (0); 2532 } 2533 2534 #endif /* __powerpc__ */ 2535 2536 2537 /* 2538 * Match an event name `name' with its canonical form. 2539 * 2540 * Matches are case insensitive and spaces, periods, underscores and 2541 * hyphen characters are considered to match each other. 2542 * 2543 * Returns 1 for a match, 0 otherwise. 2544 */ 2545 2546 static int 2547 pmc_match_event_name(const char *name, const char *canonicalname) 2548 { 2549 int cc, nc; 2550 const unsigned char *c, *n; 2551 2552 c = (const unsigned char *) canonicalname; 2553 n = (const unsigned char *) name; 2554 2555 for (; (nc = *n) && (cc = *c); n++, c++) { 2556 2557 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2558 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2559 continue; 2560 2561 if (toupper(nc) == toupper(cc)) 2562 continue; 2563 2564 2565 return (0); 2566 } 2567 2568 if (*n == '\0' && *c == '\0') 2569 return (1); 2570 2571 return (0); 2572 } 2573 2574 /* 2575 * Match an event name against all the event named supported by a 2576 * PMC class. 2577 * 2578 * Returns an event descriptor pointer on match or NULL otherwise. 2579 */ 2580 static const struct pmc_event_descr * 2581 pmc_match_event_class(const char *name, 2582 const struct pmc_class_descr *pcd) 2583 { 2584 size_t n; 2585 const struct pmc_event_descr *ev; 2586 2587 ev = pcd->pm_evc_event_table; 2588 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2589 if (pmc_match_event_name(name, ev->pm_ev_name)) 2590 return (ev); 2591 2592 return (NULL); 2593 } 2594 2595 static int 2596 pmc_mdep_is_compatible_class(enum pmc_class pc) 2597 { 2598 size_t n; 2599 2600 for (n = 0; n < pmc_mdep_class_list_size; n++) 2601 if (pmc_mdep_class_list[n] == pc) 2602 return (1); 2603 return (0); 2604 } 2605 2606 /* 2607 * API entry points 2608 */ 2609 2610 int 2611 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2612 uint32_t flags, int cpu, pmc_id_t *pmcid) 2613 { 2614 size_t n; 2615 int retval; 2616 char *r, *spec_copy; 2617 const char *ctrname; 2618 const struct pmc_event_descr *ev; 2619 const struct pmc_event_alias *alias; 2620 struct pmc_op_pmcallocate pmc_config; 2621 const struct pmc_class_descr *pcd; 2622 2623 spec_copy = NULL; 2624 retval = -1; 2625 2626 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2627 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2628 errno = EINVAL; 2629 goto out; 2630 } 2631 2632 /* replace an event alias with the canonical event specifier */ 2633 if (pmc_mdep_event_aliases) 2634 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2635 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2636 spec_copy = strdup(alias->pm_spec); 2637 break; 2638 } 2639 2640 if (spec_copy == NULL) 2641 spec_copy = strdup(ctrspec); 2642 2643 r = spec_copy; 2644 ctrname = strsep(&r, ","); 2645 2646 /* 2647 * If a explicit class prefix was given by the user, restrict the 2648 * search for the event to the specified PMC class. 2649 */ 2650 ev = NULL; 2651 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2652 pcd = pmc_class_table[n]; 2653 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2654 strncasecmp(ctrname, pcd->pm_evc_name, 2655 pcd->pm_evc_name_size) == 0) { 2656 if ((ev = pmc_match_event_class(ctrname + 2657 pcd->pm_evc_name_size, pcd)) == NULL) { 2658 errno = EINVAL; 2659 goto out; 2660 } 2661 break; 2662 } 2663 } 2664 2665 /* 2666 * Otherwise, search for this event in all compatible PMC 2667 * classes. 2668 */ 2669 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2670 pcd = pmc_class_table[n]; 2671 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2672 ev = pmc_match_event_class(ctrname, pcd); 2673 } 2674 2675 if (ev == NULL) { 2676 errno = EINVAL; 2677 goto out; 2678 } 2679 2680 bzero(&pmc_config, sizeof(pmc_config)); 2681 pmc_config.pm_ev = ev->pm_ev_code; 2682 pmc_config.pm_class = pcd->pm_evc_class; 2683 pmc_config.pm_cpu = cpu; 2684 pmc_config.pm_mode = mode; 2685 pmc_config.pm_flags = flags; 2686 2687 if (PMC_IS_SAMPLING_MODE(mode)) 2688 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2689 2690 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2691 errno = EINVAL; 2692 goto out; 2693 } 2694 2695 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2696 goto out; 2697 2698 *pmcid = pmc_config.pm_pmcid; 2699 2700 retval = 0; 2701 2702 out: 2703 if (spec_copy) 2704 free(spec_copy); 2705 2706 return (retval); 2707 } 2708 2709 int 2710 pmc_attach(pmc_id_t pmc, pid_t pid) 2711 { 2712 struct pmc_op_pmcattach pmc_attach_args; 2713 2714 pmc_attach_args.pm_pmc = pmc; 2715 pmc_attach_args.pm_pid = pid; 2716 2717 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2718 } 2719 2720 int 2721 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2722 { 2723 unsigned int i; 2724 enum pmc_class cl; 2725 2726 cl = PMC_ID_TO_CLASS(pmcid); 2727 for (i = 0; i < cpu_info.pm_nclass; i++) 2728 if (cpu_info.pm_classes[i].pm_class == cl) { 2729 *caps = cpu_info.pm_classes[i].pm_caps; 2730 return (0); 2731 } 2732 errno = EINVAL; 2733 return (-1); 2734 } 2735 2736 int 2737 pmc_configure_logfile(int fd) 2738 { 2739 struct pmc_op_configurelog cla; 2740 2741 cla.pm_logfd = fd; 2742 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2743 return (-1); 2744 return (0); 2745 } 2746 2747 int 2748 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2749 { 2750 if (pmc_syscall == -1) { 2751 errno = ENXIO; 2752 return (-1); 2753 } 2754 2755 *pci = &cpu_info; 2756 return (0); 2757 } 2758 2759 int 2760 pmc_detach(pmc_id_t pmc, pid_t pid) 2761 { 2762 struct pmc_op_pmcattach pmc_detach_args; 2763 2764 pmc_detach_args.pm_pmc = pmc; 2765 pmc_detach_args.pm_pid = pid; 2766 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2767 } 2768 2769 int 2770 pmc_disable(int cpu, int pmc) 2771 { 2772 struct pmc_op_pmcadmin ssa; 2773 2774 ssa.pm_cpu = cpu; 2775 ssa.pm_pmc = pmc; 2776 ssa.pm_state = PMC_STATE_DISABLED; 2777 return (PMC_CALL(PMCADMIN, &ssa)); 2778 } 2779 2780 int 2781 pmc_enable(int cpu, int pmc) 2782 { 2783 struct pmc_op_pmcadmin ssa; 2784 2785 ssa.pm_cpu = cpu; 2786 ssa.pm_pmc = pmc; 2787 ssa.pm_state = PMC_STATE_FREE; 2788 return (PMC_CALL(PMCADMIN, &ssa)); 2789 } 2790 2791 /* 2792 * Return a list of events known to a given PMC class. 'cl' is the 2793 * PMC class identifier, 'eventnames' is the returned list of 'const 2794 * char *' pointers pointing to the names of the events. 'nevents' is 2795 * the number of event name pointers returned. 2796 * 2797 * The space for 'eventnames' is allocated using malloc(3). The caller 2798 * is responsible for freeing this space when done. 2799 */ 2800 int 2801 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2802 int *nevents) 2803 { 2804 int count; 2805 const char **names; 2806 const struct pmc_event_descr *ev; 2807 2808 switch (cl) 2809 { 2810 case PMC_CLASS_IAF: 2811 ev = iaf_event_table; 2812 count = PMC_EVENT_TABLE_SIZE(iaf); 2813 break; 2814 case PMC_CLASS_IAP: 2815 /* 2816 * Return the most appropriate set of event name 2817 * spellings for the current CPU. 2818 */ 2819 switch (cpu_info.pm_cputype) { 2820 default: 2821 case PMC_CPU_INTEL_ATOM: 2822 ev = atom_event_table; 2823 count = PMC_EVENT_TABLE_SIZE(atom); 2824 break; 2825 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2826 ev = atom_silvermont_event_table; 2827 count = PMC_EVENT_TABLE_SIZE(atom_silvermont); 2828 break; 2829 case PMC_CPU_INTEL_CORE: 2830 ev = core_event_table; 2831 count = PMC_EVENT_TABLE_SIZE(core); 2832 break; 2833 case PMC_CPU_INTEL_CORE2: 2834 case PMC_CPU_INTEL_CORE2EXTREME: 2835 ev = core2_event_table; 2836 count = PMC_EVENT_TABLE_SIZE(core2); 2837 break; 2838 case PMC_CPU_INTEL_COREI7: 2839 ev = corei7_event_table; 2840 count = PMC_EVENT_TABLE_SIZE(corei7); 2841 break; 2842 case PMC_CPU_INTEL_NEHALEM_EX: 2843 ev = nehalem_ex_event_table; 2844 count = PMC_EVENT_TABLE_SIZE(nehalem_ex); 2845 break; 2846 case PMC_CPU_INTEL_HASWELL: 2847 ev = haswell_event_table; 2848 count = PMC_EVENT_TABLE_SIZE(haswell); 2849 break; 2850 case PMC_CPU_INTEL_HASWELL_XEON: 2851 ev = haswell_xeon_event_table; 2852 count = PMC_EVENT_TABLE_SIZE(haswell_xeon); 2853 break; 2854 case PMC_CPU_INTEL_IVYBRIDGE: 2855 ev = ivybridge_event_table; 2856 count = PMC_EVENT_TABLE_SIZE(ivybridge); 2857 break; 2858 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2859 ev = ivybridge_xeon_event_table; 2860 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 2861 break; 2862 case PMC_CPU_INTEL_SANDYBRIDGE: 2863 ev = sandybridge_event_table; 2864 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2865 break; 2866 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2867 ev = sandybridge_xeon_event_table; 2868 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 2869 break; 2870 case PMC_CPU_INTEL_WESTMERE: 2871 ev = westmere_event_table; 2872 count = PMC_EVENT_TABLE_SIZE(westmere); 2873 break; 2874 case PMC_CPU_INTEL_WESTMERE_EX: 2875 ev = westmere_ex_event_table; 2876 count = PMC_EVENT_TABLE_SIZE(westmere_ex); 2877 break; 2878 } 2879 break; 2880 case PMC_CLASS_UCF: 2881 ev = ucf_event_table; 2882 count = PMC_EVENT_TABLE_SIZE(ucf); 2883 break; 2884 case PMC_CLASS_UCP: 2885 /* 2886 * Return the most appropriate set of event name 2887 * spellings for the current CPU. 2888 */ 2889 switch (cpu_info.pm_cputype) { 2890 default: 2891 case PMC_CPU_INTEL_COREI7: 2892 ev = corei7uc_event_table; 2893 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2894 break; 2895 case PMC_CPU_INTEL_HASWELL: 2896 ev = haswelluc_event_table; 2897 count = PMC_EVENT_TABLE_SIZE(haswelluc); 2898 break; 2899 case PMC_CPU_INTEL_SANDYBRIDGE: 2900 ev = sandybridgeuc_event_table; 2901 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2902 break; 2903 case PMC_CPU_INTEL_WESTMERE: 2904 ev = westmereuc_event_table; 2905 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2906 break; 2907 } 2908 break; 2909 case PMC_CLASS_TSC: 2910 ev = tsc_event_table; 2911 count = PMC_EVENT_TABLE_SIZE(tsc); 2912 break; 2913 case PMC_CLASS_K7: 2914 ev = k7_event_table; 2915 count = PMC_EVENT_TABLE_SIZE(k7); 2916 break; 2917 case PMC_CLASS_K8: 2918 ev = k8_event_table; 2919 count = PMC_EVENT_TABLE_SIZE(k8); 2920 break; 2921 case PMC_CLASS_P4: 2922 ev = p4_event_table; 2923 count = PMC_EVENT_TABLE_SIZE(p4); 2924 break; 2925 case PMC_CLASS_P5: 2926 ev = p5_event_table; 2927 count = PMC_EVENT_TABLE_SIZE(p5); 2928 break; 2929 case PMC_CLASS_P6: 2930 ev = p6_event_table; 2931 count = PMC_EVENT_TABLE_SIZE(p6); 2932 break; 2933 case PMC_CLASS_XSCALE: 2934 ev = xscale_event_table; 2935 count = PMC_EVENT_TABLE_SIZE(xscale); 2936 break; 2937 case PMC_CLASS_ARMV7: 2938 ev = armv7_event_table; 2939 count = PMC_EVENT_TABLE_SIZE(armv7); 2940 break; 2941 case PMC_CLASS_MIPS24K: 2942 ev = mips24k_event_table; 2943 count = PMC_EVENT_TABLE_SIZE(mips24k); 2944 break; 2945 case PMC_CLASS_MIPS74K: 2946 ev = mips74k_event_table; 2947 count = PMC_EVENT_TABLE_SIZE(mips74k); 2948 break; 2949 case PMC_CLASS_OCTEON: 2950 ev = octeon_event_table; 2951 count = PMC_EVENT_TABLE_SIZE(octeon); 2952 break; 2953 case PMC_CLASS_PPC7450: 2954 ev = ppc7450_event_table; 2955 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2956 break; 2957 case PMC_CLASS_PPC970: 2958 ev = ppc970_event_table; 2959 count = PMC_EVENT_TABLE_SIZE(ppc970); 2960 break; 2961 case PMC_CLASS_E500: 2962 ev = e500_event_table; 2963 count = PMC_EVENT_TABLE_SIZE(e500); 2964 break; 2965 case PMC_CLASS_SOFT: 2966 ev = soft_event_table; 2967 count = soft_event_info.pm_nevent; 2968 break; 2969 default: 2970 errno = EINVAL; 2971 return (-1); 2972 } 2973 2974 if ((names = malloc(count * sizeof(const char *))) == NULL) 2975 return (-1); 2976 2977 *eventnames = names; 2978 *nevents = count; 2979 2980 for (;count--; ev++, names++) 2981 *names = ev->pm_ev_name; 2982 2983 return (0); 2984 } 2985 2986 int 2987 pmc_flush_logfile(void) 2988 { 2989 return (PMC_CALL(FLUSHLOG,0)); 2990 } 2991 2992 int 2993 pmc_close_logfile(void) 2994 { 2995 return (PMC_CALL(CLOSELOG,0)); 2996 } 2997 2998 int 2999 pmc_get_driver_stats(struct pmc_driverstats *ds) 3000 { 3001 struct pmc_op_getdriverstats gms; 3002 3003 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 3004 return (-1); 3005 3006 /* copy out fields in the current userland<->library interface */ 3007 ds->pm_intr_ignored = gms.pm_intr_ignored; 3008 ds->pm_intr_processed = gms.pm_intr_processed; 3009 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 3010 ds->pm_syscalls = gms.pm_syscalls; 3011 ds->pm_syscall_errors = gms.pm_syscall_errors; 3012 ds->pm_buffer_requests = gms.pm_buffer_requests; 3013 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 3014 ds->pm_log_sweeps = gms.pm_log_sweeps; 3015 return (0); 3016 } 3017 3018 int 3019 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 3020 { 3021 struct pmc_op_getmsr gm; 3022 3023 gm.pm_pmcid = pmc; 3024 if (PMC_CALL(PMCGETMSR, &gm) < 0) 3025 return (-1); 3026 *msr = gm.pm_msr; 3027 return (0); 3028 } 3029 3030 int 3031 pmc_init(void) 3032 { 3033 int error, pmc_mod_id; 3034 unsigned int n; 3035 uint32_t abi_version; 3036 struct module_stat pmc_modstat; 3037 struct pmc_op_getcpuinfo op_cpu_info; 3038 #if defined(__amd64__) || defined(__i386__) 3039 int cpu_has_iaf_counters; 3040 unsigned int t; 3041 #endif 3042 3043 if (pmc_syscall != -1) /* already inited */ 3044 return (0); 3045 3046 /* retrieve the system call number from the KLD */ 3047 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 3048 return (-1); 3049 3050 pmc_modstat.version = sizeof(struct module_stat); 3051 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 3052 return (-1); 3053 3054 pmc_syscall = pmc_modstat.data.intval; 3055 3056 /* check the kernel module's ABI against our compiled-in version */ 3057 abi_version = PMC_VERSION; 3058 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 3059 return (pmc_syscall = -1); 3060 3061 /* ignore patch & minor numbers for the comparision */ 3062 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 3063 errno = EPROGMISMATCH; 3064 return (pmc_syscall = -1); 3065 } 3066 3067 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 3068 return (pmc_syscall = -1); 3069 3070 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 3071 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 3072 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 3073 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 3074 for (n = 0; n < cpu_info.pm_nclass; n++) 3075 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 3076 3077 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 3078 sizeof(struct pmc_class_descr *)); 3079 3080 if (pmc_class_table == NULL) 3081 return (-1); 3082 3083 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 3084 pmc_class_table[n] = NULL; 3085 3086 /* 3087 * Get soft events list. 3088 */ 3089 soft_event_info.pm_class = PMC_CLASS_SOFT; 3090 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 3091 return (pmc_syscall = -1); 3092 3093 /* Map soft events to static list. */ 3094 for (n = 0; n < soft_event_info.pm_nevent; n++) { 3095 soft_event_table[n].pm_ev_name = 3096 soft_event_info.pm_events[n].pm_ev_name; 3097 soft_event_table[n].pm_ev_code = 3098 soft_event_info.pm_events[n].pm_ev_code; 3099 } 3100 soft_class_table_descr.pm_evc_event_table_size = \ 3101 soft_event_info.pm_nevent; 3102 soft_class_table_descr.pm_evc_event_table = \ 3103 soft_event_table; 3104 3105 /* 3106 * Fill in the class table. 3107 */ 3108 n = 0; 3109 3110 /* Fill soft events information. */ 3111 pmc_class_table[n++] = &soft_class_table_descr; 3112 #if defined(__amd64__) || defined(__i386__) 3113 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 3114 pmc_class_table[n++] = &tsc_class_table_descr; 3115 3116 /* 3117 * Check if this CPU has fixed function counters. 3118 */ 3119 cpu_has_iaf_counters = 0; 3120 for (t = 0; t < cpu_info.pm_nclass; t++) 3121 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 3122 cpu_info.pm_classes[t].pm_num > 0) 3123 cpu_has_iaf_counters = 1; 3124 #endif 3125 3126 #define PMC_MDEP_INIT(C) do { \ 3127 pmc_mdep_event_aliases = C##_aliases; \ 3128 pmc_mdep_class_list = C##_pmc_classes; \ 3129 pmc_mdep_class_list_size = \ 3130 PMC_TABLE_SIZE(C##_pmc_classes); \ 3131 } while (0) 3132 3133 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 3134 PMC_MDEP_INIT(C); \ 3135 pmc_class_table[n++] = &iaf_class_table_descr; \ 3136 if (!cpu_has_iaf_counters) \ 3137 pmc_mdep_event_aliases = \ 3138 C##_aliases_without_iaf; \ 3139 pmc_class_table[n] = &C##_class_table_descr; \ 3140 } while (0) 3141 3142 /* Configure the event name parser. */ 3143 switch (cpu_info.pm_cputype) { 3144 #if defined(__i386__) 3145 case PMC_CPU_AMD_K7: 3146 PMC_MDEP_INIT(k7); 3147 pmc_class_table[n] = &k7_class_table_descr; 3148 break; 3149 case PMC_CPU_INTEL_P5: 3150 PMC_MDEP_INIT(p5); 3151 pmc_class_table[n] = &p5_class_table_descr; 3152 break; 3153 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 3154 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 3155 case PMC_CPU_INTEL_PIII: 3156 case PMC_CPU_INTEL_PM: 3157 PMC_MDEP_INIT(p6); 3158 pmc_class_table[n] = &p6_class_table_descr; 3159 break; 3160 #endif 3161 #if defined(__amd64__) || defined(__i386__) 3162 case PMC_CPU_AMD_K8: 3163 PMC_MDEP_INIT(k8); 3164 pmc_class_table[n] = &k8_class_table_descr; 3165 break; 3166 case PMC_CPU_INTEL_ATOM: 3167 PMC_MDEP_INIT_INTEL_V2(atom); 3168 break; 3169 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3170 PMC_MDEP_INIT_INTEL_V2(atom_silvermont); 3171 break; 3172 case PMC_CPU_INTEL_CORE: 3173 PMC_MDEP_INIT(core); 3174 pmc_class_table[n] = &core_class_table_descr; 3175 break; 3176 case PMC_CPU_INTEL_CORE2: 3177 case PMC_CPU_INTEL_CORE2EXTREME: 3178 PMC_MDEP_INIT_INTEL_V2(core2); 3179 break; 3180 case PMC_CPU_INTEL_COREI7: 3181 pmc_class_table[n++] = &ucf_class_table_descr; 3182 pmc_class_table[n++] = &corei7uc_class_table_descr; 3183 PMC_MDEP_INIT_INTEL_V2(corei7); 3184 break; 3185 case PMC_CPU_INTEL_NEHALEM_EX: 3186 PMC_MDEP_INIT_INTEL_V2(nehalem_ex); 3187 break; 3188 case PMC_CPU_INTEL_HASWELL: 3189 pmc_class_table[n++] = &ucf_class_table_descr; 3190 pmc_class_table[n++] = &haswelluc_class_table_descr; 3191 PMC_MDEP_INIT_INTEL_V2(haswell); 3192 break; 3193 case PMC_CPU_INTEL_HASWELL_XEON: 3194 PMC_MDEP_INIT_INTEL_V2(haswell_xeon); 3195 break; 3196 case PMC_CPU_INTEL_IVYBRIDGE: 3197 PMC_MDEP_INIT_INTEL_V2(ivybridge); 3198 break; 3199 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3200 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); 3201 break; 3202 case PMC_CPU_INTEL_SANDYBRIDGE: 3203 pmc_class_table[n++] = &ucf_class_table_descr; 3204 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 3205 PMC_MDEP_INIT_INTEL_V2(sandybridge); 3206 break; 3207 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3208 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); 3209 break; 3210 case PMC_CPU_INTEL_WESTMERE: 3211 pmc_class_table[n++] = &ucf_class_table_descr; 3212 pmc_class_table[n++] = &westmereuc_class_table_descr; 3213 PMC_MDEP_INIT_INTEL_V2(westmere); 3214 break; 3215 case PMC_CPU_INTEL_WESTMERE_EX: 3216 PMC_MDEP_INIT_INTEL_V2(westmere_ex); 3217 break; 3218 case PMC_CPU_INTEL_PIV: 3219 PMC_MDEP_INIT(p4); 3220 pmc_class_table[n] = &p4_class_table_descr; 3221 break; 3222 #endif 3223 case PMC_CPU_GENERIC: 3224 PMC_MDEP_INIT(generic); 3225 break; 3226 #if defined(__arm__) 3227 #if defined(__XSCALE__) 3228 case PMC_CPU_INTEL_XSCALE: 3229 PMC_MDEP_INIT(xscale); 3230 pmc_class_table[n] = &xscale_class_table_descr; 3231 break; 3232 #endif 3233 case PMC_CPU_ARMV7: 3234 PMC_MDEP_INIT(armv7); 3235 pmc_class_table[n] = &armv7_class_table_descr; 3236 break; 3237 #endif 3238 #if defined(__mips__) 3239 case PMC_CPU_MIPS_24K: 3240 PMC_MDEP_INIT(mips24k); 3241 pmc_class_table[n] = &mips24k_class_table_descr; 3242 break; 3243 case PMC_CPU_MIPS_74K: 3244 PMC_MDEP_INIT(mips74k); 3245 pmc_class_table[n] = &mips74k_class_table_descr; 3246 break; 3247 case PMC_CPU_MIPS_OCTEON: 3248 PMC_MDEP_INIT(octeon); 3249 pmc_class_table[n] = &octeon_class_table_descr; 3250 break; 3251 #endif /* __mips__ */ 3252 #if defined(__powerpc__) 3253 case PMC_CPU_PPC_7450: 3254 PMC_MDEP_INIT(ppc7450); 3255 pmc_class_table[n] = &ppc7450_class_table_descr; 3256 break; 3257 case PMC_CPU_PPC_970: 3258 PMC_MDEP_INIT(ppc970); 3259 pmc_class_table[n] = &ppc970_class_table_descr; 3260 break; 3261 case PMC_CPU_PPC_E500: 3262 PMC_MDEP_INIT(e500); 3263 pmc_class_table[n] = &e500_class_table_descr; 3264 break; 3265 #endif 3266 default: 3267 /* 3268 * Some kind of CPU this version of the library knows nothing 3269 * about. This shouldn't happen since the abi version check 3270 * should have caught this. 3271 */ 3272 errno = ENXIO; 3273 return (pmc_syscall = -1); 3274 } 3275 3276 return (0); 3277 } 3278 3279 const char * 3280 pmc_name_of_capability(enum pmc_caps cap) 3281 { 3282 int i; 3283 3284 /* 3285 * 'cap' should have a single bit set and should be in 3286 * range. 3287 */ 3288 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 3289 cap > PMC_CAP_LAST) { 3290 errno = EINVAL; 3291 return (NULL); 3292 } 3293 3294 i = ffs(cap); 3295 return (pmc_capability_names[i - 1]); 3296 } 3297 3298 const char * 3299 pmc_name_of_class(enum pmc_class pc) 3300 { 3301 if ((int) pc >= PMC_CLASS_FIRST && 3302 pc <= PMC_CLASS_LAST) 3303 return (pmc_class_names[pc]); 3304 3305 errno = EINVAL; 3306 return (NULL); 3307 } 3308 3309 const char * 3310 pmc_name_of_cputype(enum pmc_cputype cp) 3311 { 3312 size_t n; 3313 3314 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 3315 if (cp == pmc_cputype_names[n].pm_cputype) 3316 return (pmc_cputype_names[n].pm_name); 3317 3318 errno = EINVAL; 3319 return (NULL); 3320 } 3321 3322 const char * 3323 pmc_name_of_disposition(enum pmc_disp pd) 3324 { 3325 if ((int) pd >= PMC_DISP_FIRST && 3326 pd <= PMC_DISP_LAST) 3327 return (pmc_disposition_names[pd]); 3328 3329 errno = EINVAL; 3330 return (NULL); 3331 } 3332 3333 const char * 3334 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 3335 { 3336 const struct pmc_event_descr *ev, *evfence; 3337 3338 ev = evfence = NULL; 3339 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 3340 ev = iaf_event_table; 3341 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 3342 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 3343 switch (cpu) { 3344 case PMC_CPU_INTEL_ATOM: 3345 ev = atom_event_table; 3346 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 3347 break; 3348 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3349 ev = atom_silvermont_event_table; 3350 evfence = atom_silvermont_event_table + 3351 PMC_EVENT_TABLE_SIZE(atom_silvermont); 3352 break; 3353 case PMC_CPU_INTEL_CORE: 3354 ev = core_event_table; 3355 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 3356 break; 3357 case PMC_CPU_INTEL_CORE2: 3358 case PMC_CPU_INTEL_CORE2EXTREME: 3359 ev = core2_event_table; 3360 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 3361 break; 3362 case PMC_CPU_INTEL_COREI7: 3363 ev = corei7_event_table; 3364 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 3365 break; 3366 case PMC_CPU_INTEL_NEHALEM_EX: 3367 ev = nehalem_ex_event_table; 3368 evfence = nehalem_ex_event_table + 3369 PMC_EVENT_TABLE_SIZE(nehalem_ex); 3370 break; 3371 case PMC_CPU_INTEL_HASWELL: 3372 ev = haswell_event_table; 3373 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); 3374 break; 3375 case PMC_CPU_INTEL_HASWELL_XEON: 3376 ev = haswell_xeon_event_table; 3377 evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon); 3378 break; 3379 3380 case PMC_CPU_INTEL_IVYBRIDGE: 3381 ev = ivybridge_event_table; 3382 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); 3383 break; 3384 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3385 ev = ivybridge_xeon_event_table; 3386 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 3387 break; 3388 case PMC_CPU_INTEL_SANDYBRIDGE: 3389 ev = sandybridge_event_table; 3390 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 3391 break; 3392 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3393 ev = sandybridge_xeon_event_table; 3394 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 3395 break; 3396 case PMC_CPU_INTEL_WESTMERE: 3397 ev = westmere_event_table; 3398 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 3399 break; 3400 case PMC_CPU_INTEL_WESTMERE_EX: 3401 ev = westmere_ex_event_table; 3402 evfence = westmere_ex_event_table + 3403 PMC_EVENT_TABLE_SIZE(westmere_ex); 3404 break; 3405 default: /* Unknown CPU type. */ 3406 break; 3407 } 3408 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 3409 ev = ucf_event_table; 3410 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 3411 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 3412 switch (cpu) { 3413 case PMC_CPU_INTEL_COREI7: 3414 ev = corei7uc_event_table; 3415 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 3416 break; 3417 case PMC_CPU_INTEL_SANDYBRIDGE: 3418 ev = sandybridgeuc_event_table; 3419 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 3420 break; 3421 case PMC_CPU_INTEL_WESTMERE: 3422 ev = westmereuc_event_table; 3423 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 3424 break; 3425 default: /* Unknown CPU type. */ 3426 break; 3427 } 3428 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3429 ev = k7_event_table; 3430 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3431 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3432 ev = k8_event_table; 3433 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3434 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3435 ev = p4_event_table; 3436 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3437 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3438 ev = p5_event_table; 3439 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3440 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3441 ev = p6_event_table; 3442 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3443 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3444 ev = xscale_event_table; 3445 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3446 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 3447 ev = armv7_event_table; 3448 evfence = armv7_event_table + PMC_EVENT_TABLE_SIZE(armv7); 3449 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3450 ev = mips24k_event_table; 3451 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 3452 } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { 3453 ev = mips74k_event_table; 3454 evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); 3455 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 3456 ev = octeon_event_table; 3457 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 3458 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3459 ev = ppc7450_event_table; 3460 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 3461 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 3462 ev = ppc970_event_table; 3463 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 3464 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { 3465 ev = e500_event_table; 3466 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); 3467 } else if (pe == PMC_EV_TSC_TSC) { 3468 ev = tsc_event_table; 3469 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3470 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 3471 ev = soft_event_table; 3472 evfence = soft_event_table + soft_event_info.pm_nevent; 3473 } 3474 3475 for (; ev != evfence; ev++) 3476 if (pe == ev->pm_ev_code) 3477 return (ev->pm_ev_name); 3478 3479 return (NULL); 3480 } 3481 3482 const char * 3483 pmc_name_of_event(enum pmc_event pe) 3484 { 3485 const char *n; 3486 3487 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3488 return (n); 3489 3490 errno = EINVAL; 3491 return (NULL); 3492 } 3493 3494 const char * 3495 pmc_name_of_mode(enum pmc_mode pm) 3496 { 3497 if ((int) pm >= PMC_MODE_FIRST && 3498 pm <= PMC_MODE_LAST) 3499 return (pmc_mode_names[pm]); 3500 3501 errno = EINVAL; 3502 return (NULL); 3503 } 3504 3505 const char * 3506 pmc_name_of_state(enum pmc_state ps) 3507 { 3508 if ((int) ps >= PMC_STATE_FIRST && 3509 ps <= PMC_STATE_LAST) 3510 return (pmc_state_names[ps]); 3511 3512 errno = EINVAL; 3513 return (NULL); 3514 } 3515 3516 int 3517 pmc_ncpu(void) 3518 { 3519 if (pmc_syscall == -1) { 3520 errno = ENXIO; 3521 return (-1); 3522 } 3523 3524 return (cpu_info.pm_ncpu); 3525 } 3526 3527 int 3528 pmc_npmc(int cpu) 3529 { 3530 if (pmc_syscall == -1) { 3531 errno = ENXIO; 3532 return (-1); 3533 } 3534 3535 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3536 errno = EINVAL; 3537 return (-1); 3538 } 3539 3540 return (cpu_info.pm_npmc); 3541 } 3542 3543 int 3544 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3545 { 3546 int nbytes, npmc; 3547 struct pmc_op_getpmcinfo *pmci; 3548 3549 if ((npmc = pmc_npmc(cpu)) < 0) 3550 return (-1); 3551 3552 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3553 npmc * sizeof(struct pmc_info); 3554 3555 if ((pmci = calloc(1, nbytes)) == NULL) 3556 return (-1); 3557 3558 pmci->pm_cpu = cpu; 3559 3560 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3561 free(pmci); 3562 return (-1); 3563 } 3564 3565 /* kernel<->library, library<->userland interfaces are identical */ 3566 *ppmci = (struct pmc_pmcinfo *) pmci; 3567 return (0); 3568 } 3569 3570 int 3571 pmc_read(pmc_id_t pmc, pmc_value_t *value) 3572 { 3573 struct pmc_op_pmcrw pmc_read_op; 3574 3575 pmc_read_op.pm_pmcid = pmc; 3576 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3577 pmc_read_op.pm_value = -1; 3578 3579 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3580 return (-1); 3581 3582 *value = pmc_read_op.pm_value; 3583 return (0); 3584 } 3585 3586 int 3587 pmc_release(pmc_id_t pmc) 3588 { 3589 struct pmc_op_simple pmc_release_args; 3590 3591 pmc_release_args.pm_pmcid = pmc; 3592 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3593 } 3594 3595 int 3596 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3597 { 3598 struct pmc_op_pmcrw pmc_rw_op; 3599 3600 pmc_rw_op.pm_pmcid = pmc; 3601 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3602 pmc_rw_op.pm_value = newvalue; 3603 3604 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3605 return (-1); 3606 3607 *oldvaluep = pmc_rw_op.pm_value; 3608 return (0); 3609 } 3610 3611 int 3612 pmc_set(pmc_id_t pmc, pmc_value_t value) 3613 { 3614 struct pmc_op_pmcsetcount sc; 3615 3616 sc.pm_pmcid = pmc; 3617 sc.pm_count = value; 3618 3619 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3620 return (-1); 3621 return (0); 3622 } 3623 3624 int 3625 pmc_start(pmc_id_t pmc) 3626 { 3627 struct pmc_op_simple pmc_start_args; 3628 3629 pmc_start_args.pm_pmcid = pmc; 3630 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3631 } 3632 3633 int 3634 pmc_stop(pmc_id_t pmc) 3635 { 3636 struct pmc_op_simple pmc_stop_args; 3637 3638 pmc_stop_args.pm_pmcid = pmc; 3639 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3640 } 3641 3642 int 3643 pmc_width(pmc_id_t pmcid, uint32_t *width) 3644 { 3645 unsigned int i; 3646 enum pmc_class cl; 3647 3648 cl = PMC_ID_TO_CLASS(pmcid); 3649 for (i = 0; i < cpu_info.pm_nclass; i++) 3650 if (cpu_info.pm_classes[i].pm_class == cl) { 3651 *width = cpu_info.pm_classes[i].pm_width; 3652 return (0); 3653 } 3654 errno = EINVAL; 3655 return (-1); 3656 } 3657 3658 int 3659 pmc_write(pmc_id_t pmc, pmc_value_t value) 3660 { 3661 struct pmc_op_pmcrw pmc_write_op; 3662 3663 pmc_write_op.pm_pmcid = pmc; 3664 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3665 pmc_write_op.pm_value = value; 3666 return (PMC_CALL(PMCRW, &pmc_write_op)); 3667 } 3668 3669 int 3670 pmc_writelog(uint32_t userdata) 3671 { 3672 struct pmc_op_writelog wl; 3673 3674 wl.pm_userdata = userdata; 3675 return (PMC_CALL(WRITELOG, &wl)); 3676 } 3677