1 /*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/pmc.h> 34 #include <sys/syscall.h> 35 36 #include <ctype.h> 37 #include <errno.h> 38 #include <fcntl.h> 39 #include <pmc.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <unistd.h> 45 46 #include "libpmcinternal.h" 47 48 /* Function prototypes */ 49 #if defined(__i386__) 50 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 51 struct pmc_op_pmcallocate *_pmc_config); 52 #endif 53 #if defined(__amd64__) || defined(__i386__) 54 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 57 struct pmc_op_pmcallocate *_pmc_config); 58 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 61 struct pmc_op_pmcallocate *_pmc_config); 62 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 63 struct pmc_op_pmcallocate *_pmc_config); 64 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 65 struct pmc_op_pmcallocate *_pmc_config); 66 #endif 67 #if defined(__i386__) 68 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 69 struct pmc_op_pmcallocate *_pmc_config); 70 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72 #endif 73 #if defined(__amd64__) || defined(__i386__) 74 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 #endif 77 #if defined(__arm__) 78 #if defined(__XSCALE__) 79 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 80 struct pmc_op_pmcallocate *_pmc_config); 81 #endif 82 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84 #endif 85 #if defined(__mips__) 86 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 87 struct pmc_op_pmcallocate *_pmc_config); 88 #endif /* __mips__ */ 89 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 90 struct pmc_op_pmcallocate *_pmc_config); 91 92 #if defined(__powerpc__) 93 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 94 struct pmc_op_pmcallocate *_pmc_config); 95 #endif /* __powerpc__ */ 96 97 #define PMC_CALL(cmd, params) \ 98 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 99 100 /* 101 * Event aliases provide a way for the user to ask for generic events 102 * like "cache-misses", or "instructions-retired". These aliases are 103 * mapped to the appropriate canonical event descriptions using a 104 * lookup table. 105 */ 106 struct pmc_event_alias { 107 const char *pm_alias; 108 const char *pm_spec; 109 }; 110 111 static const struct pmc_event_alias *pmc_mdep_event_aliases; 112 113 /* 114 * The pmc_event_descr structure maps symbolic names known to the user 115 * to integer codes used by the PMC KLD. 116 */ 117 struct pmc_event_descr { 118 const char *pm_ev_name; 119 enum pmc_event pm_ev_code; 120 }; 121 122 /* 123 * The pmc_class_descr structure maps class name prefixes for 124 * event names to event tables and other PMC class data. 125 */ 126 struct pmc_class_descr { 127 const char *pm_evc_name; 128 size_t pm_evc_name_size; 129 enum pmc_class pm_evc_class; 130 const struct pmc_event_descr *pm_evc_event_table; 131 size_t pm_evc_event_table_size; 132 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 133 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 134 }; 135 136 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 137 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 138 139 #undef __PMC_EV 140 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 141 142 /* 143 * PMC_CLASSDEP_TABLE(NAME, CLASS) 144 * 145 * Define a table mapping event names and aliases to HWPMC event IDs. 146 */ 147 #define PMC_CLASSDEP_TABLE(N, C) \ 148 static const struct pmc_event_descr N##_event_table[] = \ 149 { \ 150 __PMC_EV_##C() \ 151 } 152 153 PMC_CLASSDEP_TABLE(iaf, IAF); 154 PMC_CLASSDEP_TABLE(k7, K7); 155 PMC_CLASSDEP_TABLE(k8, K8); 156 PMC_CLASSDEP_TABLE(p4, P4); 157 PMC_CLASSDEP_TABLE(p5, P5); 158 PMC_CLASSDEP_TABLE(p6, P6); 159 PMC_CLASSDEP_TABLE(xscale, XSCALE); 160 PMC_CLASSDEP_TABLE(armv7, ARMV7); 161 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 162 PMC_CLASSDEP_TABLE(octeon, OCTEON); 163 PMC_CLASSDEP_TABLE(ucf, UCF); 164 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 165 PMC_CLASSDEP_TABLE(ppc970, PPC970); 166 167 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 168 169 #undef __PMC_EV_ALIAS 170 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 171 172 static const struct pmc_event_descr atom_event_table[] = 173 { 174 __PMC_EV_ALIAS_ATOM() 175 }; 176 177 static const struct pmc_event_descr atom_silvermont_event_table[] = 178 { 179 __PMC_EV_ALIAS_ATOM_SILVERMONT() 180 }; 181 182 static const struct pmc_event_descr core_event_table[] = 183 { 184 __PMC_EV_ALIAS_CORE() 185 }; 186 187 188 static const struct pmc_event_descr core2_event_table[] = 189 { 190 __PMC_EV_ALIAS_CORE2() 191 }; 192 193 static const struct pmc_event_descr corei7_event_table[] = 194 { 195 __PMC_EV_ALIAS_COREI7() 196 }; 197 198 static const struct pmc_event_descr nehalem_ex_event_table[] = 199 { 200 __PMC_EV_ALIAS_COREI7() 201 }; 202 203 static const struct pmc_event_descr haswell_event_table[] = 204 { 205 __PMC_EV_ALIAS_HASWELL() 206 }; 207 208 static const struct pmc_event_descr haswell_xeon_event_table[] = 209 { 210 __PMC_EV_ALIAS_HASWELL_XEON() 211 }; 212 213 214 static const struct pmc_event_descr ivybridge_event_table[] = 215 { 216 __PMC_EV_ALIAS_IVYBRIDGE() 217 }; 218 219 static const struct pmc_event_descr ivybridge_xeon_event_table[] = 220 { 221 __PMC_EV_ALIAS_IVYBRIDGE_XEON() 222 }; 223 224 static const struct pmc_event_descr sandybridge_event_table[] = 225 { 226 __PMC_EV_ALIAS_SANDYBRIDGE() 227 }; 228 229 static const struct pmc_event_descr sandybridge_xeon_event_table[] = 230 { 231 __PMC_EV_ALIAS_SANDYBRIDGE_XEON() 232 }; 233 234 static const struct pmc_event_descr westmere_event_table[] = 235 { 236 __PMC_EV_ALIAS_WESTMERE() 237 }; 238 239 static const struct pmc_event_descr westmere_ex_event_table[] = 240 { 241 __PMC_EV_ALIAS_WESTMERE() 242 }; 243 244 static const struct pmc_event_descr corei7uc_event_table[] = 245 { 246 __PMC_EV_ALIAS_COREI7UC() 247 }; 248 249 static const struct pmc_event_descr haswelluc_event_table[] = 250 { 251 __PMC_EV_ALIAS_HASWELLUC() 252 }; 253 254 static const struct pmc_event_descr sandybridgeuc_event_table[] = 255 { 256 __PMC_EV_ALIAS_SANDYBRIDGEUC() 257 }; 258 259 static const struct pmc_event_descr westmereuc_event_table[] = 260 { 261 __PMC_EV_ALIAS_WESTMEREUC() 262 }; 263 264 /* 265 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 266 * 267 * Map a CPU to the PMC classes it supports. 268 */ 269 #define PMC_MDEP_TABLE(N,C,...) \ 270 static const enum pmc_class N##_pmc_classes[] = { \ 271 PMC_CLASS_##C, __VA_ARGS__ \ 272 } 273 274 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 275 PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 276 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); 277 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 278 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 279 PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 280 PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 281 PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 282 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 283 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 284 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 285 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 286 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 287 PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 288 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); 289 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 290 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); 291 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); 292 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); 293 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 294 PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 295 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 296 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 297 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450); 298 PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970); 299 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 300 301 static const struct pmc_event_descr tsc_event_table[] = 302 { 303 __PMC_EV_TSC() 304 }; 305 306 #undef PMC_CLASS_TABLE_DESC 307 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 308 static const struct pmc_class_descr NAME##_class_table_descr = \ 309 { \ 310 .pm_evc_name = #CLASS "-", \ 311 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 312 .pm_evc_class = PMC_CLASS_##CLASS , \ 313 .pm_evc_event_table = EVENTS##_event_table , \ 314 .pm_evc_event_table_size = \ 315 PMC_EVENT_TABLE_SIZE(EVENTS), \ 316 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 317 } 318 319 #if defined(__i386__) || defined(__amd64__) 320 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 321 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 322 PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); 323 PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 324 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 325 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 326 PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); 327 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); 328 PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell, iap); 329 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); 330 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); 331 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 332 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); 333 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 334 PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); 335 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 336 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 337 PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); 338 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 339 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 340 #endif 341 #if defined(__i386__) 342 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 343 #endif 344 #if defined(__i386__) || defined(__amd64__) 345 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 346 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 347 #endif 348 #if defined(__i386__) 349 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 350 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 351 #endif 352 #if defined(__i386__) || defined(__amd64__) 353 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 354 #endif 355 #if defined(__arm__) 356 #if defined(__XSCALE__) 357 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 358 #endif 359 PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7); 360 #endif 361 #if defined(__mips__) 362 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 363 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 364 #endif /* __mips__ */ 365 #if defined(__powerpc__) 366 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 367 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 368 #endif 369 370 static struct pmc_class_descr soft_class_table_descr = 371 { 372 .pm_evc_name = "SOFT-", 373 .pm_evc_name_size = sizeof("SOFT-") - 1, 374 .pm_evc_class = PMC_CLASS_SOFT, 375 .pm_evc_event_table = NULL, 376 .pm_evc_event_table_size = 0, 377 .pm_evc_allocate_pmc = soft_allocate_pmc 378 }; 379 380 #undef PMC_CLASS_TABLE_DESC 381 382 static const struct pmc_class_descr **pmc_class_table; 383 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 384 385 static const enum pmc_class *pmc_mdep_class_list; 386 static size_t pmc_mdep_class_list_size; 387 388 /* 389 * Mapping tables, mapping enumeration values to human readable 390 * strings. 391 */ 392 393 static const char * pmc_capability_names[] = { 394 #undef __PMC_CAP 395 #define __PMC_CAP(N,V,D) #N , 396 __PMC_CAPS() 397 }; 398 399 static const char * pmc_class_names[] = { 400 #undef __PMC_CLASS 401 #define __PMC_CLASS(C) #C , 402 __PMC_CLASSES() 403 }; 404 405 struct pmc_cputype_map { 406 enum pmc_cputype pm_cputype; 407 const char *pm_name; 408 }; 409 410 static const struct pmc_cputype_map pmc_cputype_names[] = { 411 #undef __PMC_CPU 412 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 413 __PMC_CPUS() 414 }; 415 416 static const char * pmc_disposition_names[] = { 417 #undef __PMC_DISP 418 #define __PMC_DISP(D) #D , 419 __PMC_DISPOSITIONS() 420 }; 421 422 static const char * pmc_mode_names[] = { 423 #undef __PMC_MODE 424 #define __PMC_MODE(M,N) #M , 425 __PMC_MODES() 426 }; 427 428 static const char * pmc_state_names[] = { 429 #undef __PMC_STATE 430 #define __PMC_STATE(S) #S , 431 __PMC_STATES() 432 }; 433 434 /* 435 * Filled in by pmc_init(). 436 */ 437 static int pmc_syscall = -1; 438 static struct pmc_cpuinfo cpu_info; 439 static struct pmc_op_getdyneventinfo soft_event_info; 440 441 /* Event masks for events */ 442 struct pmc_masks { 443 const char *pm_name; 444 const uint64_t pm_value; 445 }; 446 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 447 #define NULLMASK { .pm_name = NULL } 448 449 #if defined(__amd64__) || defined(__i386__) 450 static int 451 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 452 { 453 const struct pmc_masks *pm; 454 char *q, *r; 455 int c; 456 457 if (pmask == NULL) /* no mask keywords */ 458 return (-1); 459 q = strchr(p, '='); /* skip '=' */ 460 if (*++q == '\0') /* no more data */ 461 return (-1); 462 c = 0; /* count of mask keywords seen */ 463 while ((r = strsep(&q, "+")) != NULL) { 464 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 465 pm++) 466 ; 467 if (pm->pm_name == NULL) /* not found */ 468 return (-1); 469 *evmask |= pm->pm_value; 470 c++; 471 } 472 return (c); 473 } 474 #endif 475 476 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 477 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 478 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 479 480 #if defined(__i386__) 481 482 /* 483 * AMD K7 (Athlon) CPUs. 484 */ 485 486 static struct pmc_event_alias k7_aliases[] = { 487 EV_ALIAS("branches", "k7-retired-branches"), 488 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 489 EV_ALIAS("cycles", "tsc"), 490 EV_ALIAS("dc-misses", "k7-dc-misses"), 491 EV_ALIAS("ic-misses", "k7-ic-misses"), 492 EV_ALIAS("instructions", "k7-retired-instructions"), 493 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 494 EV_ALIAS(NULL, NULL) 495 }; 496 497 #define K7_KW_COUNT "count" 498 #define K7_KW_EDGE "edge" 499 #define K7_KW_INV "inv" 500 #define K7_KW_OS "os" 501 #define K7_KW_UNITMASK "unitmask" 502 #define K7_KW_USR "usr" 503 504 static int 505 k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 506 struct pmc_op_pmcallocate *pmc_config) 507 { 508 char *e, *p, *q; 509 int c, has_unitmask; 510 uint32_t count, unitmask; 511 512 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 513 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 514 515 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 516 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 517 pe == PMC_EV_K7_DC_WRITEBACKS) { 518 has_unitmask = 1; 519 unitmask = AMD_PMC_UNITMASK_MOESI; 520 } else 521 unitmask = has_unitmask = 0; 522 523 while ((p = strsep(&ctrspec, ",")) != NULL) { 524 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 525 q = strchr(p, '='); 526 if (*++q == '\0') /* skip '=' */ 527 return (-1); 528 529 count = strtol(q, &e, 0); 530 if (e == q || *e != '\0') 531 return (-1); 532 533 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 534 pmc_config->pm_md.pm_amd.pm_amd_config |= 535 AMD_PMC_TO_COUNTER(count); 536 537 } else if (KWMATCH(p, K7_KW_EDGE)) { 538 pmc_config->pm_caps |= PMC_CAP_EDGE; 539 } else if (KWMATCH(p, K7_KW_INV)) { 540 pmc_config->pm_caps |= PMC_CAP_INVERT; 541 } else if (KWMATCH(p, K7_KW_OS)) { 542 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 543 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 544 if (has_unitmask == 0) 545 return (-1); 546 unitmask = 0; 547 q = strchr(p, '='); 548 if (*++q == '\0') /* skip '=' */ 549 return (-1); 550 551 while ((c = tolower(*q++)) != 0) 552 if (c == 'm') 553 unitmask |= AMD_PMC_UNITMASK_M; 554 else if (c == 'o') 555 unitmask |= AMD_PMC_UNITMASK_O; 556 else if (c == 'e') 557 unitmask |= AMD_PMC_UNITMASK_E; 558 else if (c == 's') 559 unitmask |= AMD_PMC_UNITMASK_S; 560 else if (c == 'i') 561 unitmask |= AMD_PMC_UNITMASK_I; 562 else if (c == '+') 563 continue; 564 else 565 return (-1); 566 567 if (unitmask == 0) 568 return (-1); 569 570 } else if (KWMATCH(p, K7_KW_USR)) { 571 pmc_config->pm_caps |= PMC_CAP_USER; 572 } else 573 return (-1); 574 } 575 576 if (has_unitmask) { 577 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 578 pmc_config->pm_md.pm_amd.pm_amd_config |= 579 AMD_PMC_TO_UNITMASK(unitmask); 580 } 581 582 return (0); 583 584 } 585 586 #endif 587 588 #if defined(__amd64__) || defined(__i386__) 589 590 /* 591 * Intel Core (Family 6, Model E) PMCs. 592 */ 593 594 static struct pmc_event_alias core_aliases[] = { 595 EV_ALIAS("branches", "iap-br-instr-ret"), 596 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 597 EV_ALIAS("cycles", "tsc-tsc"), 598 EV_ALIAS("ic-misses", "iap-icache-misses"), 599 EV_ALIAS("instructions", "iap-instr-ret"), 600 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 601 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 602 EV_ALIAS(NULL, NULL) 603 }; 604 605 /* 606 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 607 * and Atom (Family 6, model 1CH) PMCs. 608 * 609 * We map aliases to events on the fixed-function counters if these 610 * are present. Note that not all CPUs in this family contain fixed-function 611 * counters. 612 */ 613 614 static struct pmc_event_alias core2_aliases[] = { 615 EV_ALIAS("branches", "iap-br-inst-retired.any"), 616 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 617 EV_ALIAS("cycles", "tsc-tsc"), 618 EV_ALIAS("ic-misses", "iap-l1i-misses"), 619 EV_ALIAS("instructions", "iaf-instr-retired.any"), 620 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 621 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 622 EV_ALIAS(NULL, NULL) 623 }; 624 625 static struct pmc_event_alias core2_aliases_without_iaf[] = { 626 EV_ALIAS("branches", "iap-br-inst-retired.any"), 627 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 628 EV_ALIAS("cycles", "tsc-tsc"), 629 EV_ALIAS("ic-misses", "iap-l1i-misses"), 630 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 631 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 632 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 633 EV_ALIAS(NULL, NULL) 634 }; 635 636 #define atom_aliases core2_aliases 637 #define atom_aliases_without_iaf core2_aliases_without_iaf 638 #define atom_silvermont_aliases core2_aliases 639 #define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf 640 #define corei7_aliases core2_aliases 641 #define corei7_aliases_without_iaf core2_aliases_without_iaf 642 #define nehalem_ex_aliases core2_aliases 643 #define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf 644 #define haswell_aliases core2_aliases 645 #define haswell_aliases_without_iaf core2_aliases_without_iaf 646 #define haswell_xeon_aliases core2_aliases 647 #define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf 648 #define ivybridge_aliases core2_aliases 649 #define ivybridge_aliases_without_iaf core2_aliases_without_iaf 650 #define ivybridge_xeon_aliases core2_aliases 651 #define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 652 #define sandybridge_aliases core2_aliases 653 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf 654 #define sandybridge_xeon_aliases core2_aliases 655 #define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 656 #define westmere_aliases core2_aliases 657 #define westmere_aliases_without_iaf core2_aliases_without_iaf 658 #define westmere_ex_aliases core2_aliases 659 #define westmere_ex_aliases_without_iaf core2_aliases_without_iaf 660 661 #define IAF_KW_OS "os" 662 #define IAF_KW_USR "usr" 663 #define IAF_KW_ANYTHREAD "anythread" 664 665 /* 666 * Parse an event specifier for Intel fixed function counters. 667 */ 668 static int 669 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 670 struct pmc_op_pmcallocate *pmc_config) 671 { 672 char *p; 673 674 (void) pe; 675 676 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 677 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 678 679 while ((p = strsep(&ctrspec, ",")) != NULL) { 680 if (KWMATCH(p, IAF_KW_OS)) 681 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 682 else if (KWMATCH(p, IAF_KW_USR)) 683 pmc_config->pm_caps |= PMC_CAP_USER; 684 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 685 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 686 else 687 return (-1); 688 } 689 690 return (0); 691 } 692 693 /* 694 * Core/Core2 support. 695 */ 696 697 #define IAP_KW_AGENT "agent" 698 #define IAP_KW_ANYTHREAD "anythread" 699 #define IAP_KW_CACHESTATE "cachestate" 700 #define IAP_KW_CMASK "cmask" 701 #define IAP_KW_CORE "core" 702 #define IAP_KW_EDGE "edge" 703 #define IAP_KW_INV "inv" 704 #define IAP_KW_OS "os" 705 #define IAP_KW_PREFETCH "prefetch" 706 #define IAP_KW_SNOOPRESPONSE "snoopresponse" 707 #define IAP_KW_SNOOPTYPE "snooptype" 708 #define IAP_KW_TRANSITION "trans" 709 #define IAP_KW_USR "usr" 710 #define IAP_KW_RSP "rsp" 711 712 static struct pmc_masks iap_core_mask[] = { 713 PMCMASK(all, (0x3 << 14)), 714 PMCMASK(this, (0x1 << 14)), 715 NULLMASK 716 }; 717 718 static struct pmc_masks iap_agent_mask[] = { 719 PMCMASK(this, 0), 720 PMCMASK(any, (0x1 << 13)), 721 NULLMASK 722 }; 723 724 static struct pmc_masks iap_prefetch_mask[] = { 725 PMCMASK(both, (0x3 << 12)), 726 PMCMASK(only, (0x1 << 12)), 727 PMCMASK(exclude, 0), 728 NULLMASK 729 }; 730 731 static struct pmc_masks iap_cachestate_mask[] = { 732 PMCMASK(i, (1 << 8)), 733 PMCMASK(s, (1 << 9)), 734 PMCMASK(e, (1 << 10)), 735 PMCMASK(m, (1 << 11)), 736 NULLMASK 737 }; 738 739 static struct pmc_masks iap_snoopresponse_mask[] = { 740 PMCMASK(clean, (1 << 8)), 741 PMCMASK(hit, (1 << 9)), 742 PMCMASK(hitm, (1 << 11)), 743 NULLMASK 744 }; 745 746 static struct pmc_masks iap_snooptype_mask[] = { 747 PMCMASK(cmp2s, (1 << 8)), 748 PMCMASK(cmp2i, (1 << 9)), 749 NULLMASK 750 }; 751 752 static struct pmc_masks iap_transition_mask[] = { 753 PMCMASK(any, 0x00), 754 PMCMASK(frequency, 0x10), 755 NULLMASK 756 }; 757 758 static struct pmc_masks iap_rsp_mask_i7_wm[] = { 759 PMCMASK(DMND_DATA_RD, (1 << 0)), 760 PMCMASK(DMND_RFO, (1 << 1)), 761 PMCMASK(DMND_IFETCH, (1 << 2)), 762 PMCMASK(WB, (1 << 3)), 763 PMCMASK(PF_DATA_RD, (1 << 4)), 764 PMCMASK(PF_RFO, (1 << 5)), 765 PMCMASK(PF_IFETCH, (1 << 6)), 766 PMCMASK(OTHER, (1 << 7)), 767 PMCMASK(UNCORE_HIT, (1 << 8)), 768 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 769 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 770 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 771 PMCMASK(REMOTE_DRAM, (1 << 13)), 772 PMCMASK(LOCAL_DRAM, (1 << 14)), 773 PMCMASK(NON_DRAM, (1 << 15)), 774 NULLMASK 775 }; 776 777 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { 778 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 779 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 780 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 781 PMCMASK(REQ_WB, (1ULL << 3)), 782 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 783 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 784 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 785 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), 786 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), 787 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), 788 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), 789 PMCMASK(REQ_STRM_ST, (1ULL << 11)), 790 PMCMASK(REQ_OTHER, (1ULL << 15)), 791 PMCMASK(RES_ANY, (1ULL << 16)), 792 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 793 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 794 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 795 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 796 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 797 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 798 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 799 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 800 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 801 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 802 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 803 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 804 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 805 NULLMASK 806 }; 807 808 static struct pmc_masks iap_rsp_mask_haswell[] = { 809 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 810 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 811 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 812 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 813 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 814 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 815 PMCMASK(REQ_OTHER, (1ULL << 15)), 816 PMCMASK(RES_ANY, (1ULL << 16)), 817 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 818 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 819 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 820 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 821 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 822 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 823 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 824 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 825 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 826 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 827 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 828 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 829 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 830 NULLMASK 831 }; 832 833 static int 834 iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 835 struct pmc_op_pmcallocate *pmc_config) 836 { 837 char *e, *p, *q; 838 uint64_t cachestate, evmask, rsp; 839 int count, n; 840 841 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 842 PMC_CAP_QUALIFIER); 843 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 844 845 cachestate = evmask = rsp = 0; 846 847 /* Parse additional modifiers if present */ 848 while ((p = strsep(&ctrspec, ",")) != NULL) { 849 850 n = 0; 851 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 852 q = strchr(p, '='); 853 if (*++q == '\0') /* skip '=' */ 854 return (-1); 855 count = strtol(q, &e, 0); 856 if (e == q || *e != '\0') 857 return (-1); 858 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 859 pmc_config->pm_md.pm_iap.pm_iap_config |= 860 IAP_CMASK(count); 861 } else if (KWMATCH(p, IAP_KW_EDGE)) { 862 pmc_config->pm_caps |= PMC_CAP_EDGE; 863 } else if (KWMATCH(p, IAP_KW_INV)) { 864 pmc_config->pm_caps |= PMC_CAP_INVERT; 865 } else if (KWMATCH(p, IAP_KW_OS)) { 866 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 867 } else if (KWMATCH(p, IAP_KW_USR)) { 868 pmc_config->pm_caps |= PMC_CAP_USER; 869 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 870 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 871 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 872 n = pmc_parse_mask(iap_core_mask, p, &evmask); 873 if (n != 1) 874 return (-1); 875 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 876 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 877 if (n != 1) 878 return (-1); 879 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 880 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 881 if (n != 1) 882 return (-1); 883 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 884 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 885 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 886 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 887 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 888 if (n != 1) 889 return (-1); 890 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 891 cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 892 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 893 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 894 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 895 n = pmc_parse_mask(iap_snoopresponse_mask, p, 896 &evmask); 897 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 898 n = pmc_parse_mask(iap_snooptype_mask, p, 899 &evmask); 900 } else 901 return (-1); 902 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 903 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || 904 cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || 905 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { 906 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 907 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); 908 } else 909 return (-1); 910 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 911 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 912 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || 913 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { 914 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 915 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); 916 } else 917 return (-1); 918 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL || 919 cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) { 920 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 921 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); 922 } else 923 return (-1); 924 } else 925 return (-1); 926 927 if (n < 0) /* Parsing failed. */ 928 return (-1); 929 } 930 931 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 932 933 /* 934 * If the event requires a 'cachestate' qualifier but was not 935 * specified by the user, use a sensible default. 936 */ 937 switch (pe) { 938 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 939 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 940 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 941 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 942 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 943 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 944 case PMC_EV_IAP_EVENT_32H: /* Core */ 945 case PMC_EV_IAP_EVENT_40H: /* Core */ 946 case PMC_EV_IAP_EVENT_41H: /* Core */ 947 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 948 if (cachestate == 0) 949 cachestate = (0xF << 8); 950 break; 951 case PMC_EV_IAP_EVENT_77H: /* Atom */ 952 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 953 * Atom processor 954 */ 955 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 956 cachestate = (0xF << 8); 957 break; 958 default: 959 break; 960 } 961 962 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 963 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 964 965 return (0); 966 } 967 968 /* 969 * Intel Uncore. 970 */ 971 972 static int 973 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 974 struct pmc_op_pmcallocate *pmc_config) 975 { 976 (void) pe; 977 (void) ctrspec; 978 979 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 980 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 981 982 return (0); 983 } 984 985 #define UCP_KW_CMASK "cmask" 986 #define UCP_KW_EDGE "edge" 987 #define UCP_KW_INV "inv" 988 989 static int 990 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 991 struct pmc_op_pmcallocate *pmc_config) 992 { 993 char *e, *p, *q; 994 int count, n; 995 996 (void) pe; 997 998 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 999 PMC_CAP_QUALIFIER); 1000 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 1001 1002 /* Parse additional modifiers if present */ 1003 while ((p = strsep(&ctrspec, ",")) != NULL) { 1004 1005 n = 0; 1006 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 1007 q = strchr(p, '='); 1008 if (*++q == '\0') /* skip '=' */ 1009 return (-1); 1010 count = strtol(q, &e, 0); 1011 if (e == q || *e != '\0') 1012 return (-1); 1013 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1014 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 1015 UCP_CMASK(count); 1016 } else if (KWMATCH(p, UCP_KW_EDGE)) { 1017 pmc_config->pm_caps |= PMC_CAP_EDGE; 1018 } else if (KWMATCH(p, UCP_KW_INV)) { 1019 pmc_config->pm_caps |= PMC_CAP_INVERT; 1020 } else 1021 return (-1); 1022 1023 if (n < 0) /* Parsing failed. */ 1024 return (-1); 1025 } 1026 1027 return (0); 1028 } 1029 1030 /* 1031 * AMD K8 PMCs. 1032 * 1033 * These are very similar to AMD K7 PMCs, but support more kinds of 1034 * events. 1035 */ 1036 1037 static struct pmc_event_alias k8_aliases[] = { 1038 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 1039 EV_ALIAS("branch-mispredicts", 1040 "k8-fr-retired-taken-branches-mispredicted"), 1041 EV_ALIAS("cycles", "tsc"), 1042 EV_ALIAS("dc-misses", "k8-dc-miss"), 1043 EV_ALIAS("ic-misses", "k8-ic-miss"), 1044 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 1045 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 1046 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 1047 EV_ALIAS(NULL, NULL) 1048 }; 1049 1050 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 1051 1052 /* 1053 * Parsing tables 1054 */ 1055 1056 /* fp dispatched fpu ops */ 1057 static const struct pmc_masks k8_mask_fdfo[] = { 1058 __K8MASK(add-pipe-excluding-junk-ops, 0), 1059 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 1060 __K8MASK(store-pipe-excluding-junk-ops, 2), 1061 __K8MASK(add-pipe-junk-ops, 3), 1062 __K8MASK(multiply-pipe-junk-ops, 4), 1063 __K8MASK(store-pipe-junk-ops, 5), 1064 NULLMASK 1065 }; 1066 1067 /* ls segment register loads */ 1068 static const struct pmc_masks k8_mask_lsrl[] = { 1069 __K8MASK(es, 0), 1070 __K8MASK(cs, 1), 1071 __K8MASK(ss, 2), 1072 __K8MASK(ds, 3), 1073 __K8MASK(fs, 4), 1074 __K8MASK(gs, 5), 1075 __K8MASK(hs, 6), 1076 NULLMASK 1077 }; 1078 1079 /* ls locked operation */ 1080 static const struct pmc_masks k8_mask_llo[] = { 1081 __K8MASK(locked-instructions, 0), 1082 __K8MASK(cycles-in-request, 1), 1083 __K8MASK(cycles-to-complete, 2), 1084 NULLMASK 1085 }; 1086 1087 /* dc refill from {l2,system} and dc copyback */ 1088 static const struct pmc_masks k8_mask_dc[] = { 1089 __K8MASK(invalid, 0), 1090 __K8MASK(shared, 1), 1091 __K8MASK(exclusive, 2), 1092 __K8MASK(owner, 3), 1093 __K8MASK(modified, 4), 1094 NULLMASK 1095 }; 1096 1097 /* dc one bit ecc error */ 1098 static const struct pmc_masks k8_mask_dobee[] = { 1099 __K8MASK(scrubber, 0), 1100 __K8MASK(piggyback, 1), 1101 NULLMASK 1102 }; 1103 1104 /* dc dispatched prefetch instructions */ 1105 static const struct pmc_masks k8_mask_ddpi[] = { 1106 __K8MASK(load, 0), 1107 __K8MASK(store, 1), 1108 __K8MASK(nta, 2), 1109 NULLMASK 1110 }; 1111 1112 /* dc dcache accesses by locks */ 1113 static const struct pmc_masks k8_mask_dabl[] = { 1114 __K8MASK(accesses, 0), 1115 __K8MASK(misses, 1), 1116 NULLMASK 1117 }; 1118 1119 /* bu internal l2 request */ 1120 static const struct pmc_masks k8_mask_bilr[] = { 1121 __K8MASK(ic-fill, 0), 1122 __K8MASK(dc-fill, 1), 1123 __K8MASK(tlb-reload, 2), 1124 __K8MASK(tag-snoop, 3), 1125 __K8MASK(cancelled, 4), 1126 NULLMASK 1127 }; 1128 1129 /* bu fill request l2 miss */ 1130 static const struct pmc_masks k8_mask_bfrlm[] = { 1131 __K8MASK(ic-fill, 0), 1132 __K8MASK(dc-fill, 1), 1133 __K8MASK(tlb-reload, 2), 1134 NULLMASK 1135 }; 1136 1137 /* bu fill into l2 */ 1138 static const struct pmc_masks k8_mask_bfil[] = { 1139 __K8MASK(dirty-l2-victim, 0), 1140 __K8MASK(victim-from-l2, 1), 1141 NULLMASK 1142 }; 1143 1144 /* fr retired fpu instructions */ 1145 static const struct pmc_masks k8_mask_frfi[] = { 1146 __K8MASK(x87, 0), 1147 __K8MASK(mmx-3dnow, 1), 1148 __K8MASK(packed-sse-sse2, 2), 1149 __K8MASK(scalar-sse-sse2, 3), 1150 NULLMASK 1151 }; 1152 1153 /* fr retired fastpath double op instructions */ 1154 static const struct pmc_masks k8_mask_frfdoi[] = { 1155 __K8MASK(low-op-pos-0, 0), 1156 __K8MASK(low-op-pos-1, 1), 1157 __K8MASK(low-op-pos-2, 2), 1158 NULLMASK 1159 }; 1160 1161 /* fr fpu exceptions */ 1162 static const struct pmc_masks k8_mask_ffe[] = { 1163 __K8MASK(x87-reclass-microfaults, 0), 1164 __K8MASK(sse-retype-microfaults, 1), 1165 __K8MASK(sse-reclass-microfaults, 2), 1166 __K8MASK(sse-and-x87-microtraps, 3), 1167 NULLMASK 1168 }; 1169 1170 /* nb memory controller page access event */ 1171 static const struct pmc_masks k8_mask_nmcpae[] = { 1172 __K8MASK(page-hit, 0), 1173 __K8MASK(page-miss, 1), 1174 __K8MASK(page-conflict, 2), 1175 NULLMASK 1176 }; 1177 1178 /* nb memory controller turnaround */ 1179 static const struct pmc_masks k8_mask_nmct[] = { 1180 __K8MASK(dimm-turnaround, 0), 1181 __K8MASK(read-to-write-turnaround, 1), 1182 __K8MASK(write-to-read-turnaround, 2), 1183 NULLMASK 1184 }; 1185 1186 /* nb memory controller bypass saturation */ 1187 static const struct pmc_masks k8_mask_nmcbs[] = { 1188 __K8MASK(memory-controller-hi-pri-bypass, 0), 1189 __K8MASK(memory-controller-lo-pri-bypass, 1), 1190 __K8MASK(dram-controller-interface-bypass, 2), 1191 __K8MASK(dram-controller-queue-bypass, 3), 1192 NULLMASK 1193 }; 1194 1195 /* nb sized commands */ 1196 static const struct pmc_masks k8_mask_nsc[] = { 1197 __K8MASK(nonpostwrszbyte, 0), 1198 __K8MASK(nonpostwrszdword, 1), 1199 __K8MASK(postwrszbyte, 2), 1200 __K8MASK(postwrszdword, 3), 1201 __K8MASK(rdszbyte, 4), 1202 __K8MASK(rdszdword, 5), 1203 __K8MASK(rdmodwr, 6), 1204 NULLMASK 1205 }; 1206 1207 /* nb probe result */ 1208 static const struct pmc_masks k8_mask_npr[] = { 1209 __K8MASK(probe-miss, 0), 1210 __K8MASK(probe-hit, 1), 1211 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1212 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1213 NULLMASK 1214 }; 1215 1216 /* nb hypertransport bus bandwidth */ 1217 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1218 __K8MASK(command, 0), 1219 __K8MASK(data, 1), 1220 __K8MASK(buffer-release, 2), 1221 __K8MASK(nop, 3), 1222 NULLMASK 1223 }; 1224 1225 #undef __K8MASK 1226 1227 #define K8_KW_COUNT "count" 1228 #define K8_KW_EDGE "edge" 1229 #define K8_KW_INV "inv" 1230 #define K8_KW_MASK "mask" 1231 #define K8_KW_OS "os" 1232 #define K8_KW_USR "usr" 1233 1234 static int 1235 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1236 struct pmc_op_pmcallocate *pmc_config) 1237 { 1238 char *e, *p, *q; 1239 int n; 1240 uint32_t count; 1241 uint64_t evmask; 1242 const struct pmc_masks *pm, *pmask; 1243 1244 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1245 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1246 1247 pmask = NULL; 1248 evmask = 0; 1249 1250 #define __K8SETMASK(M) pmask = k8_mask_##M 1251 1252 /* setup parsing tables */ 1253 switch (pe) { 1254 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1255 __K8SETMASK(fdfo); 1256 break; 1257 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1258 __K8SETMASK(lsrl); 1259 break; 1260 case PMC_EV_K8_LS_LOCKED_OPERATION: 1261 __K8SETMASK(llo); 1262 break; 1263 case PMC_EV_K8_DC_REFILL_FROM_L2: 1264 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1265 case PMC_EV_K8_DC_COPYBACK: 1266 __K8SETMASK(dc); 1267 break; 1268 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1269 __K8SETMASK(dobee); 1270 break; 1271 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1272 __K8SETMASK(ddpi); 1273 break; 1274 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1275 __K8SETMASK(dabl); 1276 break; 1277 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1278 __K8SETMASK(bilr); 1279 break; 1280 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1281 __K8SETMASK(bfrlm); 1282 break; 1283 case PMC_EV_K8_BU_FILL_INTO_L2: 1284 __K8SETMASK(bfil); 1285 break; 1286 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1287 __K8SETMASK(frfi); 1288 break; 1289 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1290 __K8SETMASK(frfdoi); 1291 break; 1292 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1293 __K8SETMASK(ffe); 1294 break; 1295 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1296 __K8SETMASK(nmcpae); 1297 break; 1298 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1299 __K8SETMASK(nmct); 1300 break; 1301 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1302 __K8SETMASK(nmcbs); 1303 break; 1304 case PMC_EV_K8_NB_SIZED_COMMANDS: 1305 __K8SETMASK(nsc); 1306 break; 1307 case PMC_EV_K8_NB_PROBE_RESULT: 1308 __K8SETMASK(npr); 1309 break; 1310 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1311 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1312 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1313 __K8SETMASK(nhbb); 1314 break; 1315 1316 default: 1317 break; /* no options defined */ 1318 } 1319 1320 while ((p = strsep(&ctrspec, ",")) != NULL) { 1321 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1322 q = strchr(p, '='); 1323 if (*++q == '\0') /* skip '=' */ 1324 return (-1); 1325 1326 count = strtol(q, &e, 0); 1327 if (e == q || *e != '\0') 1328 return (-1); 1329 1330 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1331 pmc_config->pm_md.pm_amd.pm_amd_config |= 1332 AMD_PMC_TO_COUNTER(count); 1333 1334 } else if (KWMATCH(p, K8_KW_EDGE)) { 1335 pmc_config->pm_caps |= PMC_CAP_EDGE; 1336 } else if (KWMATCH(p, K8_KW_INV)) { 1337 pmc_config->pm_caps |= PMC_CAP_INVERT; 1338 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1339 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1340 return (-1); 1341 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1342 } else if (KWMATCH(p, K8_KW_OS)) { 1343 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1344 } else if (KWMATCH(p, K8_KW_USR)) { 1345 pmc_config->pm_caps |= PMC_CAP_USER; 1346 } else 1347 return (-1); 1348 } 1349 1350 /* other post processing */ 1351 switch (pe) { 1352 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1353 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1354 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1355 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1356 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1357 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1358 /* XXX only available in rev B and later */ 1359 break; 1360 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1361 /* XXX only available in rev C and later */ 1362 break; 1363 case PMC_EV_K8_LS_LOCKED_OPERATION: 1364 /* XXX CPU Rev A,B evmask is to be zero */ 1365 if (evmask & (evmask - 1)) /* > 1 bit set */ 1366 return (-1); 1367 if (evmask == 0) { 1368 evmask = 0x01; /* Rev C and later: #instrs */ 1369 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1370 } 1371 break; 1372 default: 1373 if (evmask == 0 && pmask != NULL) { 1374 for (pm = pmask; pm->pm_name; pm++) 1375 evmask |= pm->pm_value; 1376 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1377 } 1378 } 1379 1380 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1381 pmc_config->pm_md.pm_amd.pm_amd_config = 1382 AMD_PMC_TO_UNITMASK(evmask); 1383 1384 return (0); 1385 } 1386 1387 #endif 1388 1389 #if defined(__amd64__) || defined(__i386__) 1390 1391 /* 1392 * Intel P4 PMCs 1393 */ 1394 1395 static struct pmc_event_alias p4_aliases[] = { 1396 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1397 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1398 EV_ALIAS("cycles", "tsc"), 1399 EV_ALIAS("instructions", 1400 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1401 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1402 EV_ALIAS(NULL, NULL) 1403 }; 1404 1405 #define P4_KW_ACTIVE "active" 1406 #define P4_KW_ACTIVE_ANY "any" 1407 #define P4_KW_ACTIVE_BOTH "both" 1408 #define P4_KW_ACTIVE_NONE "none" 1409 #define P4_KW_ACTIVE_SINGLE "single" 1410 #define P4_KW_BUSREQTYPE "busreqtype" 1411 #define P4_KW_CASCADE "cascade" 1412 #define P4_KW_EDGE "edge" 1413 #define P4_KW_INV "complement" 1414 #define P4_KW_OS "os" 1415 #define P4_KW_MASK "mask" 1416 #define P4_KW_PRECISE "precise" 1417 #define P4_KW_TAG "tag" 1418 #define P4_KW_THRESHOLD "threshold" 1419 #define P4_KW_USR "usr" 1420 1421 #define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1422 1423 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1424 __P4MASK(dd, 0), 1425 __P4MASK(db, 1), 1426 __P4MASK(di, 2), 1427 __P4MASK(bd, 3), 1428 __P4MASK(bb, 4), 1429 __P4MASK(bi, 5), 1430 __P4MASK(id, 6), 1431 __P4MASK(ib, 7), 1432 NULLMASK 1433 }; 1434 1435 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1436 __P4MASK(tcmiss, 0), 1437 NULLMASK, 1438 }; 1439 1440 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1441 __P4MASK(hit, 0), 1442 __P4MASK(miss, 1), 1443 __P4MASK(hit-uc, 2), 1444 NULLMASK 1445 }; 1446 1447 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1448 __P4MASK(st-rb-full, 2), 1449 __P4MASK(64k-conf, 3), 1450 NULLMASK 1451 }; 1452 1453 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1454 __P4MASK(lsc, 0), 1455 __P4MASK(ssc, 1), 1456 NULLMASK 1457 }; 1458 1459 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1460 __P4MASK(split-ld, 1), 1461 NULLMASK 1462 }; 1463 1464 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1465 __P4MASK(split-st, 1), 1466 NULLMASK 1467 }; 1468 1469 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1470 __P4MASK(no-sta, 1), 1471 __P4MASK(no-std, 3), 1472 __P4MASK(partial-data, 4), 1473 __P4MASK(unalgn-addr, 5), 1474 NULLMASK 1475 }; 1476 1477 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1478 __P4MASK(dtmiss, 0), 1479 __P4MASK(itmiss, 1), 1480 NULLMASK 1481 }; 1482 1483 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1484 __P4MASK(rd-2ndl-hits, 0), 1485 __P4MASK(rd-2ndl-hite, 1), 1486 __P4MASK(rd-2ndl-hitm, 2), 1487 __P4MASK(rd-3rdl-hits, 3), 1488 __P4MASK(rd-3rdl-hite, 4), 1489 __P4MASK(rd-3rdl-hitm, 5), 1490 __P4MASK(rd-2ndl-miss, 8), 1491 __P4MASK(rd-3rdl-miss, 9), 1492 __P4MASK(wr-2ndl-miss, 10), 1493 NULLMASK 1494 }; 1495 1496 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1497 __P4MASK(all-read, 5), 1498 __P4MASK(all-write, 6), 1499 __P4MASK(mem-uc, 7), 1500 __P4MASK(mem-wc, 8), 1501 __P4MASK(mem-wt, 9), 1502 __P4MASK(mem-wp, 10), 1503 __P4MASK(mem-wb, 11), 1504 __P4MASK(own, 13), 1505 __P4MASK(other, 14), 1506 __P4MASK(prefetch, 15), 1507 NULLMASK 1508 }; 1509 1510 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1511 __P4MASK(all-read, 5), 1512 __P4MASK(all-write, 6), 1513 __P4MASK(mem-uc, 7), 1514 __P4MASK(mem-wc, 8), 1515 __P4MASK(mem-wt, 9), 1516 __P4MASK(mem-wp, 10), 1517 __P4MASK(mem-wb, 11), 1518 __P4MASK(own, 13), 1519 __P4MASK(other, 14), 1520 __P4MASK(prefetch, 15), 1521 NULLMASK 1522 }; 1523 1524 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1525 __P4MASK(drdy-drv, 0), 1526 __P4MASK(drdy-own, 1), 1527 __P4MASK(drdy-other, 2), 1528 __P4MASK(dbsy-drv, 3), 1529 __P4MASK(dbsy-own, 4), 1530 __P4MASK(dbsy-other, 5), 1531 NULLMASK 1532 }; 1533 1534 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1535 __P4MASK(req-type0, 0), 1536 __P4MASK(req-type1, 1), 1537 __P4MASK(req-len0, 2), 1538 __P4MASK(req-len1, 3), 1539 __P4MASK(req-io-type, 5), 1540 __P4MASK(req-lock-type, 6), 1541 __P4MASK(req-cache-type, 7), 1542 __P4MASK(req-split-type, 8), 1543 __P4MASK(req-dem-type, 9), 1544 __P4MASK(req-ord-type, 10), 1545 __P4MASK(mem-type0, 11), 1546 __P4MASK(mem-type1, 12), 1547 __P4MASK(mem-type2, 13), 1548 NULLMASK 1549 }; 1550 1551 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1552 __P4MASK(all, 15), 1553 NULLMASK 1554 }; 1555 1556 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1557 __P4MASK(all, 15), 1558 NULLMASK 1559 }; 1560 1561 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1562 __P4MASK(all, 15), 1563 NULLMASK 1564 }; 1565 1566 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1567 __P4MASK(all, 15), 1568 NULLMASK 1569 }; 1570 1571 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1572 __P4MASK(all, 15), 1573 NULLMASK 1574 }; 1575 1576 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1577 __P4MASK(all, 15), 1578 NULLMASK 1579 }; 1580 1581 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1582 __P4MASK(all, 15), 1583 NULLMASK 1584 }; 1585 1586 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1587 __P4MASK(all, 15), 1588 NULLMASK 1589 }; 1590 1591 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1592 __P4MASK(allp0, 3), 1593 __P4MASK(allp2, 4), 1594 NULLMASK 1595 }; 1596 1597 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1598 __P4MASK(running, 0), 1599 NULLMASK 1600 }; 1601 1602 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1603 __P4MASK(cisc, 0), 1604 NULLMASK 1605 }; 1606 1607 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1608 __P4MASK(from-tc-build, 0), 1609 __P4MASK(from-tc-deliver, 1), 1610 __P4MASK(from-rom, 2), 1611 NULLMASK 1612 }; 1613 1614 static const struct pmc_masks p4_mask_rmbt[] = { 1615 /* retired mispred branch type */ 1616 __P4MASK(conditional, 1), 1617 __P4MASK(call, 2), 1618 __P4MASK(return, 3), 1619 __P4MASK(indirect, 4), 1620 NULLMASK 1621 }; 1622 1623 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1624 __P4MASK(conditional, 1), 1625 __P4MASK(call, 2), 1626 __P4MASK(retired, 3), 1627 __P4MASK(indirect, 4), 1628 NULLMASK 1629 }; 1630 1631 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1632 __P4MASK(sbfull, 5), 1633 NULLMASK 1634 }; 1635 1636 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1637 __P4MASK(wcb-evicts, 0), 1638 __P4MASK(wcb-full-evict, 1), 1639 NULLMASK 1640 }; 1641 1642 static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1643 __P4MASK(nbogus, 0), 1644 __P4MASK(bogus, 1), 1645 NULLMASK 1646 }; 1647 1648 static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1649 __P4MASK(nbogus0, 0), 1650 __P4MASK(nbogus1, 1), 1651 __P4MASK(nbogus2, 2), 1652 __P4MASK(nbogus3, 3), 1653 __P4MASK(bogus0, 4), 1654 __P4MASK(bogus1, 5), 1655 __P4MASK(bogus2, 6), 1656 __P4MASK(bogus3, 7), 1657 NULLMASK 1658 }; 1659 1660 static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1661 __P4MASK(nbogus, 0), 1662 __P4MASK(bogus, 1), 1663 NULLMASK 1664 }; 1665 1666 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1667 __P4MASK(nbogusntag, 0), 1668 __P4MASK(nbogustag, 1), 1669 __P4MASK(bogusntag, 2), 1670 __P4MASK(bogustag, 3), 1671 NULLMASK 1672 }; 1673 1674 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1675 __P4MASK(nbogus, 0), 1676 __P4MASK(bogus, 1), 1677 NULLMASK 1678 }; 1679 1680 static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1681 __P4MASK(tagloads, 1), 1682 __P4MASK(tagstores, 2), 1683 NULLMASK 1684 }; 1685 1686 static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1687 __P4MASK(mmnp, 0), 1688 __P4MASK(mmnm, 1), 1689 __P4MASK(mmtp, 2), 1690 __P4MASK(mmtm, 3), 1691 NULLMASK 1692 }; 1693 1694 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1695 __P4MASK(nbogus, 0), 1696 NULLMASK 1697 }; 1698 1699 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1700 __P4MASK(fpsu, 0), 1701 __P4MASK(fpso, 1), 1702 __P4MASK(poao, 2), 1703 __P4MASK(poau, 3), 1704 __P4MASK(prea, 4), 1705 NULLMASK 1706 }; 1707 1708 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1709 __P4MASK(clear, 0), 1710 __P4MASK(moclear, 2), 1711 __P4MASK(smclear, 3), 1712 NULLMASK 1713 }; 1714 1715 /* P4 event parser */ 1716 static int 1717 p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1718 struct pmc_op_pmcallocate *pmc_config) 1719 { 1720 1721 char *e, *p, *q; 1722 int count, has_tag, has_busreqtype, n; 1723 uint32_t cccractivemask; 1724 uint64_t evmask; 1725 const struct pmc_masks *pm, *pmask; 1726 1727 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1728 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1729 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1730 1731 pmask = NULL; 1732 evmask = 0; 1733 cccractivemask = 0x3; 1734 has_tag = has_busreqtype = 0; 1735 1736 #define __P4SETMASK(M) do { \ 1737 pmask = p4_mask_##M; \ 1738 } while (0) 1739 1740 switch (pe) { 1741 case PMC_EV_P4_TC_DELIVER_MODE: 1742 __P4SETMASK(tcdm); 1743 break; 1744 case PMC_EV_P4_BPU_FETCH_REQUEST: 1745 __P4SETMASK(bfr); 1746 break; 1747 case PMC_EV_P4_ITLB_REFERENCE: 1748 __P4SETMASK(ir); 1749 break; 1750 case PMC_EV_P4_MEMORY_CANCEL: 1751 __P4SETMASK(memcan); 1752 break; 1753 case PMC_EV_P4_MEMORY_COMPLETE: 1754 __P4SETMASK(memcomp); 1755 break; 1756 case PMC_EV_P4_LOAD_PORT_REPLAY: 1757 __P4SETMASK(lpr); 1758 break; 1759 case PMC_EV_P4_STORE_PORT_REPLAY: 1760 __P4SETMASK(spr); 1761 break; 1762 case PMC_EV_P4_MOB_LOAD_REPLAY: 1763 __P4SETMASK(mlr); 1764 break; 1765 case PMC_EV_P4_PAGE_WALK_TYPE: 1766 __P4SETMASK(pwt); 1767 break; 1768 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1769 __P4SETMASK(bcr); 1770 break; 1771 case PMC_EV_P4_IOQ_ALLOCATION: 1772 __P4SETMASK(ia); 1773 has_busreqtype = 1; 1774 break; 1775 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1776 __P4SETMASK(iae); 1777 has_busreqtype = 1; 1778 break; 1779 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1780 __P4SETMASK(fda); 1781 break; 1782 case PMC_EV_P4_BSQ_ALLOCATION: 1783 __P4SETMASK(ba); 1784 break; 1785 case PMC_EV_P4_SSE_INPUT_ASSIST: 1786 __P4SETMASK(sia); 1787 break; 1788 case PMC_EV_P4_PACKED_SP_UOP: 1789 __P4SETMASK(psu); 1790 break; 1791 case PMC_EV_P4_PACKED_DP_UOP: 1792 __P4SETMASK(pdu); 1793 break; 1794 case PMC_EV_P4_SCALAR_SP_UOP: 1795 __P4SETMASK(ssu); 1796 break; 1797 case PMC_EV_P4_SCALAR_DP_UOP: 1798 __P4SETMASK(sdu); 1799 break; 1800 case PMC_EV_P4_64BIT_MMX_UOP: 1801 __P4SETMASK(64bmu); 1802 break; 1803 case PMC_EV_P4_128BIT_MMX_UOP: 1804 __P4SETMASK(128bmu); 1805 break; 1806 case PMC_EV_P4_X87_FP_UOP: 1807 __P4SETMASK(xfu); 1808 break; 1809 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1810 __P4SETMASK(xsmu); 1811 break; 1812 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1813 __P4SETMASK(gpe); 1814 break; 1815 case PMC_EV_P4_TC_MS_XFER: 1816 __P4SETMASK(tmx); 1817 break; 1818 case PMC_EV_P4_UOP_QUEUE_WRITES: 1819 __P4SETMASK(uqw); 1820 break; 1821 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1822 __P4SETMASK(rmbt); 1823 break; 1824 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1825 __P4SETMASK(rbt); 1826 break; 1827 case PMC_EV_P4_RESOURCE_STALL: 1828 __P4SETMASK(rs); 1829 break; 1830 case PMC_EV_P4_WC_BUFFER: 1831 __P4SETMASK(wb); 1832 break; 1833 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1834 case PMC_EV_P4_B2B_CYCLES: 1835 case PMC_EV_P4_BNR: 1836 case PMC_EV_P4_SNOOP: 1837 case PMC_EV_P4_RESPONSE: 1838 break; 1839 case PMC_EV_P4_FRONT_END_EVENT: 1840 __P4SETMASK(fee); 1841 break; 1842 case PMC_EV_P4_EXECUTION_EVENT: 1843 __P4SETMASK(ee); 1844 break; 1845 case PMC_EV_P4_REPLAY_EVENT: 1846 __P4SETMASK(re); 1847 break; 1848 case PMC_EV_P4_INSTR_RETIRED: 1849 __P4SETMASK(insret); 1850 break; 1851 case PMC_EV_P4_UOPS_RETIRED: 1852 __P4SETMASK(ur); 1853 break; 1854 case PMC_EV_P4_UOP_TYPE: 1855 __P4SETMASK(ut); 1856 break; 1857 case PMC_EV_P4_BRANCH_RETIRED: 1858 __P4SETMASK(br); 1859 break; 1860 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1861 __P4SETMASK(mbr); 1862 break; 1863 case PMC_EV_P4_X87_ASSIST: 1864 __P4SETMASK(xa); 1865 break; 1866 case PMC_EV_P4_MACHINE_CLEAR: 1867 __P4SETMASK(machclr); 1868 break; 1869 default: 1870 return (-1); 1871 } 1872 1873 /* process additional flags */ 1874 while ((p = strsep(&ctrspec, ",")) != NULL) { 1875 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1876 q = strchr(p, '='); 1877 if (*++q == '\0') /* skip '=' */ 1878 return (-1); 1879 1880 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1881 cccractivemask = 0x0; 1882 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1883 cccractivemask = 0x1; 1884 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1885 cccractivemask = 0x2; 1886 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1887 cccractivemask = 0x3; 1888 else 1889 return (-1); 1890 1891 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1892 if (has_busreqtype == 0) 1893 return (-1); 1894 1895 q = strchr(p, '='); 1896 if (*++q == '\0') /* skip '=' */ 1897 return (-1); 1898 1899 count = strtol(q, &e, 0); 1900 if (e == q || *e != '\0') 1901 return (-1); 1902 evmask = (evmask & ~0x1F) | (count & 0x1F); 1903 } else if (KWMATCH(p, P4_KW_CASCADE)) 1904 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1905 else if (KWMATCH(p, P4_KW_EDGE)) 1906 pmc_config->pm_caps |= PMC_CAP_EDGE; 1907 else if (KWMATCH(p, P4_KW_INV)) 1908 pmc_config->pm_caps |= PMC_CAP_INVERT; 1909 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1910 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1911 return (-1); 1912 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1913 } else if (KWMATCH(p, P4_KW_OS)) 1914 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1915 else if (KWMATCH(p, P4_KW_PRECISE)) 1916 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1917 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1918 if (has_tag == 0) 1919 return (-1); 1920 1921 q = strchr(p, '='); 1922 if (*++q == '\0') /* skip '=' */ 1923 return (-1); 1924 1925 count = strtol(q, &e, 0); 1926 if (e == q || *e != '\0') 1927 return (-1); 1928 1929 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1930 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1931 P4_ESCR_TO_TAG_VALUE(count); 1932 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1933 q = strchr(p, '='); 1934 if (*++q == '\0') /* skip '=' */ 1935 return (-1); 1936 1937 count = strtol(q, &e, 0); 1938 if (e == q || *e != '\0') 1939 return (-1); 1940 1941 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1942 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1943 ~P4_CCCR_THRESHOLD_MASK; 1944 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1945 P4_CCCR_TO_THRESHOLD(count); 1946 } else if (KWMATCH(p, P4_KW_USR)) 1947 pmc_config->pm_caps |= PMC_CAP_USER; 1948 else 1949 return (-1); 1950 } 1951 1952 /* other post processing */ 1953 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1954 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1955 pe == PMC_EV_P4_BSQ_ALLOCATION) 1956 pmc_config->pm_caps |= PMC_CAP_EDGE; 1957 1958 /* fill in thread activity mask */ 1959 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1960 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1961 1962 if (evmask) 1963 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1964 1965 switch (pe) { 1966 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1967 if ((evmask & 0x06) == 0x06 || 1968 (evmask & 0x18) == 0x18) 1969 return (-1); /* can't have own+other bits together */ 1970 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1971 evmask = 0x1D; 1972 break; 1973 case PMC_EV_P4_MACHINE_CLEAR: 1974 /* only one bit is allowed to be set */ 1975 if ((evmask & (evmask - 1)) != 0) 1976 return (-1); 1977 if (evmask == 0) { 1978 evmask = 0x1; /* 'CLEAR' */ 1979 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1980 } 1981 break; 1982 default: 1983 if (evmask == 0 && pmask) { 1984 for (pm = pmask; pm->pm_name; pm++) 1985 evmask |= pm->pm_value; 1986 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1987 } 1988 } 1989 1990 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1991 P4_ESCR_TO_EVENT_MASK(evmask); 1992 1993 return (0); 1994 } 1995 1996 #endif 1997 1998 #if defined(__i386__) 1999 2000 /* 2001 * Pentium style PMCs 2002 */ 2003 2004 static struct pmc_event_alias p5_aliases[] = { 2005 EV_ALIAS("branches", "p5-taken-branches"), 2006 EV_ALIAS("cycles", "tsc"), 2007 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 2008 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 2009 EV_ALIAS("instructions", "p5-instructions-executed"), 2010 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 2011 EV_ALIAS("unhalted-cycles", 2012 "p5-number-of-cycles-not-in-halt-state"), 2013 EV_ALIAS(NULL, NULL) 2014 }; 2015 2016 static int 2017 p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 2018 struct pmc_op_pmcallocate *pmc_config) 2019 { 2020 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 2021 } 2022 2023 /* 2024 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 2025 * and Pentium M CPUs. 2026 */ 2027 2028 static struct pmc_event_alias p6_aliases[] = { 2029 EV_ALIAS("branches", "p6-br-inst-retired"), 2030 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 2031 EV_ALIAS("cycles", "tsc"), 2032 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 2033 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 2034 EV_ALIAS("instructions", "p6-inst-retired"), 2035 EV_ALIAS("interrupts", "p6-hw-int-rx"), 2036 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 2037 EV_ALIAS(NULL, NULL) 2038 }; 2039 2040 #define P6_KW_CMASK "cmask" 2041 #define P6_KW_EDGE "edge" 2042 #define P6_KW_INV "inv" 2043 #define P6_KW_OS "os" 2044 #define P6_KW_UMASK "umask" 2045 #define P6_KW_USR "usr" 2046 2047 static struct pmc_masks p6_mask_mesi[] = { 2048 PMCMASK(m, 0x01), 2049 PMCMASK(e, 0x02), 2050 PMCMASK(s, 0x04), 2051 PMCMASK(i, 0x08), 2052 NULLMASK 2053 }; 2054 2055 static struct pmc_masks p6_mask_mesihw[] = { 2056 PMCMASK(m, 0x01), 2057 PMCMASK(e, 0x02), 2058 PMCMASK(s, 0x04), 2059 PMCMASK(i, 0x08), 2060 PMCMASK(nonhw, 0x00), 2061 PMCMASK(hw, 0x10), 2062 PMCMASK(both, 0x30), 2063 NULLMASK 2064 }; 2065 2066 static struct pmc_masks p6_mask_hw[] = { 2067 PMCMASK(nonhw, 0x00), 2068 PMCMASK(hw, 0x10), 2069 PMCMASK(both, 0x30), 2070 NULLMASK 2071 }; 2072 2073 static struct pmc_masks p6_mask_any[] = { 2074 PMCMASK(self, 0x00), 2075 PMCMASK(any, 0x20), 2076 NULLMASK 2077 }; 2078 2079 static struct pmc_masks p6_mask_ekp[] = { 2080 PMCMASK(nta, 0x00), 2081 PMCMASK(t1, 0x01), 2082 PMCMASK(t2, 0x02), 2083 PMCMASK(wos, 0x03), 2084 NULLMASK 2085 }; 2086 2087 static struct pmc_masks p6_mask_pps[] = { 2088 PMCMASK(packed-and-scalar, 0x00), 2089 PMCMASK(scalar, 0x01), 2090 NULLMASK 2091 }; 2092 2093 static struct pmc_masks p6_mask_mite[] = { 2094 PMCMASK(packed-multiply, 0x01), 2095 PMCMASK(packed-shift, 0x02), 2096 PMCMASK(pack, 0x04), 2097 PMCMASK(unpack, 0x08), 2098 PMCMASK(packed-logical, 0x10), 2099 PMCMASK(packed-arithmetic, 0x20), 2100 NULLMASK 2101 }; 2102 2103 static struct pmc_masks p6_mask_fmt[] = { 2104 PMCMASK(mmxtofp, 0x00), 2105 PMCMASK(fptommx, 0x01), 2106 NULLMASK 2107 }; 2108 2109 static struct pmc_masks p6_mask_sr[] = { 2110 PMCMASK(es, 0x01), 2111 PMCMASK(ds, 0x02), 2112 PMCMASK(fs, 0x04), 2113 PMCMASK(gs, 0x08), 2114 NULLMASK 2115 }; 2116 2117 static struct pmc_masks p6_mask_eet[] = { 2118 PMCMASK(all, 0x00), 2119 PMCMASK(freq, 0x02), 2120 NULLMASK 2121 }; 2122 2123 static struct pmc_masks p6_mask_efur[] = { 2124 PMCMASK(all, 0x00), 2125 PMCMASK(loadop, 0x01), 2126 PMCMASK(stdsta, 0x02), 2127 NULLMASK 2128 }; 2129 2130 static struct pmc_masks p6_mask_essir[] = { 2131 PMCMASK(sse-packed-single, 0x00), 2132 PMCMASK(sse-packed-single-scalar-single, 0x01), 2133 PMCMASK(sse2-packed-double, 0x02), 2134 PMCMASK(sse2-scalar-double, 0x03), 2135 NULLMASK 2136 }; 2137 2138 static struct pmc_masks p6_mask_esscir[] = { 2139 PMCMASK(sse-packed-single, 0x00), 2140 PMCMASK(sse-scalar-single, 0x01), 2141 PMCMASK(sse2-packed-double, 0x02), 2142 PMCMASK(sse2-scalar-double, 0x03), 2143 NULLMASK 2144 }; 2145 2146 /* P6 event parser */ 2147 static int 2148 p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 2149 struct pmc_op_pmcallocate *pmc_config) 2150 { 2151 char *e, *p, *q; 2152 uint64_t evmask; 2153 int count, n; 2154 const struct pmc_masks *pm, *pmask; 2155 2156 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2157 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 2158 2159 evmask = 0; 2160 2161 #define P6MASKSET(M) pmask = p6_mask_ ## M 2162 2163 switch(pe) { 2164 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 2165 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 2166 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 2167 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 2168 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2169 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2170 case PMC_EV_P6_BUS_TRAN_BRD: 2171 case PMC_EV_P6_BUS_TRAN_RFO: 2172 case PMC_EV_P6_BUS_TRANS_WB: 2173 case PMC_EV_P6_BUS_TRAN_IFETCH: 2174 case PMC_EV_P6_BUS_TRAN_INVAL: 2175 case PMC_EV_P6_BUS_TRAN_PWR: 2176 case PMC_EV_P6_BUS_TRANS_P: 2177 case PMC_EV_P6_BUS_TRANS_IO: 2178 case PMC_EV_P6_BUS_TRAN_DEF: 2179 case PMC_EV_P6_BUS_TRAN_BURST: 2180 case PMC_EV_P6_BUS_TRAN_ANY: 2181 case PMC_EV_P6_BUS_TRAN_MEM: 2182 P6MASKSET(any); break; 2183 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2184 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2185 P6MASKSET(ekp); break; 2186 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2187 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2188 P6MASKSET(pps); break; 2189 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2190 P6MASKSET(mite); break; 2191 case PMC_EV_P6_FP_MMX_TRANS: 2192 P6MASKSET(fmt); break; 2193 case PMC_EV_P6_SEG_RENAME_STALLS: 2194 case PMC_EV_P6_SEG_REG_RENAMES: 2195 P6MASKSET(sr); break; 2196 case PMC_EV_P6_EMON_EST_TRANS: 2197 P6MASKSET(eet); break; 2198 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2199 P6MASKSET(efur); break; 2200 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2201 P6MASKSET(essir); break; 2202 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2203 P6MASKSET(esscir); break; 2204 default: 2205 pmask = NULL; 2206 break; 2207 } 2208 2209 /* Pentium M PMCs have a few events with different semantics */ 2210 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2211 if (pe == PMC_EV_P6_L2_LD || 2212 pe == PMC_EV_P6_L2_LINES_IN || 2213 pe == PMC_EV_P6_L2_LINES_OUT) 2214 P6MASKSET(mesihw); 2215 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2216 P6MASKSET(hw); 2217 } 2218 2219 /* Parse additional modifiers if present */ 2220 while ((p = strsep(&ctrspec, ",")) != NULL) { 2221 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2222 q = strchr(p, '='); 2223 if (*++q == '\0') /* skip '=' */ 2224 return (-1); 2225 count = strtol(q, &e, 0); 2226 if (e == q || *e != '\0') 2227 return (-1); 2228 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2229 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2230 P6_EVSEL_TO_CMASK(count); 2231 } else if (KWMATCH(p, P6_KW_EDGE)) { 2232 pmc_config->pm_caps |= PMC_CAP_EDGE; 2233 } else if (KWMATCH(p, P6_KW_INV)) { 2234 pmc_config->pm_caps |= PMC_CAP_INVERT; 2235 } else if (KWMATCH(p, P6_KW_OS)) { 2236 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2237 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2238 evmask = 0; 2239 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2240 return (-1); 2241 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2242 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2243 pe == PMC_EV_P6_BUS_TRAN_BRD || 2244 pe == PMC_EV_P6_BUS_TRAN_RFO || 2245 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2246 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2247 pe == PMC_EV_P6_BUS_TRAN_PWR || 2248 pe == PMC_EV_P6_BUS_TRAN_DEF || 2249 pe == PMC_EV_P6_BUS_TRAN_BURST || 2250 pe == PMC_EV_P6_BUS_TRAN_ANY || 2251 pe == PMC_EV_P6_BUS_TRAN_MEM || 2252 pe == PMC_EV_P6_BUS_TRANS_IO || 2253 pe == PMC_EV_P6_BUS_TRANS_P || 2254 pe == PMC_EV_P6_BUS_TRANS_WB || 2255 pe == PMC_EV_P6_EMON_EST_TRANS || 2256 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2257 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2258 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2259 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2260 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2261 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2262 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2263 pe == PMC_EV_P6_FP_MMX_TRANS) 2264 && (n > 1)) /* Only one mask keyword is allowed. */ 2265 return (-1); 2266 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2267 } else if (KWMATCH(p, P6_KW_USR)) { 2268 pmc_config->pm_caps |= PMC_CAP_USER; 2269 } else 2270 return (-1); 2271 } 2272 2273 /* post processing */ 2274 switch (pe) { 2275 2276 /* 2277 * The following events default to an evmask of 0 2278 */ 2279 2280 /* default => 'self' */ 2281 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2282 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2283 case PMC_EV_P6_BUS_TRAN_BRD: 2284 case PMC_EV_P6_BUS_TRAN_RFO: 2285 case PMC_EV_P6_BUS_TRANS_WB: 2286 case PMC_EV_P6_BUS_TRAN_IFETCH: 2287 case PMC_EV_P6_BUS_TRAN_INVAL: 2288 case PMC_EV_P6_BUS_TRAN_PWR: 2289 case PMC_EV_P6_BUS_TRANS_P: 2290 case PMC_EV_P6_BUS_TRANS_IO: 2291 case PMC_EV_P6_BUS_TRAN_DEF: 2292 case PMC_EV_P6_BUS_TRAN_BURST: 2293 case PMC_EV_P6_BUS_TRAN_ANY: 2294 case PMC_EV_P6_BUS_TRAN_MEM: 2295 2296 /* default => 'nta' */ 2297 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2298 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2299 2300 /* default => 'packed and scalar' */ 2301 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2302 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2303 2304 /* default => 'mmx to fp transitions' */ 2305 case PMC_EV_P6_FP_MMX_TRANS: 2306 2307 /* default => 'SSE Packed Single' */ 2308 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2309 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2310 2311 /* default => 'all fused micro-ops' */ 2312 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2313 2314 /* default => 'all transitions' */ 2315 case PMC_EV_P6_EMON_EST_TRANS: 2316 break; 2317 2318 case PMC_EV_P6_MMX_UOPS_EXEC: 2319 evmask = 0x0F; /* only value allowed */ 2320 break; 2321 2322 default: 2323 /* 2324 * For all other events, set the default event mask 2325 * to a logical OR of all the allowed event mask bits. 2326 */ 2327 if (evmask == 0 && pmask) { 2328 for (pm = pmask; pm->pm_name; pm++) 2329 evmask |= pm->pm_value; 2330 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2331 } 2332 2333 break; 2334 } 2335 2336 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2337 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2338 P6_EVSEL_TO_UMASK(evmask); 2339 2340 return (0); 2341 } 2342 2343 #endif 2344 2345 #if defined(__i386__) || defined(__amd64__) 2346 static int 2347 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2348 struct pmc_op_pmcallocate *pmc_config) 2349 { 2350 if (pe != PMC_EV_TSC_TSC) 2351 return (-1); 2352 2353 /* TSC events must be unqualified. */ 2354 if (ctrspec && *ctrspec != '\0') 2355 return (-1); 2356 2357 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2358 pmc_config->pm_caps |= PMC_CAP_READ; 2359 2360 return (0); 2361 } 2362 #endif 2363 2364 static struct pmc_event_alias generic_aliases[] = { 2365 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 2366 EV_ALIAS(NULL, NULL) 2367 }; 2368 2369 static int 2370 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 2371 struct pmc_op_pmcallocate *pmc_config) 2372 { 2373 (void)ctrspec; 2374 (void)pmc_config; 2375 2376 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 2377 return (-1); 2378 2379 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2380 return (0); 2381 } 2382 2383 #if defined(__arm__) 2384 #if defined(__XSCALE__) 2385 2386 static struct pmc_event_alias xscale_aliases[] = { 2387 EV_ALIAS("branches", "BRANCH_RETIRED"), 2388 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2389 EV_ALIAS("dc-misses", "DC_MISS"), 2390 EV_ALIAS("ic-misses", "IC_MISS"), 2391 EV_ALIAS("instructions", "INSTR_RETIRED"), 2392 EV_ALIAS(NULL, NULL) 2393 }; 2394 static int 2395 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2396 struct pmc_op_pmcallocate *pmc_config __unused) 2397 { 2398 switch (pe) { 2399 default: 2400 break; 2401 } 2402 2403 return (0); 2404 } 2405 #endif 2406 2407 static struct pmc_event_alias armv7_aliases[] = { 2408 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 2409 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 2410 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2411 EV_ALIAS(NULL, NULL) 2412 }; 2413 static int 2414 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2415 struct pmc_op_pmcallocate *pmc_config __unused) 2416 { 2417 switch (pe) { 2418 default: 2419 break; 2420 } 2421 2422 return (0); 2423 } 2424 #endif 2425 2426 #if defined(__mips__) 2427 2428 static struct pmc_event_alias mips24k_aliases[] = { 2429 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2430 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2431 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2432 EV_ALIAS(NULL, NULL) 2433 }; 2434 2435 static struct pmc_event_alias octeon_aliases[] = { 2436 EV_ALIAS("instructions", "RET"), 2437 EV_ALIAS("branches", "BR"), 2438 EV_ALIAS("branch-mispredicts", "BRMIS"), 2439 EV_ALIAS(NULL, NULL) 2440 }; 2441 2442 #define MIPS_KW_OS "os" 2443 #define MIPS_KW_USR "usr" 2444 #define MIPS_KW_ANYTHREAD "anythread" 2445 2446 static int 2447 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2448 struct pmc_op_pmcallocate *pmc_config __unused) 2449 { 2450 char *p; 2451 2452 (void) pe; 2453 2454 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2455 2456 while ((p = strsep(&ctrspec, ",")) != NULL) { 2457 if (KWMATCH(p, MIPS_KW_OS)) 2458 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2459 else if (KWMATCH(p, MIPS_KW_USR)) 2460 pmc_config->pm_caps |= PMC_CAP_USER; 2461 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 2462 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2463 else 2464 return (-1); 2465 } 2466 2467 return (0); 2468 } 2469 2470 #endif /* __mips__ */ 2471 2472 #if defined(__powerpc__) 2473 2474 static struct pmc_event_alias ppc7450_aliases[] = { 2475 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2476 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2477 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2478 EV_ALIAS(NULL, NULL) 2479 }; 2480 2481 static struct pmc_event_alias ppc970_aliases[] = { 2482 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2483 EV_ALIAS("cycles", "CYCLES"), 2484 EV_ALIAS(NULL, NULL) 2485 }; 2486 2487 #define POWERPC_KW_OS "os" 2488 #define POWERPC_KW_USR "usr" 2489 #define POWERPC_KW_ANYTHREAD "anythread" 2490 2491 static int 2492 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2493 struct pmc_op_pmcallocate *pmc_config __unused) 2494 { 2495 char *p; 2496 2497 (void) pe; 2498 2499 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2500 2501 while ((p = strsep(&ctrspec, ",")) != NULL) { 2502 if (KWMATCH(p, POWERPC_KW_OS)) 2503 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2504 else if (KWMATCH(p, POWERPC_KW_USR)) 2505 pmc_config->pm_caps |= PMC_CAP_USER; 2506 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 2507 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2508 else 2509 return (-1); 2510 } 2511 2512 return (0); 2513 } 2514 2515 #endif /* __powerpc__ */ 2516 2517 2518 /* 2519 * Match an event name `name' with its canonical form. 2520 * 2521 * Matches are case insensitive and spaces, periods, underscores and 2522 * hyphen characters are considered to match each other. 2523 * 2524 * Returns 1 for a match, 0 otherwise. 2525 */ 2526 2527 static int 2528 pmc_match_event_name(const char *name, const char *canonicalname) 2529 { 2530 int cc, nc; 2531 const unsigned char *c, *n; 2532 2533 c = (const unsigned char *) canonicalname; 2534 n = (const unsigned char *) name; 2535 2536 for (; (nc = *n) && (cc = *c); n++, c++) { 2537 2538 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2539 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2540 continue; 2541 2542 if (toupper(nc) == toupper(cc)) 2543 continue; 2544 2545 2546 return (0); 2547 } 2548 2549 if (*n == '\0' && *c == '\0') 2550 return (1); 2551 2552 return (0); 2553 } 2554 2555 /* 2556 * Match an event name against all the event named supported by a 2557 * PMC class. 2558 * 2559 * Returns an event descriptor pointer on match or NULL otherwise. 2560 */ 2561 static const struct pmc_event_descr * 2562 pmc_match_event_class(const char *name, 2563 const struct pmc_class_descr *pcd) 2564 { 2565 size_t n; 2566 const struct pmc_event_descr *ev; 2567 2568 ev = pcd->pm_evc_event_table; 2569 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2570 if (pmc_match_event_name(name, ev->pm_ev_name)) 2571 return (ev); 2572 2573 return (NULL); 2574 } 2575 2576 static int 2577 pmc_mdep_is_compatible_class(enum pmc_class pc) 2578 { 2579 size_t n; 2580 2581 for (n = 0; n < pmc_mdep_class_list_size; n++) 2582 if (pmc_mdep_class_list[n] == pc) 2583 return (1); 2584 return (0); 2585 } 2586 2587 /* 2588 * API entry points 2589 */ 2590 2591 int 2592 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2593 uint32_t flags, int cpu, pmc_id_t *pmcid) 2594 { 2595 size_t n; 2596 int retval; 2597 char *r, *spec_copy; 2598 const char *ctrname; 2599 const struct pmc_event_descr *ev; 2600 const struct pmc_event_alias *alias; 2601 struct pmc_op_pmcallocate pmc_config; 2602 const struct pmc_class_descr *pcd; 2603 2604 spec_copy = NULL; 2605 retval = -1; 2606 2607 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2608 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2609 errno = EINVAL; 2610 goto out; 2611 } 2612 2613 /* replace an event alias with the canonical event specifier */ 2614 if (pmc_mdep_event_aliases) 2615 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2616 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2617 spec_copy = strdup(alias->pm_spec); 2618 break; 2619 } 2620 2621 if (spec_copy == NULL) 2622 spec_copy = strdup(ctrspec); 2623 2624 r = spec_copy; 2625 ctrname = strsep(&r, ","); 2626 2627 /* 2628 * If a explicit class prefix was given by the user, restrict the 2629 * search for the event to the specified PMC class. 2630 */ 2631 ev = NULL; 2632 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2633 pcd = pmc_class_table[n]; 2634 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2635 strncasecmp(ctrname, pcd->pm_evc_name, 2636 pcd->pm_evc_name_size) == 0) { 2637 if ((ev = pmc_match_event_class(ctrname + 2638 pcd->pm_evc_name_size, pcd)) == NULL) { 2639 errno = EINVAL; 2640 goto out; 2641 } 2642 break; 2643 } 2644 } 2645 2646 /* 2647 * Otherwise, search for this event in all compatible PMC 2648 * classes. 2649 */ 2650 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2651 pcd = pmc_class_table[n]; 2652 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2653 ev = pmc_match_event_class(ctrname, pcd); 2654 } 2655 2656 if (ev == NULL) { 2657 errno = EINVAL; 2658 goto out; 2659 } 2660 2661 bzero(&pmc_config, sizeof(pmc_config)); 2662 pmc_config.pm_ev = ev->pm_ev_code; 2663 pmc_config.pm_class = pcd->pm_evc_class; 2664 pmc_config.pm_cpu = cpu; 2665 pmc_config.pm_mode = mode; 2666 pmc_config.pm_flags = flags; 2667 2668 if (PMC_IS_SAMPLING_MODE(mode)) 2669 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2670 2671 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2672 errno = EINVAL; 2673 goto out; 2674 } 2675 2676 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2677 goto out; 2678 2679 *pmcid = pmc_config.pm_pmcid; 2680 2681 retval = 0; 2682 2683 out: 2684 if (spec_copy) 2685 free(spec_copy); 2686 2687 return (retval); 2688 } 2689 2690 int 2691 pmc_attach(pmc_id_t pmc, pid_t pid) 2692 { 2693 struct pmc_op_pmcattach pmc_attach_args; 2694 2695 pmc_attach_args.pm_pmc = pmc; 2696 pmc_attach_args.pm_pid = pid; 2697 2698 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2699 } 2700 2701 int 2702 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2703 { 2704 unsigned int i; 2705 enum pmc_class cl; 2706 2707 cl = PMC_ID_TO_CLASS(pmcid); 2708 for (i = 0; i < cpu_info.pm_nclass; i++) 2709 if (cpu_info.pm_classes[i].pm_class == cl) { 2710 *caps = cpu_info.pm_classes[i].pm_caps; 2711 return (0); 2712 } 2713 errno = EINVAL; 2714 return (-1); 2715 } 2716 2717 int 2718 pmc_configure_logfile(int fd) 2719 { 2720 struct pmc_op_configurelog cla; 2721 2722 cla.pm_logfd = fd; 2723 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2724 return (-1); 2725 return (0); 2726 } 2727 2728 int 2729 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2730 { 2731 if (pmc_syscall == -1) { 2732 errno = ENXIO; 2733 return (-1); 2734 } 2735 2736 *pci = &cpu_info; 2737 return (0); 2738 } 2739 2740 int 2741 pmc_detach(pmc_id_t pmc, pid_t pid) 2742 { 2743 struct pmc_op_pmcattach pmc_detach_args; 2744 2745 pmc_detach_args.pm_pmc = pmc; 2746 pmc_detach_args.pm_pid = pid; 2747 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2748 } 2749 2750 int 2751 pmc_disable(int cpu, int pmc) 2752 { 2753 struct pmc_op_pmcadmin ssa; 2754 2755 ssa.pm_cpu = cpu; 2756 ssa.pm_pmc = pmc; 2757 ssa.pm_state = PMC_STATE_DISABLED; 2758 return (PMC_CALL(PMCADMIN, &ssa)); 2759 } 2760 2761 int 2762 pmc_enable(int cpu, int pmc) 2763 { 2764 struct pmc_op_pmcadmin ssa; 2765 2766 ssa.pm_cpu = cpu; 2767 ssa.pm_pmc = pmc; 2768 ssa.pm_state = PMC_STATE_FREE; 2769 return (PMC_CALL(PMCADMIN, &ssa)); 2770 } 2771 2772 /* 2773 * Return a list of events known to a given PMC class. 'cl' is the 2774 * PMC class identifier, 'eventnames' is the returned list of 'const 2775 * char *' pointers pointing to the names of the events. 'nevents' is 2776 * the number of event name pointers returned. 2777 * 2778 * The space for 'eventnames' is allocated using malloc(3). The caller 2779 * is responsible for freeing this space when done. 2780 */ 2781 int 2782 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2783 int *nevents) 2784 { 2785 int count; 2786 const char **names; 2787 const struct pmc_event_descr *ev; 2788 2789 switch (cl) 2790 { 2791 case PMC_CLASS_IAF: 2792 ev = iaf_event_table; 2793 count = PMC_EVENT_TABLE_SIZE(iaf); 2794 break; 2795 case PMC_CLASS_IAP: 2796 /* 2797 * Return the most appropriate set of event name 2798 * spellings for the current CPU. 2799 */ 2800 switch (cpu_info.pm_cputype) { 2801 default: 2802 case PMC_CPU_INTEL_ATOM: 2803 ev = atom_event_table; 2804 count = PMC_EVENT_TABLE_SIZE(atom); 2805 break; 2806 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2807 ev = atom_silvermont_event_table; 2808 count = PMC_EVENT_TABLE_SIZE(atom_silvermont); 2809 break; 2810 case PMC_CPU_INTEL_CORE: 2811 ev = core_event_table; 2812 count = PMC_EVENT_TABLE_SIZE(core); 2813 break; 2814 case PMC_CPU_INTEL_CORE2: 2815 case PMC_CPU_INTEL_CORE2EXTREME: 2816 ev = core2_event_table; 2817 count = PMC_EVENT_TABLE_SIZE(core2); 2818 break; 2819 case PMC_CPU_INTEL_COREI7: 2820 ev = corei7_event_table; 2821 count = PMC_EVENT_TABLE_SIZE(corei7); 2822 break; 2823 case PMC_CPU_INTEL_NEHALEM_EX: 2824 ev = nehalem_ex_event_table; 2825 count = PMC_EVENT_TABLE_SIZE(nehalem_ex); 2826 break; 2827 case PMC_CPU_INTEL_HASWELL: 2828 ev = haswell_event_table; 2829 count = PMC_EVENT_TABLE_SIZE(haswell); 2830 break; 2831 case PMC_CPU_INTEL_HASWELL_XEON: 2832 ev = haswell_xeon_event_table; 2833 count = PMC_EVENT_TABLE_SIZE(haswell_xeon); 2834 break; 2835 case PMC_CPU_INTEL_IVYBRIDGE: 2836 ev = ivybridge_event_table; 2837 count = PMC_EVENT_TABLE_SIZE(ivybridge); 2838 break; 2839 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2840 ev = ivybridge_xeon_event_table; 2841 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 2842 break; 2843 case PMC_CPU_INTEL_SANDYBRIDGE: 2844 ev = sandybridge_event_table; 2845 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2846 break; 2847 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2848 ev = sandybridge_xeon_event_table; 2849 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 2850 break; 2851 case PMC_CPU_INTEL_WESTMERE: 2852 ev = westmere_event_table; 2853 count = PMC_EVENT_TABLE_SIZE(westmere); 2854 break; 2855 case PMC_CPU_INTEL_WESTMERE_EX: 2856 ev = westmere_ex_event_table; 2857 count = PMC_EVENT_TABLE_SIZE(westmere_ex); 2858 break; 2859 } 2860 break; 2861 case PMC_CLASS_UCF: 2862 ev = ucf_event_table; 2863 count = PMC_EVENT_TABLE_SIZE(ucf); 2864 break; 2865 case PMC_CLASS_UCP: 2866 /* 2867 * Return the most appropriate set of event name 2868 * spellings for the current CPU. 2869 */ 2870 switch (cpu_info.pm_cputype) { 2871 default: 2872 case PMC_CPU_INTEL_COREI7: 2873 ev = corei7uc_event_table; 2874 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2875 break; 2876 case PMC_CPU_INTEL_HASWELL: 2877 ev = haswelluc_event_table; 2878 count = PMC_EVENT_TABLE_SIZE(haswelluc); 2879 break; 2880 case PMC_CPU_INTEL_SANDYBRIDGE: 2881 ev = sandybridgeuc_event_table; 2882 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2883 break; 2884 case PMC_CPU_INTEL_WESTMERE: 2885 ev = westmereuc_event_table; 2886 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2887 break; 2888 } 2889 break; 2890 case PMC_CLASS_TSC: 2891 ev = tsc_event_table; 2892 count = PMC_EVENT_TABLE_SIZE(tsc); 2893 break; 2894 case PMC_CLASS_K7: 2895 ev = k7_event_table; 2896 count = PMC_EVENT_TABLE_SIZE(k7); 2897 break; 2898 case PMC_CLASS_K8: 2899 ev = k8_event_table; 2900 count = PMC_EVENT_TABLE_SIZE(k8); 2901 break; 2902 case PMC_CLASS_P4: 2903 ev = p4_event_table; 2904 count = PMC_EVENT_TABLE_SIZE(p4); 2905 break; 2906 case PMC_CLASS_P5: 2907 ev = p5_event_table; 2908 count = PMC_EVENT_TABLE_SIZE(p5); 2909 break; 2910 case PMC_CLASS_P6: 2911 ev = p6_event_table; 2912 count = PMC_EVENT_TABLE_SIZE(p6); 2913 break; 2914 case PMC_CLASS_XSCALE: 2915 ev = xscale_event_table; 2916 count = PMC_EVENT_TABLE_SIZE(xscale); 2917 break; 2918 case PMC_CLASS_ARMV7: 2919 ev = armv7_event_table; 2920 count = PMC_EVENT_TABLE_SIZE(armv7); 2921 break; 2922 case PMC_CLASS_MIPS24K: 2923 ev = mips24k_event_table; 2924 count = PMC_EVENT_TABLE_SIZE(mips24k); 2925 break; 2926 case PMC_CLASS_OCTEON: 2927 ev = octeon_event_table; 2928 count = PMC_EVENT_TABLE_SIZE(octeon); 2929 break; 2930 case PMC_CLASS_PPC7450: 2931 ev = ppc7450_event_table; 2932 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2933 break; 2934 case PMC_CLASS_PPC970: 2935 ev = ppc970_event_table; 2936 count = PMC_EVENT_TABLE_SIZE(ppc970); 2937 break; 2938 case PMC_CLASS_SOFT: 2939 ev = soft_event_table; 2940 count = soft_event_info.pm_nevent; 2941 break; 2942 default: 2943 errno = EINVAL; 2944 return (-1); 2945 } 2946 2947 if ((names = malloc(count * sizeof(const char *))) == NULL) 2948 return (-1); 2949 2950 *eventnames = names; 2951 *nevents = count; 2952 2953 for (;count--; ev++, names++) 2954 *names = ev->pm_ev_name; 2955 2956 return (0); 2957 } 2958 2959 int 2960 pmc_flush_logfile(void) 2961 { 2962 return (PMC_CALL(FLUSHLOG,0)); 2963 } 2964 2965 int 2966 pmc_close_logfile(void) 2967 { 2968 return (PMC_CALL(CLOSELOG,0)); 2969 } 2970 2971 int 2972 pmc_get_driver_stats(struct pmc_driverstats *ds) 2973 { 2974 struct pmc_op_getdriverstats gms; 2975 2976 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2977 return (-1); 2978 2979 /* copy out fields in the current userland<->library interface */ 2980 ds->pm_intr_ignored = gms.pm_intr_ignored; 2981 ds->pm_intr_processed = gms.pm_intr_processed; 2982 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2983 ds->pm_syscalls = gms.pm_syscalls; 2984 ds->pm_syscall_errors = gms.pm_syscall_errors; 2985 ds->pm_buffer_requests = gms.pm_buffer_requests; 2986 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 2987 ds->pm_log_sweeps = gms.pm_log_sweeps; 2988 return (0); 2989 } 2990 2991 int 2992 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 2993 { 2994 struct pmc_op_getmsr gm; 2995 2996 gm.pm_pmcid = pmc; 2997 if (PMC_CALL(PMCGETMSR, &gm) < 0) 2998 return (-1); 2999 *msr = gm.pm_msr; 3000 return (0); 3001 } 3002 3003 int 3004 pmc_init(void) 3005 { 3006 int error, pmc_mod_id; 3007 unsigned int n; 3008 uint32_t abi_version; 3009 struct module_stat pmc_modstat; 3010 struct pmc_op_getcpuinfo op_cpu_info; 3011 #if defined(__amd64__) || defined(__i386__) 3012 int cpu_has_iaf_counters; 3013 unsigned int t; 3014 #endif 3015 3016 if (pmc_syscall != -1) /* already inited */ 3017 return (0); 3018 3019 /* retrieve the system call number from the KLD */ 3020 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 3021 return (-1); 3022 3023 pmc_modstat.version = sizeof(struct module_stat); 3024 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 3025 return (-1); 3026 3027 pmc_syscall = pmc_modstat.data.intval; 3028 3029 /* check the kernel module's ABI against our compiled-in version */ 3030 abi_version = PMC_VERSION; 3031 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 3032 return (pmc_syscall = -1); 3033 3034 /* ignore patch & minor numbers for the comparision */ 3035 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 3036 errno = EPROGMISMATCH; 3037 return (pmc_syscall = -1); 3038 } 3039 3040 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 3041 return (pmc_syscall = -1); 3042 3043 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 3044 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 3045 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 3046 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 3047 for (n = 0; n < cpu_info.pm_nclass; n++) 3048 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 3049 3050 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 3051 sizeof(struct pmc_class_descr *)); 3052 3053 if (pmc_class_table == NULL) 3054 return (-1); 3055 3056 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 3057 pmc_class_table[n] = NULL; 3058 3059 /* 3060 * Get soft events list. 3061 */ 3062 soft_event_info.pm_class = PMC_CLASS_SOFT; 3063 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 3064 return (pmc_syscall = -1); 3065 3066 /* Map soft events to static list. */ 3067 for (n = 0; n < soft_event_info.pm_nevent; n++) { 3068 soft_event_table[n].pm_ev_name = 3069 soft_event_info.pm_events[n].pm_ev_name; 3070 soft_event_table[n].pm_ev_code = 3071 soft_event_info.pm_events[n].pm_ev_code; 3072 } 3073 soft_class_table_descr.pm_evc_event_table_size = \ 3074 soft_event_info.pm_nevent; 3075 soft_class_table_descr.pm_evc_event_table = \ 3076 soft_event_table; 3077 3078 /* 3079 * Fill in the class table. 3080 */ 3081 n = 0; 3082 3083 /* Fill soft events information. */ 3084 pmc_class_table[n++] = &soft_class_table_descr; 3085 #if defined(__amd64__) || defined(__i386__) 3086 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 3087 pmc_class_table[n++] = &tsc_class_table_descr; 3088 3089 /* 3090 * Check if this CPU has fixed function counters. 3091 */ 3092 cpu_has_iaf_counters = 0; 3093 for (t = 0; t < cpu_info.pm_nclass; t++) 3094 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 3095 cpu_info.pm_classes[t].pm_num > 0) 3096 cpu_has_iaf_counters = 1; 3097 #endif 3098 3099 #define PMC_MDEP_INIT(C) do { \ 3100 pmc_mdep_event_aliases = C##_aliases; \ 3101 pmc_mdep_class_list = C##_pmc_classes; \ 3102 pmc_mdep_class_list_size = \ 3103 PMC_TABLE_SIZE(C##_pmc_classes); \ 3104 } while (0) 3105 3106 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 3107 PMC_MDEP_INIT(C); \ 3108 pmc_class_table[n++] = &iaf_class_table_descr; \ 3109 if (!cpu_has_iaf_counters) \ 3110 pmc_mdep_event_aliases = \ 3111 C##_aliases_without_iaf; \ 3112 pmc_class_table[n] = &C##_class_table_descr; \ 3113 } while (0) 3114 3115 /* Configure the event name parser. */ 3116 switch (cpu_info.pm_cputype) { 3117 #if defined(__i386__) 3118 case PMC_CPU_AMD_K7: 3119 PMC_MDEP_INIT(k7); 3120 pmc_class_table[n] = &k7_class_table_descr; 3121 break; 3122 case PMC_CPU_INTEL_P5: 3123 PMC_MDEP_INIT(p5); 3124 pmc_class_table[n] = &p5_class_table_descr; 3125 break; 3126 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 3127 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 3128 case PMC_CPU_INTEL_PIII: 3129 case PMC_CPU_INTEL_PM: 3130 PMC_MDEP_INIT(p6); 3131 pmc_class_table[n] = &p6_class_table_descr; 3132 break; 3133 #endif 3134 #if defined(__amd64__) || defined(__i386__) 3135 case PMC_CPU_AMD_K8: 3136 PMC_MDEP_INIT(k8); 3137 pmc_class_table[n] = &k8_class_table_descr; 3138 break; 3139 case PMC_CPU_INTEL_ATOM: 3140 PMC_MDEP_INIT_INTEL_V2(atom); 3141 break; 3142 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3143 PMC_MDEP_INIT_INTEL_V2(atom_silvermont); 3144 break; 3145 case PMC_CPU_INTEL_CORE: 3146 PMC_MDEP_INIT(core); 3147 pmc_class_table[n] = &core_class_table_descr; 3148 break; 3149 case PMC_CPU_INTEL_CORE2: 3150 case PMC_CPU_INTEL_CORE2EXTREME: 3151 PMC_MDEP_INIT_INTEL_V2(core2); 3152 break; 3153 case PMC_CPU_INTEL_COREI7: 3154 pmc_class_table[n++] = &ucf_class_table_descr; 3155 pmc_class_table[n++] = &corei7uc_class_table_descr; 3156 PMC_MDEP_INIT_INTEL_V2(corei7); 3157 break; 3158 case PMC_CPU_INTEL_NEHALEM_EX: 3159 PMC_MDEP_INIT_INTEL_V2(nehalem_ex); 3160 break; 3161 case PMC_CPU_INTEL_HASWELL: 3162 pmc_class_table[n++] = &ucf_class_table_descr; 3163 pmc_class_table[n++] = &haswelluc_class_table_descr; 3164 PMC_MDEP_INIT_INTEL_V2(haswell); 3165 break; 3166 case PMC_CPU_INTEL_HASWELL_XEON: 3167 PMC_MDEP_INIT_INTEL_V2(haswell_xeon); 3168 break; 3169 case PMC_CPU_INTEL_IVYBRIDGE: 3170 PMC_MDEP_INIT_INTEL_V2(ivybridge); 3171 break; 3172 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3173 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); 3174 break; 3175 case PMC_CPU_INTEL_SANDYBRIDGE: 3176 pmc_class_table[n++] = &ucf_class_table_descr; 3177 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 3178 PMC_MDEP_INIT_INTEL_V2(sandybridge); 3179 break; 3180 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3181 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); 3182 break; 3183 case PMC_CPU_INTEL_WESTMERE: 3184 pmc_class_table[n++] = &ucf_class_table_descr; 3185 pmc_class_table[n++] = &westmereuc_class_table_descr; 3186 PMC_MDEP_INIT_INTEL_V2(westmere); 3187 break; 3188 case PMC_CPU_INTEL_WESTMERE_EX: 3189 PMC_MDEP_INIT_INTEL_V2(westmere_ex); 3190 break; 3191 case PMC_CPU_INTEL_PIV: 3192 PMC_MDEP_INIT(p4); 3193 pmc_class_table[n] = &p4_class_table_descr; 3194 break; 3195 #endif 3196 case PMC_CPU_GENERIC: 3197 PMC_MDEP_INIT(generic); 3198 break; 3199 #if defined(__arm__) 3200 #if defined(__XSCALE__) 3201 case PMC_CPU_INTEL_XSCALE: 3202 PMC_MDEP_INIT(xscale); 3203 pmc_class_table[n] = &xscale_class_table_descr; 3204 break; 3205 #endif 3206 case PMC_CPU_ARMV7: 3207 PMC_MDEP_INIT(armv7); 3208 pmc_class_table[n] = &armv7_class_table_descr; 3209 break; 3210 #endif 3211 #if defined(__mips__) 3212 case PMC_CPU_MIPS_24K: 3213 PMC_MDEP_INIT(mips24k); 3214 pmc_class_table[n] = &mips24k_class_table_descr; 3215 break; 3216 case PMC_CPU_MIPS_OCTEON: 3217 PMC_MDEP_INIT(octeon); 3218 pmc_class_table[n] = &octeon_class_table_descr; 3219 break; 3220 #endif /* __mips__ */ 3221 #if defined(__powerpc__) 3222 case PMC_CPU_PPC_7450: 3223 PMC_MDEP_INIT(ppc7450); 3224 pmc_class_table[n] = &ppc7450_class_table_descr; 3225 break; 3226 case PMC_CPU_PPC_970: 3227 PMC_MDEP_INIT(ppc970); 3228 pmc_class_table[n] = &ppc970_class_table_descr; 3229 break; 3230 #endif 3231 default: 3232 /* 3233 * Some kind of CPU this version of the library knows nothing 3234 * about. This shouldn't happen since the abi version check 3235 * should have caught this. 3236 */ 3237 errno = ENXIO; 3238 return (pmc_syscall = -1); 3239 } 3240 3241 return (0); 3242 } 3243 3244 const char * 3245 pmc_name_of_capability(enum pmc_caps cap) 3246 { 3247 int i; 3248 3249 /* 3250 * 'cap' should have a single bit set and should be in 3251 * range. 3252 */ 3253 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 3254 cap > PMC_CAP_LAST) { 3255 errno = EINVAL; 3256 return (NULL); 3257 } 3258 3259 i = ffs(cap); 3260 return (pmc_capability_names[i - 1]); 3261 } 3262 3263 const char * 3264 pmc_name_of_class(enum pmc_class pc) 3265 { 3266 if ((int) pc >= PMC_CLASS_FIRST && 3267 pc <= PMC_CLASS_LAST) 3268 return (pmc_class_names[pc]); 3269 3270 errno = EINVAL; 3271 return (NULL); 3272 } 3273 3274 const char * 3275 pmc_name_of_cputype(enum pmc_cputype cp) 3276 { 3277 size_t n; 3278 3279 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 3280 if (cp == pmc_cputype_names[n].pm_cputype) 3281 return (pmc_cputype_names[n].pm_name); 3282 3283 errno = EINVAL; 3284 return (NULL); 3285 } 3286 3287 const char * 3288 pmc_name_of_disposition(enum pmc_disp pd) 3289 { 3290 if ((int) pd >= PMC_DISP_FIRST && 3291 pd <= PMC_DISP_LAST) 3292 return (pmc_disposition_names[pd]); 3293 3294 errno = EINVAL; 3295 return (NULL); 3296 } 3297 3298 const char * 3299 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 3300 { 3301 const struct pmc_event_descr *ev, *evfence; 3302 3303 ev = evfence = NULL; 3304 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 3305 ev = iaf_event_table; 3306 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 3307 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 3308 switch (cpu) { 3309 case PMC_CPU_INTEL_ATOM: 3310 ev = atom_event_table; 3311 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 3312 break; 3313 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3314 ev = atom_silvermont_event_table; 3315 evfence = atom_silvermont_event_table + 3316 PMC_EVENT_TABLE_SIZE(atom_silvermont); 3317 break; 3318 case PMC_CPU_INTEL_CORE: 3319 ev = core_event_table; 3320 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 3321 break; 3322 case PMC_CPU_INTEL_CORE2: 3323 case PMC_CPU_INTEL_CORE2EXTREME: 3324 ev = core2_event_table; 3325 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 3326 break; 3327 case PMC_CPU_INTEL_COREI7: 3328 ev = corei7_event_table; 3329 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 3330 break; 3331 case PMC_CPU_INTEL_NEHALEM_EX: 3332 ev = nehalem_ex_event_table; 3333 evfence = nehalem_ex_event_table + 3334 PMC_EVENT_TABLE_SIZE(nehalem_ex); 3335 break; 3336 case PMC_CPU_INTEL_HASWELL: 3337 ev = haswell_event_table; 3338 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); 3339 break; 3340 case PMC_CPU_INTEL_HASWELL_XEON: 3341 ev = haswell_xeon_event_table; 3342 evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon); 3343 break; 3344 3345 case PMC_CPU_INTEL_IVYBRIDGE: 3346 ev = ivybridge_event_table; 3347 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); 3348 break; 3349 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3350 ev = ivybridge_xeon_event_table; 3351 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 3352 break; 3353 case PMC_CPU_INTEL_SANDYBRIDGE: 3354 ev = sandybridge_event_table; 3355 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 3356 break; 3357 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3358 ev = sandybridge_xeon_event_table; 3359 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 3360 break; 3361 case PMC_CPU_INTEL_WESTMERE: 3362 ev = westmere_event_table; 3363 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 3364 break; 3365 case PMC_CPU_INTEL_WESTMERE_EX: 3366 ev = westmere_ex_event_table; 3367 evfence = westmere_ex_event_table + 3368 PMC_EVENT_TABLE_SIZE(westmere_ex); 3369 break; 3370 default: /* Unknown CPU type. */ 3371 break; 3372 } 3373 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 3374 ev = ucf_event_table; 3375 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 3376 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 3377 switch (cpu) { 3378 case PMC_CPU_INTEL_COREI7: 3379 ev = corei7uc_event_table; 3380 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 3381 break; 3382 case PMC_CPU_INTEL_SANDYBRIDGE: 3383 ev = sandybridgeuc_event_table; 3384 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 3385 break; 3386 case PMC_CPU_INTEL_WESTMERE: 3387 ev = westmereuc_event_table; 3388 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 3389 break; 3390 default: /* Unknown CPU type. */ 3391 break; 3392 } 3393 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3394 ev = k7_event_table; 3395 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3396 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3397 ev = k8_event_table; 3398 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3399 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3400 ev = p4_event_table; 3401 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3402 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3403 ev = p5_event_table; 3404 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3405 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3406 ev = p6_event_table; 3407 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3408 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3409 ev = xscale_event_table; 3410 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3411 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 3412 ev = armv7_event_table; 3413 evfence = armv7_event_table + PMC_EVENT_TABLE_SIZE(armv7); 3414 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3415 ev = mips24k_event_table; 3416 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 3417 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 3418 ev = octeon_event_table; 3419 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 3420 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3421 ev = ppc7450_event_table; 3422 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 3423 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 3424 ev = ppc970_event_table; 3425 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 3426 } else if (pe == PMC_EV_TSC_TSC) { 3427 ev = tsc_event_table; 3428 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3429 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 3430 ev = soft_event_table; 3431 evfence = soft_event_table + soft_event_info.pm_nevent; 3432 } 3433 3434 for (; ev != evfence; ev++) 3435 if (pe == ev->pm_ev_code) 3436 return (ev->pm_ev_name); 3437 3438 return (NULL); 3439 } 3440 3441 const char * 3442 pmc_name_of_event(enum pmc_event pe) 3443 { 3444 const char *n; 3445 3446 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3447 return (n); 3448 3449 errno = EINVAL; 3450 return (NULL); 3451 } 3452 3453 const char * 3454 pmc_name_of_mode(enum pmc_mode pm) 3455 { 3456 if ((int) pm >= PMC_MODE_FIRST && 3457 pm <= PMC_MODE_LAST) 3458 return (pmc_mode_names[pm]); 3459 3460 errno = EINVAL; 3461 return (NULL); 3462 } 3463 3464 const char * 3465 pmc_name_of_state(enum pmc_state ps) 3466 { 3467 if ((int) ps >= PMC_STATE_FIRST && 3468 ps <= PMC_STATE_LAST) 3469 return (pmc_state_names[ps]); 3470 3471 errno = EINVAL; 3472 return (NULL); 3473 } 3474 3475 int 3476 pmc_ncpu(void) 3477 { 3478 if (pmc_syscall == -1) { 3479 errno = ENXIO; 3480 return (-1); 3481 } 3482 3483 return (cpu_info.pm_ncpu); 3484 } 3485 3486 int 3487 pmc_npmc(int cpu) 3488 { 3489 if (pmc_syscall == -1) { 3490 errno = ENXIO; 3491 return (-1); 3492 } 3493 3494 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3495 errno = EINVAL; 3496 return (-1); 3497 } 3498 3499 return (cpu_info.pm_npmc); 3500 } 3501 3502 int 3503 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3504 { 3505 int nbytes, npmc; 3506 struct pmc_op_getpmcinfo *pmci; 3507 3508 if ((npmc = pmc_npmc(cpu)) < 0) 3509 return (-1); 3510 3511 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3512 npmc * sizeof(struct pmc_info); 3513 3514 if ((pmci = calloc(1, nbytes)) == NULL) 3515 return (-1); 3516 3517 pmci->pm_cpu = cpu; 3518 3519 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3520 free(pmci); 3521 return (-1); 3522 } 3523 3524 /* kernel<->library, library<->userland interfaces are identical */ 3525 *ppmci = (struct pmc_pmcinfo *) pmci; 3526 return (0); 3527 } 3528 3529 int 3530 pmc_read(pmc_id_t pmc, pmc_value_t *value) 3531 { 3532 struct pmc_op_pmcrw pmc_read_op; 3533 3534 pmc_read_op.pm_pmcid = pmc; 3535 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3536 pmc_read_op.pm_value = -1; 3537 3538 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3539 return (-1); 3540 3541 *value = pmc_read_op.pm_value; 3542 return (0); 3543 } 3544 3545 int 3546 pmc_release(pmc_id_t pmc) 3547 { 3548 struct pmc_op_simple pmc_release_args; 3549 3550 pmc_release_args.pm_pmcid = pmc; 3551 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3552 } 3553 3554 int 3555 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3556 { 3557 struct pmc_op_pmcrw pmc_rw_op; 3558 3559 pmc_rw_op.pm_pmcid = pmc; 3560 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3561 pmc_rw_op.pm_value = newvalue; 3562 3563 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3564 return (-1); 3565 3566 *oldvaluep = pmc_rw_op.pm_value; 3567 return (0); 3568 } 3569 3570 int 3571 pmc_set(pmc_id_t pmc, pmc_value_t value) 3572 { 3573 struct pmc_op_pmcsetcount sc; 3574 3575 sc.pm_pmcid = pmc; 3576 sc.pm_count = value; 3577 3578 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3579 return (-1); 3580 return (0); 3581 } 3582 3583 int 3584 pmc_start(pmc_id_t pmc) 3585 { 3586 struct pmc_op_simple pmc_start_args; 3587 3588 pmc_start_args.pm_pmcid = pmc; 3589 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3590 } 3591 3592 int 3593 pmc_stop(pmc_id_t pmc) 3594 { 3595 struct pmc_op_simple pmc_stop_args; 3596 3597 pmc_stop_args.pm_pmcid = pmc; 3598 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3599 } 3600 3601 int 3602 pmc_width(pmc_id_t pmcid, uint32_t *width) 3603 { 3604 unsigned int i; 3605 enum pmc_class cl; 3606 3607 cl = PMC_ID_TO_CLASS(pmcid); 3608 for (i = 0; i < cpu_info.pm_nclass; i++) 3609 if (cpu_info.pm_classes[i].pm_class == cl) { 3610 *width = cpu_info.pm_classes[i].pm_width; 3611 return (0); 3612 } 3613 errno = EINVAL; 3614 return (-1); 3615 } 3616 3617 int 3618 pmc_write(pmc_id_t pmc, pmc_value_t value) 3619 { 3620 struct pmc_op_pmcrw pmc_write_op; 3621 3622 pmc_write_op.pm_pmcid = pmc; 3623 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3624 pmc_write_op.pm_value = value; 3625 return (PMC_CALL(PMCRW, &pmc_write_op)); 3626 } 3627 3628 int 3629 pmc_writelog(uint32_t userdata) 3630 { 3631 struct pmc_op_writelog wl; 3632 3633 wl.pm_userdata = userdata; 3634 return (PMC_CALL(WRITELOG, &wl)); 3635 } 3636