1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/types.h> 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/pmc.h> 33 #include <sys/syscall.h> 34 35 #if defined(__amd64__) || defined(__i386__) 36 #include <machine/cpufunc.h> 37 #endif 38 39 #include <ctype.h> 40 #include <errno.h> 41 #include <err.h> 42 #include <fcntl.h> 43 #include <pmc.h> 44 #include <stdio.h> 45 #include <stdlib.h> 46 #include <string.h> 47 #include <strings.h> 48 #include <sysexits.h> 49 #include <unistd.h> 50 51 #include "libpmcinternal.h" 52 53 /* Function prototypes */ 54 #if defined(__amd64__) || defined(__i386__) 55 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 56 struct pmc_op_pmcallocate *_pmc_config); 57 static int ibs_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 58 struct pmc_op_pmcallocate *_pmc_config); 59 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 60 struct pmc_op_pmcallocate *_pmc_config); 61 static int rapl_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 62 struct pmc_op_pmcallocate *_pmc_config); 63 static int perf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65 #endif 66 #if defined(__arm__) 67 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 68 struct pmc_op_pmcallocate *_pmc_config); 69 #endif 70 #if defined(__aarch64__) 71 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 72 struct pmc_op_pmcallocate *_pmc_config); 73 static int cmn600_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 74 struct pmc_op_pmcallocate *_pmc_config); 75 static int dmc620_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 76 struct pmc_op_pmcallocate *_pmc_config); 77 #endif 78 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 79 struct pmc_op_pmcallocate *_pmc_config); 80 81 #if defined(__powerpc__) 82 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84 #endif /* __powerpc__ */ 85 86 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params)) 87 88 /* 89 * Event aliases provide a way for the user to ask for generic events 90 * like "cache-misses", or "instructions-retired". These aliases are 91 * mapped to the appropriate canonical event descriptions using a 92 * lookup table. 93 */ 94 struct pmc_event_alias { 95 const char *pm_alias; 96 const char *pm_spec; 97 }; 98 99 static const struct pmc_event_alias *pmc_mdep_event_aliases; 100 101 /* 102 * The pmc_event_descr structure maps symbolic names known to the user 103 * to integer codes used by the PMC KLD. 104 */ 105 struct pmc_event_descr { 106 const char *pm_ev_name; 107 enum pmc_event pm_ev_code; 108 }; 109 110 /* 111 * The pmc_class_descr structure maps class name prefixes for 112 * event names to event tables and other PMC class data. 113 */ 114 struct pmc_class_descr { 115 const char *pm_evc_name; 116 size_t pm_evc_name_size; 117 enum pmc_class pm_evc_class; 118 const struct pmc_event_descr *pm_evc_event_table; 119 size_t pm_evc_event_table_size; 120 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 121 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 122 }; 123 124 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 125 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 126 127 #undef __PMC_EV 128 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 129 130 /* 131 * PMC_CLASSDEP_TABLE(NAME, CLASS) 132 * 133 * Define a table mapping event names and aliases to HWPMC event IDs. 134 */ 135 #define PMC_CLASSDEP_TABLE(N, C) \ 136 static const struct pmc_event_descr N##_event_table[] = \ 137 { \ 138 __PMC_EV_##C() \ 139 } 140 141 PMC_CLASSDEP_TABLE(iaf, IAF); 142 PMC_CLASSDEP_TABLE(k8, K8); 143 PMC_CLASSDEP_TABLE(ibs, IBS); 144 PMC_CLASSDEP_TABLE(perf, PERF); 145 PMC_CLASSDEP_TABLE(armv7, ARMV7); 146 PMC_CLASSDEP_TABLE(armv8, ARMV8); 147 PMC_CLASSDEP_TABLE(cmn600_pmu, CMN600_PMU); 148 PMC_CLASSDEP_TABLE(dmc620_pmu_cd2, DMC620_PMU_CD2); 149 PMC_CLASSDEP_TABLE(dmc620_pmu_c, DMC620_PMU_C); 150 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 151 PMC_CLASSDEP_TABLE(ppc970, PPC970); 152 PMC_CLASSDEP_TABLE(e500, E500); 153 154 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 155 156 #undef __PMC_EV_ALIAS 157 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 158 159 /* 160 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table 161 * rather than duplicating for each core. 162 */ 163 164 static const struct pmc_event_descr cortex_a8_event_table[] = 165 { 166 __PMC_EV_ALIAS_ARMV7_CORTEX_A8() 167 __PMC_EV_ARMV7() 168 }; 169 170 static const struct pmc_event_descr cortex_a9_event_table[] = 171 { 172 __PMC_EV_ALIAS_ARMV7_CORTEX_A9() 173 __PMC_EV_ARMV7() 174 }; 175 176 static const struct pmc_event_descr cortex_a53_event_table[] = 177 { 178 __PMC_EV_ALIAS_ARMV8_CORTEX_A53() 179 __PMC_EV_ARMV8() 180 }; 181 182 static const struct pmc_event_descr cortex_a57_event_table[] = 183 { 184 __PMC_EV_ALIAS_ARMV8_CORTEX_A57() 185 __PMC_EV_ARMV8() 186 }; 187 188 static const struct pmc_event_descr cortex_a76_event_table[] = 189 { 190 __PMC_EV_ALIAS_ARMV8_CORTEX_A76() 191 __PMC_EV_ARMV8() 192 }; 193 194 static const struct pmc_event_descr tsc_event_table[] = 195 { 196 __PMC_EV_ALIAS_TSC() 197 }; 198 199 static const struct pmc_event_descr rapl_event_table[] = 200 { 201 __PMC_EV_RAPL() 202 }; 203 204 #undef PMC_CLASS_TABLE_DESC 205 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 206 static const struct pmc_class_descr NAME##_class_table_descr = \ 207 { \ 208 .pm_evc_name = #CLASS "-", \ 209 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 210 .pm_evc_class = PMC_CLASS_##CLASS , \ 211 .pm_evc_event_table = EVENTS##_event_table , \ 212 .pm_evc_event_table_size = \ 213 PMC_EVENT_TABLE_SIZE(EVENTS), \ 214 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 215 } 216 217 #if defined(__i386__) || defined(__amd64__) 218 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 219 PMC_CLASS_TABLE_DESC(ibs, IBS, ibs, ibs); 220 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 221 PMC_CLASS_TABLE_DESC(rapl, RAPL, rapl, rapl); 222 PMC_CLASS_TABLE_DESC(perf, PERF, perf, perf); 223 #endif 224 #if defined(__arm__) 225 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7); 226 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); 227 #endif 228 #if defined(__aarch64__) 229 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); 230 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); 231 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64); 232 PMC_CLASS_TABLE_DESC(cmn600_pmu, CMN600_PMU, cmn600_pmu, cmn600_pmu); 233 PMC_CLASS_TABLE_DESC(dmc620_pmu_cd2, DMC620_PMU_CD2, dmc620_pmu_cd2, dmc620_pmu); 234 PMC_CLASS_TABLE_DESC(dmc620_pmu_c, DMC620_PMU_C, dmc620_pmu_c, dmc620_pmu); 235 #endif 236 #if defined(__powerpc__) 237 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 238 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 239 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); 240 #endif 241 242 static struct pmc_class_descr soft_class_table_descr = 243 { 244 .pm_evc_name = "SOFT-", 245 .pm_evc_name_size = sizeof("SOFT-") - 1, 246 .pm_evc_class = PMC_CLASS_SOFT, 247 .pm_evc_event_table = NULL, 248 .pm_evc_event_table_size = 0, 249 .pm_evc_allocate_pmc = soft_allocate_pmc 250 }; 251 252 #undef PMC_CLASS_TABLE_DESC 253 254 static const struct pmc_class_descr **pmc_class_table; 255 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 256 257 /* 258 * Mapping tables, mapping enumeration values to human readable 259 * strings. 260 */ 261 262 static const char * pmc_capability_names[] = { 263 #undef __PMC_CAP 264 #define __PMC_CAP(N,V,D) #N , 265 __PMC_CAPS() 266 }; 267 268 struct pmc_class_map { 269 enum pmc_class pm_class; 270 const char *pm_name; 271 }; 272 273 static const struct pmc_class_map pmc_class_names[] = { 274 #undef __PMC_CLASS 275 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } , 276 __PMC_CLASSES() 277 }; 278 279 struct pmc_cputype_map { 280 enum pmc_cputype pm_cputype; 281 const char *pm_name; 282 }; 283 284 static const struct pmc_cputype_map pmc_cputype_names[] = { 285 #undef __PMC_CPU 286 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 287 __PMC_CPUS() 288 }; 289 290 static const char * pmc_disposition_names[] = { 291 #undef __PMC_DISP 292 #define __PMC_DISP(D) #D , 293 __PMC_DISPOSITIONS() 294 }; 295 296 static const char * pmc_mode_names[] = { 297 #undef __PMC_MODE 298 #define __PMC_MODE(M,N) #M , 299 __PMC_MODES() 300 }; 301 302 static const char * pmc_state_names[] = { 303 #undef __PMC_STATE 304 #define __PMC_STATE(S) #S , 305 __PMC_STATES() 306 }; 307 308 /* 309 * Filled in by pmc_init(). 310 */ 311 static int pmc_syscall = -1; 312 static struct pmc_cpuinfo cpu_info; 313 static struct pmc_op_getdyneventinfo soft_event_info; 314 315 /* Event masks for events */ 316 struct pmc_masks { 317 const char *pm_name; 318 const uint64_t pm_value; 319 }; 320 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 321 #define NULLMASK { .pm_name = NULL } 322 323 #if defined(__amd64__) || defined(__i386__) 324 static int 325 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 326 { 327 const struct pmc_masks *pm; 328 char *q, *r; 329 int c; 330 331 if (pmask == NULL) /* no mask keywords */ 332 return (-1); 333 q = strchr(p, '='); /* skip '=' */ 334 if (*++q == '\0') /* no more data */ 335 return (-1); 336 c = 0; /* count of mask keywords seen */ 337 while ((r = strsep(&q, "+")) != NULL) { 338 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 339 pm++) 340 ; 341 if (pm->pm_name == NULL) /* not found */ 342 return (-1); 343 *evmask |= pm->pm_value; 344 c++; 345 } 346 return (c); 347 } 348 #endif 349 350 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 351 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 352 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 353 354 #if defined(__amd64__) || defined(__i386__) 355 /* 356 * AMD K8 PMCs. 357 * 358 */ 359 360 static struct pmc_event_alias k8_aliases[] = { 361 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 362 EV_ALIAS("branch-mispredicts", 363 "k8-fr-retired-taken-branches-mispredicted"), 364 EV_ALIAS("cycles", "tsc"), 365 EV_ALIAS("dc-misses", "k8-dc-miss"), 366 EV_ALIAS("ic-misses", "k8-ic-miss"), 367 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 368 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 369 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 370 EV_ALIAS(NULL, NULL) 371 }; 372 373 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 374 375 /* 376 * Parsing tables 377 */ 378 379 /* fp dispatched fpu ops */ 380 static const struct pmc_masks k8_mask_fdfo[] = { 381 __K8MASK(add-pipe-excluding-junk-ops, 0), 382 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 383 __K8MASK(store-pipe-excluding-junk-ops, 2), 384 __K8MASK(add-pipe-junk-ops, 3), 385 __K8MASK(multiply-pipe-junk-ops, 4), 386 __K8MASK(store-pipe-junk-ops, 5), 387 NULLMASK 388 }; 389 390 /* ls segment register loads */ 391 static const struct pmc_masks k8_mask_lsrl[] = { 392 __K8MASK(es, 0), 393 __K8MASK(cs, 1), 394 __K8MASK(ss, 2), 395 __K8MASK(ds, 3), 396 __K8MASK(fs, 4), 397 __K8MASK(gs, 5), 398 __K8MASK(hs, 6), 399 NULLMASK 400 }; 401 402 /* ls locked operation */ 403 static const struct pmc_masks k8_mask_llo[] = { 404 __K8MASK(locked-instructions, 0), 405 __K8MASK(cycles-in-request, 1), 406 __K8MASK(cycles-to-complete, 2), 407 NULLMASK 408 }; 409 410 /* dc refill from {l2,system} and dc copyback */ 411 static const struct pmc_masks k8_mask_dc[] = { 412 __K8MASK(invalid, 0), 413 __K8MASK(shared, 1), 414 __K8MASK(exclusive, 2), 415 __K8MASK(owner, 3), 416 __K8MASK(modified, 4), 417 NULLMASK 418 }; 419 420 /* dc one bit ecc error */ 421 static const struct pmc_masks k8_mask_dobee[] = { 422 __K8MASK(scrubber, 0), 423 __K8MASK(piggyback, 1), 424 NULLMASK 425 }; 426 427 /* dc dispatched prefetch instructions */ 428 static const struct pmc_masks k8_mask_ddpi[] = { 429 __K8MASK(load, 0), 430 __K8MASK(store, 1), 431 __K8MASK(nta, 2), 432 NULLMASK 433 }; 434 435 /* dc dcache accesses by locks */ 436 static const struct pmc_masks k8_mask_dabl[] = { 437 __K8MASK(accesses, 0), 438 __K8MASK(misses, 1), 439 NULLMASK 440 }; 441 442 /* bu internal l2 request */ 443 static const struct pmc_masks k8_mask_bilr[] = { 444 __K8MASK(ic-fill, 0), 445 __K8MASK(dc-fill, 1), 446 __K8MASK(tlb-reload, 2), 447 __K8MASK(tag-snoop, 3), 448 __K8MASK(cancelled, 4), 449 NULLMASK 450 }; 451 452 /* bu fill request l2 miss */ 453 static const struct pmc_masks k8_mask_bfrlm[] = { 454 __K8MASK(ic-fill, 0), 455 __K8MASK(dc-fill, 1), 456 __K8MASK(tlb-reload, 2), 457 NULLMASK 458 }; 459 460 /* bu fill into l2 */ 461 static const struct pmc_masks k8_mask_bfil[] = { 462 __K8MASK(dirty-l2-victim, 0), 463 __K8MASK(victim-from-l2, 1), 464 NULLMASK 465 }; 466 467 /* fr retired fpu instructions */ 468 static const struct pmc_masks k8_mask_frfi[] = { 469 __K8MASK(x87, 0), 470 __K8MASK(mmx-3dnow, 1), 471 __K8MASK(packed-sse-sse2, 2), 472 __K8MASK(scalar-sse-sse2, 3), 473 NULLMASK 474 }; 475 476 /* fr retired fastpath double op instructions */ 477 static const struct pmc_masks k8_mask_frfdoi[] = { 478 __K8MASK(low-op-pos-0, 0), 479 __K8MASK(low-op-pos-1, 1), 480 __K8MASK(low-op-pos-2, 2), 481 NULLMASK 482 }; 483 484 /* fr fpu exceptions */ 485 static const struct pmc_masks k8_mask_ffe[] = { 486 __K8MASK(x87-reclass-microfaults, 0), 487 __K8MASK(sse-retype-microfaults, 1), 488 __K8MASK(sse-reclass-microfaults, 2), 489 __K8MASK(sse-and-x87-microtraps, 3), 490 NULLMASK 491 }; 492 493 /* nb memory controller page access event */ 494 static const struct pmc_masks k8_mask_nmcpae[] = { 495 __K8MASK(page-hit, 0), 496 __K8MASK(page-miss, 1), 497 __K8MASK(page-conflict, 2), 498 NULLMASK 499 }; 500 501 /* nb memory controller turnaround */ 502 static const struct pmc_masks k8_mask_nmct[] = { 503 __K8MASK(dimm-turnaround, 0), 504 __K8MASK(read-to-write-turnaround, 1), 505 __K8MASK(write-to-read-turnaround, 2), 506 NULLMASK 507 }; 508 509 /* nb memory controller bypass saturation */ 510 static const struct pmc_masks k8_mask_nmcbs[] = { 511 __K8MASK(memory-controller-hi-pri-bypass, 0), 512 __K8MASK(memory-controller-lo-pri-bypass, 1), 513 __K8MASK(dram-controller-interface-bypass, 2), 514 __K8MASK(dram-controller-queue-bypass, 3), 515 NULLMASK 516 }; 517 518 /* nb sized commands */ 519 static const struct pmc_masks k8_mask_nsc[] = { 520 __K8MASK(nonpostwrszbyte, 0), 521 __K8MASK(nonpostwrszdword, 1), 522 __K8MASK(postwrszbyte, 2), 523 __K8MASK(postwrszdword, 3), 524 __K8MASK(rdszbyte, 4), 525 __K8MASK(rdszdword, 5), 526 __K8MASK(rdmodwr, 6), 527 NULLMASK 528 }; 529 530 /* nb probe result */ 531 static const struct pmc_masks k8_mask_npr[] = { 532 __K8MASK(probe-miss, 0), 533 __K8MASK(probe-hit, 1), 534 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 535 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 536 NULLMASK 537 }; 538 539 /* nb hypertransport bus bandwidth */ 540 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 541 __K8MASK(command, 0), 542 __K8MASK(data, 1), 543 __K8MASK(buffer-release, 2), 544 __K8MASK(nop, 3), 545 NULLMASK 546 }; 547 548 #undef __K8MASK 549 550 #define K8_KW_COUNT "count" 551 #define K8_KW_EDGE "edge" 552 #define K8_KW_INV "inv" 553 #define K8_KW_MASK "mask" 554 #define K8_KW_OS "os" 555 #define K8_KW_USR "usr" 556 557 static int 558 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 559 struct pmc_op_pmcallocate *pmc_config) 560 { 561 char *e, *p, *q; 562 int n; 563 uint32_t count; 564 uint64_t evmask; 565 const struct pmc_masks *pm, *pmask; 566 567 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 568 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 569 570 pmask = NULL; 571 evmask = 0; 572 573 #define __K8SETMASK(M) pmask = k8_mask_##M 574 575 /* setup parsing tables */ 576 switch (pe) { 577 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 578 __K8SETMASK(fdfo); 579 break; 580 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 581 __K8SETMASK(lsrl); 582 break; 583 case PMC_EV_K8_LS_LOCKED_OPERATION: 584 __K8SETMASK(llo); 585 break; 586 case PMC_EV_K8_DC_REFILL_FROM_L2: 587 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 588 case PMC_EV_K8_DC_COPYBACK: 589 __K8SETMASK(dc); 590 break; 591 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 592 __K8SETMASK(dobee); 593 break; 594 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 595 __K8SETMASK(ddpi); 596 break; 597 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 598 __K8SETMASK(dabl); 599 break; 600 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 601 __K8SETMASK(bilr); 602 break; 603 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 604 __K8SETMASK(bfrlm); 605 break; 606 case PMC_EV_K8_BU_FILL_INTO_L2: 607 __K8SETMASK(bfil); 608 break; 609 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 610 __K8SETMASK(frfi); 611 break; 612 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 613 __K8SETMASK(frfdoi); 614 break; 615 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 616 __K8SETMASK(ffe); 617 break; 618 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 619 __K8SETMASK(nmcpae); 620 break; 621 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 622 __K8SETMASK(nmct); 623 break; 624 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 625 __K8SETMASK(nmcbs); 626 break; 627 case PMC_EV_K8_NB_SIZED_COMMANDS: 628 __K8SETMASK(nsc); 629 break; 630 case PMC_EV_K8_NB_PROBE_RESULT: 631 __K8SETMASK(npr); 632 break; 633 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 634 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 635 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 636 __K8SETMASK(nhbb); 637 break; 638 639 default: 640 break; /* no options defined */ 641 } 642 643 while ((p = strsep(&ctrspec, ",")) != NULL) { 644 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 645 q = strchr(p, '='); 646 if (*++q == '\0') /* skip '=' */ 647 return (-1); 648 649 count = strtol(q, &e, 0); 650 if (e == q || *e != '\0') 651 return (-1); 652 653 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 654 pmc_config->pm_md.pm_amd.pm_amd_config |= 655 AMD_PMC_TO_COUNTER(count); 656 657 } else if (KWMATCH(p, K8_KW_EDGE)) { 658 pmc_config->pm_caps |= PMC_CAP_EDGE; 659 } else if (KWMATCH(p, K8_KW_INV)) { 660 pmc_config->pm_caps |= PMC_CAP_INVERT; 661 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 662 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 663 return (-1); 664 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 665 } else if (KWMATCH(p, K8_KW_OS)) { 666 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 667 } else if (KWMATCH(p, K8_KW_USR)) { 668 pmc_config->pm_caps |= PMC_CAP_USER; 669 } else 670 return (-1); 671 } 672 673 /* other post processing */ 674 switch (pe) { 675 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 676 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 677 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 678 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 679 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 680 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 681 /* XXX only available in rev B and later */ 682 break; 683 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 684 /* XXX only available in rev C and later */ 685 break; 686 case PMC_EV_K8_LS_LOCKED_OPERATION: 687 /* XXX CPU Rev A,B evmask is to be zero */ 688 if (evmask & (evmask - 1)) /* > 1 bit set */ 689 return (-1); 690 if (evmask == 0) { 691 evmask = 0x01; /* Rev C and later: #instrs */ 692 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 693 } 694 break; 695 default: 696 if (evmask == 0 && pmask != NULL) { 697 for (pm = pmask; pm->pm_name; pm++) 698 evmask |= pm->pm_value; 699 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 700 } 701 } 702 703 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 704 pmc_config->pm_md.pm_amd.pm_amd_config = 705 AMD_PMC_TO_UNITMASK(evmask); 706 707 return (0); 708 } 709 710 static int 711 ibs_allocate_pmc(enum pmc_event pe, char *ctrspec, 712 struct pmc_op_pmcallocate *pmc_config) 713 { 714 char *e, *p, *q; 715 uint64_t ctl, ctl2, ldlat, fetchlat; 716 u_int ibs_features; 717 u_int regs[4]; 718 719 pmc_config->pm_caps |= 720 (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE); 721 pmc_config->pm_md.pm_ibs.ibs_ctl = 0; 722 pmc_config->pm_md.pm_ibs.ibs_ctl2 = 0; 723 724 /* setup parsing tables */ 725 switch (pe) { 726 case PMC_EV_IBS_FETCH: 727 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_FETCH; 728 break; 729 case PMC_EV_IBS_OP: 730 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_OP; 731 break; 732 default: 733 return (-1); 734 } 735 736 /* IBS only supports sampling mode */ 737 if (!PMC_IS_SAMPLING_MODE(pmc_config->pm_mode)) { 738 return (-1); 739 } 740 741 /* Read the ibs feature flags */ 742 ibs_features = 0; 743 do_cpuid(0x80000000, regs); 744 if (regs[0] >= CPUID_IBSID) { 745 do_cpuid(CPUID_IBSID, regs); 746 ibs_features = regs[0]; 747 } 748 749 /* parse parameters */ 750 ctl = 0; 751 ctl2 = 0; 752 if (pe == PMC_EV_IBS_FETCH) { 753 while ((p = strsep(&ctrspec, ",")) != NULL) { 754 if (KWMATCH(p, "l3miss")) { 755 if ((ibs_features & CPUID_IBSID_ZEN4IBSEXTENSIONS) == 0) 756 return (-1); 757 758 ctl |= IBS_FETCH_CTL_L3MISSONLY; 759 } else if (KWMATCH(p, "randomize")) { 760 ctl |= IBS_FETCH_CTL_RANDOMIZE; 761 } else if (KWPREFIXMATCH(p, "fetchlat=")) { 762 if ((ibs_features & CPUID_IBSID_FETCHLATFILTERING) == 0) 763 return (-1); 764 765 q = strchr(p, '='); 766 if (*++q == '\0') 767 return (-1); 768 769 fetchlat = strtoull(q, &e, 0); 770 if (e == q || *e != '\0') 771 return (-1); 772 773 if (fetchlat < IBS_FETCH_CTL2_LAT_MIN || 774 fetchlat > IBS_FETCH_CTL2_LAT_MAX) 775 return (-1); 776 if ((fetchlat % IBS_FETCH_CTL2_LAT_STEP) != 0) 777 return (-1); 778 779 /* clear prior threshold */ 780 ctl2 &= ~IBS_FETCH_CTL2_LATFILTERMASK; 781 ctl2 |= IBS_FETCH_CTL2_LAT_TO_CTL(fetchlat); 782 } else if (KWMATCH(p, "usr")) { 783 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 784 return (-1); 785 786 pmc_config->pm_caps |= PMC_CAP_USER; 787 } else if (KWMATCH(p, "os")) { 788 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 789 return (-1); 790 791 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 792 } else { 793 return (-1); 794 } 795 } 796 797 if (pmc_config->pm_count < IBS_FETCH_MIN_RATE || 798 pmc_config->pm_count > IBS_FETCH_MAX_RATE) 799 return (-1); 800 801 ctl |= IBS_FETCH_INTERVAL_TO_CTL(pmc_config->pm_count); 802 } else { 803 while ((p = strsep(&ctrspec, ",")) != NULL) { 804 if (KWMATCH(p, "l3miss")) { 805 ctl |= IBS_OP_CTL_L3MISSONLY; 806 } else if (KWPREFIXMATCH(p, "ldlat=")) { 807 if ((ibs_features & CPUID_IBSID_IBSLOADLATENCYFILT) == 0) 808 return (-1); 809 810 q = strchr(p, '='); 811 if (*++q == '\0') /* skip '=' */ 812 return (-1); 813 814 ldlat = strtoull(q, &e, 0); 815 if (e == q || *e != '\0') 816 return (-1); 817 818 /* 819 * IBS load latency filtering requires the 820 * latency to be a multiple of 128 and between 821 * 128 and 2048. The latency is stored in the 822 * IbsOpLatThrsh field, which only contains 823 * four bits so the processor computes 824 * (IbsOpLatThrsh+1)*128 as the value. 825 * 826 * AMD PPR Vol 1 for AMD Family 1Ah Model 02h 827 * C1 (57238) 2026-03-06 Revision 0.49. 828 */ 829 if (ldlat < 128 || ldlat > 2048) 830 return (-1); 831 832 /* clear prior ldlat threshold */ 833 ctl &= ~IBS_OP_CTL_LDLATTRSHMASK; 834 ctl |= IBS_OP_CTL_LDLAT_TO_CTL(ldlat); 835 ctl |= IBS_OP_CTL_L3MISSONLY | IBS_OP_CTL_LATFLTEN; 836 } else if (KWMATCH(p, "opcount")) { 837 if ((ibs_features & CPUID_IBSID_OPCNT) == 0) 838 return (-1); 839 840 ctl |= IBS_OP_CTL_COUNTERCONTROL; 841 } else if (KWMATCH(p, "usr")) { 842 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 843 return (-1); 844 845 pmc_config->pm_caps |= PMC_CAP_USER; 846 } else if (KWMATCH(p, "os")) { 847 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 848 return (-1); 849 850 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 851 } else if (KWMATCH(p, "streamstore")) { 852 if ((ibs_features & CPUID_IBSID_STRMSTANDRMTSOCKET) == 0) 853 return (-1); 854 855 ctl2 |= IBS_OP_CTL2_STRMSTFILTER; 856 } else { 857 return (-1); 858 } 859 } 860 861 if (pmc_config->pm_count < IBS_OP_MIN_RATE || 862 pmc_config->pm_count > IBS_OP_MAX_RATE) 863 return (-1); 864 865 if (((ibs_features & CPUID_IBSID_OPCNTEXT) == 0) && 866 (pmc_config->pm_count > IBS_OP_MAX_RATE_PREEXT)) 867 return (-1); 868 869 ctl |= IBS_OP_INTERVAL_TO_CTL(pmc_config->pm_count); 870 } 871 872 pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl; 873 pmc_config->pm_md.pm_ibs.ibs_ctl2 |= ctl2; 874 875 return (0); 876 } 877 878 static int 879 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 880 struct pmc_op_pmcallocate *pmc_config) 881 { 882 if (pe != PMC_EV_TSC_TSC) 883 return (-1); 884 885 /* TSC events must be unqualified. */ 886 if (ctrspec && *ctrspec != '\0') 887 return (-1); 888 889 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 890 pmc_config->pm_caps |= PMC_CAP_READ; 891 892 return (0); 893 } 894 895 static int 896 rapl_allocate_pmc(enum pmc_event pe, char *ctrspec, 897 struct pmc_op_pmcallocate *pmc_config) 898 { 899 if (pe < PMC_EV_RAPL_FIRST || pe > PMC_EV_RAPL_LAST) 900 return (-1); 901 902 /* RAPL events must be unqualified. */ 903 if (ctrspec != NULL && *ctrspec != '\0') 904 return (-1); 905 906 pmc_config->pm_caps |= PMC_CAP_READ; 907 908 return (0); 909 } 910 911 static int 912 perf_allocate_pmc(enum pmc_event pe, char *ctrspec, 913 struct pmc_op_pmcallocate *pmc_config) 914 { 915 if (pe < PMC_EV_PERF_FIRST || pe > PMC_EV_PERF_LAST) 916 return (-1); 917 918 /* PERF events must be unqualified. */ 919 if (ctrspec != NULL && *ctrspec != '\0') 920 return (-1); 921 922 pmc_config->pm_caps |= PMC_CAP_READ; 923 924 return (0); 925 } 926 #endif 927 928 static struct pmc_event_alias generic_aliases[] = { 929 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 930 EV_ALIAS(NULL, NULL) 931 }; 932 933 static int 934 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 935 struct pmc_op_pmcallocate *pmc_config) 936 { 937 (void)ctrspec; 938 (void)pmc_config; 939 940 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 941 return (-1); 942 943 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 944 return (0); 945 } 946 947 #if defined(__arm__) 948 static struct pmc_event_alias cortex_a8_aliases[] = { 949 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 950 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 951 EV_ALIAS("instructions", "INSTR_EXECUTED"), 952 EV_ALIAS(NULL, NULL) 953 }; 954 955 static struct pmc_event_alias cortex_a9_aliases[] = { 956 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 957 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 958 EV_ALIAS("instructions", "INSTR_EXECUTED"), 959 EV_ALIAS(NULL, NULL) 960 }; 961 962 static int 963 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 964 struct pmc_op_pmcallocate *pmc_config __unused) 965 { 966 switch (pe) { 967 default: 968 break; 969 } 970 971 return (0); 972 } 973 #endif 974 975 #if defined(__aarch64__) 976 static struct pmc_event_alias cortex_a53_aliases[] = { 977 EV_ALIAS(NULL, NULL) 978 }; 979 static struct pmc_event_alias cortex_a57_aliases[] = { 980 EV_ALIAS(NULL, NULL) 981 }; 982 static struct pmc_event_alias cortex_a76_aliases[] = { 983 EV_ALIAS(NULL, NULL) 984 }; 985 986 static int 987 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec, 988 struct pmc_op_pmcallocate *pmc_config) 989 { 990 char *p; 991 992 while ((p = strsep(&ctrspec, ",")) != NULL) { 993 if (KWMATCH(p, "os")) 994 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 995 else if (KWMATCH(p, "usr")) 996 pmc_config->pm_caps |= PMC_CAP_USER; 997 else 998 return (-1); 999 } 1000 1001 return (0); 1002 } 1003 1004 static int 1005 cmn600_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec, 1006 struct pmc_op_pmcallocate *pmc_config) 1007 { 1008 uint32_t nodeid, occupancy, xpport, xpchannel; 1009 char *e, *p, *q; 1010 unsigned int i; 1011 char *xpport_names[] = { "East", "West", "North", "South", "devport0", 1012 "devport1" }; 1013 char *xpchannel_names[] = { "REQ", "RSP", "SNP", "DAT" }; 1014 1015 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1016 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1017 pmc_config->pm_md.pm_cmn600.pma_cmn600_config = 0; 1018 /* 1019 * CMN600 extra fields: 1020 * * nodeid - node coordinates x[2-3],y[2-3],p[1],s[2] 1021 * width of x and y fields depend on matrix size. 1022 * * occupancy - numeric value to select desired filter. 1023 * * xpport - East, West, North, South, devport0, devport1 (or 0, 1, ..., 5) 1024 * * xpchannel - REQ, RSP, SNP, DAT (or 0, 1, 2, 3) 1025 */ 1026 1027 while ((p = strsep(&ctrspec, ",")) != NULL) { 1028 if (KWPREFIXMATCH(p, "nodeid=")) { 1029 q = strchr(p, '='); 1030 if (*++q == '\0') /* skip '=' */ 1031 return (-1); 1032 1033 nodeid = strtol(q, &e, 0); 1034 if (e == q || *e != '\0') 1035 return (-1); 1036 1037 pmc_config->pm_md.pm_cmn600.pma_cmn600_nodeid |= nodeid; 1038 1039 } else if (KWPREFIXMATCH(p, "occupancy=")) { 1040 q = strchr(p, '='); 1041 if (*++q == '\0') /* skip '=' */ 1042 return (-1); 1043 1044 occupancy = strtol(q, &e, 0); 1045 if (e == q || *e != '\0') 1046 return (-1); 1047 1048 pmc_config->pm_md.pm_cmn600.pma_cmn600_occupancy = occupancy; 1049 } else if (KWPREFIXMATCH(p, "xpport=")) { 1050 q = strchr(p, '='); 1051 if (*++q == '\0') /* skip '=' */ 1052 return (-1); 1053 1054 xpport = strtol(q, &e, 0); 1055 if (e == q || *e != '\0') { 1056 for (i = 0; i < nitems(xpport_names); i++) { 1057 if (strcasecmp(xpport_names[i], q) == 0) { 1058 xpport = i; 1059 break; 1060 } 1061 } 1062 if (i == nitems(xpport_names)) 1063 return (-1); 1064 } 1065 1066 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpport << 2; 1067 } else if (KWPREFIXMATCH(p, "xpchannel=")) { 1068 q = strchr(p, '='); 1069 if (*++q == '\0') /* skip '=' */ 1070 return (-1); 1071 1072 xpchannel = strtol(q, &e, 0); 1073 if (e == q || *e != '\0') { 1074 for (i = 0; i < nitems(xpchannel_names); i++) { 1075 if (strcasecmp(xpchannel_names[i], q) == 0) { 1076 xpchannel = i; 1077 break; 1078 } 1079 } 1080 if (i == nitems(xpchannel_names)) 1081 return (-1); 1082 } 1083 1084 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpchannel << 5; 1085 } else 1086 return (-1); 1087 } 1088 1089 return (0); 1090 } 1091 1092 static int 1093 dmc620_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec, 1094 struct pmc_op_pmcallocate *pmc_config) 1095 { 1096 char *e, *p, *q; 1097 uint64_t match, mask; 1098 uint32_t count; 1099 1100 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1101 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1102 pmc_config->pm_md.pm_dmc620.pm_dmc620_config = 0; 1103 1104 while ((p = strsep(&ctrspec, ",")) != NULL) { 1105 if (KWPREFIXMATCH(p, "count=")) { 1106 q = strchr(p, '='); 1107 if (*++q == '\0') /* skip '=' */ 1108 return (-1); 1109 1110 count = strtol(q, &e, 0); 1111 if (e == q || *e != '\0') 1112 return (-1); 1113 1114 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1115 pmc_config->pm_md.pm_dmc620.pm_dmc620_config |= count; 1116 1117 } else if (KWMATCH(p, "inv")) { 1118 pmc_config->pm_caps |= PMC_CAP_INVERT; 1119 } else if (KWPREFIXMATCH(p, "match=")) { 1120 match = strtol(q, &e, 0); 1121 if (e == q || *e != '\0') 1122 return (-1); 1123 1124 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1125 pmc_config->pm_md.pm_dmc620.pm_dmc620_match = match; 1126 } else if (KWPREFIXMATCH(p, "mask=")) { 1127 q = strchr(p, '='); 1128 if (*++q == '\0') /* skip '=' */ 1129 return (-1); 1130 1131 mask = strtol(q, &e, 0); 1132 if (e == q || *e != '\0') 1133 return (-1); 1134 1135 pmc_config->pm_md.pm_dmc620.pm_dmc620_mask = mask; 1136 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1137 } else 1138 return (-1); 1139 } 1140 1141 return (0); 1142 } 1143 #endif 1144 1145 #if defined(__powerpc__) 1146 1147 static struct pmc_event_alias ppc7450_aliases[] = { 1148 EV_ALIAS("instructions", "INSTR_COMPLETED"), 1149 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 1150 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 1151 EV_ALIAS(NULL, NULL) 1152 }; 1153 1154 static struct pmc_event_alias ppc970_aliases[] = { 1155 EV_ALIAS("instructions", "INSTR_COMPLETED"), 1156 EV_ALIAS("cycles", "CYCLES"), 1157 EV_ALIAS(NULL, NULL) 1158 }; 1159 1160 static struct pmc_event_alias e500_aliases[] = { 1161 EV_ALIAS("instructions", "INSTR_COMPLETED"), 1162 EV_ALIAS("cycles", "CYCLES"), 1163 EV_ALIAS(NULL, NULL) 1164 }; 1165 1166 #define POWERPC_KW_OS "os" 1167 #define POWERPC_KW_USR "usr" 1168 #define POWERPC_KW_ANYTHREAD "anythread" 1169 1170 static int 1171 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 1172 struct pmc_op_pmcallocate *pmc_config __unused) 1173 { 1174 char *p; 1175 1176 (void) pe; 1177 1178 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1179 1180 while ((p = strsep(&ctrspec, ",")) != NULL) { 1181 if (KWMATCH(p, POWERPC_KW_OS)) 1182 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1183 else if (KWMATCH(p, POWERPC_KW_USR)) 1184 pmc_config->pm_caps |= PMC_CAP_USER; 1185 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 1186 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 1187 else 1188 return (-1); 1189 } 1190 1191 return (0); 1192 } 1193 1194 #endif /* __powerpc__ */ 1195 1196 1197 /* 1198 * Match an event name `name' with its canonical form. 1199 * 1200 * Matches are case insensitive and spaces, periods, underscores and 1201 * hyphen characters are considered to match each other. 1202 * 1203 * Returns 1 for a match, 0 otherwise. 1204 */ 1205 1206 static int 1207 pmc_match_event_name(const char *name, const char *canonicalname) 1208 { 1209 int cc, nc; 1210 const unsigned char *c, *n; 1211 1212 c = (const unsigned char *) canonicalname; 1213 n = (const unsigned char *) name; 1214 1215 for (; (nc = *n) && (cc = *c); n++, c++) { 1216 1217 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 1218 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 1219 continue; 1220 1221 if (toupper(nc) == toupper(cc)) 1222 continue; 1223 1224 1225 return (0); 1226 } 1227 1228 if (*n == '\0' && *c == '\0') 1229 return (1); 1230 1231 return (0); 1232 } 1233 1234 /* 1235 * Match an event name against all the event named supported by a 1236 * PMC class. 1237 * 1238 * Returns an event descriptor pointer on match or NULL otherwise. 1239 */ 1240 static const struct pmc_event_descr * 1241 pmc_match_event_class(const char *name, 1242 const struct pmc_class_descr *pcd) 1243 { 1244 size_t n; 1245 const struct pmc_event_descr *ev; 1246 1247 ev = pcd->pm_evc_event_table; 1248 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 1249 if (pmc_match_event_name(name, ev->pm_ev_name)) 1250 return (ev); 1251 1252 return (NULL); 1253 } 1254 1255 /* 1256 * API entry points 1257 */ 1258 1259 int 1260 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 1261 uint32_t flags, int cpu, pmc_id_t *pmcid, 1262 uint64_t count) 1263 { 1264 size_t n; 1265 int retval; 1266 char *r, *spec_copy; 1267 const char *ctrname; 1268 const struct pmc_event_descr *ev; 1269 const struct pmc_event_alias *alias; 1270 struct pmc_op_pmcallocate pmc_config; 1271 const struct pmc_class_descr *pcd; 1272 1273 spec_copy = NULL; 1274 retval = -1; 1275 1276 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 1277 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 1278 errno = EINVAL; 1279 goto out; 1280 } 1281 bzero(&pmc_config, sizeof(pmc_config)); 1282 pmc_config.pm_cpu = cpu; 1283 pmc_config.pm_mode = mode; 1284 pmc_config.pm_flags = flags; 1285 pmc_config.pm_count = count; 1286 if (PMC_IS_SAMPLING_MODE(mode)) 1287 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 1288 1289 /* 1290 * Try to pull the raw event ID directly from the pmu-events table. If 1291 * this is unsupported on the platform, or the event is not found, 1292 * continue with searching the regular event tables. 1293 */ 1294 r = spec_copy = strdup(ctrspec); 1295 ctrname = strsep(&r, ","); 1296 if (pmc_pmu_enabled()) { 1297 errno = pmc_pmu_pmcallocate(ctrname, &pmc_config); 1298 if (errno == 0) 1299 goto found; 1300 if (errno == EOPNOTSUPP) 1301 goto out; 1302 } 1303 free(spec_copy); 1304 spec_copy = NULL; 1305 1306 /* replace an event alias with the canonical event specifier */ 1307 if (pmc_mdep_event_aliases) 1308 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 1309 if (!strcasecmp(ctrspec, alias->pm_alias)) { 1310 spec_copy = strdup(alias->pm_spec); 1311 break; 1312 } 1313 1314 if (spec_copy == NULL) 1315 spec_copy = strdup(ctrspec); 1316 1317 r = spec_copy; 1318 ctrname = strsep(&r, ","); 1319 1320 /* 1321 * If a explicit class prefix was given by the user, restrict the 1322 * search for the event to the specified PMC class. 1323 */ 1324 ev = NULL; 1325 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 1326 pcd = pmc_class_table[n]; 1327 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name, 1328 pcd->pm_evc_name_size) == 0) { 1329 if ((ev = pmc_match_event_class(ctrname + 1330 pcd->pm_evc_name_size, pcd)) == NULL) { 1331 errno = EINVAL; 1332 goto out; 1333 } 1334 break; 1335 } 1336 } 1337 1338 /* 1339 * Otherwise, search for this event in all compatible PMC 1340 * classes. 1341 */ 1342 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 1343 pcd = pmc_class_table[n]; 1344 if (pcd != NULL) 1345 ev = pmc_match_event_class(ctrname, pcd); 1346 } 1347 1348 if (ev == NULL) { 1349 errno = EINVAL; 1350 goto out; 1351 } 1352 1353 pmc_config.pm_ev = ev->pm_ev_code; 1354 pmc_config.pm_class = pcd->pm_evc_class; 1355 1356 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 1357 errno = EINVAL; 1358 goto out; 1359 } 1360 1361 found: 1362 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) { 1363 *pmcid = pmc_config.pm_pmcid; 1364 retval = 0; 1365 } 1366 out: 1367 if (spec_copy) 1368 free(spec_copy); 1369 1370 return (retval); 1371 } 1372 1373 int 1374 pmc_attach(pmc_id_t pmc, pid_t pid) 1375 { 1376 struct pmc_op_pmcattach pmc_attach_args; 1377 1378 pmc_attach_args.pm_pmc = pmc; 1379 pmc_attach_args.pm_pid = pid; 1380 1381 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args)); 1382 } 1383 1384 int 1385 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 1386 { 1387 struct pmc_op_caps args; 1388 int status; 1389 1390 args.pm_pmcid = pmcid; 1391 args.pm_caps = 0; 1392 1393 status = PMC_CALL(PMC_OP_GETCAPS, &args); 1394 *caps = args.pm_caps; 1395 1396 return (status); 1397 } 1398 1399 int 1400 pmc_configure_logfile(int fd) 1401 { 1402 struct pmc_op_configurelog cla; 1403 1404 cla.pm_flags = 0; 1405 cla.pm_logfd = fd; 1406 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0) 1407 return (-1); 1408 return (0); 1409 } 1410 1411 int 1412 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 1413 { 1414 if (pmc_syscall == -1) { 1415 errno = ENXIO; 1416 return (-1); 1417 } 1418 1419 *pci = &cpu_info; 1420 return (0); 1421 } 1422 1423 int 1424 pmc_detach(pmc_id_t pmc, pid_t pid) 1425 { 1426 struct pmc_op_pmcattach pmc_detach_args; 1427 1428 pmc_detach_args.pm_pmc = pmc; 1429 pmc_detach_args.pm_pid = pid; 1430 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args)); 1431 } 1432 1433 int 1434 pmc_disable(int cpu, int pmc) 1435 { 1436 struct pmc_op_pmcadmin ssa; 1437 1438 ssa.pm_cpu = cpu; 1439 ssa.pm_pmc = pmc; 1440 ssa.pm_state = PMC_STATE_DISABLED; 1441 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa)); 1442 } 1443 1444 int 1445 pmc_enable(int cpu, int pmc) 1446 { 1447 struct pmc_op_pmcadmin ssa; 1448 1449 ssa.pm_cpu = cpu; 1450 ssa.pm_pmc = pmc; 1451 ssa.pm_state = PMC_STATE_FREE; 1452 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa)); 1453 } 1454 1455 /* 1456 * Return a list of events known to a given PMC class. 'cl' is the 1457 * PMC class identifier, 'eventnames' is the returned list of 'const 1458 * char *' pointers pointing to the names of the events. 'nevents' is 1459 * the number of event name pointers returned. 1460 * 1461 * The space for 'eventnames' is allocated using malloc(3). The caller 1462 * is responsible for freeing this space when done. 1463 */ 1464 int 1465 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 1466 int *nevents) 1467 { 1468 int count; 1469 const char **names; 1470 const struct pmc_event_descr *ev; 1471 1472 switch (cl) 1473 { 1474 case PMC_CLASS_IAF: 1475 ev = iaf_event_table; 1476 count = PMC_EVENT_TABLE_SIZE(iaf); 1477 break; 1478 case PMC_CLASS_TSC: 1479 ev = tsc_event_table; 1480 count = PMC_EVENT_TABLE_SIZE(tsc); 1481 break; 1482 case PMC_CLASS_RAPL: 1483 ev = rapl_event_table; 1484 count = PMC_EVENT_TABLE_SIZE(rapl); 1485 break; 1486 case PMC_CLASS_PERF: 1487 ev = perf_event_table; 1488 count = PMC_EVENT_TABLE_SIZE(perf); 1489 break; 1490 case PMC_CLASS_K8: 1491 ev = k8_event_table; 1492 count = PMC_EVENT_TABLE_SIZE(k8); 1493 break; 1494 case PMC_CLASS_IBS: 1495 ev = ibs_event_table; 1496 count = PMC_EVENT_TABLE_SIZE(ibs); 1497 break; 1498 case PMC_CLASS_ARMV7: 1499 switch (cpu_info.pm_cputype) { 1500 default: 1501 case PMC_CPU_ARMV7_CORTEX_A8: 1502 ev = cortex_a8_event_table; 1503 count = PMC_EVENT_TABLE_SIZE(cortex_a8); 1504 break; 1505 case PMC_CPU_ARMV7_CORTEX_A9: 1506 ev = cortex_a9_event_table; 1507 count = PMC_EVENT_TABLE_SIZE(cortex_a9); 1508 break; 1509 } 1510 break; 1511 case PMC_CLASS_ARMV8: 1512 switch (cpu_info.pm_cputype) { 1513 default: 1514 case PMC_CPU_ARMV8_CORTEX_A53: 1515 ev = cortex_a53_event_table; 1516 count = PMC_EVENT_TABLE_SIZE(cortex_a53); 1517 break; 1518 case PMC_CPU_ARMV8_CORTEX_A57: 1519 ev = cortex_a57_event_table; 1520 count = PMC_EVENT_TABLE_SIZE(cortex_a57); 1521 break; 1522 case PMC_CPU_ARMV8_CORTEX_A76: 1523 ev = cortex_a76_event_table; 1524 count = PMC_EVENT_TABLE_SIZE(cortex_a76); 1525 break; 1526 } 1527 break; 1528 case PMC_CLASS_CMN600_PMU: 1529 ev = cmn600_pmu_event_table; 1530 count = PMC_EVENT_TABLE_SIZE(cmn600_pmu); 1531 break; 1532 case PMC_CLASS_DMC620_PMU_CD2: 1533 ev = dmc620_pmu_cd2_event_table; 1534 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2); 1535 break; 1536 case PMC_CLASS_DMC620_PMU_C: 1537 ev = dmc620_pmu_c_event_table; 1538 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_c); 1539 break; 1540 case PMC_CLASS_PPC7450: 1541 ev = ppc7450_event_table; 1542 count = PMC_EVENT_TABLE_SIZE(ppc7450); 1543 break; 1544 case PMC_CLASS_PPC970: 1545 ev = ppc970_event_table; 1546 count = PMC_EVENT_TABLE_SIZE(ppc970); 1547 break; 1548 case PMC_CLASS_E500: 1549 ev = e500_event_table; 1550 count = PMC_EVENT_TABLE_SIZE(e500); 1551 break; 1552 case PMC_CLASS_SOFT: 1553 ev = soft_event_table; 1554 count = soft_event_info.pm_nevent; 1555 break; 1556 default: 1557 errno = EINVAL; 1558 return (-1); 1559 } 1560 1561 if ((names = malloc(count * sizeof(const char *))) == NULL) 1562 return (-1); 1563 1564 *eventnames = names; 1565 *nevents = count; 1566 1567 for (;count--; ev++, names++) 1568 *names = ev->pm_ev_name; 1569 1570 return (0); 1571 } 1572 1573 int 1574 pmc_flush_logfile(void) 1575 { 1576 return (PMC_CALL(PMC_OP_FLUSHLOG, 0)); 1577 } 1578 1579 int 1580 pmc_close_logfile(void) 1581 { 1582 return (PMC_CALL(PMC_OP_CLOSELOG, 0)); 1583 } 1584 1585 int 1586 pmc_get_driver_stats(struct pmc_driverstats *ds) 1587 { 1588 struct pmc_op_getdriverstats gms; 1589 1590 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0) 1591 return (-1); 1592 1593 /* copy out fields in the current userland<->library interface */ 1594 ds->pm_intr_ignored = gms.pm_intr_ignored; 1595 ds->pm_intr_processed = gms.pm_intr_processed; 1596 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 1597 ds->pm_syscalls = gms.pm_syscalls; 1598 ds->pm_syscall_errors = gms.pm_syscall_errors; 1599 ds->pm_buffer_requests = gms.pm_buffer_requests; 1600 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 1601 ds->pm_log_sweeps = gms.pm_log_sweeps; 1602 return (0); 1603 } 1604 1605 int 1606 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 1607 { 1608 struct pmc_op_getmsr gm; 1609 1610 gm.pm_pmcid = pmc; 1611 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0) 1612 return (-1); 1613 *msr = gm.pm_msr; 1614 return (0); 1615 } 1616 1617 int 1618 pmc_init(void) 1619 { 1620 int error, pmc_mod_id; 1621 unsigned int n; 1622 uint32_t abi_version; 1623 struct module_stat pmc_modstat; 1624 struct pmc_op_getcpuinfo op_cpu_info; 1625 1626 if (pmc_syscall != -1) /* already inited */ 1627 return (0); 1628 1629 /* retrieve the system call number from the KLD */ 1630 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 1631 return (-1); 1632 1633 pmc_modstat.version = sizeof(struct module_stat); 1634 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 1635 return (-1); 1636 1637 pmc_syscall = pmc_modstat.data.intval; 1638 1639 /* check the kernel module's ABI against our compiled-in version */ 1640 abi_version = PMC_VERSION; 1641 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0) 1642 return (pmc_syscall = -1); 1643 1644 /* ignore patch & minor numbers for the comparison */ 1645 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 1646 errno = EPROGMISMATCH; 1647 return (pmc_syscall = -1); 1648 } 1649 1650 bzero(&op_cpu_info, sizeof(op_cpu_info)); 1651 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0) 1652 return (pmc_syscall = -1); 1653 1654 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 1655 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 1656 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 1657 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 1658 for (n = 0; n < op_cpu_info.pm_nclass; n++) 1659 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n], 1660 sizeof(cpu_info.pm_classes[n])); 1661 1662 pmc_class_table = calloc(PMC_CLASS_TABLE_SIZE, 1663 sizeof(struct pmc_class_descr *)); 1664 1665 if (pmc_class_table == NULL) 1666 return (-1); 1667 1668 /* 1669 * Get soft events list. 1670 */ 1671 soft_event_info.pm_class = PMC_CLASS_SOFT; 1672 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0) 1673 return (pmc_syscall = -1); 1674 1675 /* Map soft events to static list. */ 1676 for (n = 0; n < soft_event_info.pm_nevent; n++) { 1677 soft_event_table[n].pm_ev_name = 1678 soft_event_info.pm_events[n].pm_ev_name; 1679 soft_event_table[n].pm_ev_code = 1680 soft_event_info.pm_events[n].pm_ev_code; 1681 } 1682 soft_class_table_descr.pm_evc_event_table_size = \ 1683 soft_event_info.pm_nevent; 1684 soft_class_table_descr.pm_evc_event_table = \ 1685 soft_event_table; 1686 1687 /* 1688 * Fill in the class table. 1689 */ 1690 n = 0; 1691 for (unsigned i = 0; i < PMC_CLASS_TABLE_SIZE; i++) { 1692 switch (cpu_info.pm_classes[i].pm_class) { 1693 #if defined(__amd64__) || defined(__i386__) 1694 case PMC_CLASS_TSC: 1695 pmc_class_table[n++] = &tsc_class_table_descr; 1696 break; 1697 1698 case PMC_CLASS_RAPL: 1699 pmc_class_table[n++] = &rapl_class_table_descr; 1700 break; 1701 1702 case PMC_CLASS_PERF: 1703 pmc_class_table[n++] = &perf_class_table_descr; 1704 break; 1705 1706 case PMC_CLASS_K8: 1707 pmc_class_table[n++] = &k8_class_table_descr; 1708 break; 1709 1710 case PMC_CLASS_IBS: 1711 pmc_class_table[n++] = &ibs_class_table_descr; 1712 break; 1713 #endif 1714 1715 case PMC_CLASS_SOFT: 1716 pmc_class_table[n++] = &soft_class_table_descr; 1717 break; 1718 1719 #if defined(__arm__) 1720 case PMC_CLASS_ARMV7: 1721 switch (cpu_info.pm_cputype) { 1722 case PMC_CPU_ARMV7_CORTEX_A8: 1723 pmc_class_table[n++] = 1724 &cortex_a8_class_table_descr; 1725 break; 1726 case PMC_CPU_ARMV7_CORTEX_A9: 1727 pmc_class_table[n++] = 1728 &cortex_a9_class_table_descr; 1729 break; 1730 default: 1731 errno = ENXIO; 1732 return (pmc_syscall = -1); 1733 } 1734 break; 1735 #endif 1736 1737 #if defined(__aarch64__) 1738 case PMC_CLASS_ARMV8: 1739 switch (cpu_info.pm_cputype) { 1740 case PMC_CPU_ARMV8_CORTEX_A53: 1741 pmc_class_table[n++] = 1742 &cortex_a53_class_table_descr; 1743 break; 1744 case PMC_CPU_ARMV8_CORTEX_A57: 1745 pmc_class_table[n++] = 1746 &cortex_a57_class_table_descr; 1747 break; 1748 case PMC_CPU_ARMV8_CORTEX_A76: 1749 pmc_class_table[n++] = 1750 &cortex_a76_class_table_descr; 1751 break; 1752 default: 1753 errno = ENXIO; 1754 return (pmc_syscall = -1); 1755 } 1756 break; 1757 1758 case PMC_CLASS_DMC620_PMU_CD2: 1759 pmc_class_table[n++] = 1760 &dmc620_pmu_cd2_class_table_descr; 1761 break; 1762 1763 case PMC_CLASS_DMC620_PMU_C: 1764 pmc_class_table[n++] = &dmc620_pmu_c_class_table_descr; 1765 break; 1766 1767 case PMC_CLASS_CMN600_PMU: 1768 pmc_class_table[n++] = &cmn600_pmu_class_table_descr; 1769 break; 1770 #endif 1771 1772 #if defined(__powerpc__) 1773 case PMC_CLASS_PPC7450: 1774 pmc_class_table[n++] = &ppc7450_class_table_descr; 1775 break; 1776 1777 case PMC_CLASS_PPC970: 1778 pmc_class_table[n++] = &ppc970_class_table_descr; 1779 break; 1780 1781 case PMC_CLASS_E500: 1782 pmc_class_table[n++] = &e500_class_table_descr; 1783 break; 1784 #endif 1785 1786 default: 1787 #if defined(DEBUG) 1788 printf("pm_class: 0x%x\n", 1789 cpu_info.pm_classes[i].pm_class); 1790 #endif 1791 break; 1792 } 1793 } 1794 1795 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases 1796 1797 /* Configure the event name parser. */ 1798 switch (cpu_info.pm_cputype) { 1799 #if defined(__amd64__) || defined(__i386__) 1800 case PMC_CPU_AMD_K8: 1801 PMC_MDEP_INIT(k8); 1802 break; 1803 #endif 1804 case PMC_CPU_GENERIC: 1805 PMC_MDEP_INIT(generic); 1806 break; 1807 #if defined(__arm__) 1808 case PMC_CPU_ARMV7_CORTEX_A8: 1809 PMC_MDEP_INIT(cortex_a8); 1810 break; 1811 case PMC_CPU_ARMV7_CORTEX_A9: 1812 PMC_MDEP_INIT(cortex_a9); 1813 break; 1814 #endif 1815 #if defined(__aarch64__) 1816 case PMC_CPU_ARMV8_CORTEX_A53: 1817 PMC_MDEP_INIT(cortex_a53); 1818 break; 1819 case PMC_CPU_ARMV8_CORTEX_A57: 1820 PMC_MDEP_INIT(cortex_a57); 1821 break; 1822 case PMC_CPU_ARMV8_CORTEX_A76: 1823 PMC_MDEP_INIT(cortex_a76); 1824 break; 1825 #endif 1826 #if defined(__powerpc__) 1827 case PMC_CPU_PPC_7450: 1828 PMC_MDEP_INIT(ppc7450); 1829 break; 1830 case PMC_CPU_PPC_970: 1831 PMC_MDEP_INIT(ppc970); 1832 break; 1833 case PMC_CPU_PPC_E500: 1834 PMC_MDEP_INIT(e500); 1835 break; 1836 #endif 1837 default: 1838 /* 1839 * Some kind of CPU this version of the library knows nothing 1840 * about. This shouldn't happen since the abi version check 1841 * should have caught this. 1842 */ 1843 #if defined(__amd64__) || defined(__i386__) || defined(__powerpc64__) 1844 break; 1845 #endif 1846 errno = ENXIO; 1847 return (pmc_syscall = -1); 1848 } 1849 1850 return (0); 1851 } 1852 1853 const char * 1854 pmc_name_of_capability(enum pmc_caps cap) 1855 { 1856 int i; 1857 1858 /* 1859 * 'cap' should have a single bit set and should be in 1860 * range. 1861 */ 1862 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 1863 cap > PMC_CAP_LAST) { 1864 errno = EINVAL; 1865 return (NULL); 1866 } 1867 1868 i = ffs(cap); 1869 return (pmc_capability_names[i - 1]); 1870 } 1871 1872 const char * 1873 pmc_name_of_class(enum pmc_class pc) 1874 { 1875 size_t n; 1876 1877 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++) 1878 if (pc == pmc_class_names[n].pm_class) 1879 return (pmc_class_names[n].pm_name); 1880 1881 errno = EINVAL; 1882 return (NULL); 1883 } 1884 1885 const char * 1886 pmc_name_of_cputype(enum pmc_cputype cp) 1887 { 1888 size_t n; 1889 1890 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 1891 if (cp == pmc_cputype_names[n].pm_cputype) 1892 return (pmc_cputype_names[n].pm_name); 1893 1894 errno = EINVAL; 1895 return (NULL); 1896 } 1897 1898 const char * 1899 pmc_name_of_disposition(enum pmc_disp pd) 1900 { 1901 if ((int) pd >= PMC_DISP_FIRST && 1902 pd <= PMC_DISP_LAST) 1903 return (pmc_disposition_names[pd]); 1904 1905 errno = EINVAL; 1906 return (NULL); 1907 } 1908 1909 const char * 1910 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 1911 { 1912 const struct pmc_event_descr *ev, *evfence; 1913 1914 ev = evfence = NULL; 1915 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 1916 ev = k8_event_table; 1917 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 1918 } else if (pe >= PMC_EV_IBS_FIRST && pe <= PMC_EV_IBS_LAST) { 1919 ev = ibs_event_table; 1920 evfence = ibs_event_table + PMC_EVENT_TABLE_SIZE(ibs); 1921 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 1922 switch (cpu) { 1923 case PMC_CPU_ARMV7_CORTEX_A8: 1924 ev = cortex_a8_event_table; 1925 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8); 1926 break; 1927 case PMC_CPU_ARMV7_CORTEX_A9: 1928 ev = cortex_a9_event_table; 1929 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9); 1930 break; 1931 default: /* Unknown CPU type. */ 1932 break; 1933 } 1934 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { 1935 switch (cpu) { 1936 case PMC_CPU_ARMV8_CORTEX_A53: 1937 ev = cortex_a53_event_table; 1938 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); 1939 break; 1940 case PMC_CPU_ARMV8_CORTEX_A57: 1941 ev = cortex_a57_event_table; 1942 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); 1943 break; 1944 case PMC_CPU_ARMV8_CORTEX_A76: 1945 ev = cortex_a76_event_table; 1946 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76); 1947 break; 1948 default: /* Unknown CPU type. */ 1949 break; 1950 } 1951 } else if (pe >= PMC_EV_CMN600_PMU_FIRST && 1952 pe <= PMC_EV_CMN600_PMU_LAST) { 1953 ev = cmn600_pmu_event_table; 1954 evfence = cmn600_pmu_event_table + 1955 PMC_EVENT_TABLE_SIZE(cmn600_pmu); 1956 } else if (pe >= PMC_EV_DMC620_PMU_CD2_FIRST && 1957 pe <= PMC_EV_DMC620_PMU_CD2_LAST) { 1958 ev = dmc620_pmu_cd2_event_table; 1959 evfence = dmc620_pmu_cd2_event_table + 1960 PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2); 1961 } else if (pe >= PMC_EV_DMC620_PMU_C_FIRST && 1962 pe <= PMC_EV_DMC620_PMU_C_LAST) { 1963 ev = dmc620_pmu_c_event_table; 1964 evfence = dmc620_pmu_c_event_table + 1965 PMC_EVENT_TABLE_SIZE(dmc620_pmu_c); 1966 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 1967 ev = ppc7450_event_table; 1968 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 1969 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 1970 ev = ppc970_event_table; 1971 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 1972 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { 1973 ev = e500_event_table; 1974 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); 1975 } else if (pe == PMC_EV_TSC_TSC) { 1976 ev = tsc_event_table; 1977 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 1978 } else if (pe >= PMC_EV_RAPL_FIRST && pe <= PMC_EV_RAPL_LAST) { 1979 ev = rapl_event_table; 1980 evfence = rapl_event_table + PMC_EVENT_TABLE_SIZE(rapl); 1981 } else if (pe >= PMC_EV_PERF_FIRST && pe <= PMC_EV_PERF_LAST) { 1982 ev = perf_event_table; 1983 evfence = perf_event_table + PMC_EVENT_TABLE_SIZE(perf); 1984 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 1985 ev = soft_event_table; 1986 evfence = soft_event_table + soft_event_info.pm_nevent; 1987 } 1988 1989 for (; ev != evfence; ev++) 1990 if (pe == ev->pm_ev_code) 1991 return (ev->pm_ev_name); 1992 1993 return (NULL); 1994 } 1995 1996 const char * 1997 pmc_name_of_event(enum pmc_event pe) 1998 { 1999 const char *n; 2000 2001 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 2002 return (n); 2003 2004 errno = EINVAL; 2005 return (NULL); 2006 } 2007 2008 const char * 2009 pmc_name_of_mode(enum pmc_mode pm) 2010 { 2011 if ((int) pm >= PMC_MODE_FIRST && 2012 pm <= PMC_MODE_LAST) 2013 return (pmc_mode_names[pm]); 2014 2015 errno = EINVAL; 2016 return (NULL); 2017 } 2018 2019 const char * 2020 pmc_name_of_state(enum pmc_state ps) 2021 { 2022 if ((int) ps >= PMC_STATE_FIRST && 2023 ps <= PMC_STATE_LAST) 2024 return (pmc_state_names[ps]); 2025 2026 errno = EINVAL; 2027 return (NULL); 2028 } 2029 2030 int 2031 pmc_ncpu(void) 2032 { 2033 if (pmc_syscall == -1) { 2034 errno = ENXIO; 2035 return (-1); 2036 } 2037 2038 return (cpu_info.pm_ncpu); 2039 } 2040 2041 int 2042 pmc_npmc(int cpu) 2043 { 2044 if (pmc_syscall == -1) { 2045 errno = ENXIO; 2046 return (-1); 2047 } 2048 2049 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 2050 errno = EINVAL; 2051 return (-1); 2052 } 2053 2054 return (cpu_info.pm_npmc); 2055 } 2056 2057 int 2058 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 2059 { 2060 int nbytes, npmc; 2061 struct pmc_op_getpmcinfo *pmci; 2062 2063 if ((npmc = pmc_npmc(cpu)) < 0) 2064 return (-1); 2065 2066 nbytes = sizeof(struct pmc_op_getpmcinfo) + 2067 npmc * sizeof(struct pmc_info); 2068 2069 if ((pmci = calloc(1, nbytes)) == NULL) 2070 return (-1); 2071 2072 pmci->pm_cpu = cpu; 2073 2074 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) { 2075 free(pmci); 2076 return (-1); 2077 } 2078 2079 /* kernel<->library, library<->userland interfaces are identical */ 2080 *ppmci = (struct pmc_pmcinfo *) pmci; 2081 return (0); 2082 } 2083 2084 int 2085 pmc_read(pmc_id_t pmc, pmc_value_t *value) 2086 { 2087 struct pmc_op_pmcrw pmc_read_op; 2088 2089 pmc_read_op.pm_pmcid = pmc; 2090 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 2091 pmc_read_op.pm_value = -1; 2092 2093 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0) 2094 return (-1); 2095 2096 *value = pmc_read_op.pm_value; 2097 return (0); 2098 } 2099 2100 int 2101 pmc_release(pmc_id_t pmc) 2102 { 2103 struct pmc_op_simple pmc_release_args; 2104 2105 pmc_release_args.pm_pmcid = pmc; 2106 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args)); 2107 } 2108 2109 int 2110 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 2111 { 2112 struct pmc_op_pmcrw pmc_rw_op; 2113 2114 pmc_rw_op.pm_pmcid = pmc; 2115 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 2116 pmc_rw_op.pm_value = newvalue; 2117 2118 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0) 2119 return (-1); 2120 2121 *oldvaluep = pmc_rw_op.pm_value; 2122 return (0); 2123 } 2124 2125 int 2126 pmc_set(pmc_id_t pmc, pmc_value_t value) 2127 { 2128 struct pmc_op_pmcsetcount sc; 2129 2130 sc.pm_pmcid = pmc; 2131 sc.pm_count = value; 2132 2133 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0) 2134 return (-1); 2135 return (0); 2136 } 2137 2138 int 2139 pmc_start(pmc_id_t pmc) 2140 { 2141 struct pmc_op_simple pmc_start_args; 2142 2143 pmc_start_args.pm_pmcid = pmc; 2144 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args)); 2145 } 2146 2147 int 2148 pmc_stop(pmc_id_t pmc) 2149 { 2150 struct pmc_op_simple pmc_stop_args; 2151 2152 pmc_stop_args.pm_pmcid = pmc; 2153 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args)); 2154 } 2155 2156 int 2157 pmc_width(pmc_id_t pmcid, uint32_t *width) 2158 { 2159 unsigned int i; 2160 enum pmc_class cl; 2161 2162 cl = PMC_ID_TO_CLASS(pmcid); 2163 for (i = 0; i < cpu_info.pm_nclass; i++) 2164 if (cpu_info.pm_classes[i].pm_class == cl) { 2165 *width = cpu_info.pm_classes[i].pm_width; 2166 return (0); 2167 } 2168 errno = EINVAL; 2169 return (-1); 2170 } 2171 2172 int 2173 pmc_write(pmc_id_t pmc, pmc_value_t value) 2174 { 2175 struct pmc_op_pmcrw pmc_write_op; 2176 2177 pmc_write_op.pm_pmcid = pmc; 2178 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 2179 pmc_write_op.pm_value = value; 2180 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op)); 2181 } 2182 2183 int 2184 pmc_writelog(uint32_t userdata) 2185 { 2186 struct pmc_op_writelog wl; 2187 2188 wl.pm_userdata = userdata; 2189 return (PMC_CALL(PMC_OP_WRITELOG, &wl)); 2190 } 2191