1 /*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/pmc.h> 34 #include <sys/syscall.h> 35 36 #include <ctype.h> 37 #include <errno.h> 38 #include <fcntl.h> 39 #include <pmc.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <unistd.h> 45 46 #include "libpmcinternal.h" 47 48 /* Function prototypes */ 49 #if defined(__i386__) 50 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 51 struct pmc_op_pmcallocate *_pmc_config); 52 #endif 53 #if defined(__amd64__) || defined(__i386__) 54 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 57 struct pmc_op_pmcallocate *_pmc_config); 58 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 61 struct pmc_op_pmcallocate *_pmc_config); 62 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 63 struct pmc_op_pmcallocate *_pmc_config); 64 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 65 struct pmc_op_pmcallocate *_pmc_config); 66 #endif 67 #if defined(__i386__) 68 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 69 struct pmc_op_pmcallocate *_pmc_config); 70 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72 #endif 73 #if defined(__amd64__) || defined(__i386__) 74 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 #endif 77 #if defined(__arm__) 78 #if defined(__XSCALE__) 79 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 80 struct pmc_op_pmcallocate *_pmc_config); 81 #endif 82 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84 #endif 85 #if defined(__mips__) 86 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 87 struct pmc_op_pmcallocate *_pmc_config); 88 #endif /* __mips__ */ 89 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 90 struct pmc_op_pmcallocate *_pmc_config); 91 92 #if defined(__powerpc__) 93 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 94 struct pmc_op_pmcallocate *_pmc_config); 95 #endif /* __powerpc__ */ 96 97 #define PMC_CALL(cmd, params) \ 98 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 99 100 /* 101 * Event aliases provide a way for the user to ask for generic events 102 * like "cache-misses", or "instructions-retired". These aliases are 103 * mapped to the appropriate canonical event descriptions using a 104 * lookup table. 105 */ 106 struct pmc_event_alias { 107 const char *pm_alias; 108 const char *pm_spec; 109 }; 110 111 static const struct pmc_event_alias *pmc_mdep_event_aliases; 112 113 /* 114 * The pmc_event_descr structure maps symbolic names known to the user 115 * to integer codes used by the PMC KLD. 116 */ 117 struct pmc_event_descr { 118 const char *pm_ev_name; 119 enum pmc_event pm_ev_code; 120 }; 121 122 /* 123 * The pmc_class_descr structure maps class name prefixes for 124 * event names to event tables and other PMC class data. 125 */ 126 struct pmc_class_descr { 127 const char *pm_evc_name; 128 size_t pm_evc_name_size; 129 enum pmc_class pm_evc_class; 130 const struct pmc_event_descr *pm_evc_event_table; 131 size_t pm_evc_event_table_size; 132 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 133 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 134 }; 135 136 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 137 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 138 139 #undef __PMC_EV 140 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 141 142 /* 143 * PMC_CLASSDEP_TABLE(NAME, CLASS) 144 * 145 * Define a table mapping event names and aliases to HWPMC event IDs. 146 */ 147 #define PMC_CLASSDEP_TABLE(N, C) \ 148 static const struct pmc_event_descr N##_event_table[] = \ 149 { \ 150 __PMC_EV_##C() \ 151 } 152 153 PMC_CLASSDEP_TABLE(iaf, IAF); 154 PMC_CLASSDEP_TABLE(k7, K7); 155 PMC_CLASSDEP_TABLE(k8, K8); 156 PMC_CLASSDEP_TABLE(p4, P4); 157 PMC_CLASSDEP_TABLE(p5, P5); 158 PMC_CLASSDEP_TABLE(p6, P6); 159 PMC_CLASSDEP_TABLE(xscale, XSCALE); 160 PMC_CLASSDEP_TABLE(armv7, ARMV7); 161 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 162 PMC_CLASSDEP_TABLE(mips74k, MIPS74K); 163 PMC_CLASSDEP_TABLE(octeon, OCTEON); 164 PMC_CLASSDEP_TABLE(ucf, UCF); 165 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 166 PMC_CLASSDEP_TABLE(ppc970, PPC970); 167 168 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 169 170 #undef __PMC_EV_ALIAS 171 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 172 173 static const struct pmc_event_descr atom_event_table[] = 174 { 175 __PMC_EV_ALIAS_ATOM() 176 }; 177 178 static const struct pmc_event_descr atom_silvermont_event_table[] = 179 { 180 __PMC_EV_ALIAS_ATOM_SILVERMONT() 181 }; 182 183 static const struct pmc_event_descr core_event_table[] = 184 { 185 __PMC_EV_ALIAS_CORE() 186 }; 187 188 189 static const struct pmc_event_descr core2_event_table[] = 190 { 191 __PMC_EV_ALIAS_CORE2() 192 }; 193 194 static const struct pmc_event_descr corei7_event_table[] = 195 { 196 __PMC_EV_ALIAS_COREI7() 197 }; 198 199 static const struct pmc_event_descr nehalem_ex_event_table[] = 200 { 201 __PMC_EV_ALIAS_COREI7() 202 }; 203 204 static const struct pmc_event_descr haswell_event_table[] = 205 { 206 __PMC_EV_ALIAS_HASWELL() 207 }; 208 209 static const struct pmc_event_descr haswell_xeon_event_table[] = 210 { 211 __PMC_EV_ALIAS_HASWELL_XEON() 212 }; 213 214 215 static const struct pmc_event_descr ivybridge_event_table[] = 216 { 217 __PMC_EV_ALIAS_IVYBRIDGE() 218 }; 219 220 static const struct pmc_event_descr ivybridge_xeon_event_table[] = 221 { 222 __PMC_EV_ALIAS_IVYBRIDGE_XEON() 223 }; 224 225 static const struct pmc_event_descr sandybridge_event_table[] = 226 { 227 __PMC_EV_ALIAS_SANDYBRIDGE() 228 }; 229 230 static const struct pmc_event_descr sandybridge_xeon_event_table[] = 231 { 232 __PMC_EV_ALIAS_SANDYBRIDGE_XEON() 233 }; 234 235 static const struct pmc_event_descr westmere_event_table[] = 236 { 237 __PMC_EV_ALIAS_WESTMERE() 238 }; 239 240 static const struct pmc_event_descr westmere_ex_event_table[] = 241 { 242 __PMC_EV_ALIAS_WESTMERE() 243 }; 244 245 static const struct pmc_event_descr corei7uc_event_table[] = 246 { 247 __PMC_EV_ALIAS_COREI7UC() 248 }; 249 250 static const struct pmc_event_descr haswelluc_event_table[] = 251 { 252 __PMC_EV_ALIAS_HASWELLUC() 253 }; 254 255 static const struct pmc_event_descr sandybridgeuc_event_table[] = 256 { 257 __PMC_EV_ALIAS_SANDYBRIDGEUC() 258 }; 259 260 static const struct pmc_event_descr westmereuc_event_table[] = 261 { 262 __PMC_EV_ALIAS_WESTMEREUC() 263 }; 264 265 /* 266 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 267 * 268 * Map a CPU to the PMC classes it supports. 269 */ 270 #define PMC_MDEP_TABLE(N,C,...) \ 271 static const enum pmc_class N##_pmc_classes[] = { \ 272 PMC_CLASS_##C, __VA_ARGS__ \ 273 } 274 275 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 276 PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 277 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); 278 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 279 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 280 PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 281 PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 282 PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 283 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 284 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 285 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 286 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 287 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 288 PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 289 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); 290 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 291 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); 292 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); 293 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); 294 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 295 PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 296 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 297 PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); 298 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 299 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450); 300 PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970); 301 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 302 303 static const struct pmc_event_descr tsc_event_table[] = 304 { 305 __PMC_EV_TSC() 306 }; 307 308 #undef PMC_CLASS_TABLE_DESC 309 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 310 static const struct pmc_class_descr NAME##_class_table_descr = \ 311 { \ 312 .pm_evc_name = #CLASS "-", \ 313 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 314 .pm_evc_class = PMC_CLASS_##CLASS , \ 315 .pm_evc_event_table = EVENTS##_event_table , \ 316 .pm_evc_event_table_size = \ 317 PMC_EVENT_TABLE_SIZE(EVENTS), \ 318 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 319 } 320 321 #if defined(__i386__) || defined(__amd64__) 322 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 323 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 324 PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); 325 PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 326 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 327 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 328 PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); 329 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); 330 PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap); 331 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); 332 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); 333 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 334 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); 335 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 336 PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); 337 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 338 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 339 PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); 340 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 341 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 342 #endif 343 #if defined(__i386__) 344 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 345 #endif 346 #if defined(__i386__) || defined(__amd64__) 347 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 348 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 349 #endif 350 #if defined(__i386__) 351 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 352 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 353 #endif 354 #if defined(__i386__) || defined(__amd64__) 355 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 356 #endif 357 #if defined(__arm__) 358 #if defined(__XSCALE__) 359 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 360 #endif 361 PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7); 362 #endif 363 #if defined(__mips__) 364 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 365 PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); 366 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 367 #endif /* __mips__ */ 368 #if defined(__powerpc__) 369 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 370 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 371 #endif 372 373 static struct pmc_class_descr soft_class_table_descr = 374 { 375 .pm_evc_name = "SOFT-", 376 .pm_evc_name_size = sizeof("SOFT-") - 1, 377 .pm_evc_class = PMC_CLASS_SOFT, 378 .pm_evc_event_table = NULL, 379 .pm_evc_event_table_size = 0, 380 .pm_evc_allocate_pmc = soft_allocate_pmc 381 }; 382 383 #undef PMC_CLASS_TABLE_DESC 384 385 static const struct pmc_class_descr **pmc_class_table; 386 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 387 388 static const enum pmc_class *pmc_mdep_class_list; 389 static size_t pmc_mdep_class_list_size; 390 391 /* 392 * Mapping tables, mapping enumeration values to human readable 393 * strings. 394 */ 395 396 static const char * pmc_capability_names[] = { 397 #undef __PMC_CAP 398 #define __PMC_CAP(N,V,D) #N , 399 __PMC_CAPS() 400 }; 401 402 static const char * pmc_class_names[] = { 403 #undef __PMC_CLASS 404 #define __PMC_CLASS(C) #C , 405 __PMC_CLASSES() 406 }; 407 408 struct pmc_cputype_map { 409 enum pmc_cputype pm_cputype; 410 const char *pm_name; 411 }; 412 413 static const struct pmc_cputype_map pmc_cputype_names[] = { 414 #undef __PMC_CPU 415 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 416 __PMC_CPUS() 417 }; 418 419 static const char * pmc_disposition_names[] = { 420 #undef __PMC_DISP 421 #define __PMC_DISP(D) #D , 422 __PMC_DISPOSITIONS() 423 }; 424 425 static const char * pmc_mode_names[] = { 426 #undef __PMC_MODE 427 #define __PMC_MODE(M,N) #M , 428 __PMC_MODES() 429 }; 430 431 static const char * pmc_state_names[] = { 432 #undef __PMC_STATE 433 #define __PMC_STATE(S) #S , 434 __PMC_STATES() 435 }; 436 437 /* 438 * Filled in by pmc_init(). 439 */ 440 static int pmc_syscall = -1; 441 static struct pmc_cpuinfo cpu_info; 442 static struct pmc_op_getdyneventinfo soft_event_info; 443 444 /* Event masks for events */ 445 struct pmc_masks { 446 const char *pm_name; 447 const uint64_t pm_value; 448 }; 449 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 450 #define NULLMASK { .pm_name = NULL } 451 452 #if defined(__amd64__) || defined(__i386__) 453 static int 454 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 455 { 456 const struct pmc_masks *pm; 457 char *q, *r; 458 int c; 459 460 if (pmask == NULL) /* no mask keywords */ 461 return (-1); 462 q = strchr(p, '='); /* skip '=' */ 463 if (*++q == '\0') /* no more data */ 464 return (-1); 465 c = 0; /* count of mask keywords seen */ 466 while ((r = strsep(&q, "+")) != NULL) { 467 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 468 pm++) 469 ; 470 if (pm->pm_name == NULL) /* not found */ 471 return (-1); 472 *evmask |= pm->pm_value; 473 c++; 474 } 475 return (c); 476 } 477 #endif 478 479 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 480 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 481 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 482 483 #if defined(__i386__) 484 485 /* 486 * AMD K7 (Athlon) CPUs. 487 */ 488 489 static struct pmc_event_alias k7_aliases[] = { 490 EV_ALIAS("branches", "k7-retired-branches"), 491 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 492 EV_ALIAS("cycles", "tsc"), 493 EV_ALIAS("dc-misses", "k7-dc-misses"), 494 EV_ALIAS("ic-misses", "k7-ic-misses"), 495 EV_ALIAS("instructions", "k7-retired-instructions"), 496 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 497 EV_ALIAS(NULL, NULL) 498 }; 499 500 #define K7_KW_COUNT "count" 501 #define K7_KW_EDGE "edge" 502 #define K7_KW_INV "inv" 503 #define K7_KW_OS "os" 504 #define K7_KW_UNITMASK "unitmask" 505 #define K7_KW_USR "usr" 506 507 static int 508 k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 509 struct pmc_op_pmcallocate *pmc_config) 510 { 511 char *e, *p, *q; 512 int c, has_unitmask; 513 uint32_t count, unitmask; 514 515 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 516 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 517 518 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 519 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 520 pe == PMC_EV_K7_DC_WRITEBACKS) { 521 has_unitmask = 1; 522 unitmask = AMD_PMC_UNITMASK_MOESI; 523 } else 524 unitmask = has_unitmask = 0; 525 526 while ((p = strsep(&ctrspec, ",")) != NULL) { 527 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 528 q = strchr(p, '='); 529 if (*++q == '\0') /* skip '=' */ 530 return (-1); 531 532 count = strtol(q, &e, 0); 533 if (e == q || *e != '\0') 534 return (-1); 535 536 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 537 pmc_config->pm_md.pm_amd.pm_amd_config |= 538 AMD_PMC_TO_COUNTER(count); 539 540 } else if (KWMATCH(p, K7_KW_EDGE)) { 541 pmc_config->pm_caps |= PMC_CAP_EDGE; 542 } else if (KWMATCH(p, K7_KW_INV)) { 543 pmc_config->pm_caps |= PMC_CAP_INVERT; 544 } else if (KWMATCH(p, K7_KW_OS)) { 545 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 546 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 547 if (has_unitmask == 0) 548 return (-1); 549 unitmask = 0; 550 q = strchr(p, '='); 551 if (*++q == '\0') /* skip '=' */ 552 return (-1); 553 554 while ((c = tolower(*q++)) != 0) 555 if (c == 'm') 556 unitmask |= AMD_PMC_UNITMASK_M; 557 else if (c == 'o') 558 unitmask |= AMD_PMC_UNITMASK_O; 559 else if (c == 'e') 560 unitmask |= AMD_PMC_UNITMASK_E; 561 else if (c == 's') 562 unitmask |= AMD_PMC_UNITMASK_S; 563 else if (c == 'i') 564 unitmask |= AMD_PMC_UNITMASK_I; 565 else if (c == '+') 566 continue; 567 else 568 return (-1); 569 570 if (unitmask == 0) 571 return (-1); 572 573 } else if (KWMATCH(p, K7_KW_USR)) { 574 pmc_config->pm_caps |= PMC_CAP_USER; 575 } else 576 return (-1); 577 } 578 579 if (has_unitmask) { 580 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 581 pmc_config->pm_md.pm_amd.pm_amd_config |= 582 AMD_PMC_TO_UNITMASK(unitmask); 583 } 584 585 return (0); 586 587 } 588 589 #endif 590 591 #if defined(__amd64__) || defined(__i386__) 592 593 /* 594 * Intel Core (Family 6, Model E) PMCs. 595 */ 596 597 static struct pmc_event_alias core_aliases[] = { 598 EV_ALIAS("branches", "iap-br-instr-ret"), 599 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 600 EV_ALIAS("cycles", "tsc-tsc"), 601 EV_ALIAS("ic-misses", "iap-icache-misses"), 602 EV_ALIAS("instructions", "iap-instr-ret"), 603 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 604 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 605 EV_ALIAS(NULL, NULL) 606 }; 607 608 /* 609 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 610 * and Atom (Family 6, model 1CH) PMCs. 611 * 612 * We map aliases to events on the fixed-function counters if these 613 * are present. Note that not all CPUs in this family contain fixed-function 614 * counters. 615 */ 616 617 static struct pmc_event_alias core2_aliases[] = { 618 EV_ALIAS("branches", "iap-br-inst-retired.any"), 619 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 620 EV_ALIAS("cycles", "tsc-tsc"), 621 EV_ALIAS("ic-misses", "iap-l1i-misses"), 622 EV_ALIAS("instructions", "iaf-instr-retired.any"), 623 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 624 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 625 EV_ALIAS(NULL, NULL) 626 }; 627 628 static struct pmc_event_alias core2_aliases_without_iaf[] = { 629 EV_ALIAS("branches", "iap-br-inst-retired.any"), 630 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 631 EV_ALIAS("cycles", "tsc-tsc"), 632 EV_ALIAS("ic-misses", "iap-l1i-misses"), 633 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 634 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 635 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 636 EV_ALIAS(NULL, NULL) 637 }; 638 639 #define atom_aliases core2_aliases 640 #define atom_aliases_without_iaf core2_aliases_without_iaf 641 #define atom_silvermont_aliases core2_aliases 642 #define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf 643 #define corei7_aliases core2_aliases 644 #define corei7_aliases_without_iaf core2_aliases_without_iaf 645 #define nehalem_ex_aliases core2_aliases 646 #define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf 647 #define haswell_aliases core2_aliases 648 #define haswell_aliases_without_iaf core2_aliases_without_iaf 649 #define haswell_xeon_aliases core2_aliases 650 #define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf 651 #define ivybridge_aliases core2_aliases 652 #define ivybridge_aliases_without_iaf core2_aliases_without_iaf 653 #define ivybridge_xeon_aliases core2_aliases 654 #define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 655 #define sandybridge_aliases core2_aliases 656 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf 657 #define sandybridge_xeon_aliases core2_aliases 658 #define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 659 #define westmere_aliases core2_aliases 660 #define westmere_aliases_without_iaf core2_aliases_without_iaf 661 #define westmere_ex_aliases core2_aliases 662 #define westmere_ex_aliases_without_iaf core2_aliases_without_iaf 663 664 #define IAF_KW_OS "os" 665 #define IAF_KW_USR "usr" 666 #define IAF_KW_ANYTHREAD "anythread" 667 668 /* 669 * Parse an event specifier for Intel fixed function counters. 670 */ 671 static int 672 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 673 struct pmc_op_pmcallocate *pmc_config) 674 { 675 char *p; 676 677 (void) pe; 678 679 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 680 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 681 682 while ((p = strsep(&ctrspec, ",")) != NULL) { 683 if (KWMATCH(p, IAF_KW_OS)) 684 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 685 else if (KWMATCH(p, IAF_KW_USR)) 686 pmc_config->pm_caps |= PMC_CAP_USER; 687 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 688 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 689 else 690 return (-1); 691 } 692 693 return (0); 694 } 695 696 /* 697 * Core/Core2 support. 698 */ 699 700 #define IAP_KW_AGENT "agent" 701 #define IAP_KW_ANYTHREAD "anythread" 702 #define IAP_KW_CACHESTATE "cachestate" 703 #define IAP_KW_CMASK "cmask" 704 #define IAP_KW_CORE "core" 705 #define IAP_KW_EDGE "edge" 706 #define IAP_KW_INV "inv" 707 #define IAP_KW_OS "os" 708 #define IAP_KW_PREFETCH "prefetch" 709 #define IAP_KW_SNOOPRESPONSE "snoopresponse" 710 #define IAP_KW_SNOOPTYPE "snooptype" 711 #define IAP_KW_TRANSITION "trans" 712 #define IAP_KW_USR "usr" 713 #define IAP_KW_RSP "rsp" 714 715 static struct pmc_masks iap_core_mask[] = { 716 PMCMASK(all, (0x3 << 14)), 717 PMCMASK(this, (0x1 << 14)), 718 NULLMASK 719 }; 720 721 static struct pmc_masks iap_agent_mask[] = { 722 PMCMASK(this, 0), 723 PMCMASK(any, (0x1 << 13)), 724 NULLMASK 725 }; 726 727 static struct pmc_masks iap_prefetch_mask[] = { 728 PMCMASK(both, (0x3 << 12)), 729 PMCMASK(only, (0x1 << 12)), 730 PMCMASK(exclude, 0), 731 NULLMASK 732 }; 733 734 static struct pmc_masks iap_cachestate_mask[] = { 735 PMCMASK(i, (1 << 8)), 736 PMCMASK(s, (1 << 9)), 737 PMCMASK(e, (1 << 10)), 738 PMCMASK(m, (1 << 11)), 739 NULLMASK 740 }; 741 742 static struct pmc_masks iap_snoopresponse_mask[] = { 743 PMCMASK(clean, (1 << 8)), 744 PMCMASK(hit, (1 << 9)), 745 PMCMASK(hitm, (1 << 11)), 746 NULLMASK 747 }; 748 749 static struct pmc_masks iap_snooptype_mask[] = { 750 PMCMASK(cmp2s, (1 << 8)), 751 PMCMASK(cmp2i, (1 << 9)), 752 NULLMASK 753 }; 754 755 static struct pmc_masks iap_transition_mask[] = { 756 PMCMASK(any, 0x00), 757 PMCMASK(frequency, 0x10), 758 NULLMASK 759 }; 760 761 static struct pmc_masks iap_rsp_mask_i7_wm[] = { 762 PMCMASK(DMND_DATA_RD, (1 << 0)), 763 PMCMASK(DMND_RFO, (1 << 1)), 764 PMCMASK(DMND_IFETCH, (1 << 2)), 765 PMCMASK(WB, (1 << 3)), 766 PMCMASK(PF_DATA_RD, (1 << 4)), 767 PMCMASK(PF_RFO, (1 << 5)), 768 PMCMASK(PF_IFETCH, (1 << 6)), 769 PMCMASK(OTHER, (1 << 7)), 770 PMCMASK(UNCORE_HIT, (1 << 8)), 771 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 772 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 773 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 774 PMCMASK(REMOTE_DRAM, (1 << 13)), 775 PMCMASK(LOCAL_DRAM, (1 << 14)), 776 PMCMASK(NON_DRAM, (1 << 15)), 777 NULLMASK 778 }; 779 780 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { 781 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 782 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 783 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 784 PMCMASK(REQ_WB, (1ULL << 3)), 785 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 786 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 787 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 788 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), 789 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), 790 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), 791 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), 792 PMCMASK(REQ_STRM_ST, (1ULL << 11)), 793 PMCMASK(REQ_OTHER, (1ULL << 15)), 794 PMCMASK(RES_ANY, (1ULL << 16)), 795 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 796 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 797 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 798 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 799 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 800 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 801 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 802 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 803 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 804 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 805 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 806 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 807 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 808 NULLMASK 809 }; 810 811 static struct pmc_masks iap_rsp_mask_haswell[] = { 812 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 813 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 814 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 815 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 816 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 817 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 818 PMCMASK(REQ_OTHER, (1ULL << 15)), 819 PMCMASK(RES_ANY, (1ULL << 16)), 820 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 821 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 822 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 823 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 824 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 825 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 826 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 827 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 828 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 829 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 830 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 831 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 832 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 833 NULLMASK 834 }; 835 836 static int 837 iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 838 struct pmc_op_pmcallocate *pmc_config) 839 { 840 char *e, *p, *q; 841 uint64_t cachestate, evmask, rsp; 842 int count, n; 843 844 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 845 PMC_CAP_QUALIFIER); 846 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 847 848 cachestate = evmask = rsp = 0; 849 850 /* Parse additional modifiers if present */ 851 while ((p = strsep(&ctrspec, ",")) != NULL) { 852 853 n = 0; 854 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 855 q = strchr(p, '='); 856 if (*++q == '\0') /* skip '=' */ 857 return (-1); 858 count = strtol(q, &e, 0); 859 if (e == q || *e != '\0') 860 return (-1); 861 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 862 pmc_config->pm_md.pm_iap.pm_iap_config |= 863 IAP_CMASK(count); 864 } else if (KWMATCH(p, IAP_KW_EDGE)) { 865 pmc_config->pm_caps |= PMC_CAP_EDGE; 866 } else if (KWMATCH(p, IAP_KW_INV)) { 867 pmc_config->pm_caps |= PMC_CAP_INVERT; 868 } else if (KWMATCH(p, IAP_KW_OS)) { 869 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 870 } else if (KWMATCH(p, IAP_KW_USR)) { 871 pmc_config->pm_caps |= PMC_CAP_USER; 872 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 873 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 874 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 875 n = pmc_parse_mask(iap_core_mask, p, &evmask); 876 if (n != 1) 877 return (-1); 878 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 879 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 880 if (n != 1) 881 return (-1); 882 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 883 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 884 if (n != 1) 885 return (-1); 886 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 887 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 888 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 889 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 890 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 891 if (n != 1) 892 return (-1); 893 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 894 cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 895 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 896 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 897 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 898 n = pmc_parse_mask(iap_snoopresponse_mask, p, 899 &evmask); 900 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 901 n = pmc_parse_mask(iap_snooptype_mask, p, 902 &evmask); 903 } else 904 return (-1); 905 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 906 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || 907 cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || 908 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { 909 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 910 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); 911 } else 912 return (-1); 913 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 914 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 915 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || 916 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { 917 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 918 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); 919 } else 920 return (-1); 921 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL || 922 cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) { 923 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 924 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); 925 } else 926 return (-1); 927 } else 928 return (-1); 929 930 if (n < 0) /* Parsing failed. */ 931 return (-1); 932 } 933 934 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 935 936 /* 937 * If the event requires a 'cachestate' qualifier but was not 938 * specified by the user, use a sensible default. 939 */ 940 switch (pe) { 941 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 942 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 943 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 944 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 945 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 946 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 947 case PMC_EV_IAP_EVENT_32H: /* Core */ 948 case PMC_EV_IAP_EVENT_40H: /* Core */ 949 case PMC_EV_IAP_EVENT_41H: /* Core */ 950 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 951 if (cachestate == 0) 952 cachestate = (0xF << 8); 953 break; 954 case PMC_EV_IAP_EVENT_77H: /* Atom */ 955 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 956 * Atom processor 957 */ 958 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 959 cachestate = (0xF << 8); 960 break; 961 default: 962 break; 963 } 964 965 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 966 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 967 968 return (0); 969 } 970 971 /* 972 * Intel Uncore. 973 */ 974 975 static int 976 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 977 struct pmc_op_pmcallocate *pmc_config) 978 { 979 (void) pe; 980 (void) ctrspec; 981 982 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 983 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 984 985 return (0); 986 } 987 988 #define UCP_KW_CMASK "cmask" 989 #define UCP_KW_EDGE "edge" 990 #define UCP_KW_INV "inv" 991 992 static int 993 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 994 struct pmc_op_pmcallocate *pmc_config) 995 { 996 char *e, *p, *q; 997 int count, n; 998 999 (void) pe; 1000 1001 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 1002 PMC_CAP_QUALIFIER); 1003 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 1004 1005 /* Parse additional modifiers if present */ 1006 while ((p = strsep(&ctrspec, ",")) != NULL) { 1007 1008 n = 0; 1009 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 1010 q = strchr(p, '='); 1011 if (*++q == '\0') /* skip '=' */ 1012 return (-1); 1013 count = strtol(q, &e, 0); 1014 if (e == q || *e != '\0') 1015 return (-1); 1016 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1017 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 1018 UCP_CMASK(count); 1019 } else if (KWMATCH(p, UCP_KW_EDGE)) { 1020 pmc_config->pm_caps |= PMC_CAP_EDGE; 1021 } else if (KWMATCH(p, UCP_KW_INV)) { 1022 pmc_config->pm_caps |= PMC_CAP_INVERT; 1023 } else 1024 return (-1); 1025 1026 if (n < 0) /* Parsing failed. */ 1027 return (-1); 1028 } 1029 1030 return (0); 1031 } 1032 1033 /* 1034 * AMD K8 PMCs. 1035 * 1036 * These are very similar to AMD K7 PMCs, but support more kinds of 1037 * events. 1038 */ 1039 1040 static struct pmc_event_alias k8_aliases[] = { 1041 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 1042 EV_ALIAS("branch-mispredicts", 1043 "k8-fr-retired-taken-branches-mispredicted"), 1044 EV_ALIAS("cycles", "tsc"), 1045 EV_ALIAS("dc-misses", "k8-dc-miss"), 1046 EV_ALIAS("ic-misses", "k8-ic-miss"), 1047 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 1048 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 1049 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 1050 EV_ALIAS(NULL, NULL) 1051 }; 1052 1053 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 1054 1055 /* 1056 * Parsing tables 1057 */ 1058 1059 /* fp dispatched fpu ops */ 1060 static const struct pmc_masks k8_mask_fdfo[] = { 1061 __K8MASK(add-pipe-excluding-junk-ops, 0), 1062 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 1063 __K8MASK(store-pipe-excluding-junk-ops, 2), 1064 __K8MASK(add-pipe-junk-ops, 3), 1065 __K8MASK(multiply-pipe-junk-ops, 4), 1066 __K8MASK(store-pipe-junk-ops, 5), 1067 NULLMASK 1068 }; 1069 1070 /* ls segment register loads */ 1071 static const struct pmc_masks k8_mask_lsrl[] = { 1072 __K8MASK(es, 0), 1073 __K8MASK(cs, 1), 1074 __K8MASK(ss, 2), 1075 __K8MASK(ds, 3), 1076 __K8MASK(fs, 4), 1077 __K8MASK(gs, 5), 1078 __K8MASK(hs, 6), 1079 NULLMASK 1080 }; 1081 1082 /* ls locked operation */ 1083 static const struct pmc_masks k8_mask_llo[] = { 1084 __K8MASK(locked-instructions, 0), 1085 __K8MASK(cycles-in-request, 1), 1086 __K8MASK(cycles-to-complete, 2), 1087 NULLMASK 1088 }; 1089 1090 /* dc refill from {l2,system} and dc copyback */ 1091 static const struct pmc_masks k8_mask_dc[] = { 1092 __K8MASK(invalid, 0), 1093 __K8MASK(shared, 1), 1094 __K8MASK(exclusive, 2), 1095 __K8MASK(owner, 3), 1096 __K8MASK(modified, 4), 1097 NULLMASK 1098 }; 1099 1100 /* dc one bit ecc error */ 1101 static const struct pmc_masks k8_mask_dobee[] = { 1102 __K8MASK(scrubber, 0), 1103 __K8MASK(piggyback, 1), 1104 NULLMASK 1105 }; 1106 1107 /* dc dispatched prefetch instructions */ 1108 static const struct pmc_masks k8_mask_ddpi[] = { 1109 __K8MASK(load, 0), 1110 __K8MASK(store, 1), 1111 __K8MASK(nta, 2), 1112 NULLMASK 1113 }; 1114 1115 /* dc dcache accesses by locks */ 1116 static const struct pmc_masks k8_mask_dabl[] = { 1117 __K8MASK(accesses, 0), 1118 __K8MASK(misses, 1), 1119 NULLMASK 1120 }; 1121 1122 /* bu internal l2 request */ 1123 static const struct pmc_masks k8_mask_bilr[] = { 1124 __K8MASK(ic-fill, 0), 1125 __K8MASK(dc-fill, 1), 1126 __K8MASK(tlb-reload, 2), 1127 __K8MASK(tag-snoop, 3), 1128 __K8MASK(cancelled, 4), 1129 NULLMASK 1130 }; 1131 1132 /* bu fill request l2 miss */ 1133 static const struct pmc_masks k8_mask_bfrlm[] = { 1134 __K8MASK(ic-fill, 0), 1135 __K8MASK(dc-fill, 1), 1136 __K8MASK(tlb-reload, 2), 1137 NULLMASK 1138 }; 1139 1140 /* bu fill into l2 */ 1141 static const struct pmc_masks k8_mask_bfil[] = { 1142 __K8MASK(dirty-l2-victim, 0), 1143 __K8MASK(victim-from-l2, 1), 1144 NULLMASK 1145 }; 1146 1147 /* fr retired fpu instructions */ 1148 static const struct pmc_masks k8_mask_frfi[] = { 1149 __K8MASK(x87, 0), 1150 __K8MASK(mmx-3dnow, 1), 1151 __K8MASK(packed-sse-sse2, 2), 1152 __K8MASK(scalar-sse-sse2, 3), 1153 NULLMASK 1154 }; 1155 1156 /* fr retired fastpath double op instructions */ 1157 static const struct pmc_masks k8_mask_frfdoi[] = { 1158 __K8MASK(low-op-pos-0, 0), 1159 __K8MASK(low-op-pos-1, 1), 1160 __K8MASK(low-op-pos-2, 2), 1161 NULLMASK 1162 }; 1163 1164 /* fr fpu exceptions */ 1165 static const struct pmc_masks k8_mask_ffe[] = { 1166 __K8MASK(x87-reclass-microfaults, 0), 1167 __K8MASK(sse-retype-microfaults, 1), 1168 __K8MASK(sse-reclass-microfaults, 2), 1169 __K8MASK(sse-and-x87-microtraps, 3), 1170 NULLMASK 1171 }; 1172 1173 /* nb memory controller page access event */ 1174 static const struct pmc_masks k8_mask_nmcpae[] = { 1175 __K8MASK(page-hit, 0), 1176 __K8MASK(page-miss, 1), 1177 __K8MASK(page-conflict, 2), 1178 NULLMASK 1179 }; 1180 1181 /* nb memory controller turnaround */ 1182 static const struct pmc_masks k8_mask_nmct[] = { 1183 __K8MASK(dimm-turnaround, 0), 1184 __K8MASK(read-to-write-turnaround, 1), 1185 __K8MASK(write-to-read-turnaround, 2), 1186 NULLMASK 1187 }; 1188 1189 /* nb memory controller bypass saturation */ 1190 static const struct pmc_masks k8_mask_nmcbs[] = { 1191 __K8MASK(memory-controller-hi-pri-bypass, 0), 1192 __K8MASK(memory-controller-lo-pri-bypass, 1), 1193 __K8MASK(dram-controller-interface-bypass, 2), 1194 __K8MASK(dram-controller-queue-bypass, 3), 1195 NULLMASK 1196 }; 1197 1198 /* nb sized commands */ 1199 static const struct pmc_masks k8_mask_nsc[] = { 1200 __K8MASK(nonpostwrszbyte, 0), 1201 __K8MASK(nonpostwrszdword, 1), 1202 __K8MASK(postwrszbyte, 2), 1203 __K8MASK(postwrszdword, 3), 1204 __K8MASK(rdszbyte, 4), 1205 __K8MASK(rdszdword, 5), 1206 __K8MASK(rdmodwr, 6), 1207 NULLMASK 1208 }; 1209 1210 /* nb probe result */ 1211 static const struct pmc_masks k8_mask_npr[] = { 1212 __K8MASK(probe-miss, 0), 1213 __K8MASK(probe-hit, 1), 1214 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1215 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1216 NULLMASK 1217 }; 1218 1219 /* nb hypertransport bus bandwidth */ 1220 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1221 __K8MASK(command, 0), 1222 __K8MASK(data, 1), 1223 __K8MASK(buffer-release, 2), 1224 __K8MASK(nop, 3), 1225 NULLMASK 1226 }; 1227 1228 #undef __K8MASK 1229 1230 #define K8_KW_COUNT "count" 1231 #define K8_KW_EDGE "edge" 1232 #define K8_KW_INV "inv" 1233 #define K8_KW_MASK "mask" 1234 #define K8_KW_OS "os" 1235 #define K8_KW_USR "usr" 1236 1237 static int 1238 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1239 struct pmc_op_pmcallocate *pmc_config) 1240 { 1241 char *e, *p, *q; 1242 int n; 1243 uint32_t count; 1244 uint64_t evmask; 1245 const struct pmc_masks *pm, *pmask; 1246 1247 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1248 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1249 1250 pmask = NULL; 1251 evmask = 0; 1252 1253 #define __K8SETMASK(M) pmask = k8_mask_##M 1254 1255 /* setup parsing tables */ 1256 switch (pe) { 1257 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1258 __K8SETMASK(fdfo); 1259 break; 1260 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1261 __K8SETMASK(lsrl); 1262 break; 1263 case PMC_EV_K8_LS_LOCKED_OPERATION: 1264 __K8SETMASK(llo); 1265 break; 1266 case PMC_EV_K8_DC_REFILL_FROM_L2: 1267 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1268 case PMC_EV_K8_DC_COPYBACK: 1269 __K8SETMASK(dc); 1270 break; 1271 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1272 __K8SETMASK(dobee); 1273 break; 1274 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1275 __K8SETMASK(ddpi); 1276 break; 1277 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1278 __K8SETMASK(dabl); 1279 break; 1280 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1281 __K8SETMASK(bilr); 1282 break; 1283 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1284 __K8SETMASK(bfrlm); 1285 break; 1286 case PMC_EV_K8_BU_FILL_INTO_L2: 1287 __K8SETMASK(bfil); 1288 break; 1289 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1290 __K8SETMASK(frfi); 1291 break; 1292 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1293 __K8SETMASK(frfdoi); 1294 break; 1295 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1296 __K8SETMASK(ffe); 1297 break; 1298 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1299 __K8SETMASK(nmcpae); 1300 break; 1301 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1302 __K8SETMASK(nmct); 1303 break; 1304 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1305 __K8SETMASK(nmcbs); 1306 break; 1307 case PMC_EV_K8_NB_SIZED_COMMANDS: 1308 __K8SETMASK(nsc); 1309 break; 1310 case PMC_EV_K8_NB_PROBE_RESULT: 1311 __K8SETMASK(npr); 1312 break; 1313 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1314 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1315 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1316 __K8SETMASK(nhbb); 1317 break; 1318 1319 default: 1320 break; /* no options defined */ 1321 } 1322 1323 while ((p = strsep(&ctrspec, ",")) != NULL) { 1324 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1325 q = strchr(p, '='); 1326 if (*++q == '\0') /* skip '=' */ 1327 return (-1); 1328 1329 count = strtol(q, &e, 0); 1330 if (e == q || *e != '\0') 1331 return (-1); 1332 1333 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1334 pmc_config->pm_md.pm_amd.pm_amd_config |= 1335 AMD_PMC_TO_COUNTER(count); 1336 1337 } else if (KWMATCH(p, K8_KW_EDGE)) { 1338 pmc_config->pm_caps |= PMC_CAP_EDGE; 1339 } else if (KWMATCH(p, K8_KW_INV)) { 1340 pmc_config->pm_caps |= PMC_CAP_INVERT; 1341 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1342 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1343 return (-1); 1344 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1345 } else if (KWMATCH(p, K8_KW_OS)) { 1346 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1347 } else if (KWMATCH(p, K8_KW_USR)) { 1348 pmc_config->pm_caps |= PMC_CAP_USER; 1349 } else 1350 return (-1); 1351 } 1352 1353 /* other post processing */ 1354 switch (pe) { 1355 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1356 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1357 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1358 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1359 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1360 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1361 /* XXX only available in rev B and later */ 1362 break; 1363 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1364 /* XXX only available in rev C and later */ 1365 break; 1366 case PMC_EV_K8_LS_LOCKED_OPERATION: 1367 /* XXX CPU Rev A,B evmask is to be zero */ 1368 if (evmask & (evmask - 1)) /* > 1 bit set */ 1369 return (-1); 1370 if (evmask == 0) { 1371 evmask = 0x01; /* Rev C and later: #instrs */ 1372 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1373 } 1374 break; 1375 default: 1376 if (evmask == 0 && pmask != NULL) { 1377 for (pm = pmask; pm->pm_name; pm++) 1378 evmask |= pm->pm_value; 1379 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1380 } 1381 } 1382 1383 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1384 pmc_config->pm_md.pm_amd.pm_amd_config = 1385 AMD_PMC_TO_UNITMASK(evmask); 1386 1387 return (0); 1388 } 1389 1390 #endif 1391 1392 #if defined(__amd64__) || defined(__i386__) 1393 1394 /* 1395 * Intel P4 PMCs 1396 */ 1397 1398 static struct pmc_event_alias p4_aliases[] = { 1399 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1400 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1401 EV_ALIAS("cycles", "tsc"), 1402 EV_ALIAS("instructions", 1403 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1404 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1405 EV_ALIAS(NULL, NULL) 1406 }; 1407 1408 #define P4_KW_ACTIVE "active" 1409 #define P4_KW_ACTIVE_ANY "any" 1410 #define P4_KW_ACTIVE_BOTH "both" 1411 #define P4_KW_ACTIVE_NONE "none" 1412 #define P4_KW_ACTIVE_SINGLE "single" 1413 #define P4_KW_BUSREQTYPE "busreqtype" 1414 #define P4_KW_CASCADE "cascade" 1415 #define P4_KW_EDGE "edge" 1416 #define P4_KW_INV "complement" 1417 #define P4_KW_OS "os" 1418 #define P4_KW_MASK "mask" 1419 #define P4_KW_PRECISE "precise" 1420 #define P4_KW_TAG "tag" 1421 #define P4_KW_THRESHOLD "threshold" 1422 #define P4_KW_USR "usr" 1423 1424 #define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1425 1426 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1427 __P4MASK(dd, 0), 1428 __P4MASK(db, 1), 1429 __P4MASK(di, 2), 1430 __P4MASK(bd, 3), 1431 __P4MASK(bb, 4), 1432 __P4MASK(bi, 5), 1433 __P4MASK(id, 6), 1434 __P4MASK(ib, 7), 1435 NULLMASK 1436 }; 1437 1438 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1439 __P4MASK(tcmiss, 0), 1440 NULLMASK, 1441 }; 1442 1443 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1444 __P4MASK(hit, 0), 1445 __P4MASK(miss, 1), 1446 __P4MASK(hit-uc, 2), 1447 NULLMASK 1448 }; 1449 1450 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1451 __P4MASK(st-rb-full, 2), 1452 __P4MASK(64k-conf, 3), 1453 NULLMASK 1454 }; 1455 1456 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1457 __P4MASK(lsc, 0), 1458 __P4MASK(ssc, 1), 1459 NULLMASK 1460 }; 1461 1462 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1463 __P4MASK(split-ld, 1), 1464 NULLMASK 1465 }; 1466 1467 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1468 __P4MASK(split-st, 1), 1469 NULLMASK 1470 }; 1471 1472 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1473 __P4MASK(no-sta, 1), 1474 __P4MASK(no-std, 3), 1475 __P4MASK(partial-data, 4), 1476 __P4MASK(unalgn-addr, 5), 1477 NULLMASK 1478 }; 1479 1480 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1481 __P4MASK(dtmiss, 0), 1482 __P4MASK(itmiss, 1), 1483 NULLMASK 1484 }; 1485 1486 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1487 __P4MASK(rd-2ndl-hits, 0), 1488 __P4MASK(rd-2ndl-hite, 1), 1489 __P4MASK(rd-2ndl-hitm, 2), 1490 __P4MASK(rd-3rdl-hits, 3), 1491 __P4MASK(rd-3rdl-hite, 4), 1492 __P4MASK(rd-3rdl-hitm, 5), 1493 __P4MASK(rd-2ndl-miss, 8), 1494 __P4MASK(rd-3rdl-miss, 9), 1495 __P4MASK(wr-2ndl-miss, 10), 1496 NULLMASK 1497 }; 1498 1499 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1500 __P4MASK(all-read, 5), 1501 __P4MASK(all-write, 6), 1502 __P4MASK(mem-uc, 7), 1503 __P4MASK(mem-wc, 8), 1504 __P4MASK(mem-wt, 9), 1505 __P4MASK(mem-wp, 10), 1506 __P4MASK(mem-wb, 11), 1507 __P4MASK(own, 13), 1508 __P4MASK(other, 14), 1509 __P4MASK(prefetch, 15), 1510 NULLMASK 1511 }; 1512 1513 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1514 __P4MASK(all-read, 5), 1515 __P4MASK(all-write, 6), 1516 __P4MASK(mem-uc, 7), 1517 __P4MASK(mem-wc, 8), 1518 __P4MASK(mem-wt, 9), 1519 __P4MASK(mem-wp, 10), 1520 __P4MASK(mem-wb, 11), 1521 __P4MASK(own, 13), 1522 __P4MASK(other, 14), 1523 __P4MASK(prefetch, 15), 1524 NULLMASK 1525 }; 1526 1527 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1528 __P4MASK(drdy-drv, 0), 1529 __P4MASK(drdy-own, 1), 1530 __P4MASK(drdy-other, 2), 1531 __P4MASK(dbsy-drv, 3), 1532 __P4MASK(dbsy-own, 4), 1533 __P4MASK(dbsy-other, 5), 1534 NULLMASK 1535 }; 1536 1537 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1538 __P4MASK(req-type0, 0), 1539 __P4MASK(req-type1, 1), 1540 __P4MASK(req-len0, 2), 1541 __P4MASK(req-len1, 3), 1542 __P4MASK(req-io-type, 5), 1543 __P4MASK(req-lock-type, 6), 1544 __P4MASK(req-cache-type, 7), 1545 __P4MASK(req-split-type, 8), 1546 __P4MASK(req-dem-type, 9), 1547 __P4MASK(req-ord-type, 10), 1548 __P4MASK(mem-type0, 11), 1549 __P4MASK(mem-type1, 12), 1550 __P4MASK(mem-type2, 13), 1551 NULLMASK 1552 }; 1553 1554 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1555 __P4MASK(all, 15), 1556 NULLMASK 1557 }; 1558 1559 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1560 __P4MASK(all, 15), 1561 NULLMASK 1562 }; 1563 1564 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1565 __P4MASK(all, 15), 1566 NULLMASK 1567 }; 1568 1569 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1570 __P4MASK(all, 15), 1571 NULLMASK 1572 }; 1573 1574 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1575 __P4MASK(all, 15), 1576 NULLMASK 1577 }; 1578 1579 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1580 __P4MASK(all, 15), 1581 NULLMASK 1582 }; 1583 1584 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1585 __P4MASK(all, 15), 1586 NULLMASK 1587 }; 1588 1589 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1590 __P4MASK(all, 15), 1591 NULLMASK 1592 }; 1593 1594 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1595 __P4MASK(allp0, 3), 1596 __P4MASK(allp2, 4), 1597 NULLMASK 1598 }; 1599 1600 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1601 __P4MASK(running, 0), 1602 NULLMASK 1603 }; 1604 1605 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1606 __P4MASK(cisc, 0), 1607 NULLMASK 1608 }; 1609 1610 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1611 __P4MASK(from-tc-build, 0), 1612 __P4MASK(from-tc-deliver, 1), 1613 __P4MASK(from-rom, 2), 1614 NULLMASK 1615 }; 1616 1617 static const struct pmc_masks p4_mask_rmbt[] = { 1618 /* retired mispred branch type */ 1619 __P4MASK(conditional, 1), 1620 __P4MASK(call, 2), 1621 __P4MASK(return, 3), 1622 __P4MASK(indirect, 4), 1623 NULLMASK 1624 }; 1625 1626 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1627 __P4MASK(conditional, 1), 1628 __P4MASK(call, 2), 1629 __P4MASK(retired, 3), 1630 __P4MASK(indirect, 4), 1631 NULLMASK 1632 }; 1633 1634 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1635 __P4MASK(sbfull, 5), 1636 NULLMASK 1637 }; 1638 1639 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1640 __P4MASK(wcb-evicts, 0), 1641 __P4MASK(wcb-full-evict, 1), 1642 NULLMASK 1643 }; 1644 1645 static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1646 __P4MASK(nbogus, 0), 1647 __P4MASK(bogus, 1), 1648 NULLMASK 1649 }; 1650 1651 static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1652 __P4MASK(nbogus0, 0), 1653 __P4MASK(nbogus1, 1), 1654 __P4MASK(nbogus2, 2), 1655 __P4MASK(nbogus3, 3), 1656 __P4MASK(bogus0, 4), 1657 __P4MASK(bogus1, 5), 1658 __P4MASK(bogus2, 6), 1659 __P4MASK(bogus3, 7), 1660 NULLMASK 1661 }; 1662 1663 static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1664 __P4MASK(nbogus, 0), 1665 __P4MASK(bogus, 1), 1666 NULLMASK 1667 }; 1668 1669 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1670 __P4MASK(nbogusntag, 0), 1671 __P4MASK(nbogustag, 1), 1672 __P4MASK(bogusntag, 2), 1673 __P4MASK(bogustag, 3), 1674 NULLMASK 1675 }; 1676 1677 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1678 __P4MASK(nbogus, 0), 1679 __P4MASK(bogus, 1), 1680 NULLMASK 1681 }; 1682 1683 static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1684 __P4MASK(tagloads, 1), 1685 __P4MASK(tagstores, 2), 1686 NULLMASK 1687 }; 1688 1689 static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1690 __P4MASK(mmnp, 0), 1691 __P4MASK(mmnm, 1), 1692 __P4MASK(mmtp, 2), 1693 __P4MASK(mmtm, 3), 1694 NULLMASK 1695 }; 1696 1697 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1698 __P4MASK(nbogus, 0), 1699 NULLMASK 1700 }; 1701 1702 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1703 __P4MASK(fpsu, 0), 1704 __P4MASK(fpso, 1), 1705 __P4MASK(poao, 2), 1706 __P4MASK(poau, 3), 1707 __P4MASK(prea, 4), 1708 NULLMASK 1709 }; 1710 1711 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1712 __P4MASK(clear, 0), 1713 __P4MASK(moclear, 2), 1714 __P4MASK(smclear, 3), 1715 NULLMASK 1716 }; 1717 1718 /* P4 event parser */ 1719 static int 1720 p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1721 struct pmc_op_pmcallocate *pmc_config) 1722 { 1723 1724 char *e, *p, *q; 1725 int count, has_tag, has_busreqtype, n; 1726 uint32_t cccractivemask; 1727 uint64_t evmask; 1728 const struct pmc_masks *pm, *pmask; 1729 1730 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1731 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1732 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1733 1734 pmask = NULL; 1735 evmask = 0; 1736 cccractivemask = 0x3; 1737 has_tag = has_busreqtype = 0; 1738 1739 #define __P4SETMASK(M) do { \ 1740 pmask = p4_mask_##M; \ 1741 } while (0) 1742 1743 switch (pe) { 1744 case PMC_EV_P4_TC_DELIVER_MODE: 1745 __P4SETMASK(tcdm); 1746 break; 1747 case PMC_EV_P4_BPU_FETCH_REQUEST: 1748 __P4SETMASK(bfr); 1749 break; 1750 case PMC_EV_P4_ITLB_REFERENCE: 1751 __P4SETMASK(ir); 1752 break; 1753 case PMC_EV_P4_MEMORY_CANCEL: 1754 __P4SETMASK(memcan); 1755 break; 1756 case PMC_EV_P4_MEMORY_COMPLETE: 1757 __P4SETMASK(memcomp); 1758 break; 1759 case PMC_EV_P4_LOAD_PORT_REPLAY: 1760 __P4SETMASK(lpr); 1761 break; 1762 case PMC_EV_P4_STORE_PORT_REPLAY: 1763 __P4SETMASK(spr); 1764 break; 1765 case PMC_EV_P4_MOB_LOAD_REPLAY: 1766 __P4SETMASK(mlr); 1767 break; 1768 case PMC_EV_P4_PAGE_WALK_TYPE: 1769 __P4SETMASK(pwt); 1770 break; 1771 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1772 __P4SETMASK(bcr); 1773 break; 1774 case PMC_EV_P4_IOQ_ALLOCATION: 1775 __P4SETMASK(ia); 1776 has_busreqtype = 1; 1777 break; 1778 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1779 __P4SETMASK(iae); 1780 has_busreqtype = 1; 1781 break; 1782 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1783 __P4SETMASK(fda); 1784 break; 1785 case PMC_EV_P4_BSQ_ALLOCATION: 1786 __P4SETMASK(ba); 1787 break; 1788 case PMC_EV_P4_SSE_INPUT_ASSIST: 1789 __P4SETMASK(sia); 1790 break; 1791 case PMC_EV_P4_PACKED_SP_UOP: 1792 __P4SETMASK(psu); 1793 break; 1794 case PMC_EV_P4_PACKED_DP_UOP: 1795 __P4SETMASK(pdu); 1796 break; 1797 case PMC_EV_P4_SCALAR_SP_UOP: 1798 __P4SETMASK(ssu); 1799 break; 1800 case PMC_EV_P4_SCALAR_DP_UOP: 1801 __P4SETMASK(sdu); 1802 break; 1803 case PMC_EV_P4_64BIT_MMX_UOP: 1804 __P4SETMASK(64bmu); 1805 break; 1806 case PMC_EV_P4_128BIT_MMX_UOP: 1807 __P4SETMASK(128bmu); 1808 break; 1809 case PMC_EV_P4_X87_FP_UOP: 1810 __P4SETMASK(xfu); 1811 break; 1812 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1813 __P4SETMASK(xsmu); 1814 break; 1815 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1816 __P4SETMASK(gpe); 1817 break; 1818 case PMC_EV_P4_TC_MS_XFER: 1819 __P4SETMASK(tmx); 1820 break; 1821 case PMC_EV_P4_UOP_QUEUE_WRITES: 1822 __P4SETMASK(uqw); 1823 break; 1824 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1825 __P4SETMASK(rmbt); 1826 break; 1827 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1828 __P4SETMASK(rbt); 1829 break; 1830 case PMC_EV_P4_RESOURCE_STALL: 1831 __P4SETMASK(rs); 1832 break; 1833 case PMC_EV_P4_WC_BUFFER: 1834 __P4SETMASK(wb); 1835 break; 1836 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1837 case PMC_EV_P4_B2B_CYCLES: 1838 case PMC_EV_P4_BNR: 1839 case PMC_EV_P4_SNOOP: 1840 case PMC_EV_P4_RESPONSE: 1841 break; 1842 case PMC_EV_P4_FRONT_END_EVENT: 1843 __P4SETMASK(fee); 1844 break; 1845 case PMC_EV_P4_EXECUTION_EVENT: 1846 __P4SETMASK(ee); 1847 break; 1848 case PMC_EV_P4_REPLAY_EVENT: 1849 __P4SETMASK(re); 1850 break; 1851 case PMC_EV_P4_INSTR_RETIRED: 1852 __P4SETMASK(insret); 1853 break; 1854 case PMC_EV_P4_UOPS_RETIRED: 1855 __P4SETMASK(ur); 1856 break; 1857 case PMC_EV_P4_UOP_TYPE: 1858 __P4SETMASK(ut); 1859 break; 1860 case PMC_EV_P4_BRANCH_RETIRED: 1861 __P4SETMASK(br); 1862 break; 1863 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1864 __P4SETMASK(mbr); 1865 break; 1866 case PMC_EV_P4_X87_ASSIST: 1867 __P4SETMASK(xa); 1868 break; 1869 case PMC_EV_P4_MACHINE_CLEAR: 1870 __P4SETMASK(machclr); 1871 break; 1872 default: 1873 return (-1); 1874 } 1875 1876 /* process additional flags */ 1877 while ((p = strsep(&ctrspec, ",")) != NULL) { 1878 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1879 q = strchr(p, '='); 1880 if (*++q == '\0') /* skip '=' */ 1881 return (-1); 1882 1883 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1884 cccractivemask = 0x0; 1885 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1886 cccractivemask = 0x1; 1887 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1888 cccractivemask = 0x2; 1889 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1890 cccractivemask = 0x3; 1891 else 1892 return (-1); 1893 1894 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1895 if (has_busreqtype == 0) 1896 return (-1); 1897 1898 q = strchr(p, '='); 1899 if (*++q == '\0') /* skip '=' */ 1900 return (-1); 1901 1902 count = strtol(q, &e, 0); 1903 if (e == q || *e != '\0') 1904 return (-1); 1905 evmask = (evmask & ~0x1F) | (count & 0x1F); 1906 } else if (KWMATCH(p, P4_KW_CASCADE)) 1907 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1908 else if (KWMATCH(p, P4_KW_EDGE)) 1909 pmc_config->pm_caps |= PMC_CAP_EDGE; 1910 else if (KWMATCH(p, P4_KW_INV)) 1911 pmc_config->pm_caps |= PMC_CAP_INVERT; 1912 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1913 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1914 return (-1); 1915 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1916 } else if (KWMATCH(p, P4_KW_OS)) 1917 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1918 else if (KWMATCH(p, P4_KW_PRECISE)) 1919 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1920 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1921 if (has_tag == 0) 1922 return (-1); 1923 1924 q = strchr(p, '='); 1925 if (*++q == '\0') /* skip '=' */ 1926 return (-1); 1927 1928 count = strtol(q, &e, 0); 1929 if (e == q || *e != '\0') 1930 return (-1); 1931 1932 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1933 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1934 P4_ESCR_TO_TAG_VALUE(count); 1935 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1936 q = strchr(p, '='); 1937 if (*++q == '\0') /* skip '=' */ 1938 return (-1); 1939 1940 count = strtol(q, &e, 0); 1941 if (e == q || *e != '\0') 1942 return (-1); 1943 1944 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1945 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1946 ~P4_CCCR_THRESHOLD_MASK; 1947 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1948 P4_CCCR_TO_THRESHOLD(count); 1949 } else if (KWMATCH(p, P4_KW_USR)) 1950 pmc_config->pm_caps |= PMC_CAP_USER; 1951 else 1952 return (-1); 1953 } 1954 1955 /* other post processing */ 1956 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1957 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1958 pe == PMC_EV_P4_BSQ_ALLOCATION) 1959 pmc_config->pm_caps |= PMC_CAP_EDGE; 1960 1961 /* fill in thread activity mask */ 1962 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1963 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1964 1965 if (evmask) 1966 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1967 1968 switch (pe) { 1969 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1970 if ((evmask & 0x06) == 0x06 || 1971 (evmask & 0x18) == 0x18) 1972 return (-1); /* can't have own+other bits together */ 1973 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1974 evmask = 0x1D; 1975 break; 1976 case PMC_EV_P4_MACHINE_CLEAR: 1977 /* only one bit is allowed to be set */ 1978 if ((evmask & (evmask - 1)) != 0) 1979 return (-1); 1980 if (evmask == 0) { 1981 evmask = 0x1; /* 'CLEAR' */ 1982 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1983 } 1984 break; 1985 default: 1986 if (evmask == 0 && pmask) { 1987 for (pm = pmask; pm->pm_name; pm++) 1988 evmask |= pm->pm_value; 1989 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1990 } 1991 } 1992 1993 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1994 P4_ESCR_TO_EVENT_MASK(evmask); 1995 1996 return (0); 1997 } 1998 1999 #endif 2000 2001 #if defined(__i386__) 2002 2003 /* 2004 * Pentium style PMCs 2005 */ 2006 2007 static struct pmc_event_alias p5_aliases[] = { 2008 EV_ALIAS("branches", "p5-taken-branches"), 2009 EV_ALIAS("cycles", "tsc"), 2010 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 2011 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 2012 EV_ALIAS("instructions", "p5-instructions-executed"), 2013 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 2014 EV_ALIAS("unhalted-cycles", 2015 "p5-number-of-cycles-not-in-halt-state"), 2016 EV_ALIAS(NULL, NULL) 2017 }; 2018 2019 static int 2020 p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 2021 struct pmc_op_pmcallocate *pmc_config) 2022 { 2023 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 2024 } 2025 2026 /* 2027 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 2028 * and Pentium M CPUs. 2029 */ 2030 2031 static struct pmc_event_alias p6_aliases[] = { 2032 EV_ALIAS("branches", "p6-br-inst-retired"), 2033 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 2034 EV_ALIAS("cycles", "tsc"), 2035 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 2036 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 2037 EV_ALIAS("instructions", "p6-inst-retired"), 2038 EV_ALIAS("interrupts", "p6-hw-int-rx"), 2039 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 2040 EV_ALIAS(NULL, NULL) 2041 }; 2042 2043 #define P6_KW_CMASK "cmask" 2044 #define P6_KW_EDGE "edge" 2045 #define P6_KW_INV "inv" 2046 #define P6_KW_OS "os" 2047 #define P6_KW_UMASK "umask" 2048 #define P6_KW_USR "usr" 2049 2050 static struct pmc_masks p6_mask_mesi[] = { 2051 PMCMASK(m, 0x01), 2052 PMCMASK(e, 0x02), 2053 PMCMASK(s, 0x04), 2054 PMCMASK(i, 0x08), 2055 NULLMASK 2056 }; 2057 2058 static struct pmc_masks p6_mask_mesihw[] = { 2059 PMCMASK(m, 0x01), 2060 PMCMASK(e, 0x02), 2061 PMCMASK(s, 0x04), 2062 PMCMASK(i, 0x08), 2063 PMCMASK(nonhw, 0x00), 2064 PMCMASK(hw, 0x10), 2065 PMCMASK(both, 0x30), 2066 NULLMASK 2067 }; 2068 2069 static struct pmc_masks p6_mask_hw[] = { 2070 PMCMASK(nonhw, 0x00), 2071 PMCMASK(hw, 0x10), 2072 PMCMASK(both, 0x30), 2073 NULLMASK 2074 }; 2075 2076 static struct pmc_masks p6_mask_any[] = { 2077 PMCMASK(self, 0x00), 2078 PMCMASK(any, 0x20), 2079 NULLMASK 2080 }; 2081 2082 static struct pmc_masks p6_mask_ekp[] = { 2083 PMCMASK(nta, 0x00), 2084 PMCMASK(t1, 0x01), 2085 PMCMASK(t2, 0x02), 2086 PMCMASK(wos, 0x03), 2087 NULLMASK 2088 }; 2089 2090 static struct pmc_masks p6_mask_pps[] = { 2091 PMCMASK(packed-and-scalar, 0x00), 2092 PMCMASK(scalar, 0x01), 2093 NULLMASK 2094 }; 2095 2096 static struct pmc_masks p6_mask_mite[] = { 2097 PMCMASK(packed-multiply, 0x01), 2098 PMCMASK(packed-shift, 0x02), 2099 PMCMASK(pack, 0x04), 2100 PMCMASK(unpack, 0x08), 2101 PMCMASK(packed-logical, 0x10), 2102 PMCMASK(packed-arithmetic, 0x20), 2103 NULLMASK 2104 }; 2105 2106 static struct pmc_masks p6_mask_fmt[] = { 2107 PMCMASK(mmxtofp, 0x00), 2108 PMCMASK(fptommx, 0x01), 2109 NULLMASK 2110 }; 2111 2112 static struct pmc_masks p6_mask_sr[] = { 2113 PMCMASK(es, 0x01), 2114 PMCMASK(ds, 0x02), 2115 PMCMASK(fs, 0x04), 2116 PMCMASK(gs, 0x08), 2117 NULLMASK 2118 }; 2119 2120 static struct pmc_masks p6_mask_eet[] = { 2121 PMCMASK(all, 0x00), 2122 PMCMASK(freq, 0x02), 2123 NULLMASK 2124 }; 2125 2126 static struct pmc_masks p6_mask_efur[] = { 2127 PMCMASK(all, 0x00), 2128 PMCMASK(loadop, 0x01), 2129 PMCMASK(stdsta, 0x02), 2130 NULLMASK 2131 }; 2132 2133 static struct pmc_masks p6_mask_essir[] = { 2134 PMCMASK(sse-packed-single, 0x00), 2135 PMCMASK(sse-packed-single-scalar-single, 0x01), 2136 PMCMASK(sse2-packed-double, 0x02), 2137 PMCMASK(sse2-scalar-double, 0x03), 2138 NULLMASK 2139 }; 2140 2141 static struct pmc_masks p6_mask_esscir[] = { 2142 PMCMASK(sse-packed-single, 0x00), 2143 PMCMASK(sse-scalar-single, 0x01), 2144 PMCMASK(sse2-packed-double, 0x02), 2145 PMCMASK(sse2-scalar-double, 0x03), 2146 NULLMASK 2147 }; 2148 2149 /* P6 event parser */ 2150 static int 2151 p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 2152 struct pmc_op_pmcallocate *pmc_config) 2153 { 2154 char *e, *p, *q; 2155 uint64_t evmask; 2156 int count, n; 2157 const struct pmc_masks *pm, *pmask; 2158 2159 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2160 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 2161 2162 evmask = 0; 2163 2164 #define P6MASKSET(M) pmask = p6_mask_ ## M 2165 2166 switch(pe) { 2167 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 2168 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 2169 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 2170 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 2171 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2172 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2173 case PMC_EV_P6_BUS_TRAN_BRD: 2174 case PMC_EV_P6_BUS_TRAN_RFO: 2175 case PMC_EV_P6_BUS_TRANS_WB: 2176 case PMC_EV_P6_BUS_TRAN_IFETCH: 2177 case PMC_EV_P6_BUS_TRAN_INVAL: 2178 case PMC_EV_P6_BUS_TRAN_PWR: 2179 case PMC_EV_P6_BUS_TRANS_P: 2180 case PMC_EV_P6_BUS_TRANS_IO: 2181 case PMC_EV_P6_BUS_TRAN_DEF: 2182 case PMC_EV_P6_BUS_TRAN_BURST: 2183 case PMC_EV_P6_BUS_TRAN_ANY: 2184 case PMC_EV_P6_BUS_TRAN_MEM: 2185 P6MASKSET(any); break; 2186 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2187 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2188 P6MASKSET(ekp); break; 2189 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2190 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2191 P6MASKSET(pps); break; 2192 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2193 P6MASKSET(mite); break; 2194 case PMC_EV_P6_FP_MMX_TRANS: 2195 P6MASKSET(fmt); break; 2196 case PMC_EV_P6_SEG_RENAME_STALLS: 2197 case PMC_EV_P6_SEG_REG_RENAMES: 2198 P6MASKSET(sr); break; 2199 case PMC_EV_P6_EMON_EST_TRANS: 2200 P6MASKSET(eet); break; 2201 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2202 P6MASKSET(efur); break; 2203 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2204 P6MASKSET(essir); break; 2205 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2206 P6MASKSET(esscir); break; 2207 default: 2208 pmask = NULL; 2209 break; 2210 } 2211 2212 /* Pentium M PMCs have a few events with different semantics */ 2213 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2214 if (pe == PMC_EV_P6_L2_LD || 2215 pe == PMC_EV_P6_L2_LINES_IN || 2216 pe == PMC_EV_P6_L2_LINES_OUT) 2217 P6MASKSET(mesihw); 2218 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2219 P6MASKSET(hw); 2220 } 2221 2222 /* Parse additional modifiers if present */ 2223 while ((p = strsep(&ctrspec, ",")) != NULL) { 2224 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2225 q = strchr(p, '='); 2226 if (*++q == '\0') /* skip '=' */ 2227 return (-1); 2228 count = strtol(q, &e, 0); 2229 if (e == q || *e != '\0') 2230 return (-1); 2231 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2232 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2233 P6_EVSEL_TO_CMASK(count); 2234 } else if (KWMATCH(p, P6_KW_EDGE)) { 2235 pmc_config->pm_caps |= PMC_CAP_EDGE; 2236 } else if (KWMATCH(p, P6_KW_INV)) { 2237 pmc_config->pm_caps |= PMC_CAP_INVERT; 2238 } else if (KWMATCH(p, P6_KW_OS)) { 2239 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2240 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2241 evmask = 0; 2242 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2243 return (-1); 2244 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2245 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2246 pe == PMC_EV_P6_BUS_TRAN_BRD || 2247 pe == PMC_EV_P6_BUS_TRAN_RFO || 2248 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2249 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2250 pe == PMC_EV_P6_BUS_TRAN_PWR || 2251 pe == PMC_EV_P6_BUS_TRAN_DEF || 2252 pe == PMC_EV_P6_BUS_TRAN_BURST || 2253 pe == PMC_EV_P6_BUS_TRAN_ANY || 2254 pe == PMC_EV_P6_BUS_TRAN_MEM || 2255 pe == PMC_EV_P6_BUS_TRANS_IO || 2256 pe == PMC_EV_P6_BUS_TRANS_P || 2257 pe == PMC_EV_P6_BUS_TRANS_WB || 2258 pe == PMC_EV_P6_EMON_EST_TRANS || 2259 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2260 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2261 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2262 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2263 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2264 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2265 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2266 pe == PMC_EV_P6_FP_MMX_TRANS) 2267 && (n > 1)) /* Only one mask keyword is allowed. */ 2268 return (-1); 2269 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2270 } else if (KWMATCH(p, P6_KW_USR)) { 2271 pmc_config->pm_caps |= PMC_CAP_USER; 2272 } else 2273 return (-1); 2274 } 2275 2276 /* post processing */ 2277 switch (pe) { 2278 2279 /* 2280 * The following events default to an evmask of 0 2281 */ 2282 2283 /* default => 'self' */ 2284 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2285 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2286 case PMC_EV_P6_BUS_TRAN_BRD: 2287 case PMC_EV_P6_BUS_TRAN_RFO: 2288 case PMC_EV_P6_BUS_TRANS_WB: 2289 case PMC_EV_P6_BUS_TRAN_IFETCH: 2290 case PMC_EV_P6_BUS_TRAN_INVAL: 2291 case PMC_EV_P6_BUS_TRAN_PWR: 2292 case PMC_EV_P6_BUS_TRANS_P: 2293 case PMC_EV_P6_BUS_TRANS_IO: 2294 case PMC_EV_P6_BUS_TRAN_DEF: 2295 case PMC_EV_P6_BUS_TRAN_BURST: 2296 case PMC_EV_P6_BUS_TRAN_ANY: 2297 case PMC_EV_P6_BUS_TRAN_MEM: 2298 2299 /* default => 'nta' */ 2300 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2301 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2302 2303 /* default => 'packed and scalar' */ 2304 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2305 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2306 2307 /* default => 'mmx to fp transitions' */ 2308 case PMC_EV_P6_FP_MMX_TRANS: 2309 2310 /* default => 'SSE Packed Single' */ 2311 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2312 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2313 2314 /* default => 'all fused micro-ops' */ 2315 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2316 2317 /* default => 'all transitions' */ 2318 case PMC_EV_P6_EMON_EST_TRANS: 2319 break; 2320 2321 case PMC_EV_P6_MMX_UOPS_EXEC: 2322 evmask = 0x0F; /* only value allowed */ 2323 break; 2324 2325 default: 2326 /* 2327 * For all other events, set the default event mask 2328 * to a logical OR of all the allowed event mask bits. 2329 */ 2330 if (evmask == 0 && pmask) { 2331 for (pm = pmask; pm->pm_name; pm++) 2332 evmask |= pm->pm_value; 2333 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2334 } 2335 2336 break; 2337 } 2338 2339 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2340 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2341 P6_EVSEL_TO_UMASK(evmask); 2342 2343 return (0); 2344 } 2345 2346 #endif 2347 2348 #if defined(__i386__) || defined(__amd64__) 2349 static int 2350 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2351 struct pmc_op_pmcallocate *pmc_config) 2352 { 2353 if (pe != PMC_EV_TSC_TSC) 2354 return (-1); 2355 2356 /* TSC events must be unqualified. */ 2357 if (ctrspec && *ctrspec != '\0') 2358 return (-1); 2359 2360 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2361 pmc_config->pm_caps |= PMC_CAP_READ; 2362 2363 return (0); 2364 } 2365 #endif 2366 2367 static struct pmc_event_alias generic_aliases[] = { 2368 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 2369 EV_ALIAS(NULL, NULL) 2370 }; 2371 2372 static int 2373 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 2374 struct pmc_op_pmcallocate *pmc_config) 2375 { 2376 (void)ctrspec; 2377 (void)pmc_config; 2378 2379 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 2380 return (-1); 2381 2382 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2383 return (0); 2384 } 2385 2386 #if defined(__arm__) 2387 #if defined(__XSCALE__) 2388 2389 static struct pmc_event_alias xscale_aliases[] = { 2390 EV_ALIAS("branches", "BRANCH_RETIRED"), 2391 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2392 EV_ALIAS("dc-misses", "DC_MISS"), 2393 EV_ALIAS("ic-misses", "IC_MISS"), 2394 EV_ALIAS("instructions", "INSTR_RETIRED"), 2395 EV_ALIAS(NULL, NULL) 2396 }; 2397 static int 2398 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2399 struct pmc_op_pmcallocate *pmc_config __unused) 2400 { 2401 switch (pe) { 2402 default: 2403 break; 2404 } 2405 2406 return (0); 2407 } 2408 #endif 2409 2410 static struct pmc_event_alias armv7_aliases[] = { 2411 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 2412 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 2413 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2414 EV_ALIAS(NULL, NULL) 2415 }; 2416 static int 2417 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2418 struct pmc_op_pmcallocate *pmc_config __unused) 2419 { 2420 switch (pe) { 2421 default: 2422 break; 2423 } 2424 2425 return (0); 2426 } 2427 #endif 2428 2429 #if defined(__mips__) 2430 2431 static struct pmc_event_alias mips24k_aliases[] = { 2432 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2433 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2434 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2435 EV_ALIAS(NULL, NULL) 2436 }; 2437 2438 static struct pmc_event_alias mips74k_aliases[] = { 2439 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2440 EV_ALIAS("branches", "BRANCH_INSNS"), 2441 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"), 2442 EV_ALIAS(NULL, NULL) 2443 }; 2444 2445 static struct pmc_event_alias octeon_aliases[] = { 2446 EV_ALIAS("instructions", "RET"), 2447 EV_ALIAS("branches", "BR"), 2448 EV_ALIAS("branch-mispredicts", "BRMIS"), 2449 EV_ALIAS(NULL, NULL) 2450 }; 2451 2452 #define MIPS_KW_OS "os" 2453 #define MIPS_KW_USR "usr" 2454 #define MIPS_KW_ANYTHREAD "anythread" 2455 2456 static int 2457 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2458 struct pmc_op_pmcallocate *pmc_config __unused) 2459 { 2460 char *p; 2461 2462 (void) pe; 2463 2464 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2465 2466 while ((p = strsep(&ctrspec, ",")) != NULL) { 2467 if (KWMATCH(p, MIPS_KW_OS)) 2468 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2469 else if (KWMATCH(p, MIPS_KW_USR)) 2470 pmc_config->pm_caps |= PMC_CAP_USER; 2471 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 2472 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2473 else 2474 return (-1); 2475 } 2476 2477 return (0); 2478 } 2479 2480 #endif /* __mips__ */ 2481 2482 #if defined(__powerpc__) 2483 2484 static struct pmc_event_alias ppc7450_aliases[] = { 2485 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2486 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2487 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2488 EV_ALIAS(NULL, NULL) 2489 }; 2490 2491 static struct pmc_event_alias ppc970_aliases[] = { 2492 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2493 EV_ALIAS("cycles", "CYCLES"), 2494 EV_ALIAS(NULL, NULL) 2495 }; 2496 2497 #define POWERPC_KW_OS "os" 2498 #define POWERPC_KW_USR "usr" 2499 #define POWERPC_KW_ANYTHREAD "anythread" 2500 2501 static int 2502 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2503 struct pmc_op_pmcallocate *pmc_config __unused) 2504 { 2505 char *p; 2506 2507 (void) pe; 2508 2509 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2510 2511 while ((p = strsep(&ctrspec, ",")) != NULL) { 2512 if (KWMATCH(p, POWERPC_KW_OS)) 2513 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2514 else if (KWMATCH(p, POWERPC_KW_USR)) 2515 pmc_config->pm_caps |= PMC_CAP_USER; 2516 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 2517 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2518 else 2519 return (-1); 2520 } 2521 2522 return (0); 2523 } 2524 2525 #endif /* __powerpc__ */ 2526 2527 2528 /* 2529 * Match an event name `name' with its canonical form. 2530 * 2531 * Matches are case insensitive and spaces, periods, underscores and 2532 * hyphen characters are considered to match each other. 2533 * 2534 * Returns 1 for a match, 0 otherwise. 2535 */ 2536 2537 static int 2538 pmc_match_event_name(const char *name, const char *canonicalname) 2539 { 2540 int cc, nc; 2541 const unsigned char *c, *n; 2542 2543 c = (const unsigned char *) canonicalname; 2544 n = (const unsigned char *) name; 2545 2546 for (; (nc = *n) && (cc = *c); n++, c++) { 2547 2548 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2549 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2550 continue; 2551 2552 if (toupper(nc) == toupper(cc)) 2553 continue; 2554 2555 2556 return (0); 2557 } 2558 2559 if (*n == '\0' && *c == '\0') 2560 return (1); 2561 2562 return (0); 2563 } 2564 2565 /* 2566 * Match an event name against all the event named supported by a 2567 * PMC class. 2568 * 2569 * Returns an event descriptor pointer on match or NULL otherwise. 2570 */ 2571 static const struct pmc_event_descr * 2572 pmc_match_event_class(const char *name, 2573 const struct pmc_class_descr *pcd) 2574 { 2575 size_t n; 2576 const struct pmc_event_descr *ev; 2577 2578 ev = pcd->pm_evc_event_table; 2579 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2580 if (pmc_match_event_name(name, ev->pm_ev_name)) 2581 return (ev); 2582 2583 return (NULL); 2584 } 2585 2586 static int 2587 pmc_mdep_is_compatible_class(enum pmc_class pc) 2588 { 2589 size_t n; 2590 2591 for (n = 0; n < pmc_mdep_class_list_size; n++) 2592 if (pmc_mdep_class_list[n] == pc) 2593 return (1); 2594 return (0); 2595 } 2596 2597 /* 2598 * API entry points 2599 */ 2600 2601 int 2602 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2603 uint32_t flags, int cpu, pmc_id_t *pmcid) 2604 { 2605 size_t n; 2606 int retval; 2607 char *r, *spec_copy; 2608 const char *ctrname; 2609 const struct pmc_event_descr *ev; 2610 const struct pmc_event_alias *alias; 2611 struct pmc_op_pmcallocate pmc_config; 2612 const struct pmc_class_descr *pcd; 2613 2614 spec_copy = NULL; 2615 retval = -1; 2616 2617 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2618 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2619 errno = EINVAL; 2620 goto out; 2621 } 2622 2623 /* replace an event alias with the canonical event specifier */ 2624 if (pmc_mdep_event_aliases) 2625 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2626 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2627 spec_copy = strdup(alias->pm_spec); 2628 break; 2629 } 2630 2631 if (spec_copy == NULL) 2632 spec_copy = strdup(ctrspec); 2633 2634 r = spec_copy; 2635 ctrname = strsep(&r, ","); 2636 2637 /* 2638 * If a explicit class prefix was given by the user, restrict the 2639 * search for the event to the specified PMC class. 2640 */ 2641 ev = NULL; 2642 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2643 pcd = pmc_class_table[n]; 2644 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2645 strncasecmp(ctrname, pcd->pm_evc_name, 2646 pcd->pm_evc_name_size) == 0) { 2647 if ((ev = pmc_match_event_class(ctrname + 2648 pcd->pm_evc_name_size, pcd)) == NULL) { 2649 errno = EINVAL; 2650 goto out; 2651 } 2652 break; 2653 } 2654 } 2655 2656 /* 2657 * Otherwise, search for this event in all compatible PMC 2658 * classes. 2659 */ 2660 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2661 pcd = pmc_class_table[n]; 2662 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2663 ev = pmc_match_event_class(ctrname, pcd); 2664 } 2665 2666 if (ev == NULL) { 2667 errno = EINVAL; 2668 goto out; 2669 } 2670 2671 bzero(&pmc_config, sizeof(pmc_config)); 2672 pmc_config.pm_ev = ev->pm_ev_code; 2673 pmc_config.pm_class = pcd->pm_evc_class; 2674 pmc_config.pm_cpu = cpu; 2675 pmc_config.pm_mode = mode; 2676 pmc_config.pm_flags = flags; 2677 2678 if (PMC_IS_SAMPLING_MODE(mode)) 2679 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2680 2681 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2682 errno = EINVAL; 2683 goto out; 2684 } 2685 2686 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2687 goto out; 2688 2689 *pmcid = pmc_config.pm_pmcid; 2690 2691 retval = 0; 2692 2693 out: 2694 if (spec_copy) 2695 free(spec_copy); 2696 2697 return (retval); 2698 } 2699 2700 int 2701 pmc_attach(pmc_id_t pmc, pid_t pid) 2702 { 2703 struct pmc_op_pmcattach pmc_attach_args; 2704 2705 pmc_attach_args.pm_pmc = pmc; 2706 pmc_attach_args.pm_pid = pid; 2707 2708 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2709 } 2710 2711 int 2712 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2713 { 2714 unsigned int i; 2715 enum pmc_class cl; 2716 2717 cl = PMC_ID_TO_CLASS(pmcid); 2718 for (i = 0; i < cpu_info.pm_nclass; i++) 2719 if (cpu_info.pm_classes[i].pm_class == cl) { 2720 *caps = cpu_info.pm_classes[i].pm_caps; 2721 return (0); 2722 } 2723 errno = EINVAL; 2724 return (-1); 2725 } 2726 2727 int 2728 pmc_configure_logfile(int fd) 2729 { 2730 struct pmc_op_configurelog cla; 2731 2732 cla.pm_logfd = fd; 2733 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2734 return (-1); 2735 return (0); 2736 } 2737 2738 int 2739 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2740 { 2741 if (pmc_syscall == -1) { 2742 errno = ENXIO; 2743 return (-1); 2744 } 2745 2746 *pci = &cpu_info; 2747 return (0); 2748 } 2749 2750 int 2751 pmc_detach(pmc_id_t pmc, pid_t pid) 2752 { 2753 struct pmc_op_pmcattach pmc_detach_args; 2754 2755 pmc_detach_args.pm_pmc = pmc; 2756 pmc_detach_args.pm_pid = pid; 2757 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2758 } 2759 2760 int 2761 pmc_disable(int cpu, int pmc) 2762 { 2763 struct pmc_op_pmcadmin ssa; 2764 2765 ssa.pm_cpu = cpu; 2766 ssa.pm_pmc = pmc; 2767 ssa.pm_state = PMC_STATE_DISABLED; 2768 return (PMC_CALL(PMCADMIN, &ssa)); 2769 } 2770 2771 int 2772 pmc_enable(int cpu, int pmc) 2773 { 2774 struct pmc_op_pmcadmin ssa; 2775 2776 ssa.pm_cpu = cpu; 2777 ssa.pm_pmc = pmc; 2778 ssa.pm_state = PMC_STATE_FREE; 2779 return (PMC_CALL(PMCADMIN, &ssa)); 2780 } 2781 2782 /* 2783 * Return a list of events known to a given PMC class. 'cl' is the 2784 * PMC class identifier, 'eventnames' is the returned list of 'const 2785 * char *' pointers pointing to the names of the events. 'nevents' is 2786 * the number of event name pointers returned. 2787 * 2788 * The space for 'eventnames' is allocated using malloc(3). The caller 2789 * is responsible for freeing this space when done. 2790 */ 2791 int 2792 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2793 int *nevents) 2794 { 2795 int count; 2796 const char **names; 2797 const struct pmc_event_descr *ev; 2798 2799 switch (cl) 2800 { 2801 case PMC_CLASS_IAF: 2802 ev = iaf_event_table; 2803 count = PMC_EVENT_TABLE_SIZE(iaf); 2804 break; 2805 case PMC_CLASS_IAP: 2806 /* 2807 * Return the most appropriate set of event name 2808 * spellings for the current CPU. 2809 */ 2810 switch (cpu_info.pm_cputype) { 2811 default: 2812 case PMC_CPU_INTEL_ATOM: 2813 ev = atom_event_table; 2814 count = PMC_EVENT_TABLE_SIZE(atom); 2815 break; 2816 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2817 ev = atom_silvermont_event_table; 2818 count = PMC_EVENT_TABLE_SIZE(atom_silvermont); 2819 break; 2820 case PMC_CPU_INTEL_CORE: 2821 ev = core_event_table; 2822 count = PMC_EVENT_TABLE_SIZE(core); 2823 break; 2824 case PMC_CPU_INTEL_CORE2: 2825 case PMC_CPU_INTEL_CORE2EXTREME: 2826 ev = core2_event_table; 2827 count = PMC_EVENT_TABLE_SIZE(core2); 2828 break; 2829 case PMC_CPU_INTEL_COREI7: 2830 ev = corei7_event_table; 2831 count = PMC_EVENT_TABLE_SIZE(corei7); 2832 break; 2833 case PMC_CPU_INTEL_NEHALEM_EX: 2834 ev = nehalem_ex_event_table; 2835 count = PMC_EVENT_TABLE_SIZE(nehalem_ex); 2836 break; 2837 case PMC_CPU_INTEL_HASWELL: 2838 ev = haswell_event_table; 2839 count = PMC_EVENT_TABLE_SIZE(haswell); 2840 break; 2841 case PMC_CPU_INTEL_HASWELL_XEON: 2842 ev = haswell_xeon_event_table; 2843 count = PMC_EVENT_TABLE_SIZE(haswell_xeon); 2844 break; 2845 case PMC_CPU_INTEL_IVYBRIDGE: 2846 ev = ivybridge_event_table; 2847 count = PMC_EVENT_TABLE_SIZE(ivybridge); 2848 break; 2849 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2850 ev = ivybridge_xeon_event_table; 2851 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 2852 break; 2853 case PMC_CPU_INTEL_SANDYBRIDGE: 2854 ev = sandybridge_event_table; 2855 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2856 break; 2857 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2858 ev = sandybridge_xeon_event_table; 2859 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 2860 break; 2861 case PMC_CPU_INTEL_WESTMERE: 2862 ev = westmere_event_table; 2863 count = PMC_EVENT_TABLE_SIZE(westmere); 2864 break; 2865 case PMC_CPU_INTEL_WESTMERE_EX: 2866 ev = westmere_ex_event_table; 2867 count = PMC_EVENT_TABLE_SIZE(westmere_ex); 2868 break; 2869 } 2870 break; 2871 case PMC_CLASS_UCF: 2872 ev = ucf_event_table; 2873 count = PMC_EVENT_TABLE_SIZE(ucf); 2874 break; 2875 case PMC_CLASS_UCP: 2876 /* 2877 * Return the most appropriate set of event name 2878 * spellings for the current CPU. 2879 */ 2880 switch (cpu_info.pm_cputype) { 2881 default: 2882 case PMC_CPU_INTEL_COREI7: 2883 ev = corei7uc_event_table; 2884 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2885 break; 2886 case PMC_CPU_INTEL_HASWELL: 2887 ev = haswelluc_event_table; 2888 count = PMC_EVENT_TABLE_SIZE(haswelluc); 2889 break; 2890 case PMC_CPU_INTEL_SANDYBRIDGE: 2891 ev = sandybridgeuc_event_table; 2892 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2893 break; 2894 case PMC_CPU_INTEL_WESTMERE: 2895 ev = westmereuc_event_table; 2896 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2897 break; 2898 } 2899 break; 2900 case PMC_CLASS_TSC: 2901 ev = tsc_event_table; 2902 count = PMC_EVENT_TABLE_SIZE(tsc); 2903 break; 2904 case PMC_CLASS_K7: 2905 ev = k7_event_table; 2906 count = PMC_EVENT_TABLE_SIZE(k7); 2907 break; 2908 case PMC_CLASS_K8: 2909 ev = k8_event_table; 2910 count = PMC_EVENT_TABLE_SIZE(k8); 2911 break; 2912 case PMC_CLASS_P4: 2913 ev = p4_event_table; 2914 count = PMC_EVENT_TABLE_SIZE(p4); 2915 break; 2916 case PMC_CLASS_P5: 2917 ev = p5_event_table; 2918 count = PMC_EVENT_TABLE_SIZE(p5); 2919 break; 2920 case PMC_CLASS_P6: 2921 ev = p6_event_table; 2922 count = PMC_EVENT_TABLE_SIZE(p6); 2923 break; 2924 case PMC_CLASS_XSCALE: 2925 ev = xscale_event_table; 2926 count = PMC_EVENT_TABLE_SIZE(xscale); 2927 break; 2928 case PMC_CLASS_ARMV7: 2929 ev = armv7_event_table; 2930 count = PMC_EVENT_TABLE_SIZE(armv7); 2931 break; 2932 case PMC_CLASS_MIPS24K: 2933 ev = mips24k_event_table; 2934 count = PMC_EVENT_TABLE_SIZE(mips24k); 2935 break; 2936 case PMC_CLASS_MIPS74K: 2937 ev = mips74k_event_table; 2938 count = PMC_EVENT_TABLE_SIZE(mips74k); 2939 break; 2940 case PMC_CLASS_OCTEON: 2941 ev = octeon_event_table; 2942 count = PMC_EVENT_TABLE_SIZE(octeon); 2943 break; 2944 case PMC_CLASS_PPC7450: 2945 ev = ppc7450_event_table; 2946 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2947 break; 2948 case PMC_CLASS_PPC970: 2949 ev = ppc970_event_table; 2950 count = PMC_EVENT_TABLE_SIZE(ppc970); 2951 break; 2952 case PMC_CLASS_SOFT: 2953 ev = soft_event_table; 2954 count = soft_event_info.pm_nevent; 2955 break; 2956 default: 2957 errno = EINVAL; 2958 return (-1); 2959 } 2960 2961 if ((names = malloc(count * sizeof(const char *))) == NULL) 2962 return (-1); 2963 2964 *eventnames = names; 2965 *nevents = count; 2966 2967 for (;count--; ev++, names++) 2968 *names = ev->pm_ev_name; 2969 2970 return (0); 2971 } 2972 2973 int 2974 pmc_flush_logfile(void) 2975 { 2976 return (PMC_CALL(FLUSHLOG,0)); 2977 } 2978 2979 int 2980 pmc_close_logfile(void) 2981 { 2982 return (PMC_CALL(CLOSELOG,0)); 2983 } 2984 2985 int 2986 pmc_get_driver_stats(struct pmc_driverstats *ds) 2987 { 2988 struct pmc_op_getdriverstats gms; 2989 2990 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2991 return (-1); 2992 2993 /* copy out fields in the current userland<->library interface */ 2994 ds->pm_intr_ignored = gms.pm_intr_ignored; 2995 ds->pm_intr_processed = gms.pm_intr_processed; 2996 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2997 ds->pm_syscalls = gms.pm_syscalls; 2998 ds->pm_syscall_errors = gms.pm_syscall_errors; 2999 ds->pm_buffer_requests = gms.pm_buffer_requests; 3000 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 3001 ds->pm_log_sweeps = gms.pm_log_sweeps; 3002 return (0); 3003 } 3004 3005 int 3006 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 3007 { 3008 struct pmc_op_getmsr gm; 3009 3010 gm.pm_pmcid = pmc; 3011 if (PMC_CALL(PMCGETMSR, &gm) < 0) 3012 return (-1); 3013 *msr = gm.pm_msr; 3014 return (0); 3015 } 3016 3017 int 3018 pmc_init(void) 3019 { 3020 int error, pmc_mod_id; 3021 unsigned int n; 3022 uint32_t abi_version; 3023 struct module_stat pmc_modstat; 3024 struct pmc_op_getcpuinfo op_cpu_info; 3025 #if defined(__amd64__) || defined(__i386__) 3026 int cpu_has_iaf_counters; 3027 unsigned int t; 3028 #endif 3029 3030 if (pmc_syscall != -1) /* already inited */ 3031 return (0); 3032 3033 /* retrieve the system call number from the KLD */ 3034 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 3035 return (-1); 3036 3037 pmc_modstat.version = sizeof(struct module_stat); 3038 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 3039 return (-1); 3040 3041 pmc_syscall = pmc_modstat.data.intval; 3042 3043 /* check the kernel module's ABI against our compiled-in version */ 3044 abi_version = PMC_VERSION; 3045 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 3046 return (pmc_syscall = -1); 3047 3048 /* ignore patch & minor numbers for the comparision */ 3049 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 3050 errno = EPROGMISMATCH; 3051 return (pmc_syscall = -1); 3052 } 3053 3054 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 3055 return (pmc_syscall = -1); 3056 3057 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 3058 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 3059 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 3060 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 3061 for (n = 0; n < cpu_info.pm_nclass; n++) 3062 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 3063 3064 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 3065 sizeof(struct pmc_class_descr *)); 3066 3067 if (pmc_class_table == NULL) 3068 return (-1); 3069 3070 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 3071 pmc_class_table[n] = NULL; 3072 3073 /* 3074 * Get soft events list. 3075 */ 3076 soft_event_info.pm_class = PMC_CLASS_SOFT; 3077 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 3078 return (pmc_syscall = -1); 3079 3080 /* Map soft events to static list. */ 3081 for (n = 0; n < soft_event_info.pm_nevent; n++) { 3082 soft_event_table[n].pm_ev_name = 3083 soft_event_info.pm_events[n].pm_ev_name; 3084 soft_event_table[n].pm_ev_code = 3085 soft_event_info.pm_events[n].pm_ev_code; 3086 } 3087 soft_class_table_descr.pm_evc_event_table_size = \ 3088 soft_event_info.pm_nevent; 3089 soft_class_table_descr.pm_evc_event_table = \ 3090 soft_event_table; 3091 3092 /* 3093 * Fill in the class table. 3094 */ 3095 n = 0; 3096 3097 /* Fill soft events information. */ 3098 pmc_class_table[n++] = &soft_class_table_descr; 3099 #if defined(__amd64__) || defined(__i386__) 3100 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 3101 pmc_class_table[n++] = &tsc_class_table_descr; 3102 3103 /* 3104 * Check if this CPU has fixed function counters. 3105 */ 3106 cpu_has_iaf_counters = 0; 3107 for (t = 0; t < cpu_info.pm_nclass; t++) 3108 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 3109 cpu_info.pm_classes[t].pm_num > 0) 3110 cpu_has_iaf_counters = 1; 3111 #endif 3112 3113 #define PMC_MDEP_INIT(C) do { \ 3114 pmc_mdep_event_aliases = C##_aliases; \ 3115 pmc_mdep_class_list = C##_pmc_classes; \ 3116 pmc_mdep_class_list_size = \ 3117 PMC_TABLE_SIZE(C##_pmc_classes); \ 3118 } while (0) 3119 3120 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 3121 PMC_MDEP_INIT(C); \ 3122 pmc_class_table[n++] = &iaf_class_table_descr; \ 3123 if (!cpu_has_iaf_counters) \ 3124 pmc_mdep_event_aliases = \ 3125 C##_aliases_without_iaf; \ 3126 pmc_class_table[n] = &C##_class_table_descr; \ 3127 } while (0) 3128 3129 /* Configure the event name parser. */ 3130 switch (cpu_info.pm_cputype) { 3131 #if defined(__i386__) 3132 case PMC_CPU_AMD_K7: 3133 PMC_MDEP_INIT(k7); 3134 pmc_class_table[n] = &k7_class_table_descr; 3135 break; 3136 case PMC_CPU_INTEL_P5: 3137 PMC_MDEP_INIT(p5); 3138 pmc_class_table[n] = &p5_class_table_descr; 3139 break; 3140 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 3141 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 3142 case PMC_CPU_INTEL_PIII: 3143 case PMC_CPU_INTEL_PM: 3144 PMC_MDEP_INIT(p6); 3145 pmc_class_table[n] = &p6_class_table_descr; 3146 break; 3147 #endif 3148 #if defined(__amd64__) || defined(__i386__) 3149 case PMC_CPU_AMD_K8: 3150 PMC_MDEP_INIT(k8); 3151 pmc_class_table[n] = &k8_class_table_descr; 3152 break; 3153 case PMC_CPU_INTEL_ATOM: 3154 PMC_MDEP_INIT_INTEL_V2(atom); 3155 break; 3156 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3157 PMC_MDEP_INIT_INTEL_V2(atom_silvermont); 3158 break; 3159 case PMC_CPU_INTEL_CORE: 3160 PMC_MDEP_INIT(core); 3161 pmc_class_table[n] = &core_class_table_descr; 3162 break; 3163 case PMC_CPU_INTEL_CORE2: 3164 case PMC_CPU_INTEL_CORE2EXTREME: 3165 PMC_MDEP_INIT_INTEL_V2(core2); 3166 break; 3167 case PMC_CPU_INTEL_COREI7: 3168 pmc_class_table[n++] = &ucf_class_table_descr; 3169 pmc_class_table[n++] = &corei7uc_class_table_descr; 3170 PMC_MDEP_INIT_INTEL_V2(corei7); 3171 break; 3172 case PMC_CPU_INTEL_NEHALEM_EX: 3173 PMC_MDEP_INIT_INTEL_V2(nehalem_ex); 3174 break; 3175 case PMC_CPU_INTEL_HASWELL: 3176 pmc_class_table[n++] = &ucf_class_table_descr; 3177 pmc_class_table[n++] = &haswelluc_class_table_descr; 3178 PMC_MDEP_INIT_INTEL_V2(haswell); 3179 break; 3180 case PMC_CPU_INTEL_HASWELL_XEON: 3181 PMC_MDEP_INIT_INTEL_V2(haswell_xeon); 3182 break; 3183 case PMC_CPU_INTEL_IVYBRIDGE: 3184 PMC_MDEP_INIT_INTEL_V2(ivybridge); 3185 break; 3186 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3187 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); 3188 break; 3189 case PMC_CPU_INTEL_SANDYBRIDGE: 3190 pmc_class_table[n++] = &ucf_class_table_descr; 3191 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 3192 PMC_MDEP_INIT_INTEL_V2(sandybridge); 3193 break; 3194 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3195 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); 3196 break; 3197 case PMC_CPU_INTEL_WESTMERE: 3198 pmc_class_table[n++] = &ucf_class_table_descr; 3199 pmc_class_table[n++] = &westmereuc_class_table_descr; 3200 PMC_MDEP_INIT_INTEL_V2(westmere); 3201 break; 3202 case PMC_CPU_INTEL_WESTMERE_EX: 3203 PMC_MDEP_INIT_INTEL_V2(westmere_ex); 3204 break; 3205 case PMC_CPU_INTEL_PIV: 3206 PMC_MDEP_INIT(p4); 3207 pmc_class_table[n] = &p4_class_table_descr; 3208 break; 3209 #endif 3210 case PMC_CPU_GENERIC: 3211 PMC_MDEP_INIT(generic); 3212 break; 3213 #if defined(__arm__) 3214 #if defined(__XSCALE__) 3215 case PMC_CPU_INTEL_XSCALE: 3216 PMC_MDEP_INIT(xscale); 3217 pmc_class_table[n] = &xscale_class_table_descr; 3218 break; 3219 #endif 3220 case PMC_CPU_ARMV7: 3221 PMC_MDEP_INIT(armv7); 3222 pmc_class_table[n] = &armv7_class_table_descr; 3223 break; 3224 #endif 3225 #if defined(__mips__) 3226 case PMC_CPU_MIPS_24K: 3227 PMC_MDEP_INIT(mips24k); 3228 pmc_class_table[n] = &mips24k_class_table_descr; 3229 break; 3230 case PMC_CPU_MIPS_74K: 3231 PMC_MDEP_INIT(mips74k); 3232 pmc_class_table[n] = &mips74k_class_table_descr; 3233 break; 3234 case PMC_CPU_MIPS_OCTEON: 3235 PMC_MDEP_INIT(octeon); 3236 pmc_class_table[n] = &octeon_class_table_descr; 3237 break; 3238 #endif /* __mips__ */ 3239 #if defined(__powerpc__) 3240 case PMC_CPU_PPC_7450: 3241 PMC_MDEP_INIT(ppc7450); 3242 pmc_class_table[n] = &ppc7450_class_table_descr; 3243 break; 3244 case PMC_CPU_PPC_970: 3245 PMC_MDEP_INIT(ppc970); 3246 pmc_class_table[n] = &ppc970_class_table_descr; 3247 break; 3248 #endif 3249 default: 3250 /* 3251 * Some kind of CPU this version of the library knows nothing 3252 * about. This shouldn't happen since the abi version check 3253 * should have caught this. 3254 */ 3255 errno = ENXIO; 3256 return (pmc_syscall = -1); 3257 } 3258 3259 return (0); 3260 } 3261 3262 const char * 3263 pmc_name_of_capability(enum pmc_caps cap) 3264 { 3265 int i; 3266 3267 /* 3268 * 'cap' should have a single bit set and should be in 3269 * range. 3270 */ 3271 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 3272 cap > PMC_CAP_LAST) { 3273 errno = EINVAL; 3274 return (NULL); 3275 } 3276 3277 i = ffs(cap); 3278 return (pmc_capability_names[i - 1]); 3279 } 3280 3281 const char * 3282 pmc_name_of_class(enum pmc_class pc) 3283 { 3284 if ((int) pc >= PMC_CLASS_FIRST && 3285 pc <= PMC_CLASS_LAST) 3286 return (pmc_class_names[pc]); 3287 3288 errno = EINVAL; 3289 return (NULL); 3290 } 3291 3292 const char * 3293 pmc_name_of_cputype(enum pmc_cputype cp) 3294 { 3295 size_t n; 3296 3297 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 3298 if (cp == pmc_cputype_names[n].pm_cputype) 3299 return (pmc_cputype_names[n].pm_name); 3300 3301 errno = EINVAL; 3302 return (NULL); 3303 } 3304 3305 const char * 3306 pmc_name_of_disposition(enum pmc_disp pd) 3307 { 3308 if ((int) pd >= PMC_DISP_FIRST && 3309 pd <= PMC_DISP_LAST) 3310 return (pmc_disposition_names[pd]); 3311 3312 errno = EINVAL; 3313 return (NULL); 3314 } 3315 3316 const char * 3317 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 3318 { 3319 const struct pmc_event_descr *ev, *evfence; 3320 3321 ev = evfence = NULL; 3322 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 3323 ev = iaf_event_table; 3324 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 3325 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 3326 switch (cpu) { 3327 case PMC_CPU_INTEL_ATOM: 3328 ev = atom_event_table; 3329 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 3330 break; 3331 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3332 ev = atom_silvermont_event_table; 3333 evfence = atom_silvermont_event_table + 3334 PMC_EVENT_TABLE_SIZE(atom_silvermont); 3335 break; 3336 case PMC_CPU_INTEL_CORE: 3337 ev = core_event_table; 3338 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 3339 break; 3340 case PMC_CPU_INTEL_CORE2: 3341 case PMC_CPU_INTEL_CORE2EXTREME: 3342 ev = core2_event_table; 3343 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 3344 break; 3345 case PMC_CPU_INTEL_COREI7: 3346 ev = corei7_event_table; 3347 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 3348 break; 3349 case PMC_CPU_INTEL_NEHALEM_EX: 3350 ev = nehalem_ex_event_table; 3351 evfence = nehalem_ex_event_table + 3352 PMC_EVENT_TABLE_SIZE(nehalem_ex); 3353 break; 3354 case PMC_CPU_INTEL_HASWELL: 3355 ev = haswell_event_table; 3356 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); 3357 break; 3358 case PMC_CPU_INTEL_HASWELL_XEON: 3359 ev = haswell_xeon_event_table; 3360 evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon); 3361 break; 3362 3363 case PMC_CPU_INTEL_IVYBRIDGE: 3364 ev = ivybridge_event_table; 3365 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); 3366 break; 3367 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3368 ev = ivybridge_xeon_event_table; 3369 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 3370 break; 3371 case PMC_CPU_INTEL_SANDYBRIDGE: 3372 ev = sandybridge_event_table; 3373 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 3374 break; 3375 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3376 ev = sandybridge_xeon_event_table; 3377 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 3378 break; 3379 case PMC_CPU_INTEL_WESTMERE: 3380 ev = westmere_event_table; 3381 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 3382 break; 3383 case PMC_CPU_INTEL_WESTMERE_EX: 3384 ev = westmere_ex_event_table; 3385 evfence = westmere_ex_event_table + 3386 PMC_EVENT_TABLE_SIZE(westmere_ex); 3387 break; 3388 default: /* Unknown CPU type. */ 3389 break; 3390 } 3391 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 3392 ev = ucf_event_table; 3393 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 3394 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 3395 switch (cpu) { 3396 case PMC_CPU_INTEL_COREI7: 3397 ev = corei7uc_event_table; 3398 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 3399 break; 3400 case PMC_CPU_INTEL_SANDYBRIDGE: 3401 ev = sandybridgeuc_event_table; 3402 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 3403 break; 3404 case PMC_CPU_INTEL_WESTMERE: 3405 ev = westmereuc_event_table; 3406 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 3407 break; 3408 default: /* Unknown CPU type. */ 3409 break; 3410 } 3411 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3412 ev = k7_event_table; 3413 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3414 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3415 ev = k8_event_table; 3416 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3417 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3418 ev = p4_event_table; 3419 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3420 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3421 ev = p5_event_table; 3422 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3423 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3424 ev = p6_event_table; 3425 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3426 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3427 ev = xscale_event_table; 3428 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3429 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 3430 ev = armv7_event_table; 3431 evfence = armv7_event_table + PMC_EVENT_TABLE_SIZE(armv7); 3432 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3433 ev = mips24k_event_table; 3434 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 3435 } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { 3436 ev = mips74k_event_table; 3437 evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); 3438 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 3439 ev = octeon_event_table; 3440 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 3441 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3442 ev = ppc7450_event_table; 3443 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 3444 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 3445 ev = ppc970_event_table; 3446 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 3447 } else if (pe == PMC_EV_TSC_TSC) { 3448 ev = tsc_event_table; 3449 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3450 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 3451 ev = soft_event_table; 3452 evfence = soft_event_table + soft_event_info.pm_nevent; 3453 } 3454 3455 for (; ev != evfence; ev++) 3456 if (pe == ev->pm_ev_code) 3457 return (ev->pm_ev_name); 3458 3459 return (NULL); 3460 } 3461 3462 const char * 3463 pmc_name_of_event(enum pmc_event pe) 3464 { 3465 const char *n; 3466 3467 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3468 return (n); 3469 3470 errno = EINVAL; 3471 return (NULL); 3472 } 3473 3474 const char * 3475 pmc_name_of_mode(enum pmc_mode pm) 3476 { 3477 if ((int) pm >= PMC_MODE_FIRST && 3478 pm <= PMC_MODE_LAST) 3479 return (pmc_mode_names[pm]); 3480 3481 errno = EINVAL; 3482 return (NULL); 3483 } 3484 3485 const char * 3486 pmc_name_of_state(enum pmc_state ps) 3487 { 3488 if ((int) ps >= PMC_STATE_FIRST && 3489 ps <= PMC_STATE_LAST) 3490 return (pmc_state_names[ps]); 3491 3492 errno = EINVAL; 3493 return (NULL); 3494 } 3495 3496 int 3497 pmc_ncpu(void) 3498 { 3499 if (pmc_syscall == -1) { 3500 errno = ENXIO; 3501 return (-1); 3502 } 3503 3504 return (cpu_info.pm_ncpu); 3505 } 3506 3507 int 3508 pmc_npmc(int cpu) 3509 { 3510 if (pmc_syscall == -1) { 3511 errno = ENXIO; 3512 return (-1); 3513 } 3514 3515 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3516 errno = EINVAL; 3517 return (-1); 3518 } 3519 3520 return (cpu_info.pm_npmc); 3521 } 3522 3523 int 3524 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3525 { 3526 int nbytes, npmc; 3527 struct pmc_op_getpmcinfo *pmci; 3528 3529 if ((npmc = pmc_npmc(cpu)) < 0) 3530 return (-1); 3531 3532 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3533 npmc * sizeof(struct pmc_info); 3534 3535 if ((pmci = calloc(1, nbytes)) == NULL) 3536 return (-1); 3537 3538 pmci->pm_cpu = cpu; 3539 3540 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3541 free(pmci); 3542 return (-1); 3543 } 3544 3545 /* kernel<->library, library<->userland interfaces are identical */ 3546 *ppmci = (struct pmc_pmcinfo *) pmci; 3547 return (0); 3548 } 3549 3550 int 3551 pmc_read(pmc_id_t pmc, pmc_value_t *value) 3552 { 3553 struct pmc_op_pmcrw pmc_read_op; 3554 3555 pmc_read_op.pm_pmcid = pmc; 3556 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3557 pmc_read_op.pm_value = -1; 3558 3559 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3560 return (-1); 3561 3562 *value = pmc_read_op.pm_value; 3563 return (0); 3564 } 3565 3566 int 3567 pmc_release(pmc_id_t pmc) 3568 { 3569 struct pmc_op_simple pmc_release_args; 3570 3571 pmc_release_args.pm_pmcid = pmc; 3572 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3573 } 3574 3575 int 3576 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3577 { 3578 struct pmc_op_pmcrw pmc_rw_op; 3579 3580 pmc_rw_op.pm_pmcid = pmc; 3581 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3582 pmc_rw_op.pm_value = newvalue; 3583 3584 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3585 return (-1); 3586 3587 *oldvaluep = pmc_rw_op.pm_value; 3588 return (0); 3589 } 3590 3591 int 3592 pmc_set(pmc_id_t pmc, pmc_value_t value) 3593 { 3594 struct pmc_op_pmcsetcount sc; 3595 3596 sc.pm_pmcid = pmc; 3597 sc.pm_count = value; 3598 3599 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3600 return (-1); 3601 return (0); 3602 } 3603 3604 int 3605 pmc_start(pmc_id_t pmc) 3606 { 3607 struct pmc_op_simple pmc_start_args; 3608 3609 pmc_start_args.pm_pmcid = pmc; 3610 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3611 } 3612 3613 int 3614 pmc_stop(pmc_id_t pmc) 3615 { 3616 struct pmc_op_simple pmc_stop_args; 3617 3618 pmc_stop_args.pm_pmcid = pmc; 3619 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3620 } 3621 3622 int 3623 pmc_width(pmc_id_t pmcid, uint32_t *width) 3624 { 3625 unsigned int i; 3626 enum pmc_class cl; 3627 3628 cl = PMC_ID_TO_CLASS(pmcid); 3629 for (i = 0; i < cpu_info.pm_nclass; i++) 3630 if (cpu_info.pm_classes[i].pm_class == cl) { 3631 *width = cpu_info.pm_classes[i].pm_width; 3632 return (0); 3633 } 3634 errno = EINVAL; 3635 return (-1); 3636 } 3637 3638 int 3639 pmc_write(pmc_id_t pmc, pmc_value_t value) 3640 { 3641 struct pmc_op_pmcrw pmc_write_op; 3642 3643 pmc_write_op.pm_pmcid = pmc; 3644 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3645 pmc_write_op.pm_value = value; 3646 return (PMC_CALL(PMCRW, &pmc_write_op)); 3647 } 3648 3649 int 3650 pmc_writelog(uint32_t userdata) 3651 { 3652 struct pmc_op_writelog wl; 3653 3654 wl.pm_userdata = userdata; 3655 return (PMC_CALL(WRITELOG, &wl)); 3656 } 3657