1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/types.h> 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/pmc.h> 33 #include <sys/syscall.h> 34 35 #include <ctype.h> 36 #include <errno.h> 37 #include <err.h> 38 #include <fcntl.h> 39 #include <pmc.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <sysexits.h> 45 #include <unistd.h> 46 47 #include "libpmcinternal.h" 48 49 /* Function prototypes */ 50 #if defined(__amd64__) || defined(__i386__) 51 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 52 struct pmc_op_pmcallocate *_pmc_config); 53 static int ibs_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 54 struct pmc_op_pmcallocate *_pmc_config); 55 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 56 struct pmc_op_pmcallocate *_pmc_config); 57 #endif 58 #if defined(__arm__) 59 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 60 struct pmc_op_pmcallocate *_pmc_config); 61 #endif 62 #if defined(__aarch64__) 63 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65 static int cmn600_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 66 struct pmc_op_pmcallocate *_pmc_config); 67 static int dmc620_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 68 struct pmc_op_pmcallocate *_pmc_config); 69 #endif 70 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72 73 #if defined(__powerpc__) 74 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 #endif /* __powerpc__ */ 77 78 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params)) 79 80 /* 81 * Event aliases provide a way for the user to ask for generic events 82 * like "cache-misses", or "instructions-retired". These aliases are 83 * mapped to the appropriate canonical event descriptions using a 84 * lookup table. 85 */ 86 struct pmc_event_alias { 87 const char *pm_alias; 88 const char *pm_spec; 89 }; 90 91 static const struct pmc_event_alias *pmc_mdep_event_aliases; 92 93 /* 94 * The pmc_event_descr structure maps symbolic names known to the user 95 * to integer codes used by the PMC KLD. 96 */ 97 struct pmc_event_descr { 98 const char *pm_ev_name; 99 enum pmc_event pm_ev_code; 100 }; 101 102 /* 103 * The pmc_class_descr structure maps class name prefixes for 104 * event names to event tables and other PMC class data. 105 */ 106 struct pmc_class_descr { 107 const char *pm_evc_name; 108 size_t pm_evc_name_size; 109 enum pmc_class pm_evc_class; 110 const struct pmc_event_descr *pm_evc_event_table; 111 size_t pm_evc_event_table_size; 112 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 113 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 114 }; 115 116 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 117 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 118 119 #undef __PMC_EV 120 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 121 122 /* 123 * PMC_CLASSDEP_TABLE(NAME, CLASS) 124 * 125 * Define a table mapping event names and aliases to HWPMC event IDs. 126 */ 127 #define PMC_CLASSDEP_TABLE(N, C) \ 128 static const struct pmc_event_descr N##_event_table[] = \ 129 { \ 130 __PMC_EV_##C() \ 131 } 132 133 PMC_CLASSDEP_TABLE(iaf, IAF); 134 PMC_CLASSDEP_TABLE(k8, K8); 135 PMC_CLASSDEP_TABLE(ibs, IBS); 136 PMC_CLASSDEP_TABLE(armv7, ARMV7); 137 PMC_CLASSDEP_TABLE(armv8, ARMV8); 138 PMC_CLASSDEP_TABLE(cmn600_pmu, CMN600_PMU); 139 PMC_CLASSDEP_TABLE(dmc620_pmu_cd2, DMC620_PMU_CD2); 140 PMC_CLASSDEP_TABLE(dmc620_pmu_c, DMC620_PMU_C); 141 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 142 PMC_CLASSDEP_TABLE(ppc970, PPC970); 143 PMC_CLASSDEP_TABLE(e500, E500); 144 145 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 146 147 #undef __PMC_EV_ALIAS 148 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 149 150 /* 151 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table 152 * rather than duplicating for each core. 153 */ 154 155 static const struct pmc_event_descr cortex_a8_event_table[] = 156 { 157 __PMC_EV_ALIAS_ARMV7_CORTEX_A8() 158 __PMC_EV_ARMV7() 159 }; 160 161 static const struct pmc_event_descr cortex_a9_event_table[] = 162 { 163 __PMC_EV_ALIAS_ARMV7_CORTEX_A9() 164 __PMC_EV_ARMV7() 165 }; 166 167 static const struct pmc_event_descr cortex_a53_event_table[] = 168 { 169 __PMC_EV_ALIAS_ARMV8_CORTEX_A53() 170 __PMC_EV_ARMV8() 171 }; 172 173 static const struct pmc_event_descr cortex_a57_event_table[] = 174 { 175 __PMC_EV_ALIAS_ARMV8_CORTEX_A57() 176 __PMC_EV_ARMV8() 177 }; 178 179 static const struct pmc_event_descr cortex_a76_event_table[] = 180 { 181 __PMC_EV_ALIAS_ARMV8_CORTEX_A76() 182 __PMC_EV_ARMV8() 183 }; 184 185 static const struct pmc_event_descr tsc_event_table[] = 186 { 187 __PMC_EV_ALIAS_TSC() 188 }; 189 190 #undef PMC_CLASS_TABLE_DESC 191 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 192 static const struct pmc_class_descr NAME##_class_table_descr = \ 193 { \ 194 .pm_evc_name = #CLASS "-", \ 195 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 196 .pm_evc_class = PMC_CLASS_##CLASS , \ 197 .pm_evc_event_table = EVENTS##_event_table , \ 198 .pm_evc_event_table_size = \ 199 PMC_EVENT_TABLE_SIZE(EVENTS), \ 200 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 201 } 202 203 #if defined(__i386__) || defined(__amd64__) 204 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 205 PMC_CLASS_TABLE_DESC(ibs, IBS, ibs, ibs); 206 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 207 #endif 208 #if defined(__arm__) 209 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7); 210 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); 211 #endif 212 #if defined(__aarch64__) 213 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); 214 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); 215 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64); 216 PMC_CLASS_TABLE_DESC(cmn600_pmu, CMN600_PMU, cmn600_pmu, cmn600_pmu); 217 PMC_CLASS_TABLE_DESC(dmc620_pmu_cd2, DMC620_PMU_CD2, dmc620_pmu_cd2, dmc620_pmu); 218 PMC_CLASS_TABLE_DESC(dmc620_pmu_c, DMC620_PMU_C, dmc620_pmu_c, dmc620_pmu); 219 #endif 220 #if defined(__powerpc__) 221 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 222 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 223 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); 224 #endif 225 226 static struct pmc_class_descr soft_class_table_descr = 227 { 228 .pm_evc_name = "SOFT-", 229 .pm_evc_name_size = sizeof("SOFT-") - 1, 230 .pm_evc_class = PMC_CLASS_SOFT, 231 .pm_evc_event_table = NULL, 232 .pm_evc_event_table_size = 0, 233 .pm_evc_allocate_pmc = soft_allocate_pmc 234 }; 235 236 #undef PMC_CLASS_TABLE_DESC 237 238 static const struct pmc_class_descr **pmc_class_table; 239 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 240 241 /* 242 * Mapping tables, mapping enumeration values to human readable 243 * strings. 244 */ 245 246 static const char * pmc_capability_names[] = { 247 #undef __PMC_CAP 248 #define __PMC_CAP(N,V,D) #N , 249 __PMC_CAPS() 250 }; 251 252 struct pmc_class_map { 253 enum pmc_class pm_class; 254 const char *pm_name; 255 }; 256 257 static const struct pmc_class_map pmc_class_names[] = { 258 #undef __PMC_CLASS 259 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } , 260 __PMC_CLASSES() 261 }; 262 263 struct pmc_cputype_map { 264 enum pmc_cputype pm_cputype; 265 const char *pm_name; 266 }; 267 268 static const struct pmc_cputype_map pmc_cputype_names[] = { 269 #undef __PMC_CPU 270 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 271 __PMC_CPUS() 272 }; 273 274 static const char * pmc_disposition_names[] = { 275 #undef __PMC_DISP 276 #define __PMC_DISP(D) #D , 277 __PMC_DISPOSITIONS() 278 }; 279 280 static const char * pmc_mode_names[] = { 281 #undef __PMC_MODE 282 #define __PMC_MODE(M,N) #M , 283 __PMC_MODES() 284 }; 285 286 static const char * pmc_state_names[] = { 287 #undef __PMC_STATE 288 #define __PMC_STATE(S) #S , 289 __PMC_STATES() 290 }; 291 292 /* 293 * Filled in by pmc_init(). 294 */ 295 static int pmc_syscall = -1; 296 static struct pmc_cpuinfo cpu_info; 297 static struct pmc_op_getdyneventinfo soft_event_info; 298 299 /* Event masks for events */ 300 struct pmc_masks { 301 const char *pm_name; 302 const uint64_t pm_value; 303 }; 304 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 305 #define NULLMASK { .pm_name = NULL } 306 307 #if defined(__amd64__) || defined(__i386__) 308 static int 309 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 310 { 311 const struct pmc_masks *pm; 312 char *q, *r; 313 int c; 314 315 if (pmask == NULL) /* no mask keywords */ 316 return (-1); 317 q = strchr(p, '='); /* skip '=' */ 318 if (*++q == '\0') /* no more data */ 319 return (-1); 320 c = 0; /* count of mask keywords seen */ 321 while ((r = strsep(&q, "+")) != NULL) { 322 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 323 pm++) 324 ; 325 if (pm->pm_name == NULL) /* not found */ 326 return (-1); 327 *evmask |= pm->pm_value; 328 c++; 329 } 330 return (c); 331 } 332 #endif 333 334 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 335 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 336 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 337 338 #if defined(__amd64__) || defined(__i386__) 339 /* 340 * AMD K8 PMCs. 341 * 342 */ 343 344 static struct pmc_event_alias k8_aliases[] = { 345 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 346 EV_ALIAS("branch-mispredicts", 347 "k8-fr-retired-taken-branches-mispredicted"), 348 EV_ALIAS("cycles", "tsc"), 349 EV_ALIAS("dc-misses", "k8-dc-miss"), 350 EV_ALIAS("ic-misses", "k8-ic-miss"), 351 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 352 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 353 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 354 EV_ALIAS(NULL, NULL) 355 }; 356 357 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 358 359 /* 360 * Parsing tables 361 */ 362 363 /* fp dispatched fpu ops */ 364 static const struct pmc_masks k8_mask_fdfo[] = { 365 __K8MASK(add-pipe-excluding-junk-ops, 0), 366 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 367 __K8MASK(store-pipe-excluding-junk-ops, 2), 368 __K8MASK(add-pipe-junk-ops, 3), 369 __K8MASK(multiply-pipe-junk-ops, 4), 370 __K8MASK(store-pipe-junk-ops, 5), 371 NULLMASK 372 }; 373 374 /* ls segment register loads */ 375 static const struct pmc_masks k8_mask_lsrl[] = { 376 __K8MASK(es, 0), 377 __K8MASK(cs, 1), 378 __K8MASK(ss, 2), 379 __K8MASK(ds, 3), 380 __K8MASK(fs, 4), 381 __K8MASK(gs, 5), 382 __K8MASK(hs, 6), 383 NULLMASK 384 }; 385 386 /* ls locked operation */ 387 static const struct pmc_masks k8_mask_llo[] = { 388 __K8MASK(locked-instructions, 0), 389 __K8MASK(cycles-in-request, 1), 390 __K8MASK(cycles-to-complete, 2), 391 NULLMASK 392 }; 393 394 /* dc refill from {l2,system} and dc copyback */ 395 static const struct pmc_masks k8_mask_dc[] = { 396 __K8MASK(invalid, 0), 397 __K8MASK(shared, 1), 398 __K8MASK(exclusive, 2), 399 __K8MASK(owner, 3), 400 __K8MASK(modified, 4), 401 NULLMASK 402 }; 403 404 /* dc one bit ecc error */ 405 static const struct pmc_masks k8_mask_dobee[] = { 406 __K8MASK(scrubber, 0), 407 __K8MASK(piggyback, 1), 408 NULLMASK 409 }; 410 411 /* dc dispatched prefetch instructions */ 412 static const struct pmc_masks k8_mask_ddpi[] = { 413 __K8MASK(load, 0), 414 __K8MASK(store, 1), 415 __K8MASK(nta, 2), 416 NULLMASK 417 }; 418 419 /* dc dcache accesses by locks */ 420 static const struct pmc_masks k8_mask_dabl[] = { 421 __K8MASK(accesses, 0), 422 __K8MASK(misses, 1), 423 NULLMASK 424 }; 425 426 /* bu internal l2 request */ 427 static const struct pmc_masks k8_mask_bilr[] = { 428 __K8MASK(ic-fill, 0), 429 __K8MASK(dc-fill, 1), 430 __K8MASK(tlb-reload, 2), 431 __K8MASK(tag-snoop, 3), 432 __K8MASK(cancelled, 4), 433 NULLMASK 434 }; 435 436 /* bu fill request l2 miss */ 437 static const struct pmc_masks k8_mask_bfrlm[] = { 438 __K8MASK(ic-fill, 0), 439 __K8MASK(dc-fill, 1), 440 __K8MASK(tlb-reload, 2), 441 NULLMASK 442 }; 443 444 /* bu fill into l2 */ 445 static const struct pmc_masks k8_mask_bfil[] = { 446 __K8MASK(dirty-l2-victim, 0), 447 __K8MASK(victim-from-l2, 1), 448 NULLMASK 449 }; 450 451 /* fr retired fpu instructions */ 452 static const struct pmc_masks k8_mask_frfi[] = { 453 __K8MASK(x87, 0), 454 __K8MASK(mmx-3dnow, 1), 455 __K8MASK(packed-sse-sse2, 2), 456 __K8MASK(scalar-sse-sse2, 3), 457 NULLMASK 458 }; 459 460 /* fr retired fastpath double op instructions */ 461 static const struct pmc_masks k8_mask_frfdoi[] = { 462 __K8MASK(low-op-pos-0, 0), 463 __K8MASK(low-op-pos-1, 1), 464 __K8MASK(low-op-pos-2, 2), 465 NULLMASK 466 }; 467 468 /* fr fpu exceptions */ 469 static const struct pmc_masks k8_mask_ffe[] = { 470 __K8MASK(x87-reclass-microfaults, 0), 471 __K8MASK(sse-retype-microfaults, 1), 472 __K8MASK(sse-reclass-microfaults, 2), 473 __K8MASK(sse-and-x87-microtraps, 3), 474 NULLMASK 475 }; 476 477 /* nb memory controller page access event */ 478 static const struct pmc_masks k8_mask_nmcpae[] = { 479 __K8MASK(page-hit, 0), 480 __K8MASK(page-miss, 1), 481 __K8MASK(page-conflict, 2), 482 NULLMASK 483 }; 484 485 /* nb memory controller turnaround */ 486 static const struct pmc_masks k8_mask_nmct[] = { 487 __K8MASK(dimm-turnaround, 0), 488 __K8MASK(read-to-write-turnaround, 1), 489 __K8MASK(write-to-read-turnaround, 2), 490 NULLMASK 491 }; 492 493 /* nb memory controller bypass saturation */ 494 static const struct pmc_masks k8_mask_nmcbs[] = { 495 __K8MASK(memory-controller-hi-pri-bypass, 0), 496 __K8MASK(memory-controller-lo-pri-bypass, 1), 497 __K8MASK(dram-controller-interface-bypass, 2), 498 __K8MASK(dram-controller-queue-bypass, 3), 499 NULLMASK 500 }; 501 502 /* nb sized commands */ 503 static const struct pmc_masks k8_mask_nsc[] = { 504 __K8MASK(nonpostwrszbyte, 0), 505 __K8MASK(nonpostwrszdword, 1), 506 __K8MASK(postwrszbyte, 2), 507 __K8MASK(postwrszdword, 3), 508 __K8MASK(rdszbyte, 4), 509 __K8MASK(rdszdword, 5), 510 __K8MASK(rdmodwr, 6), 511 NULLMASK 512 }; 513 514 /* nb probe result */ 515 static const struct pmc_masks k8_mask_npr[] = { 516 __K8MASK(probe-miss, 0), 517 __K8MASK(probe-hit, 1), 518 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 519 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 520 NULLMASK 521 }; 522 523 /* nb hypertransport bus bandwidth */ 524 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 525 __K8MASK(command, 0), 526 __K8MASK(data, 1), 527 __K8MASK(buffer-release, 2), 528 __K8MASK(nop, 3), 529 NULLMASK 530 }; 531 532 #undef __K8MASK 533 534 #define K8_KW_COUNT "count" 535 #define K8_KW_EDGE "edge" 536 #define K8_KW_INV "inv" 537 #define K8_KW_MASK "mask" 538 #define K8_KW_OS "os" 539 #define K8_KW_USR "usr" 540 541 static int 542 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 543 struct pmc_op_pmcallocate *pmc_config) 544 { 545 char *e, *p, *q; 546 int n; 547 uint32_t count; 548 uint64_t evmask; 549 const struct pmc_masks *pm, *pmask; 550 551 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 552 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 553 554 pmask = NULL; 555 evmask = 0; 556 557 #define __K8SETMASK(M) pmask = k8_mask_##M 558 559 /* setup parsing tables */ 560 switch (pe) { 561 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 562 __K8SETMASK(fdfo); 563 break; 564 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 565 __K8SETMASK(lsrl); 566 break; 567 case PMC_EV_K8_LS_LOCKED_OPERATION: 568 __K8SETMASK(llo); 569 break; 570 case PMC_EV_K8_DC_REFILL_FROM_L2: 571 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 572 case PMC_EV_K8_DC_COPYBACK: 573 __K8SETMASK(dc); 574 break; 575 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 576 __K8SETMASK(dobee); 577 break; 578 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 579 __K8SETMASK(ddpi); 580 break; 581 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 582 __K8SETMASK(dabl); 583 break; 584 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 585 __K8SETMASK(bilr); 586 break; 587 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 588 __K8SETMASK(bfrlm); 589 break; 590 case PMC_EV_K8_BU_FILL_INTO_L2: 591 __K8SETMASK(bfil); 592 break; 593 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 594 __K8SETMASK(frfi); 595 break; 596 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 597 __K8SETMASK(frfdoi); 598 break; 599 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 600 __K8SETMASK(ffe); 601 break; 602 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 603 __K8SETMASK(nmcpae); 604 break; 605 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 606 __K8SETMASK(nmct); 607 break; 608 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 609 __K8SETMASK(nmcbs); 610 break; 611 case PMC_EV_K8_NB_SIZED_COMMANDS: 612 __K8SETMASK(nsc); 613 break; 614 case PMC_EV_K8_NB_PROBE_RESULT: 615 __K8SETMASK(npr); 616 break; 617 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 618 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 619 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 620 __K8SETMASK(nhbb); 621 break; 622 623 default: 624 break; /* no options defined */ 625 } 626 627 while ((p = strsep(&ctrspec, ",")) != NULL) { 628 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 629 q = strchr(p, '='); 630 if (*++q == '\0') /* skip '=' */ 631 return (-1); 632 633 count = strtol(q, &e, 0); 634 if (e == q || *e != '\0') 635 return (-1); 636 637 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 638 pmc_config->pm_md.pm_amd.pm_amd_config |= 639 AMD_PMC_TO_COUNTER(count); 640 641 } else if (KWMATCH(p, K8_KW_EDGE)) { 642 pmc_config->pm_caps |= PMC_CAP_EDGE; 643 } else if (KWMATCH(p, K8_KW_INV)) { 644 pmc_config->pm_caps |= PMC_CAP_INVERT; 645 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 646 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 647 return (-1); 648 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 649 } else if (KWMATCH(p, K8_KW_OS)) { 650 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 651 } else if (KWMATCH(p, K8_KW_USR)) { 652 pmc_config->pm_caps |= PMC_CAP_USER; 653 } else 654 return (-1); 655 } 656 657 /* other post processing */ 658 switch (pe) { 659 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 660 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 661 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 662 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 663 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 664 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 665 /* XXX only available in rev B and later */ 666 break; 667 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 668 /* XXX only available in rev C and later */ 669 break; 670 case PMC_EV_K8_LS_LOCKED_OPERATION: 671 /* XXX CPU Rev A,B evmask is to be zero */ 672 if (evmask & (evmask - 1)) /* > 1 bit set */ 673 return (-1); 674 if (evmask == 0) { 675 evmask = 0x01; /* Rev C and later: #instrs */ 676 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 677 } 678 break; 679 default: 680 if (evmask == 0 && pmask != NULL) { 681 for (pm = pmask; pm->pm_name; pm++) 682 evmask |= pm->pm_value; 683 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 684 } 685 } 686 687 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 688 pmc_config->pm_md.pm_amd.pm_amd_config = 689 AMD_PMC_TO_UNITMASK(evmask); 690 691 return (0); 692 } 693 694 static int 695 ibs_allocate_pmc(enum pmc_event pe, char *ctrspec, 696 struct pmc_op_pmcallocate *pmc_config) 697 { 698 char *e, *p, *q; 699 uint64_t ctl; 700 701 pmc_config->pm_caps |= 702 (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE); 703 pmc_config->pm_md.pm_ibs.ibs_ctl = 0; 704 705 /* setup parsing tables */ 706 switch (pe) { 707 case PMC_EV_IBS_FETCH: 708 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_FETCH; 709 break; 710 case PMC_EV_IBS_OP: 711 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_OP; 712 break; 713 default: 714 return (-1); 715 } 716 717 /* parse parameters */ 718 while ((p = strsep(&ctrspec, ",")) != NULL) { 719 if (KWPREFIXMATCH(p, "ctl=")) { 720 q = strchr(p, '='); 721 if (*++q == '\0') /* skip '=' */ 722 return (-1); 723 724 ctl = strtoull(q, &e, 0); 725 if (e == q || *e != '\0') 726 return (-1); 727 728 pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl; 729 } else { 730 return (-1); 731 } 732 } 733 734 return (0); 735 } 736 737 static int 738 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 739 struct pmc_op_pmcallocate *pmc_config) 740 { 741 if (pe != PMC_EV_TSC_TSC) 742 return (-1); 743 744 /* TSC events must be unqualified. */ 745 if (ctrspec && *ctrspec != '\0') 746 return (-1); 747 748 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 749 pmc_config->pm_caps |= PMC_CAP_READ; 750 751 return (0); 752 } 753 #endif 754 755 static struct pmc_event_alias generic_aliases[] = { 756 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 757 EV_ALIAS(NULL, NULL) 758 }; 759 760 static int 761 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 762 struct pmc_op_pmcallocate *pmc_config) 763 { 764 (void)ctrspec; 765 (void)pmc_config; 766 767 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 768 return (-1); 769 770 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 771 return (0); 772 } 773 774 #if defined(__arm__) 775 static struct pmc_event_alias cortex_a8_aliases[] = { 776 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 777 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 778 EV_ALIAS("instructions", "INSTR_EXECUTED"), 779 EV_ALIAS(NULL, NULL) 780 }; 781 782 static struct pmc_event_alias cortex_a9_aliases[] = { 783 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 784 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 785 EV_ALIAS("instructions", "INSTR_EXECUTED"), 786 EV_ALIAS(NULL, NULL) 787 }; 788 789 static int 790 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 791 struct pmc_op_pmcallocate *pmc_config __unused) 792 { 793 switch (pe) { 794 default: 795 break; 796 } 797 798 return (0); 799 } 800 #endif 801 802 #if defined(__aarch64__) 803 static struct pmc_event_alias cortex_a53_aliases[] = { 804 EV_ALIAS(NULL, NULL) 805 }; 806 static struct pmc_event_alias cortex_a57_aliases[] = { 807 EV_ALIAS(NULL, NULL) 808 }; 809 static struct pmc_event_alias cortex_a76_aliases[] = { 810 EV_ALIAS(NULL, NULL) 811 }; 812 813 static int 814 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec, 815 struct pmc_op_pmcallocate *pmc_config) 816 { 817 char *p; 818 819 while ((p = strsep(&ctrspec, ",")) != NULL) { 820 if (KWMATCH(p, "os")) 821 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 822 else if (KWMATCH(p, "usr")) 823 pmc_config->pm_caps |= PMC_CAP_USER; 824 else 825 return (-1); 826 } 827 828 return (0); 829 } 830 831 static int 832 cmn600_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec, 833 struct pmc_op_pmcallocate *pmc_config) 834 { 835 uint32_t nodeid, occupancy, xpport, xpchannel; 836 char *e, *p, *q; 837 unsigned int i; 838 char *xpport_names[] = { "East", "West", "North", "South", "devport0", 839 "devport1" }; 840 char *xpchannel_names[] = { "REQ", "RSP", "SNP", "DAT" }; 841 842 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 843 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 844 pmc_config->pm_md.pm_cmn600.pma_cmn600_config = 0; 845 /* 846 * CMN600 extra fields: 847 * * nodeid - node coordinates x[2-3],y[2-3],p[1],s[2] 848 * width of x and y fields depend on matrix size. 849 * * occupancy - numeric value to select desired filter. 850 * * xpport - East, West, North, South, devport0, devport1 (or 0, 1, ..., 5) 851 * * xpchannel - REQ, RSP, SNP, DAT (or 0, 1, 2, 3) 852 */ 853 854 while ((p = strsep(&ctrspec, ",")) != NULL) { 855 if (KWPREFIXMATCH(p, "nodeid=")) { 856 q = strchr(p, '='); 857 if (*++q == '\0') /* skip '=' */ 858 return (-1); 859 860 nodeid = strtol(q, &e, 0); 861 if (e == q || *e != '\0') 862 return (-1); 863 864 pmc_config->pm_md.pm_cmn600.pma_cmn600_nodeid |= nodeid; 865 866 } else if (KWPREFIXMATCH(p, "occupancy=")) { 867 q = strchr(p, '='); 868 if (*++q == '\0') /* skip '=' */ 869 return (-1); 870 871 occupancy = strtol(q, &e, 0); 872 if (e == q || *e != '\0') 873 return (-1); 874 875 pmc_config->pm_md.pm_cmn600.pma_cmn600_occupancy = occupancy; 876 } else if (KWPREFIXMATCH(p, "xpport=")) { 877 q = strchr(p, '='); 878 if (*++q == '\0') /* skip '=' */ 879 return (-1); 880 881 xpport = strtol(q, &e, 0); 882 if (e == q || *e != '\0') { 883 for (i = 0; i < nitems(xpport_names); i++) { 884 if (strcasecmp(xpport_names[i], q) == 0) { 885 xpport = i; 886 break; 887 } 888 } 889 if (i == nitems(xpport_names)) 890 return (-1); 891 } 892 893 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpport << 2; 894 } else if (KWPREFIXMATCH(p, "xpchannel=")) { 895 q = strchr(p, '='); 896 if (*++q == '\0') /* skip '=' */ 897 return (-1); 898 899 xpchannel = strtol(q, &e, 0); 900 if (e == q || *e != '\0') { 901 for (i = 0; i < nitems(xpchannel_names); i++) { 902 if (strcasecmp(xpchannel_names[i], q) == 0) { 903 xpchannel = i; 904 break; 905 } 906 } 907 if (i == nitems(xpchannel_names)) 908 return (-1); 909 } 910 911 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpchannel << 5; 912 } else 913 return (-1); 914 } 915 916 return (0); 917 } 918 919 static int 920 dmc620_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec, 921 struct pmc_op_pmcallocate *pmc_config) 922 { 923 char *e, *p, *q; 924 uint64_t match, mask; 925 uint32_t count; 926 927 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 928 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 929 pmc_config->pm_md.pm_dmc620.pm_dmc620_config = 0; 930 931 while ((p = strsep(&ctrspec, ",")) != NULL) { 932 if (KWPREFIXMATCH(p, "count=")) { 933 q = strchr(p, '='); 934 if (*++q == '\0') /* skip '=' */ 935 return (-1); 936 937 count = strtol(q, &e, 0); 938 if (e == q || *e != '\0') 939 return (-1); 940 941 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 942 pmc_config->pm_md.pm_dmc620.pm_dmc620_config |= count; 943 944 } else if (KWMATCH(p, "inv")) { 945 pmc_config->pm_caps |= PMC_CAP_INVERT; 946 } else if (KWPREFIXMATCH(p, "match=")) { 947 match = strtol(q, &e, 0); 948 if (e == q || *e != '\0') 949 return (-1); 950 951 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 952 pmc_config->pm_md.pm_dmc620.pm_dmc620_match = match; 953 } else if (KWPREFIXMATCH(p, "mask=")) { 954 q = strchr(p, '='); 955 if (*++q == '\0') /* skip '=' */ 956 return (-1); 957 958 mask = strtol(q, &e, 0); 959 if (e == q || *e != '\0') 960 return (-1); 961 962 pmc_config->pm_md.pm_dmc620.pm_dmc620_mask = mask; 963 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 964 } else 965 return (-1); 966 } 967 968 return (0); 969 } 970 #endif 971 972 #if defined(__powerpc__) 973 974 static struct pmc_event_alias ppc7450_aliases[] = { 975 EV_ALIAS("instructions", "INSTR_COMPLETED"), 976 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 977 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 978 EV_ALIAS(NULL, NULL) 979 }; 980 981 static struct pmc_event_alias ppc970_aliases[] = { 982 EV_ALIAS("instructions", "INSTR_COMPLETED"), 983 EV_ALIAS("cycles", "CYCLES"), 984 EV_ALIAS(NULL, NULL) 985 }; 986 987 static struct pmc_event_alias e500_aliases[] = { 988 EV_ALIAS("instructions", "INSTR_COMPLETED"), 989 EV_ALIAS("cycles", "CYCLES"), 990 EV_ALIAS(NULL, NULL) 991 }; 992 993 #define POWERPC_KW_OS "os" 994 #define POWERPC_KW_USR "usr" 995 #define POWERPC_KW_ANYTHREAD "anythread" 996 997 static int 998 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 999 struct pmc_op_pmcallocate *pmc_config __unused) 1000 { 1001 char *p; 1002 1003 (void) pe; 1004 1005 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1006 1007 while ((p = strsep(&ctrspec, ",")) != NULL) { 1008 if (KWMATCH(p, POWERPC_KW_OS)) 1009 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1010 else if (KWMATCH(p, POWERPC_KW_USR)) 1011 pmc_config->pm_caps |= PMC_CAP_USER; 1012 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 1013 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 1014 else 1015 return (-1); 1016 } 1017 1018 return (0); 1019 } 1020 1021 #endif /* __powerpc__ */ 1022 1023 1024 /* 1025 * Match an event name `name' with its canonical form. 1026 * 1027 * Matches are case insensitive and spaces, periods, underscores and 1028 * hyphen characters are considered to match each other. 1029 * 1030 * Returns 1 for a match, 0 otherwise. 1031 */ 1032 1033 static int 1034 pmc_match_event_name(const char *name, const char *canonicalname) 1035 { 1036 int cc, nc; 1037 const unsigned char *c, *n; 1038 1039 c = (const unsigned char *) canonicalname; 1040 n = (const unsigned char *) name; 1041 1042 for (; (nc = *n) && (cc = *c); n++, c++) { 1043 1044 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 1045 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 1046 continue; 1047 1048 if (toupper(nc) == toupper(cc)) 1049 continue; 1050 1051 1052 return (0); 1053 } 1054 1055 if (*n == '\0' && *c == '\0') 1056 return (1); 1057 1058 return (0); 1059 } 1060 1061 /* 1062 * Match an event name against all the event named supported by a 1063 * PMC class. 1064 * 1065 * Returns an event descriptor pointer on match or NULL otherwise. 1066 */ 1067 static const struct pmc_event_descr * 1068 pmc_match_event_class(const char *name, 1069 const struct pmc_class_descr *pcd) 1070 { 1071 size_t n; 1072 const struct pmc_event_descr *ev; 1073 1074 ev = pcd->pm_evc_event_table; 1075 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 1076 if (pmc_match_event_name(name, ev->pm_ev_name)) 1077 return (ev); 1078 1079 return (NULL); 1080 } 1081 1082 /* 1083 * API entry points 1084 */ 1085 1086 int 1087 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 1088 uint32_t flags, int cpu, pmc_id_t *pmcid, 1089 uint64_t count) 1090 { 1091 size_t n; 1092 int retval; 1093 char *r, *spec_copy; 1094 const char *ctrname; 1095 const struct pmc_event_descr *ev; 1096 const struct pmc_event_alias *alias; 1097 struct pmc_op_pmcallocate pmc_config; 1098 const struct pmc_class_descr *pcd; 1099 1100 spec_copy = NULL; 1101 retval = -1; 1102 1103 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 1104 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 1105 errno = EINVAL; 1106 goto out; 1107 } 1108 bzero(&pmc_config, sizeof(pmc_config)); 1109 pmc_config.pm_cpu = cpu; 1110 pmc_config.pm_mode = mode; 1111 pmc_config.pm_flags = flags; 1112 pmc_config.pm_count = count; 1113 if (PMC_IS_SAMPLING_MODE(mode)) 1114 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 1115 1116 /* 1117 * Try to pull the raw event ID directly from the pmu-events table. If 1118 * this is unsupported on the platform, or the event is not found, 1119 * continue with searching the regular event tables. 1120 */ 1121 r = spec_copy = strdup(ctrspec); 1122 ctrname = strsep(&r, ","); 1123 if (pmc_pmu_enabled()) { 1124 if (pmc_pmu_pmcallocate(ctrname, &pmc_config) == 0) 1125 goto found; 1126 } 1127 free(spec_copy); 1128 spec_copy = NULL; 1129 1130 /* replace an event alias with the canonical event specifier */ 1131 if (pmc_mdep_event_aliases) 1132 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 1133 if (!strcasecmp(ctrspec, alias->pm_alias)) { 1134 spec_copy = strdup(alias->pm_spec); 1135 break; 1136 } 1137 1138 if (spec_copy == NULL) 1139 spec_copy = strdup(ctrspec); 1140 1141 r = spec_copy; 1142 ctrname = strsep(&r, ","); 1143 1144 /* 1145 * If a explicit class prefix was given by the user, restrict the 1146 * search for the event to the specified PMC class. 1147 */ 1148 ev = NULL; 1149 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 1150 pcd = pmc_class_table[n]; 1151 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name, 1152 pcd->pm_evc_name_size) == 0) { 1153 if ((ev = pmc_match_event_class(ctrname + 1154 pcd->pm_evc_name_size, pcd)) == NULL) { 1155 errno = EINVAL; 1156 goto out; 1157 } 1158 break; 1159 } 1160 } 1161 1162 /* 1163 * Otherwise, search for this event in all compatible PMC 1164 * classes. 1165 */ 1166 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 1167 pcd = pmc_class_table[n]; 1168 if (pcd != NULL) 1169 ev = pmc_match_event_class(ctrname, pcd); 1170 } 1171 1172 if (ev == NULL) { 1173 errno = EINVAL; 1174 goto out; 1175 } 1176 1177 pmc_config.pm_ev = ev->pm_ev_code; 1178 pmc_config.pm_class = pcd->pm_evc_class; 1179 1180 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 1181 errno = EINVAL; 1182 goto out; 1183 } 1184 1185 found: 1186 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) { 1187 *pmcid = pmc_config.pm_pmcid; 1188 retval = 0; 1189 } 1190 out: 1191 if (spec_copy) 1192 free(spec_copy); 1193 1194 return (retval); 1195 } 1196 1197 int 1198 pmc_attach(pmc_id_t pmc, pid_t pid) 1199 { 1200 struct pmc_op_pmcattach pmc_attach_args; 1201 1202 pmc_attach_args.pm_pmc = pmc; 1203 pmc_attach_args.pm_pid = pid; 1204 1205 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args)); 1206 } 1207 1208 int 1209 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 1210 { 1211 unsigned int i; 1212 enum pmc_class cl; 1213 1214 cl = PMC_ID_TO_CLASS(pmcid); 1215 for (i = 0; i < cpu_info.pm_nclass; i++) 1216 if (cpu_info.pm_classes[i].pm_class == cl) { 1217 *caps = cpu_info.pm_classes[i].pm_caps; 1218 return (0); 1219 } 1220 errno = EINVAL; 1221 return (-1); 1222 } 1223 1224 int 1225 pmc_configure_logfile(int fd) 1226 { 1227 struct pmc_op_configurelog cla; 1228 1229 cla.pm_flags = 0; 1230 cla.pm_logfd = fd; 1231 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0) 1232 return (-1); 1233 return (0); 1234 } 1235 1236 int 1237 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 1238 { 1239 if (pmc_syscall == -1) { 1240 errno = ENXIO; 1241 return (-1); 1242 } 1243 1244 *pci = &cpu_info; 1245 return (0); 1246 } 1247 1248 int 1249 pmc_detach(pmc_id_t pmc, pid_t pid) 1250 { 1251 struct pmc_op_pmcattach pmc_detach_args; 1252 1253 pmc_detach_args.pm_pmc = pmc; 1254 pmc_detach_args.pm_pid = pid; 1255 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args)); 1256 } 1257 1258 int 1259 pmc_disable(int cpu, int pmc) 1260 { 1261 struct pmc_op_pmcadmin ssa; 1262 1263 ssa.pm_cpu = cpu; 1264 ssa.pm_pmc = pmc; 1265 ssa.pm_state = PMC_STATE_DISABLED; 1266 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa)); 1267 } 1268 1269 int 1270 pmc_enable(int cpu, int pmc) 1271 { 1272 struct pmc_op_pmcadmin ssa; 1273 1274 ssa.pm_cpu = cpu; 1275 ssa.pm_pmc = pmc; 1276 ssa.pm_state = PMC_STATE_FREE; 1277 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa)); 1278 } 1279 1280 /* 1281 * Return a list of events known to a given PMC class. 'cl' is the 1282 * PMC class identifier, 'eventnames' is the returned list of 'const 1283 * char *' pointers pointing to the names of the events. 'nevents' is 1284 * the number of event name pointers returned. 1285 * 1286 * The space for 'eventnames' is allocated using malloc(3). The caller 1287 * is responsible for freeing this space when done. 1288 */ 1289 int 1290 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 1291 int *nevents) 1292 { 1293 int count; 1294 const char **names; 1295 const struct pmc_event_descr *ev; 1296 1297 switch (cl) 1298 { 1299 case PMC_CLASS_IAF: 1300 ev = iaf_event_table; 1301 count = PMC_EVENT_TABLE_SIZE(iaf); 1302 break; 1303 case PMC_CLASS_TSC: 1304 ev = tsc_event_table; 1305 count = PMC_EVENT_TABLE_SIZE(tsc); 1306 break; 1307 case PMC_CLASS_K8: 1308 ev = k8_event_table; 1309 count = PMC_EVENT_TABLE_SIZE(k8); 1310 break; 1311 case PMC_CLASS_IBS: 1312 ev = ibs_event_table; 1313 count = PMC_EVENT_TABLE_SIZE(ibs); 1314 break; 1315 case PMC_CLASS_ARMV7: 1316 switch (cpu_info.pm_cputype) { 1317 default: 1318 case PMC_CPU_ARMV7_CORTEX_A8: 1319 ev = cortex_a8_event_table; 1320 count = PMC_EVENT_TABLE_SIZE(cortex_a8); 1321 break; 1322 case PMC_CPU_ARMV7_CORTEX_A9: 1323 ev = cortex_a9_event_table; 1324 count = PMC_EVENT_TABLE_SIZE(cortex_a9); 1325 break; 1326 } 1327 break; 1328 case PMC_CLASS_ARMV8: 1329 switch (cpu_info.pm_cputype) { 1330 default: 1331 case PMC_CPU_ARMV8_CORTEX_A53: 1332 ev = cortex_a53_event_table; 1333 count = PMC_EVENT_TABLE_SIZE(cortex_a53); 1334 break; 1335 case PMC_CPU_ARMV8_CORTEX_A57: 1336 ev = cortex_a57_event_table; 1337 count = PMC_EVENT_TABLE_SIZE(cortex_a57); 1338 break; 1339 case PMC_CPU_ARMV8_CORTEX_A76: 1340 ev = cortex_a76_event_table; 1341 count = PMC_EVENT_TABLE_SIZE(cortex_a76); 1342 break; 1343 } 1344 break; 1345 case PMC_CLASS_CMN600_PMU: 1346 ev = cmn600_pmu_event_table; 1347 count = PMC_EVENT_TABLE_SIZE(cmn600_pmu); 1348 break; 1349 case PMC_CLASS_DMC620_PMU_CD2: 1350 ev = dmc620_pmu_cd2_event_table; 1351 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2); 1352 break; 1353 case PMC_CLASS_DMC620_PMU_C: 1354 ev = dmc620_pmu_c_event_table; 1355 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_c); 1356 break; 1357 case PMC_CLASS_PPC7450: 1358 ev = ppc7450_event_table; 1359 count = PMC_EVENT_TABLE_SIZE(ppc7450); 1360 break; 1361 case PMC_CLASS_PPC970: 1362 ev = ppc970_event_table; 1363 count = PMC_EVENT_TABLE_SIZE(ppc970); 1364 break; 1365 case PMC_CLASS_E500: 1366 ev = e500_event_table; 1367 count = PMC_EVENT_TABLE_SIZE(e500); 1368 break; 1369 case PMC_CLASS_SOFT: 1370 ev = soft_event_table; 1371 count = soft_event_info.pm_nevent; 1372 break; 1373 default: 1374 errno = EINVAL; 1375 return (-1); 1376 } 1377 1378 if ((names = malloc(count * sizeof(const char *))) == NULL) 1379 return (-1); 1380 1381 *eventnames = names; 1382 *nevents = count; 1383 1384 for (;count--; ev++, names++) 1385 *names = ev->pm_ev_name; 1386 1387 return (0); 1388 } 1389 1390 int 1391 pmc_flush_logfile(void) 1392 { 1393 return (PMC_CALL(PMC_OP_FLUSHLOG, 0)); 1394 } 1395 1396 int 1397 pmc_close_logfile(void) 1398 { 1399 return (PMC_CALL(PMC_OP_CLOSELOG, 0)); 1400 } 1401 1402 int 1403 pmc_get_driver_stats(struct pmc_driverstats *ds) 1404 { 1405 struct pmc_op_getdriverstats gms; 1406 1407 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0) 1408 return (-1); 1409 1410 /* copy out fields in the current userland<->library interface */ 1411 ds->pm_intr_ignored = gms.pm_intr_ignored; 1412 ds->pm_intr_processed = gms.pm_intr_processed; 1413 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 1414 ds->pm_syscalls = gms.pm_syscalls; 1415 ds->pm_syscall_errors = gms.pm_syscall_errors; 1416 ds->pm_buffer_requests = gms.pm_buffer_requests; 1417 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 1418 ds->pm_log_sweeps = gms.pm_log_sweeps; 1419 return (0); 1420 } 1421 1422 int 1423 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 1424 { 1425 struct pmc_op_getmsr gm; 1426 1427 gm.pm_pmcid = pmc; 1428 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0) 1429 return (-1); 1430 *msr = gm.pm_msr; 1431 return (0); 1432 } 1433 1434 int 1435 pmc_init(void) 1436 { 1437 int error, pmc_mod_id; 1438 unsigned int n; 1439 uint32_t abi_version; 1440 struct module_stat pmc_modstat; 1441 struct pmc_op_getcpuinfo op_cpu_info; 1442 1443 if (pmc_syscall != -1) /* already inited */ 1444 return (0); 1445 1446 /* retrieve the system call number from the KLD */ 1447 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 1448 return (-1); 1449 1450 pmc_modstat.version = sizeof(struct module_stat); 1451 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 1452 return (-1); 1453 1454 pmc_syscall = pmc_modstat.data.intval; 1455 1456 /* check the kernel module's ABI against our compiled-in version */ 1457 abi_version = PMC_VERSION; 1458 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0) 1459 return (pmc_syscall = -1); 1460 1461 /* ignore patch & minor numbers for the comparison */ 1462 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 1463 errno = EPROGMISMATCH; 1464 return (pmc_syscall = -1); 1465 } 1466 1467 bzero(&op_cpu_info, sizeof(op_cpu_info)); 1468 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0) 1469 return (pmc_syscall = -1); 1470 1471 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 1472 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 1473 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 1474 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 1475 for (n = 0; n < op_cpu_info.pm_nclass; n++) 1476 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n], 1477 sizeof(cpu_info.pm_classes[n])); 1478 1479 pmc_class_table = calloc(PMC_CLASS_TABLE_SIZE, 1480 sizeof(struct pmc_class_descr *)); 1481 1482 if (pmc_class_table == NULL) 1483 return (-1); 1484 1485 /* 1486 * Get soft events list. 1487 */ 1488 soft_event_info.pm_class = PMC_CLASS_SOFT; 1489 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0) 1490 return (pmc_syscall = -1); 1491 1492 /* Map soft events to static list. */ 1493 for (n = 0; n < soft_event_info.pm_nevent; n++) { 1494 soft_event_table[n].pm_ev_name = 1495 soft_event_info.pm_events[n].pm_ev_name; 1496 soft_event_table[n].pm_ev_code = 1497 soft_event_info.pm_events[n].pm_ev_code; 1498 } 1499 soft_class_table_descr.pm_evc_event_table_size = \ 1500 soft_event_info.pm_nevent; 1501 soft_class_table_descr.pm_evc_event_table = \ 1502 soft_event_table; 1503 1504 /* 1505 * Fill in the class table. 1506 */ 1507 n = 0; 1508 for (unsigned i = 0; i < PMC_CLASS_TABLE_SIZE; i++) { 1509 switch (cpu_info.pm_classes[i].pm_class) { 1510 #if defined(__amd64__) || defined(__i386__) 1511 case PMC_CLASS_TSC: 1512 pmc_class_table[n++] = &tsc_class_table_descr; 1513 break; 1514 1515 case PMC_CLASS_K8: 1516 pmc_class_table[n++] = &k8_class_table_descr; 1517 break; 1518 1519 case PMC_CLASS_IBS: 1520 pmc_class_table[n++] = &ibs_class_table_descr; 1521 break; 1522 #endif 1523 1524 case PMC_CLASS_SOFT: 1525 pmc_class_table[n++] = &soft_class_table_descr; 1526 break; 1527 1528 #if defined(__arm__) 1529 case PMC_CLASS_ARMV7: 1530 switch (cpu_info.pm_cputype) { 1531 case PMC_CPU_ARMV7_CORTEX_A8: 1532 pmc_class_table[n++] = 1533 &cortex_a8_class_table_descr; 1534 break; 1535 case PMC_CPU_ARMV7_CORTEX_A9: 1536 pmc_class_table[n++] = 1537 &cortex_a9_class_table_descr; 1538 break; 1539 default: 1540 errno = ENXIO; 1541 return (pmc_syscall = -1); 1542 } 1543 break; 1544 #endif 1545 1546 #if defined(__aarch64__) 1547 case PMC_CLASS_ARMV8: 1548 switch (cpu_info.pm_cputype) { 1549 case PMC_CPU_ARMV8_CORTEX_A53: 1550 pmc_class_table[n++] = 1551 &cortex_a53_class_table_descr; 1552 break; 1553 case PMC_CPU_ARMV8_CORTEX_A57: 1554 pmc_class_table[n++] = 1555 &cortex_a57_class_table_descr; 1556 break; 1557 case PMC_CPU_ARMV8_CORTEX_A76: 1558 pmc_class_table[n++] = 1559 &cortex_a76_class_table_descr; 1560 break; 1561 default: 1562 errno = ENXIO; 1563 return (pmc_syscall = -1); 1564 } 1565 break; 1566 1567 case PMC_CLASS_DMC620_PMU_CD2: 1568 pmc_class_table[n++] = 1569 &dmc620_pmu_cd2_class_table_descr; 1570 break; 1571 1572 case PMC_CLASS_DMC620_PMU_C: 1573 pmc_class_table[n++] = &dmc620_pmu_c_class_table_descr; 1574 break; 1575 1576 case PMC_CLASS_CMN600_PMU: 1577 pmc_class_table[n++] = &cmn600_pmu_class_table_descr; 1578 break; 1579 #endif 1580 1581 #if defined(__powerpc__) 1582 case PMC_CLASS_PPC7450: 1583 pmc_class_table[n++] = &ppc7450_class_table_descr; 1584 break; 1585 1586 case PMC_CLASS_PPC970: 1587 pmc_class_table[n++] = &ppc970_class_table_descr; 1588 break; 1589 1590 case PMC_CLASS_E500: 1591 pmc_class_table[n++] = &e500_class_table_descr; 1592 break; 1593 #endif 1594 1595 default: 1596 #if defined(DEBUG) 1597 printf("pm_class: 0x%x\n", 1598 cpu_info.pm_classes[i].pm_class); 1599 #endif 1600 break; 1601 } 1602 } 1603 1604 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases 1605 1606 /* Configure the event name parser. */ 1607 switch (cpu_info.pm_cputype) { 1608 #if defined(__amd64__) || defined(__i386__) 1609 case PMC_CPU_AMD_K8: 1610 PMC_MDEP_INIT(k8); 1611 break; 1612 #endif 1613 case PMC_CPU_GENERIC: 1614 PMC_MDEP_INIT(generic); 1615 break; 1616 #if defined(__arm__) 1617 case PMC_CPU_ARMV7_CORTEX_A8: 1618 PMC_MDEP_INIT(cortex_a8); 1619 break; 1620 case PMC_CPU_ARMV7_CORTEX_A9: 1621 PMC_MDEP_INIT(cortex_a9); 1622 break; 1623 #endif 1624 #if defined(__aarch64__) 1625 case PMC_CPU_ARMV8_CORTEX_A53: 1626 PMC_MDEP_INIT(cortex_a53); 1627 break; 1628 case PMC_CPU_ARMV8_CORTEX_A57: 1629 PMC_MDEP_INIT(cortex_a57); 1630 break; 1631 case PMC_CPU_ARMV8_CORTEX_A76: 1632 PMC_MDEP_INIT(cortex_a76); 1633 break; 1634 #endif 1635 #if defined(__powerpc__) 1636 case PMC_CPU_PPC_7450: 1637 PMC_MDEP_INIT(ppc7450); 1638 break; 1639 case PMC_CPU_PPC_970: 1640 PMC_MDEP_INIT(ppc970); 1641 break; 1642 case PMC_CPU_PPC_E500: 1643 PMC_MDEP_INIT(e500); 1644 break; 1645 #endif 1646 default: 1647 /* 1648 * Some kind of CPU this version of the library knows nothing 1649 * about. This shouldn't happen since the abi version check 1650 * should have caught this. 1651 */ 1652 #if defined(__amd64__) || defined(__i386__) || defined(__powerpc64__) 1653 break; 1654 #endif 1655 errno = ENXIO; 1656 return (pmc_syscall = -1); 1657 } 1658 1659 return (0); 1660 } 1661 1662 const char * 1663 pmc_name_of_capability(enum pmc_caps cap) 1664 { 1665 int i; 1666 1667 /* 1668 * 'cap' should have a single bit set and should be in 1669 * range. 1670 */ 1671 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 1672 cap > PMC_CAP_LAST) { 1673 errno = EINVAL; 1674 return (NULL); 1675 } 1676 1677 i = ffs(cap); 1678 return (pmc_capability_names[i - 1]); 1679 } 1680 1681 const char * 1682 pmc_name_of_class(enum pmc_class pc) 1683 { 1684 size_t n; 1685 1686 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++) 1687 if (pc == pmc_class_names[n].pm_class) 1688 return (pmc_class_names[n].pm_name); 1689 1690 errno = EINVAL; 1691 return (NULL); 1692 } 1693 1694 const char * 1695 pmc_name_of_cputype(enum pmc_cputype cp) 1696 { 1697 size_t n; 1698 1699 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 1700 if (cp == pmc_cputype_names[n].pm_cputype) 1701 return (pmc_cputype_names[n].pm_name); 1702 1703 errno = EINVAL; 1704 return (NULL); 1705 } 1706 1707 const char * 1708 pmc_name_of_disposition(enum pmc_disp pd) 1709 { 1710 if ((int) pd >= PMC_DISP_FIRST && 1711 pd <= PMC_DISP_LAST) 1712 return (pmc_disposition_names[pd]); 1713 1714 errno = EINVAL; 1715 return (NULL); 1716 } 1717 1718 const char * 1719 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 1720 { 1721 const struct pmc_event_descr *ev, *evfence; 1722 1723 ev = evfence = NULL; 1724 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 1725 ev = k8_event_table; 1726 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 1727 } else if (pe >= PMC_EV_IBS_FIRST && pe <= PMC_EV_IBS_LAST) { 1728 ev = ibs_event_table; 1729 evfence = ibs_event_table + PMC_EVENT_TABLE_SIZE(ibs); 1730 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 1731 switch (cpu) { 1732 case PMC_CPU_ARMV7_CORTEX_A8: 1733 ev = cortex_a8_event_table; 1734 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8); 1735 break; 1736 case PMC_CPU_ARMV7_CORTEX_A9: 1737 ev = cortex_a9_event_table; 1738 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9); 1739 break; 1740 default: /* Unknown CPU type. */ 1741 break; 1742 } 1743 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { 1744 switch (cpu) { 1745 case PMC_CPU_ARMV8_CORTEX_A53: 1746 ev = cortex_a53_event_table; 1747 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); 1748 break; 1749 case PMC_CPU_ARMV8_CORTEX_A57: 1750 ev = cortex_a57_event_table; 1751 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); 1752 break; 1753 case PMC_CPU_ARMV8_CORTEX_A76: 1754 ev = cortex_a76_event_table; 1755 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76); 1756 break; 1757 default: /* Unknown CPU type. */ 1758 break; 1759 } 1760 } else if (pe >= PMC_EV_CMN600_PMU_FIRST && 1761 pe <= PMC_EV_CMN600_PMU_LAST) { 1762 ev = cmn600_pmu_event_table; 1763 evfence = cmn600_pmu_event_table + 1764 PMC_EVENT_TABLE_SIZE(cmn600_pmu); 1765 } else if (pe >= PMC_EV_DMC620_PMU_CD2_FIRST && 1766 pe <= PMC_EV_DMC620_PMU_CD2_LAST) { 1767 ev = dmc620_pmu_cd2_event_table; 1768 evfence = dmc620_pmu_cd2_event_table + 1769 PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2); 1770 } else if (pe >= PMC_EV_DMC620_PMU_C_FIRST && 1771 pe <= PMC_EV_DMC620_PMU_C_LAST) { 1772 ev = dmc620_pmu_c_event_table; 1773 evfence = dmc620_pmu_c_event_table + 1774 PMC_EVENT_TABLE_SIZE(dmc620_pmu_c); 1775 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 1776 ev = ppc7450_event_table; 1777 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 1778 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 1779 ev = ppc970_event_table; 1780 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 1781 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { 1782 ev = e500_event_table; 1783 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); 1784 } else if (pe == PMC_EV_TSC_TSC) { 1785 ev = tsc_event_table; 1786 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 1787 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 1788 ev = soft_event_table; 1789 evfence = soft_event_table + soft_event_info.pm_nevent; 1790 } 1791 1792 for (; ev != evfence; ev++) 1793 if (pe == ev->pm_ev_code) 1794 return (ev->pm_ev_name); 1795 1796 return (NULL); 1797 } 1798 1799 const char * 1800 pmc_name_of_event(enum pmc_event pe) 1801 { 1802 const char *n; 1803 1804 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 1805 return (n); 1806 1807 errno = EINVAL; 1808 return (NULL); 1809 } 1810 1811 const char * 1812 pmc_name_of_mode(enum pmc_mode pm) 1813 { 1814 if ((int) pm >= PMC_MODE_FIRST && 1815 pm <= PMC_MODE_LAST) 1816 return (pmc_mode_names[pm]); 1817 1818 errno = EINVAL; 1819 return (NULL); 1820 } 1821 1822 const char * 1823 pmc_name_of_state(enum pmc_state ps) 1824 { 1825 if ((int) ps >= PMC_STATE_FIRST && 1826 ps <= PMC_STATE_LAST) 1827 return (pmc_state_names[ps]); 1828 1829 errno = EINVAL; 1830 return (NULL); 1831 } 1832 1833 int 1834 pmc_ncpu(void) 1835 { 1836 if (pmc_syscall == -1) { 1837 errno = ENXIO; 1838 return (-1); 1839 } 1840 1841 return (cpu_info.pm_ncpu); 1842 } 1843 1844 int 1845 pmc_npmc(int cpu) 1846 { 1847 if (pmc_syscall == -1) { 1848 errno = ENXIO; 1849 return (-1); 1850 } 1851 1852 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 1853 errno = EINVAL; 1854 return (-1); 1855 } 1856 1857 return (cpu_info.pm_npmc); 1858 } 1859 1860 int 1861 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 1862 { 1863 int nbytes, npmc; 1864 struct pmc_op_getpmcinfo *pmci; 1865 1866 if ((npmc = pmc_npmc(cpu)) < 0) 1867 return (-1); 1868 1869 nbytes = sizeof(struct pmc_op_getpmcinfo) + 1870 npmc * sizeof(struct pmc_info); 1871 1872 if ((pmci = calloc(1, nbytes)) == NULL) 1873 return (-1); 1874 1875 pmci->pm_cpu = cpu; 1876 1877 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) { 1878 free(pmci); 1879 return (-1); 1880 } 1881 1882 /* kernel<->library, library<->userland interfaces are identical */ 1883 *ppmci = (struct pmc_pmcinfo *) pmci; 1884 return (0); 1885 } 1886 1887 int 1888 pmc_read(pmc_id_t pmc, pmc_value_t *value) 1889 { 1890 struct pmc_op_pmcrw pmc_read_op; 1891 1892 pmc_read_op.pm_pmcid = pmc; 1893 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 1894 pmc_read_op.pm_value = -1; 1895 1896 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0) 1897 return (-1); 1898 1899 *value = pmc_read_op.pm_value; 1900 return (0); 1901 } 1902 1903 int 1904 pmc_release(pmc_id_t pmc) 1905 { 1906 struct pmc_op_simple pmc_release_args; 1907 1908 pmc_release_args.pm_pmcid = pmc; 1909 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args)); 1910 } 1911 1912 int 1913 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 1914 { 1915 struct pmc_op_pmcrw pmc_rw_op; 1916 1917 pmc_rw_op.pm_pmcid = pmc; 1918 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 1919 pmc_rw_op.pm_value = newvalue; 1920 1921 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0) 1922 return (-1); 1923 1924 *oldvaluep = pmc_rw_op.pm_value; 1925 return (0); 1926 } 1927 1928 int 1929 pmc_set(pmc_id_t pmc, pmc_value_t value) 1930 { 1931 struct pmc_op_pmcsetcount sc; 1932 1933 sc.pm_pmcid = pmc; 1934 sc.pm_count = value; 1935 1936 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0) 1937 return (-1); 1938 return (0); 1939 } 1940 1941 int 1942 pmc_start(pmc_id_t pmc) 1943 { 1944 struct pmc_op_simple pmc_start_args; 1945 1946 pmc_start_args.pm_pmcid = pmc; 1947 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args)); 1948 } 1949 1950 int 1951 pmc_stop(pmc_id_t pmc) 1952 { 1953 struct pmc_op_simple pmc_stop_args; 1954 1955 pmc_stop_args.pm_pmcid = pmc; 1956 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args)); 1957 } 1958 1959 int 1960 pmc_width(pmc_id_t pmcid, uint32_t *width) 1961 { 1962 unsigned int i; 1963 enum pmc_class cl; 1964 1965 cl = PMC_ID_TO_CLASS(pmcid); 1966 for (i = 0; i < cpu_info.pm_nclass; i++) 1967 if (cpu_info.pm_classes[i].pm_class == cl) { 1968 *width = cpu_info.pm_classes[i].pm_width; 1969 return (0); 1970 } 1971 errno = EINVAL; 1972 return (-1); 1973 } 1974 1975 int 1976 pmc_write(pmc_id_t pmc, pmc_value_t value) 1977 { 1978 struct pmc_op_pmcrw pmc_write_op; 1979 1980 pmc_write_op.pm_pmcid = pmc; 1981 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 1982 pmc_write_op.pm_value = value; 1983 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op)); 1984 } 1985 1986 int 1987 pmc_writelog(uint32_t userdata) 1988 { 1989 struct pmc_op_writelog wl; 1990 1991 wl.pm_userdata = userdata; 1992 return (PMC_CALL(PMC_OP_WRITELOG, &wl)); 1993 } 1994