1 /*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/pmc.h> 34 #include <sys/syscall.h> 35 36 #include <ctype.h> 37 #include <errno.h> 38 #include <fcntl.h> 39 #include <pmc.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <unistd.h> 45 46 #include "libpmcinternal.h" 47 48 /* Function prototypes */ 49 #if defined(__i386__) 50 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 51 struct pmc_op_pmcallocate *_pmc_config); 52 #endif 53 #if defined(__amd64__) || defined(__i386__) 54 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 57 struct pmc_op_pmcallocate *_pmc_config); 58 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 61 struct pmc_op_pmcallocate *_pmc_config); 62 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 63 struct pmc_op_pmcallocate *_pmc_config); 64 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 65 struct pmc_op_pmcallocate *_pmc_config); 66 #endif 67 #if defined(__i386__) 68 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 69 struct pmc_op_pmcallocate *_pmc_config); 70 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72 #endif 73 #if defined(__amd64__) || defined(__i386__) 74 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 #endif 77 #if defined(__XSCALE__) 78 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 79 struct pmc_op_pmcallocate *_pmc_config); 80 #endif 81 #if defined(__mips__) 82 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84 #endif /* __mips__ */ 85 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 86 struct pmc_op_pmcallocate *_pmc_config); 87 88 #if defined(__powerpc__) 89 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 90 struct pmc_op_pmcallocate *_pmc_config); 91 #endif /* __powerpc__ */ 92 93 #define PMC_CALL(cmd, params) \ 94 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 95 96 /* 97 * Event aliases provide a way for the user to ask for generic events 98 * like "cache-misses", or "instructions-retired". These aliases are 99 * mapped to the appropriate canonical event descriptions using a 100 * lookup table. 101 */ 102 struct pmc_event_alias { 103 const char *pm_alias; 104 const char *pm_spec; 105 }; 106 107 static const struct pmc_event_alias *pmc_mdep_event_aliases; 108 109 /* 110 * The pmc_event_descr structure maps symbolic names known to the user 111 * to integer codes used by the PMC KLD. 112 */ 113 struct pmc_event_descr { 114 const char *pm_ev_name; 115 enum pmc_event pm_ev_code; 116 }; 117 118 /* 119 * The pmc_class_descr structure maps class name prefixes for 120 * event names to event tables and other PMC class data. 121 */ 122 struct pmc_class_descr { 123 const char *pm_evc_name; 124 size_t pm_evc_name_size; 125 enum pmc_class pm_evc_class; 126 const struct pmc_event_descr *pm_evc_event_table; 127 size_t pm_evc_event_table_size; 128 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 129 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 130 }; 131 132 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 133 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 134 135 #undef __PMC_EV 136 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 137 138 /* 139 * PMC_CLASSDEP_TABLE(NAME, CLASS) 140 * 141 * Define a table mapping event names and aliases to HWPMC event IDs. 142 */ 143 #define PMC_CLASSDEP_TABLE(N, C) \ 144 static const struct pmc_event_descr N##_event_table[] = \ 145 { \ 146 __PMC_EV_##C() \ 147 } 148 149 PMC_CLASSDEP_TABLE(iaf, IAF); 150 PMC_CLASSDEP_TABLE(k7, K7); 151 PMC_CLASSDEP_TABLE(k8, K8); 152 PMC_CLASSDEP_TABLE(p4, P4); 153 PMC_CLASSDEP_TABLE(p5, P5); 154 PMC_CLASSDEP_TABLE(p6, P6); 155 PMC_CLASSDEP_TABLE(xscale, XSCALE); 156 PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 157 PMC_CLASSDEP_TABLE(octeon, OCTEON); 158 PMC_CLASSDEP_TABLE(ucf, UCF); 159 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 160 PMC_CLASSDEP_TABLE(ppc970, PPC970); 161 162 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 163 164 #undef __PMC_EV_ALIAS 165 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 166 167 static const struct pmc_event_descr atom_event_table[] = 168 { 169 __PMC_EV_ALIAS_ATOM() 170 }; 171 172 static const struct pmc_event_descr atom_silvermont_event_table[] = 173 { 174 __PMC_EV_ALIAS_ATOM_SILVERMONT() 175 }; 176 177 static const struct pmc_event_descr core_event_table[] = 178 { 179 __PMC_EV_ALIAS_CORE() 180 }; 181 182 183 static const struct pmc_event_descr core2_event_table[] = 184 { 185 __PMC_EV_ALIAS_CORE2() 186 }; 187 188 static const struct pmc_event_descr corei7_event_table[] = 189 { 190 __PMC_EV_ALIAS_COREI7() 191 }; 192 193 static const struct pmc_event_descr nehalem_ex_event_table[] = 194 { 195 __PMC_EV_ALIAS_COREI7() 196 }; 197 198 static const struct pmc_event_descr haswell_event_table[] = 199 { 200 __PMC_EV_ALIAS_HASWELL() 201 }; 202 203 static const struct pmc_event_descr ivybridge_event_table[] = 204 { 205 __PMC_EV_ALIAS_IVYBRIDGE() 206 }; 207 208 static const struct pmc_event_descr ivybridge_xeon_event_table[] = 209 { 210 __PMC_EV_ALIAS_IVYBRIDGE_XEON() 211 }; 212 213 static const struct pmc_event_descr sandybridge_event_table[] = 214 { 215 __PMC_EV_ALIAS_SANDYBRIDGE() 216 }; 217 218 static const struct pmc_event_descr sandybridge_xeon_event_table[] = 219 { 220 __PMC_EV_ALIAS_SANDYBRIDGE_XEON() 221 }; 222 223 static const struct pmc_event_descr westmere_event_table[] = 224 { 225 __PMC_EV_ALIAS_WESTMERE() 226 }; 227 228 static const struct pmc_event_descr westmere_ex_event_table[] = 229 { 230 __PMC_EV_ALIAS_WESTMERE() 231 }; 232 233 static const struct pmc_event_descr corei7uc_event_table[] = 234 { 235 __PMC_EV_ALIAS_COREI7UC() 236 }; 237 238 static const struct pmc_event_descr haswelluc_event_table[] = 239 { 240 __PMC_EV_ALIAS_HASWELLUC() 241 }; 242 243 static const struct pmc_event_descr sandybridgeuc_event_table[] = 244 { 245 __PMC_EV_ALIAS_SANDYBRIDGEUC() 246 }; 247 248 static const struct pmc_event_descr westmereuc_event_table[] = 249 { 250 __PMC_EV_ALIAS_WESTMEREUC() 251 }; 252 253 /* 254 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 255 * 256 * Map a CPU to the PMC classes it supports. 257 */ 258 #define PMC_MDEP_TABLE(N,C,...) \ 259 static const enum pmc_class N##_pmc_classes[] = { \ 260 PMC_CLASS_##C, __VA_ARGS__ \ 261 } 262 263 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 264 PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 265 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); 266 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 267 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 268 PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 269 PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 270 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 271 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 272 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 273 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 274 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 275 PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 276 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); 277 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 278 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); 279 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); 280 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); 281 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 282 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 283 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 284 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450); 285 PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970); 286 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 287 288 static const struct pmc_event_descr tsc_event_table[] = 289 { 290 __PMC_EV_TSC() 291 }; 292 293 #undef PMC_CLASS_TABLE_DESC 294 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 295 static const struct pmc_class_descr NAME##_class_table_descr = \ 296 { \ 297 .pm_evc_name = #CLASS "-", \ 298 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 299 .pm_evc_class = PMC_CLASS_##CLASS , \ 300 .pm_evc_event_table = EVENTS##_event_table , \ 301 .pm_evc_event_table_size = \ 302 PMC_EVENT_TABLE_SIZE(EVENTS), \ 303 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 304 } 305 306 #if defined(__i386__) || defined(__amd64__) 307 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 308 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 309 PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); 310 PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 311 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 312 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 313 PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); 314 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); 315 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); 316 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); 317 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 318 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); 319 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 320 PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); 321 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 322 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 323 PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); 324 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 325 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 326 #endif 327 #if defined(__i386__) 328 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 329 #endif 330 #if defined(__i386__) || defined(__amd64__) 331 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 332 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 333 #endif 334 #if defined(__i386__) 335 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 336 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 337 #endif 338 #if defined(__i386__) || defined(__amd64__) 339 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 340 #endif 341 #if defined(__XSCALE__) 342 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 343 #endif 344 #if defined(__mips__) 345 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 346 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 347 #endif /* __mips__ */ 348 #if defined(__powerpc__) 349 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 350 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 351 #endif 352 353 static struct pmc_class_descr soft_class_table_descr = 354 { 355 .pm_evc_name = "SOFT-", 356 .pm_evc_name_size = sizeof("SOFT-") - 1, 357 .pm_evc_class = PMC_CLASS_SOFT, 358 .pm_evc_event_table = NULL, 359 .pm_evc_event_table_size = 0, 360 .pm_evc_allocate_pmc = soft_allocate_pmc 361 }; 362 363 #undef PMC_CLASS_TABLE_DESC 364 365 static const struct pmc_class_descr **pmc_class_table; 366 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 367 368 static const enum pmc_class *pmc_mdep_class_list; 369 static size_t pmc_mdep_class_list_size; 370 371 /* 372 * Mapping tables, mapping enumeration values to human readable 373 * strings. 374 */ 375 376 static const char * pmc_capability_names[] = { 377 #undef __PMC_CAP 378 #define __PMC_CAP(N,V,D) #N , 379 __PMC_CAPS() 380 }; 381 382 static const char * pmc_class_names[] = { 383 #undef __PMC_CLASS 384 #define __PMC_CLASS(C) #C , 385 __PMC_CLASSES() 386 }; 387 388 struct pmc_cputype_map { 389 enum pmc_cputype pm_cputype; 390 const char *pm_name; 391 }; 392 393 static const struct pmc_cputype_map pmc_cputype_names[] = { 394 #undef __PMC_CPU 395 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 396 __PMC_CPUS() 397 }; 398 399 static const char * pmc_disposition_names[] = { 400 #undef __PMC_DISP 401 #define __PMC_DISP(D) #D , 402 __PMC_DISPOSITIONS() 403 }; 404 405 static const char * pmc_mode_names[] = { 406 #undef __PMC_MODE 407 #define __PMC_MODE(M,N) #M , 408 __PMC_MODES() 409 }; 410 411 static const char * pmc_state_names[] = { 412 #undef __PMC_STATE 413 #define __PMC_STATE(S) #S , 414 __PMC_STATES() 415 }; 416 417 /* 418 * Filled in by pmc_init(). 419 */ 420 static int pmc_syscall = -1; 421 static struct pmc_cpuinfo cpu_info; 422 static struct pmc_op_getdyneventinfo soft_event_info; 423 424 /* Event masks for events */ 425 struct pmc_masks { 426 const char *pm_name; 427 const uint64_t pm_value; 428 }; 429 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 430 #define NULLMASK { .pm_name = NULL } 431 432 #if defined(__amd64__) || defined(__i386__) 433 static int 434 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 435 { 436 const struct pmc_masks *pm; 437 char *q, *r; 438 int c; 439 440 if (pmask == NULL) /* no mask keywords */ 441 return (-1); 442 q = strchr(p, '='); /* skip '=' */ 443 if (*++q == '\0') /* no more data */ 444 return (-1); 445 c = 0; /* count of mask keywords seen */ 446 while ((r = strsep(&q, "+")) != NULL) { 447 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 448 pm++) 449 ; 450 if (pm->pm_name == NULL) /* not found */ 451 return (-1); 452 *evmask |= pm->pm_value; 453 c++; 454 } 455 return (c); 456 } 457 #endif 458 459 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 460 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 461 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 462 463 #if defined(__i386__) 464 465 /* 466 * AMD K7 (Athlon) CPUs. 467 */ 468 469 static struct pmc_event_alias k7_aliases[] = { 470 EV_ALIAS("branches", "k7-retired-branches"), 471 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 472 EV_ALIAS("cycles", "tsc"), 473 EV_ALIAS("dc-misses", "k7-dc-misses"), 474 EV_ALIAS("ic-misses", "k7-ic-misses"), 475 EV_ALIAS("instructions", "k7-retired-instructions"), 476 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 477 EV_ALIAS(NULL, NULL) 478 }; 479 480 #define K7_KW_COUNT "count" 481 #define K7_KW_EDGE "edge" 482 #define K7_KW_INV "inv" 483 #define K7_KW_OS "os" 484 #define K7_KW_UNITMASK "unitmask" 485 #define K7_KW_USR "usr" 486 487 static int 488 k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 489 struct pmc_op_pmcallocate *pmc_config) 490 { 491 char *e, *p, *q; 492 int c, has_unitmask; 493 uint32_t count, unitmask; 494 495 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 496 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 497 498 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 499 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 500 pe == PMC_EV_K7_DC_WRITEBACKS) { 501 has_unitmask = 1; 502 unitmask = AMD_PMC_UNITMASK_MOESI; 503 } else 504 unitmask = has_unitmask = 0; 505 506 while ((p = strsep(&ctrspec, ",")) != NULL) { 507 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 508 q = strchr(p, '='); 509 if (*++q == '\0') /* skip '=' */ 510 return (-1); 511 512 count = strtol(q, &e, 0); 513 if (e == q || *e != '\0') 514 return (-1); 515 516 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 517 pmc_config->pm_md.pm_amd.pm_amd_config |= 518 AMD_PMC_TO_COUNTER(count); 519 520 } else if (KWMATCH(p, K7_KW_EDGE)) { 521 pmc_config->pm_caps |= PMC_CAP_EDGE; 522 } else if (KWMATCH(p, K7_KW_INV)) { 523 pmc_config->pm_caps |= PMC_CAP_INVERT; 524 } else if (KWMATCH(p, K7_KW_OS)) { 525 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 526 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 527 if (has_unitmask == 0) 528 return (-1); 529 unitmask = 0; 530 q = strchr(p, '='); 531 if (*++q == '\0') /* skip '=' */ 532 return (-1); 533 534 while ((c = tolower(*q++)) != 0) 535 if (c == 'm') 536 unitmask |= AMD_PMC_UNITMASK_M; 537 else if (c == 'o') 538 unitmask |= AMD_PMC_UNITMASK_O; 539 else if (c == 'e') 540 unitmask |= AMD_PMC_UNITMASK_E; 541 else if (c == 's') 542 unitmask |= AMD_PMC_UNITMASK_S; 543 else if (c == 'i') 544 unitmask |= AMD_PMC_UNITMASK_I; 545 else if (c == '+') 546 continue; 547 else 548 return (-1); 549 550 if (unitmask == 0) 551 return (-1); 552 553 } else if (KWMATCH(p, K7_KW_USR)) { 554 pmc_config->pm_caps |= PMC_CAP_USER; 555 } else 556 return (-1); 557 } 558 559 if (has_unitmask) { 560 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 561 pmc_config->pm_md.pm_amd.pm_amd_config |= 562 AMD_PMC_TO_UNITMASK(unitmask); 563 } 564 565 return (0); 566 567 } 568 569 #endif 570 571 #if defined(__amd64__) || defined(__i386__) 572 573 /* 574 * Intel Core (Family 6, Model E) PMCs. 575 */ 576 577 static struct pmc_event_alias core_aliases[] = { 578 EV_ALIAS("branches", "iap-br-instr-ret"), 579 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 580 EV_ALIAS("cycles", "tsc-tsc"), 581 EV_ALIAS("ic-misses", "iap-icache-misses"), 582 EV_ALIAS("instructions", "iap-instr-ret"), 583 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 584 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 585 EV_ALIAS(NULL, NULL) 586 }; 587 588 /* 589 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 590 * and Atom (Family 6, model 1CH) PMCs. 591 * 592 * We map aliases to events on the fixed-function counters if these 593 * are present. Note that not all CPUs in this family contain fixed-function 594 * counters. 595 */ 596 597 static struct pmc_event_alias core2_aliases[] = { 598 EV_ALIAS("branches", "iap-br-inst-retired.any"), 599 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 600 EV_ALIAS("cycles", "tsc-tsc"), 601 EV_ALIAS("ic-misses", "iap-l1i-misses"), 602 EV_ALIAS("instructions", "iaf-instr-retired.any"), 603 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 604 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 605 EV_ALIAS(NULL, NULL) 606 }; 607 608 static struct pmc_event_alias core2_aliases_without_iaf[] = { 609 EV_ALIAS("branches", "iap-br-inst-retired.any"), 610 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 611 EV_ALIAS("cycles", "tsc-tsc"), 612 EV_ALIAS("ic-misses", "iap-l1i-misses"), 613 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 614 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 615 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 616 EV_ALIAS(NULL, NULL) 617 }; 618 619 #define atom_aliases core2_aliases 620 #define atom_aliases_without_iaf core2_aliases_without_iaf 621 #define atom_silvermont_aliases core2_aliases 622 #define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf 623 #define corei7_aliases core2_aliases 624 #define corei7_aliases_without_iaf core2_aliases_without_iaf 625 #define nehalem_ex_aliases core2_aliases 626 #define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf 627 #define haswell_aliases core2_aliases 628 #define haswell_aliases_without_iaf core2_aliases_without_iaf 629 #define ivybridge_aliases core2_aliases 630 #define ivybridge_aliases_without_iaf core2_aliases_without_iaf 631 #define ivybridge_xeon_aliases core2_aliases 632 #define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 633 #define sandybridge_aliases core2_aliases 634 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf 635 #define sandybridge_xeon_aliases core2_aliases 636 #define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 637 #define westmere_aliases core2_aliases 638 #define westmere_aliases_without_iaf core2_aliases_without_iaf 639 #define westmere_ex_aliases core2_aliases 640 #define westmere_ex_aliases_without_iaf core2_aliases_without_iaf 641 642 #define IAF_KW_OS "os" 643 #define IAF_KW_USR "usr" 644 #define IAF_KW_ANYTHREAD "anythread" 645 646 /* 647 * Parse an event specifier for Intel fixed function counters. 648 */ 649 static int 650 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 651 struct pmc_op_pmcallocate *pmc_config) 652 { 653 char *p; 654 655 (void) pe; 656 657 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 658 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 659 660 while ((p = strsep(&ctrspec, ",")) != NULL) { 661 if (KWMATCH(p, IAF_KW_OS)) 662 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 663 else if (KWMATCH(p, IAF_KW_USR)) 664 pmc_config->pm_caps |= PMC_CAP_USER; 665 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 666 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 667 else 668 return (-1); 669 } 670 671 return (0); 672 } 673 674 /* 675 * Core/Core2 support. 676 */ 677 678 #define IAP_KW_AGENT "agent" 679 #define IAP_KW_ANYTHREAD "anythread" 680 #define IAP_KW_CACHESTATE "cachestate" 681 #define IAP_KW_CMASK "cmask" 682 #define IAP_KW_CORE "core" 683 #define IAP_KW_EDGE "edge" 684 #define IAP_KW_INV "inv" 685 #define IAP_KW_OS "os" 686 #define IAP_KW_PREFETCH "prefetch" 687 #define IAP_KW_SNOOPRESPONSE "snoopresponse" 688 #define IAP_KW_SNOOPTYPE "snooptype" 689 #define IAP_KW_TRANSITION "trans" 690 #define IAP_KW_USR "usr" 691 #define IAP_KW_RSP "rsp" 692 693 static struct pmc_masks iap_core_mask[] = { 694 PMCMASK(all, (0x3 << 14)), 695 PMCMASK(this, (0x1 << 14)), 696 NULLMASK 697 }; 698 699 static struct pmc_masks iap_agent_mask[] = { 700 PMCMASK(this, 0), 701 PMCMASK(any, (0x1 << 13)), 702 NULLMASK 703 }; 704 705 static struct pmc_masks iap_prefetch_mask[] = { 706 PMCMASK(both, (0x3 << 12)), 707 PMCMASK(only, (0x1 << 12)), 708 PMCMASK(exclude, 0), 709 NULLMASK 710 }; 711 712 static struct pmc_masks iap_cachestate_mask[] = { 713 PMCMASK(i, (1 << 8)), 714 PMCMASK(s, (1 << 9)), 715 PMCMASK(e, (1 << 10)), 716 PMCMASK(m, (1 << 11)), 717 NULLMASK 718 }; 719 720 static struct pmc_masks iap_snoopresponse_mask[] = { 721 PMCMASK(clean, (1 << 8)), 722 PMCMASK(hit, (1 << 9)), 723 PMCMASK(hitm, (1 << 11)), 724 NULLMASK 725 }; 726 727 static struct pmc_masks iap_snooptype_mask[] = { 728 PMCMASK(cmp2s, (1 << 8)), 729 PMCMASK(cmp2i, (1 << 9)), 730 NULLMASK 731 }; 732 733 static struct pmc_masks iap_transition_mask[] = { 734 PMCMASK(any, 0x00), 735 PMCMASK(frequency, 0x10), 736 NULLMASK 737 }; 738 739 static struct pmc_masks iap_rsp_mask_i7_wm[] = { 740 PMCMASK(DMND_DATA_RD, (1 << 0)), 741 PMCMASK(DMND_RFO, (1 << 1)), 742 PMCMASK(DMND_IFETCH, (1 << 2)), 743 PMCMASK(WB, (1 << 3)), 744 PMCMASK(PF_DATA_RD, (1 << 4)), 745 PMCMASK(PF_RFO, (1 << 5)), 746 PMCMASK(PF_IFETCH, (1 << 6)), 747 PMCMASK(OTHER, (1 << 7)), 748 PMCMASK(UNCORE_HIT, (1 << 8)), 749 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 750 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 751 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 752 PMCMASK(REMOTE_DRAM, (1 << 13)), 753 PMCMASK(LOCAL_DRAM, (1 << 14)), 754 PMCMASK(NON_DRAM, (1 << 15)), 755 NULLMASK 756 }; 757 758 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { 759 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 760 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 761 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 762 PMCMASK(REQ_WB, (1ULL << 3)), 763 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 764 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 765 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 766 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), 767 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), 768 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), 769 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), 770 PMCMASK(REQ_STRM_ST, (1ULL << 11)), 771 PMCMASK(REQ_OTHER, (1ULL << 15)), 772 PMCMASK(RES_ANY, (1ULL << 16)), 773 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 774 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 775 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 776 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 777 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 778 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 779 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 780 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 781 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 782 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 783 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 784 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 785 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 786 NULLMASK 787 }; 788 789 static struct pmc_masks iap_rsp_mask_haswell[] = { 790 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 791 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 792 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 793 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 794 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 795 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 796 PMCMASK(REQ_OTHER, (1ULL << 15)), 797 PMCMASK(RES_ANY, (1ULL << 16)), 798 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 799 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 800 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 801 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 802 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 803 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 804 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 805 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 806 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 807 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 808 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 809 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 810 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 811 NULLMASK 812 }; 813 814 static int 815 iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 816 struct pmc_op_pmcallocate *pmc_config) 817 { 818 char *e, *p, *q; 819 uint64_t cachestate, evmask, rsp; 820 int count, n; 821 822 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 823 PMC_CAP_QUALIFIER); 824 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 825 826 cachestate = evmask = rsp = 0; 827 828 /* Parse additional modifiers if present */ 829 while ((p = strsep(&ctrspec, ",")) != NULL) { 830 831 n = 0; 832 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 833 q = strchr(p, '='); 834 if (*++q == '\0') /* skip '=' */ 835 return (-1); 836 count = strtol(q, &e, 0); 837 if (e == q || *e != '\0') 838 return (-1); 839 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 840 pmc_config->pm_md.pm_iap.pm_iap_config |= 841 IAP_CMASK(count); 842 } else if (KWMATCH(p, IAP_KW_EDGE)) { 843 pmc_config->pm_caps |= PMC_CAP_EDGE; 844 } else if (KWMATCH(p, IAP_KW_INV)) { 845 pmc_config->pm_caps |= PMC_CAP_INVERT; 846 } else if (KWMATCH(p, IAP_KW_OS)) { 847 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 848 } else if (KWMATCH(p, IAP_KW_USR)) { 849 pmc_config->pm_caps |= PMC_CAP_USER; 850 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 851 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 852 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 853 n = pmc_parse_mask(iap_core_mask, p, &evmask); 854 if (n != 1) 855 return (-1); 856 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 857 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 858 if (n != 1) 859 return (-1); 860 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 861 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 862 if (n != 1) 863 return (-1); 864 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 865 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 866 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 867 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 868 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 869 if (n != 1) 870 return (-1); 871 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 872 cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 873 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 874 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 875 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 876 n = pmc_parse_mask(iap_snoopresponse_mask, p, 877 &evmask); 878 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 879 n = pmc_parse_mask(iap_snooptype_mask, p, 880 &evmask); 881 } else 882 return (-1); 883 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 884 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || 885 cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || 886 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { 887 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 888 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); 889 } else 890 return (-1); 891 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 892 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 893 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || 894 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { 895 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 896 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); 897 } else 898 return (-1); 899 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL) { 900 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 901 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); 902 } else 903 return (-1); 904 } else 905 return (-1); 906 907 if (n < 0) /* Parsing failed. */ 908 return (-1); 909 } 910 911 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 912 913 /* 914 * If the event requires a 'cachestate' qualifier but was not 915 * specified by the user, use a sensible default. 916 */ 917 switch (pe) { 918 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 919 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 920 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 921 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 922 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 923 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 924 case PMC_EV_IAP_EVENT_32H: /* Core */ 925 case PMC_EV_IAP_EVENT_40H: /* Core */ 926 case PMC_EV_IAP_EVENT_41H: /* Core */ 927 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 928 if (cachestate == 0) 929 cachestate = (0xF << 8); 930 break; 931 case PMC_EV_IAP_EVENT_77H: /* Atom */ 932 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 933 * Atom processor 934 */ 935 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 936 cachestate = (0xF << 8); 937 break; 938 default: 939 break; 940 } 941 942 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 943 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 944 945 return (0); 946 } 947 948 /* 949 * Intel Uncore. 950 */ 951 952 static int 953 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 954 struct pmc_op_pmcallocate *pmc_config) 955 { 956 (void) pe; 957 (void) ctrspec; 958 959 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 960 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 961 962 return (0); 963 } 964 965 #define UCP_KW_CMASK "cmask" 966 #define UCP_KW_EDGE "edge" 967 #define UCP_KW_INV "inv" 968 969 static int 970 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 971 struct pmc_op_pmcallocate *pmc_config) 972 { 973 char *e, *p, *q; 974 int count, n; 975 976 (void) pe; 977 978 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 979 PMC_CAP_QUALIFIER); 980 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 981 982 /* Parse additional modifiers if present */ 983 while ((p = strsep(&ctrspec, ",")) != NULL) { 984 985 n = 0; 986 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 987 q = strchr(p, '='); 988 if (*++q == '\0') /* skip '=' */ 989 return (-1); 990 count = strtol(q, &e, 0); 991 if (e == q || *e != '\0') 992 return (-1); 993 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 994 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 995 UCP_CMASK(count); 996 } else if (KWMATCH(p, UCP_KW_EDGE)) { 997 pmc_config->pm_caps |= PMC_CAP_EDGE; 998 } else if (KWMATCH(p, UCP_KW_INV)) { 999 pmc_config->pm_caps |= PMC_CAP_INVERT; 1000 } else 1001 return (-1); 1002 1003 if (n < 0) /* Parsing failed. */ 1004 return (-1); 1005 } 1006 1007 return (0); 1008 } 1009 1010 /* 1011 * AMD K8 PMCs. 1012 * 1013 * These are very similar to AMD K7 PMCs, but support more kinds of 1014 * events. 1015 */ 1016 1017 static struct pmc_event_alias k8_aliases[] = { 1018 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 1019 EV_ALIAS("branch-mispredicts", 1020 "k8-fr-retired-taken-branches-mispredicted"), 1021 EV_ALIAS("cycles", "tsc"), 1022 EV_ALIAS("dc-misses", "k8-dc-miss"), 1023 EV_ALIAS("ic-misses", "k8-ic-miss"), 1024 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 1025 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 1026 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 1027 EV_ALIAS(NULL, NULL) 1028 }; 1029 1030 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 1031 1032 /* 1033 * Parsing tables 1034 */ 1035 1036 /* fp dispatched fpu ops */ 1037 static const struct pmc_masks k8_mask_fdfo[] = { 1038 __K8MASK(add-pipe-excluding-junk-ops, 0), 1039 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 1040 __K8MASK(store-pipe-excluding-junk-ops, 2), 1041 __K8MASK(add-pipe-junk-ops, 3), 1042 __K8MASK(multiply-pipe-junk-ops, 4), 1043 __K8MASK(store-pipe-junk-ops, 5), 1044 NULLMASK 1045 }; 1046 1047 /* ls segment register loads */ 1048 static const struct pmc_masks k8_mask_lsrl[] = { 1049 __K8MASK(es, 0), 1050 __K8MASK(cs, 1), 1051 __K8MASK(ss, 2), 1052 __K8MASK(ds, 3), 1053 __K8MASK(fs, 4), 1054 __K8MASK(gs, 5), 1055 __K8MASK(hs, 6), 1056 NULLMASK 1057 }; 1058 1059 /* ls locked operation */ 1060 static const struct pmc_masks k8_mask_llo[] = { 1061 __K8MASK(locked-instructions, 0), 1062 __K8MASK(cycles-in-request, 1), 1063 __K8MASK(cycles-to-complete, 2), 1064 NULLMASK 1065 }; 1066 1067 /* dc refill from {l2,system} and dc copyback */ 1068 static const struct pmc_masks k8_mask_dc[] = { 1069 __K8MASK(invalid, 0), 1070 __K8MASK(shared, 1), 1071 __K8MASK(exclusive, 2), 1072 __K8MASK(owner, 3), 1073 __K8MASK(modified, 4), 1074 NULLMASK 1075 }; 1076 1077 /* dc one bit ecc error */ 1078 static const struct pmc_masks k8_mask_dobee[] = { 1079 __K8MASK(scrubber, 0), 1080 __K8MASK(piggyback, 1), 1081 NULLMASK 1082 }; 1083 1084 /* dc dispatched prefetch instructions */ 1085 static const struct pmc_masks k8_mask_ddpi[] = { 1086 __K8MASK(load, 0), 1087 __K8MASK(store, 1), 1088 __K8MASK(nta, 2), 1089 NULLMASK 1090 }; 1091 1092 /* dc dcache accesses by locks */ 1093 static const struct pmc_masks k8_mask_dabl[] = { 1094 __K8MASK(accesses, 0), 1095 __K8MASK(misses, 1), 1096 NULLMASK 1097 }; 1098 1099 /* bu internal l2 request */ 1100 static const struct pmc_masks k8_mask_bilr[] = { 1101 __K8MASK(ic-fill, 0), 1102 __K8MASK(dc-fill, 1), 1103 __K8MASK(tlb-reload, 2), 1104 __K8MASK(tag-snoop, 3), 1105 __K8MASK(cancelled, 4), 1106 NULLMASK 1107 }; 1108 1109 /* bu fill request l2 miss */ 1110 static const struct pmc_masks k8_mask_bfrlm[] = { 1111 __K8MASK(ic-fill, 0), 1112 __K8MASK(dc-fill, 1), 1113 __K8MASK(tlb-reload, 2), 1114 NULLMASK 1115 }; 1116 1117 /* bu fill into l2 */ 1118 static const struct pmc_masks k8_mask_bfil[] = { 1119 __K8MASK(dirty-l2-victim, 0), 1120 __K8MASK(victim-from-l2, 1), 1121 NULLMASK 1122 }; 1123 1124 /* fr retired fpu instructions */ 1125 static const struct pmc_masks k8_mask_frfi[] = { 1126 __K8MASK(x87, 0), 1127 __K8MASK(mmx-3dnow, 1), 1128 __K8MASK(packed-sse-sse2, 2), 1129 __K8MASK(scalar-sse-sse2, 3), 1130 NULLMASK 1131 }; 1132 1133 /* fr retired fastpath double op instructions */ 1134 static const struct pmc_masks k8_mask_frfdoi[] = { 1135 __K8MASK(low-op-pos-0, 0), 1136 __K8MASK(low-op-pos-1, 1), 1137 __K8MASK(low-op-pos-2, 2), 1138 NULLMASK 1139 }; 1140 1141 /* fr fpu exceptions */ 1142 static const struct pmc_masks k8_mask_ffe[] = { 1143 __K8MASK(x87-reclass-microfaults, 0), 1144 __K8MASK(sse-retype-microfaults, 1), 1145 __K8MASK(sse-reclass-microfaults, 2), 1146 __K8MASK(sse-and-x87-microtraps, 3), 1147 NULLMASK 1148 }; 1149 1150 /* nb memory controller page access event */ 1151 static const struct pmc_masks k8_mask_nmcpae[] = { 1152 __K8MASK(page-hit, 0), 1153 __K8MASK(page-miss, 1), 1154 __K8MASK(page-conflict, 2), 1155 NULLMASK 1156 }; 1157 1158 /* nb memory controller turnaround */ 1159 static const struct pmc_masks k8_mask_nmct[] = { 1160 __K8MASK(dimm-turnaround, 0), 1161 __K8MASK(read-to-write-turnaround, 1), 1162 __K8MASK(write-to-read-turnaround, 2), 1163 NULLMASK 1164 }; 1165 1166 /* nb memory controller bypass saturation */ 1167 static const struct pmc_masks k8_mask_nmcbs[] = { 1168 __K8MASK(memory-controller-hi-pri-bypass, 0), 1169 __K8MASK(memory-controller-lo-pri-bypass, 1), 1170 __K8MASK(dram-controller-interface-bypass, 2), 1171 __K8MASK(dram-controller-queue-bypass, 3), 1172 NULLMASK 1173 }; 1174 1175 /* nb sized commands */ 1176 static const struct pmc_masks k8_mask_nsc[] = { 1177 __K8MASK(nonpostwrszbyte, 0), 1178 __K8MASK(nonpostwrszdword, 1), 1179 __K8MASK(postwrszbyte, 2), 1180 __K8MASK(postwrszdword, 3), 1181 __K8MASK(rdszbyte, 4), 1182 __K8MASK(rdszdword, 5), 1183 __K8MASK(rdmodwr, 6), 1184 NULLMASK 1185 }; 1186 1187 /* nb probe result */ 1188 static const struct pmc_masks k8_mask_npr[] = { 1189 __K8MASK(probe-miss, 0), 1190 __K8MASK(probe-hit, 1), 1191 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1192 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1193 NULLMASK 1194 }; 1195 1196 /* nb hypertransport bus bandwidth */ 1197 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1198 __K8MASK(command, 0), 1199 __K8MASK(data, 1), 1200 __K8MASK(buffer-release, 2), 1201 __K8MASK(nop, 3), 1202 NULLMASK 1203 }; 1204 1205 #undef __K8MASK 1206 1207 #define K8_KW_COUNT "count" 1208 #define K8_KW_EDGE "edge" 1209 #define K8_KW_INV "inv" 1210 #define K8_KW_MASK "mask" 1211 #define K8_KW_OS "os" 1212 #define K8_KW_USR "usr" 1213 1214 static int 1215 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1216 struct pmc_op_pmcallocate *pmc_config) 1217 { 1218 char *e, *p, *q; 1219 int n; 1220 uint32_t count; 1221 uint64_t evmask; 1222 const struct pmc_masks *pm, *pmask; 1223 1224 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1225 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1226 1227 pmask = NULL; 1228 evmask = 0; 1229 1230 #define __K8SETMASK(M) pmask = k8_mask_##M 1231 1232 /* setup parsing tables */ 1233 switch (pe) { 1234 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1235 __K8SETMASK(fdfo); 1236 break; 1237 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1238 __K8SETMASK(lsrl); 1239 break; 1240 case PMC_EV_K8_LS_LOCKED_OPERATION: 1241 __K8SETMASK(llo); 1242 break; 1243 case PMC_EV_K8_DC_REFILL_FROM_L2: 1244 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1245 case PMC_EV_K8_DC_COPYBACK: 1246 __K8SETMASK(dc); 1247 break; 1248 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1249 __K8SETMASK(dobee); 1250 break; 1251 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1252 __K8SETMASK(ddpi); 1253 break; 1254 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1255 __K8SETMASK(dabl); 1256 break; 1257 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1258 __K8SETMASK(bilr); 1259 break; 1260 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1261 __K8SETMASK(bfrlm); 1262 break; 1263 case PMC_EV_K8_BU_FILL_INTO_L2: 1264 __K8SETMASK(bfil); 1265 break; 1266 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1267 __K8SETMASK(frfi); 1268 break; 1269 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1270 __K8SETMASK(frfdoi); 1271 break; 1272 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1273 __K8SETMASK(ffe); 1274 break; 1275 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1276 __K8SETMASK(nmcpae); 1277 break; 1278 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1279 __K8SETMASK(nmct); 1280 break; 1281 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1282 __K8SETMASK(nmcbs); 1283 break; 1284 case PMC_EV_K8_NB_SIZED_COMMANDS: 1285 __K8SETMASK(nsc); 1286 break; 1287 case PMC_EV_K8_NB_PROBE_RESULT: 1288 __K8SETMASK(npr); 1289 break; 1290 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1291 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1292 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1293 __K8SETMASK(nhbb); 1294 break; 1295 1296 default: 1297 break; /* no options defined */ 1298 } 1299 1300 while ((p = strsep(&ctrspec, ",")) != NULL) { 1301 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1302 q = strchr(p, '='); 1303 if (*++q == '\0') /* skip '=' */ 1304 return (-1); 1305 1306 count = strtol(q, &e, 0); 1307 if (e == q || *e != '\0') 1308 return (-1); 1309 1310 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1311 pmc_config->pm_md.pm_amd.pm_amd_config |= 1312 AMD_PMC_TO_COUNTER(count); 1313 1314 } else if (KWMATCH(p, K8_KW_EDGE)) { 1315 pmc_config->pm_caps |= PMC_CAP_EDGE; 1316 } else if (KWMATCH(p, K8_KW_INV)) { 1317 pmc_config->pm_caps |= PMC_CAP_INVERT; 1318 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1319 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1320 return (-1); 1321 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1322 } else if (KWMATCH(p, K8_KW_OS)) { 1323 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1324 } else if (KWMATCH(p, K8_KW_USR)) { 1325 pmc_config->pm_caps |= PMC_CAP_USER; 1326 } else 1327 return (-1); 1328 } 1329 1330 /* other post processing */ 1331 switch (pe) { 1332 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1333 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1334 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1335 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1336 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1337 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1338 /* XXX only available in rev B and later */ 1339 break; 1340 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1341 /* XXX only available in rev C and later */ 1342 break; 1343 case PMC_EV_K8_LS_LOCKED_OPERATION: 1344 /* XXX CPU Rev A,B evmask is to be zero */ 1345 if (evmask & (evmask - 1)) /* > 1 bit set */ 1346 return (-1); 1347 if (evmask == 0) { 1348 evmask = 0x01; /* Rev C and later: #instrs */ 1349 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1350 } 1351 break; 1352 default: 1353 if (evmask == 0 && pmask != NULL) { 1354 for (pm = pmask; pm->pm_name; pm++) 1355 evmask |= pm->pm_value; 1356 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1357 } 1358 } 1359 1360 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1361 pmc_config->pm_md.pm_amd.pm_amd_config = 1362 AMD_PMC_TO_UNITMASK(evmask); 1363 1364 return (0); 1365 } 1366 1367 #endif 1368 1369 #if defined(__amd64__) || defined(__i386__) 1370 1371 /* 1372 * Intel P4 PMCs 1373 */ 1374 1375 static struct pmc_event_alias p4_aliases[] = { 1376 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1377 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1378 EV_ALIAS("cycles", "tsc"), 1379 EV_ALIAS("instructions", 1380 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1381 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1382 EV_ALIAS(NULL, NULL) 1383 }; 1384 1385 #define P4_KW_ACTIVE "active" 1386 #define P4_KW_ACTIVE_ANY "any" 1387 #define P4_KW_ACTIVE_BOTH "both" 1388 #define P4_KW_ACTIVE_NONE "none" 1389 #define P4_KW_ACTIVE_SINGLE "single" 1390 #define P4_KW_BUSREQTYPE "busreqtype" 1391 #define P4_KW_CASCADE "cascade" 1392 #define P4_KW_EDGE "edge" 1393 #define P4_KW_INV "complement" 1394 #define P4_KW_OS "os" 1395 #define P4_KW_MASK "mask" 1396 #define P4_KW_PRECISE "precise" 1397 #define P4_KW_TAG "tag" 1398 #define P4_KW_THRESHOLD "threshold" 1399 #define P4_KW_USR "usr" 1400 1401 #define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1402 1403 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1404 __P4MASK(dd, 0), 1405 __P4MASK(db, 1), 1406 __P4MASK(di, 2), 1407 __P4MASK(bd, 3), 1408 __P4MASK(bb, 4), 1409 __P4MASK(bi, 5), 1410 __P4MASK(id, 6), 1411 __P4MASK(ib, 7), 1412 NULLMASK 1413 }; 1414 1415 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1416 __P4MASK(tcmiss, 0), 1417 NULLMASK, 1418 }; 1419 1420 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1421 __P4MASK(hit, 0), 1422 __P4MASK(miss, 1), 1423 __P4MASK(hit-uc, 2), 1424 NULLMASK 1425 }; 1426 1427 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1428 __P4MASK(st-rb-full, 2), 1429 __P4MASK(64k-conf, 3), 1430 NULLMASK 1431 }; 1432 1433 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1434 __P4MASK(lsc, 0), 1435 __P4MASK(ssc, 1), 1436 NULLMASK 1437 }; 1438 1439 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1440 __P4MASK(split-ld, 1), 1441 NULLMASK 1442 }; 1443 1444 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1445 __P4MASK(split-st, 1), 1446 NULLMASK 1447 }; 1448 1449 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1450 __P4MASK(no-sta, 1), 1451 __P4MASK(no-std, 3), 1452 __P4MASK(partial-data, 4), 1453 __P4MASK(unalgn-addr, 5), 1454 NULLMASK 1455 }; 1456 1457 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1458 __P4MASK(dtmiss, 0), 1459 __P4MASK(itmiss, 1), 1460 NULLMASK 1461 }; 1462 1463 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1464 __P4MASK(rd-2ndl-hits, 0), 1465 __P4MASK(rd-2ndl-hite, 1), 1466 __P4MASK(rd-2ndl-hitm, 2), 1467 __P4MASK(rd-3rdl-hits, 3), 1468 __P4MASK(rd-3rdl-hite, 4), 1469 __P4MASK(rd-3rdl-hitm, 5), 1470 __P4MASK(rd-2ndl-miss, 8), 1471 __P4MASK(rd-3rdl-miss, 9), 1472 __P4MASK(wr-2ndl-miss, 10), 1473 NULLMASK 1474 }; 1475 1476 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1477 __P4MASK(all-read, 5), 1478 __P4MASK(all-write, 6), 1479 __P4MASK(mem-uc, 7), 1480 __P4MASK(mem-wc, 8), 1481 __P4MASK(mem-wt, 9), 1482 __P4MASK(mem-wp, 10), 1483 __P4MASK(mem-wb, 11), 1484 __P4MASK(own, 13), 1485 __P4MASK(other, 14), 1486 __P4MASK(prefetch, 15), 1487 NULLMASK 1488 }; 1489 1490 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1491 __P4MASK(all-read, 5), 1492 __P4MASK(all-write, 6), 1493 __P4MASK(mem-uc, 7), 1494 __P4MASK(mem-wc, 8), 1495 __P4MASK(mem-wt, 9), 1496 __P4MASK(mem-wp, 10), 1497 __P4MASK(mem-wb, 11), 1498 __P4MASK(own, 13), 1499 __P4MASK(other, 14), 1500 __P4MASK(prefetch, 15), 1501 NULLMASK 1502 }; 1503 1504 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1505 __P4MASK(drdy-drv, 0), 1506 __P4MASK(drdy-own, 1), 1507 __P4MASK(drdy-other, 2), 1508 __P4MASK(dbsy-drv, 3), 1509 __P4MASK(dbsy-own, 4), 1510 __P4MASK(dbsy-other, 5), 1511 NULLMASK 1512 }; 1513 1514 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1515 __P4MASK(req-type0, 0), 1516 __P4MASK(req-type1, 1), 1517 __P4MASK(req-len0, 2), 1518 __P4MASK(req-len1, 3), 1519 __P4MASK(req-io-type, 5), 1520 __P4MASK(req-lock-type, 6), 1521 __P4MASK(req-cache-type, 7), 1522 __P4MASK(req-split-type, 8), 1523 __P4MASK(req-dem-type, 9), 1524 __P4MASK(req-ord-type, 10), 1525 __P4MASK(mem-type0, 11), 1526 __P4MASK(mem-type1, 12), 1527 __P4MASK(mem-type2, 13), 1528 NULLMASK 1529 }; 1530 1531 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1532 __P4MASK(all, 15), 1533 NULLMASK 1534 }; 1535 1536 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1537 __P4MASK(all, 15), 1538 NULLMASK 1539 }; 1540 1541 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1542 __P4MASK(all, 15), 1543 NULLMASK 1544 }; 1545 1546 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1547 __P4MASK(all, 15), 1548 NULLMASK 1549 }; 1550 1551 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1552 __P4MASK(all, 15), 1553 NULLMASK 1554 }; 1555 1556 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1557 __P4MASK(all, 15), 1558 NULLMASK 1559 }; 1560 1561 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1562 __P4MASK(all, 15), 1563 NULLMASK 1564 }; 1565 1566 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1567 __P4MASK(all, 15), 1568 NULLMASK 1569 }; 1570 1571 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1572 __P4MASK(allp0, 3), 1573 __P4MASK(allp2, 4), 1574 NULLMASK 1575 }; 1576 1577 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1578 __P4MASK(running, 0), 1579 NULLMASK 1580 }; 1581 1582 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1583 __P4MASK(cisc, 0), 1584 NULLMASK 1585 }; 1586 1587 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1588 __P4MASK(from-tc-build, 0), 1589 __P4MASK(from-tc-deliver, 1), 1590 __P4MASK(from-rom, 2), 1591 NULLMASK 1592 }; 1593 1594 static const struct pmc_masks p4_mask_rmbt[] = { 1595 /* retired mispred branch type */ 1596 __P4MASK(conditional, 1), 1597 __P4MASK(call, 2), 1598 __P4MASK(return, 3), 1599 __P4MASK(indirect, 4), 1600 NULLMASK 1601 }; 1602 1603 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1604 __P4MASK(conditional, 1), 1605 __P4MASK(call, 2), 1606 __P4MASK(retired, 3), 1607 __P4MASK(indirect, 4), 1608 NULLMASK 1609 }; 1610 1611 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1612 __P4MASK(sbfull, 5), 1613 NULLMASK 1614 }; 1615 1616 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1617 __P4MASK(wcb-evicts, 0), 1618 __P4MASK(wcb-full-evict, 1), 1619 NULLMASK 1620 }; 1621 1622 static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1623 __P4MASK(nbogus, 0), 1624 __P4MASK(bogus, 1), 1625 NULLMASK 1626 }; 1627 1628 static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1629 __P4MASK(nbogus0, 0), 1630 __P4MASK(nbogus1, 1), 1631 __P4MASK(nbogus2, 2), 1632 __P4MASK(nbogus3, 3), 1633 __P4MASK(bogus0, 4), 1634 __P4MASK(bogus1, 5), 1635 __P4MASK(bogus2, 6), 1636 __P4MASK(bogus3, 7), 1637 NULLMASK 1638 }; 1639 1640 static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1641 __P4MASK(nbogus, 0), 1642 __P4MASK(bogus, 1), 1643 NULLMASK 1644 }; 1645 1646 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1647 __P4MASK(nbogusntag, 0), 1648 __P4MASK(nbogustag, 1), 1649 __P4MASK(bogusntag, 2), 1650 __P4MASK(bogustag, 3), 1651 NULLMASK 1652 }; 1653 1654 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1655 __P4MASK(nbogus, 0), 1656 __P4MASK(bogus, 1), 1657 NULLMASK 1658 }; 1659 1660 static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1661 __P4MASK(tagloads, 1), 1662 __P4MASK(tagstores, 2), 1663 NULLMASK 1664 }; 1665 1666 static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1667 __P4MASK(mmnp, 0), 1668 __P4MASK(mmnm, 1), 1669 __P4MASK(mmtp, 2), 1670 __P4MASK(mmtm, 3), 1671 NULLMASK 1672 }; 1673 1674 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1675 __P4MASK(nbogus, 0), 1676 NULLMASK 1677 }; 1678 1679 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1680 __P4MASK(fpsu, 0), 1681 __P4MASK(fpso, 1), 1682 __P4MASK(poao, 2), 1683 __P4MASK(poau, 3), 1684 __P4MASK(prea, 4), 1685 NULLMASK 1686 }; 1687 1688 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1689 __P4MASK(clear, 0), 1690 __P4MASK(moclear, 2), 1691 __P4MASK(smclear, 3), 1692 NULLMASK 1693 }; 1694 1695 /* P4 event parser */ 1696 static int 1697 p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1698 struct pmc_op_pmcallocate *pmc_config) 1699 { 1700 1701 char *e, *p, *q; 1702 int count, has_tag, has_busreqtype, n; 1703 uint32_t cccractivemask; 1704 uint64_t evmask; 1705 const struct pmc_masks *pm, *pmask; 1706 1707 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1708 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1709 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1710 1711 pmask = NULL; 1712 evmask = 0; 1713 cccractivemask = 0x3; 1714 has_tag = has_busreqtype = 0; 1715 1716 #define __P4SETMASK(M) do { \ 1717 pmask = p4_mask_##M; \ 1718 } while (0) 1719 1720 switch (pe) { 1721 case PMC_EV_P4_TC_DELIVER_MODE: 1722 __P4SETMASK(tcdm); 1723 break; 1724 case PMC_EV_P4_BPU_FETCH_REQUEST: 1725 __P4SETMASK(bfr); 1726 break; 1727 case PMC_EV_P4_ITLB_REFERENCE: 1728 __P4SETMASK(ir); 1729 break; 1730 case PMC_EV_P4_MEMORY_CANCEL: 1731 __P4SETMASK(memcan); 1732 break; 1733 case PMC_EV_P4_MEMORY_COMPLETE: 1734 __P4SETMASK(memcomp); 1735 break; 1736 case PMC_EV_P4_LOAD_PORT_REPLAY: 1737 __P4SETMASK(lpr); 1738 break; 1739 case PMC_EV_P4_STORE_PORT_REPLAY: 1740 __P4SETMASK(spr); 1741 break; 1742 case PMC_EV_P4_MOB_LOAD_REPLAY: 1743 __P4SETMASK(mlr); 1744 break; 1745 case PMC_EV_P4_PAGE_WALK_TYPE: 1746 __P4SETMASK(pwt); 1747 break; 1748 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1749 __P4SETMASK(bcr); 1750 break; 1751 case PMC_EV_P4_IOQ_ALLOCATION: 1752 __P4SETMASK(ia); 1753 has_busreqtype = 1; 1754 break; 1755 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1756 __P4SETMASK(iae); 1757 has_busreqtype = 1; 1758 break; 1759 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1760 __P4SETMASK(fda); 1761 break; 1762 case PMC_EV_P4_BSQ_ALLOCATION: 1763 __P4SETMASK(ba); 1764 break; 1765 case PMC_EV_P4_SSE_INPUT_ASSIST: 1766 __P4SETMASK(sia); 1767 break; 1768 case PMC_EV_P4_PACKED_SP_UOP: 1769 __P4SETMASK(psu); 1770 break; 1771 case PMC_EV_P4_PACKED_DP_UOP: 1772 __P4SETMASK(pdu); 1773 break; 1774 case PMC_EV_P4_SCALAR_SP_UOP: 1775 __P4SETMASK(ssu); 1776 break; 1777 case PMC_EV_P4_SCALAR_DP_UOP: 1778 __P4SETMASK(sdu); 1779 break; 1780 case PMC_EV_P4_64BIT_MMX_UOP: 1781 __P4SETMASK(64bmu); 1782 break; 1783 case PMC_EV_P4_128BIT_MMX_UOP: 1784 __P4SETMASK(128bmu); 1785 break; 1786 case PMC_EV_P4_X87_FP_UOP: 1787 __P4SETMASK(xfu); 1788 break; 1789 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1790 __P4SETMASK(xsmu); 1791 break; 1792 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1793 __P4SETMASK(gpe); 1794 break; 1795 case PMC_EV_P4_TC_MS_XFER: 1796 __P4SETMASK(tmx); 1797 break; 1798 case PMC_EV_P4_UOP_QUEUE_WRITES: 1799 __P4SETMASK(uqw); 1800 break; 1801 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1802 __P4SETMASK(rmbt); 1803 break; 1804 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1805 __P4SETMASK(rbt); 1806 break; 1807 case PMC_EV_P4_RESOURCE_STALL: 1808 __P4SETMASK(rs); 1809 break; 1810 case PMC_EV_P4_WC_BUFFER: 1811 __P4SETMASK(wb); 1812 break; 1813 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1814 case PMC_EV_P4_B2B_CYCLES: 1815 case PMC_EV_P4_BNR: 1816 case PMC_EV_P4_SNOOP: 1817 case PMC_EV_P4_RESPONSE: 1818 break; 1819 case PMC_EV_P4_FRONT_END_EVENT: 1820 __P4SETMASK(fee); 1821 break; 1822 case PMC_EV_P4_EXECUTION_EVENT: 1823 __P4SETMASK(ee); 1824 break; 1825 case PMC_EV_P4_REPLAY_EVENT: 1826 __P4SETMASK(re); 1827 break; 1828 case PMC_EV_P4_INSTR_RETIRED: 1829 __P4SETMASK(insret); 1830 break; 1831 case PMC_EV_P4_UOPS_RETIRED: 1832 __P4SETMASK(ur); 1833 break; 1834 case PMC_EV_P4_UOP_TYPE: 1835 __P4SETMASK(ut); 1836 break; 1837 case PMC_EV_P4_BRANCH_RETIRED: 1838 __P4SETMASK(br); 1839 break; 1840 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1841 __P4SETMASK(mbr); 1842 break; 1843 case PMC_EV_P4_X87_ASSIST: 1844 __P4SETMASK(xa); 1845 break; 1846 case PMC_EV_P4_MACHINE_CLEAR: 1847 __P4SETMASK(machclr); 1848 break; 1849 default: 1850 return (-1); 1851 } 1852 1853 /* process additional flags */ 1854 while ((p = strsep(&ctrspec, ",")) != NULL) { 1855 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1856 q = strchr(p, '='); 1857 if (*++q == '\0') /* skip '=' */ 1858 return (-1); 1859 1860 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1861 cccractivemask = 0x0; 1862 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1863 cccractivemask = 0x1; 1864 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1865 cccractivemask = 0x2; 1866 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1867 cccractivemask = 0x3; 1868 else 1869 return (-1); 1870 1871 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1872 if (has_busreqtype == 0) 1873 return (-1); 1874 1875 q = strchr(p, '='); 1876 if (*++q == '\0') /* skip '=' */ 1877 return (-1); 1878 1879 count = strtol(q, &e, 0); 1880 if (e == q || *e != '\0') 1881 return (-1); 1882 evmask = (evmask & ~0x1F) | (count & 0x1F); 1883 } else if (KWMATCH(p, P4_KW_CASCADE)) 1884 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1885 else if (KWMATCH(p, P4_KW_EDGE)) 1886 pmc_config->pm_caps |= PMC_CAP_EDGE; 1887 else if (KWMATCH(p, P4_KW_INV)) 1888 pmc_config->pm_caps |= PMC_CAP_INVERT; 1889 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1890 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1891 return (-1); 1892 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1893 } else if (KWMATCH(p, P4_KW_OS)) 1894 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1895 else if (KWMATCH(p, P4_KW_PRECISE)) 1896 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1897 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1898 if (has_tag == 0) 1899 return (-1); 1900 1901 q = strchr(p, '='); 1902 if (*++q == '\0') /* skip '=' */ 1903 return (-1); 1904 1905 count = strtol(q, &e, 0); 1906 if (e == q || *e != '\0') 1907 return (-1); 1908 1909 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1910 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1911 P4_ESCR_TO_TAG_VALUE(count); 1912 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1913 q = strchr(p, '='); 1914 if (*++q == '\0') /* skip '=' */ 1915 return (-1); 1916 1917 count = strtol(q, &e, 0); 1918 if (e == q || *e != '\0') 1919 return (-1); 1920 1921 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1922 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1923 ~P4_CCCR_THRESHOLD_MASK; 1924 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1925 P4_CCCR_TO_THRESHOLD(count); 1926 } else if (KWMATCH(p, P4_KW_USR)) 1927 pmc_config->pm_caps |= PMC_CAP_USER; 1928 else 1929 return (-1); 1930 } 1931 1932 /* other post processing */ 1933 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1934 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1935 pe == PMC_EV_P4_BSQ_ALLOCATION) 1936 pmc_config->pm_caps |= PMC_CAP_EDGE; 1937 1938 /* fill in thread activity mask */ 1939 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1940 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1941 1942 if (evmask) 1943 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1944 1945 switch (pe) { 1946 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1947 if ((evmask & 0x06) == 0x06 || 1948 (evmask & 0x18) == 0x18) 1949 return (-1); /* can't have own+other bits together */ 1950 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1951 evmask = 0x1D; 1952 break; 1953 case PMC_EV_P4_MACHINE_CLEAR: 1954 /* only one bit is allowed to be set */ 1955 if ((evmask & (evmask - 1)) != 0) 1956 return (-1); 1957 if (evmask == 0) { 1958 evmask = 0x1; /* 'CLEAR' */ 1959 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1960 } 1961 break; 1962 default: 1963 if (evmask == 0 && pmask) { 1964 for (pm = pmask; pm->pm_name; pm++) 1965 evmask |= pm->pm_value; 1966 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1967 } 1968 } 1969 1970 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1971 P4_ESCR_TO_EVENT_MASK(evmask); 1972 1973 return (0); 1974 } 1975 1976 #endif 1977 1978 #if defined(__i386__) 1979 1980 /* 1981 * Pentium style PMCs 1982 */ 1983 1984 static struct pmc_event_alias p5_aliases[] = { 1985 EV_ALIAS("branches", "p5-taken-branches"), 1986 EV_ALIAS("cycles", "tsc"), 1987 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 1988 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 1989 EV_ALIAS("instructions", "p5-instructions-executed"), 1990 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 1991 EV_ALIAS("unhalted-cycles", 1992 "p5-number-of-cycles-not-in-halt-state"), 1993 EV_ALIAS(NULL, NULL) 1994 }; 1995 1996 static int 1997 p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 1998 struct pmc_op_pmcallocate *pmc_config) 1999 { 2000 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 2001 } 2002 2003 /* 2004 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 2005 * and Pentium M CPUs. 2006 */ 2007 2008 static struct pmc_event_alias p6_aliases[] = { 2009 EV_ALIAS("branches", "p6-br-inst-retired"), 2010 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 2011 EV_ALIAS("cycles", "tsc"), 2012 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 2013 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 2014 EV_ALIAS("instructions", "p6-inst-retired"), 2015 EV_ALIAS("interrupts", "p6-hw-int-rx"), 2016 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 2017 EV_ALIAS(NULL, NULL) 2018 }; 2019 2020 #define P6_KW_CMASK "cmask" 2021 #define P6_KW_EDGE "edge" 2022 #define P6_KW_INV "inv" 2023 #define P6_KW_OS "os" 2024 #define P6_KW_UMASK "umask" 2025 #define P6_KW_USR "usr" 2026 2027 static struct pmc_masks p6_mask_mesi[] = { 2028 PMCMASK(m, 0x01), 2029 PMCMASK(e, 0x02), 2030 PMCMASK(s, 0x04), 2031 PMCMASK(i, 0x08), 2032 NULLMASK 2033 }; 2034 2035 static struct pmc_masks p6_mask_mesihw[] = { 2036 PMCMASK(m, 0x01), 2037 PMCMASK(e, 0x02), 2038 PMCMASK(s, 0x04), 2039 PMCMASK(i, 0x08), 2040 PMCMASK(nonhw, 0x00), 2041 PMCMASK(hw, 0x10), 2042 PMCMASK(both, 0x30), 2043 NULLMASK 2044 }; 2045 2046 static struct pmc_masks p6_mask_hw[] = { 2047 PMCMASK(nonhw, 0x00), 2048 PMCMASK(hw, 0x10), 2049 PMCMASK(both, 0x30), 2050 NULLMASK 2051 }; 2052 2053 static struct pmc_masks p6_mask_any[] = { 2054 PMCMASK(self, 0x00), 2055 PMCMASK(any, 0x20), 2056 NULLMASK 2057 }; 2058 2059 static struct pmc_masks p6_mask_ekp[] = { 2060 PMCMASK(nta, 0x00), 2061 PMCMASK(t1, 0x01), 2062 PMCMASK(t2, 0x02), 2063 PMCMASK(wos, 0x03), 2064 NULLMASK 2065 }; 2066 2067 static struct pmc_masks p6_mask_pps[] = { 2068 PMCMASK(packed-and-scalar, 0x00), 2069 PMCMASK(scalar, 0x01), 2070 NULLMASK 2071 }; 2072 2073 static struct pmc_masks p6_mask_mite[] = { 2074 PMCMASK(packed-multiply, 0x01), 2075 PMCMASK(packed-shift, 0x02), 2076 PMCMASK(pack, 0x04), 2077 PMCMASK(unpack, 0x08), 2078 PMCMASK(packed-logical, 0x10), 2079 PMCMASK(packed-arithmetic, 0x20), 2080 NULLMASK 2081 }; 2082 2083 static struct pmc_masks p6_mask_fmt[] = { 2084 PMCMASK(mmxtofp, 0x00), 2085 PMCMASK(fptommx, 0x01), 2086 NULLMASK 2087 }; 2088 2089 static struct pmc_masks p6_mask_sr[] = { 2090 PMCMASK(es, 0x01), 2091 PMCMASK(ds, 0x02), 2092 PMCMASK(fs, 0x04), 2093 PMCMASK(gs, 0x08), 2094 NULLMASK 2095 }; 2096 2097 static struct pmc_masks p6_mask_eet[] = { 2098 PMCMASK(all, 0x00), 2099 PMCMASK(freq, 0x02), 2100 NULLMASK 2101 }; 2102 2103 static struct pmc_masks p6_mask_efur[] = { 2104 PMCMASK(all, 0x00), 2105 PMCMASK(loadop, 0x01), 2106 PMCMASK(stdsta, 0x02), 2107 NULLMASK 2108 }; 2109 2110 static struct pmc_masks p6_mask_essir[] = { 2111 PMCMASK(sse-packed-single, 0x00), 2112 PMCMASK(sse-packed-single-scalar-single, 0x01), 2113 PMCMASK(sse2-packed-double, 0x02), 2114 PMCMASK(sse2-scalar-double, 0x03), 2115 NULLMASK 2116 }; 2117 2118 static struct pmc_masks p6_mask_esscir[] = { 2119 PMCMASK(sse-packed-single, 0x00), 2120 PMCMASK(sse-scalar-single, 0x01), 2121 PMCMASK(sse2-packed-double, 0x02), 2122 PMCMASK(sse2-scalar-double, 0x03), 2123 NULLMASK 2124 }; 2125 2126 /* P6 event parser */ 2127 static int 2128 p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 2129 struct pmc_op_pmcallocate *pmc_config) 2130 { 2131 char *e, *p, *q; 2132 uint64_t evmask; 2133 int count, n; 2134 const struct pmc_masks *pm, *pmask; 2135 2136 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2137 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 2138 2139 evmask = 0; 2140 2141 #define P6MASKSET(M) pmask = p6_mask_ ## M 2142 2143 switch(pe) { 2144 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 2145 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 2146 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 2147 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 2148 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2149 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2150 case PMC_EV_P6_BUS_TRAN_BRD: 2151 case PMC_EV_P6_BUS_TRAN_RFO: 2152 case PMC_EV_P6_BUS_TRANS_WB: 2153 case PMC_EV_P6_BUS_TRAN_IFETCH: 2154 case PMC_EV_P6_BUS_TRAN_INVAL: 2155 case PMC_EV_P6_BUS_TRAN_PWR: 2156 case PMC_EV_P6_BUS_TRANS_P: 2157 case PMC_EV_P6_BUS_TRANS_IO: 2158 case PMC_EV_P6_BUS_TRAN_DEF: 2159 case PMC_EV_P6_BUS_TRAN_BURST: 2160 case PMC_EV_P6_BUS_TRAN_ANY: 2161 case PMC_EV_P6_BUS_TRAN_MEM: 2162 P6MASKSET(any); break; 2163 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2164 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2165 P6MASKSET(ekp); break; 2166 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2167 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2168 P6MASKSET(pps); break; 2169 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2170 P6MASKSET(mite); break; 2171 case PMC_EV_P6_FP_MMX_TRANS: 2172 P6MASKSET(fmt); break; 2173 case PMC_EV_P6_SEG_RENAME_STALLS: 2174 case PMC_EV_P6_SEG_REG_RENAMES: 2175 P6MASKSET(sr); break; 2176 case PMC_EV_P6_EMON_EST_TRANS: 2177 P6MASKSET(eet); break; 2178 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2179 P6MASKSET(efur); break; 2180 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2181 P6MASKSET(essir); break; 2182 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2183 P6MASKSET(esscir); break; 2184 default: 2185 pmask = NULL; 2186 break; 2187 } 2188 2189 /* Pentium M PMCs have a few events with different semantics */ 2190 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2191 if (pe == PMC_EV_P6_L2_LD || 2192 pe == PMC_EV_P6_L2_LINES_IN || 2193 pe == PMC_EV_P6_L2_LINES_OUT) 2194 P6MASKSET(mesihw); 2195 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2196 P6MASKSET(hw); 2197 } 2198 2199 /* Parse additional modifiers if present */ 2200 while ((p = strsep(&ctrspec, ",")) != NULL) { 2201 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2202 q = strchr(p, '='); 2203 if (*++q == '\0') /* skip '=' */ 2204 return (-1); 2205 count = strtol(q, &e, 0); 2206 if (e == q || *e != '\0') 2207 return (-1); 2208 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2209 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2210 P6_EVSEL_TO_CMASK(count); 2211 } else if (KWMATCH(p, P6_KW_EDGE)) { 2212 pmc_config->pm_caps |= PMC_CAP_EDGE; 2213 } else if (KWMATCH(p, P6_KW_INV)) { 2214 pmc_config->pm_caps |= PMC_CAP_INVERT; 2215 } else if (KWMATCH(p, P6_KW_OS)) { 2216 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2217 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2218 evmask = 0; 2219 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2220 return (-1); 2221 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2222 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2223 pe == PMC_EV_P6_BUS_TRAN_BRD || 2224 pe == PMC_EV_P6_BUS_TRAN_RFO || 2225 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2226 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2227 pe == PMC_EV_P6_BUS_TRAN_PWR || 2228 pe == PMC_EV_P6_BUS_TRAN_DEF || 2229 pe == PMC_EV_P6_BUS_TRAN_BURST || 2230 pe == PMC_EV_P6_BUS_TRAN_ANY || 2231 pe == PMC_EV_P6_BUS_TRAN_MEM || 2232 pe == PMC_EV_P6_BUS_TRANS_IO || 2233 pe == PMC_EV_P6_BUS_TRANS_P || 2234 pe == PMC_EV_P6_BUS_TRANS_WB || 2235 pe == PMC_EV_P6_EMON_EST_TRANS || 2236 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2237 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2238 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2239 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2240 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2241 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2242 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2243 pe == PMC_EV_P6_FP_MMX_TRANS) 2244 && (n > 1)) /* Only one mask keyword is allowed. */ 2245 return (-1); 2246 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2247 } else if (KWMATCH(p, P6_KW_USR)) { 2248 pmc_config->pm_caps |= PMC_CAP_USER; 2249 } else 2250 return (-1); 2251 } 2252 2253 /* post processing */ 2254 switch (pe) { 2255 2256 /* 2257 * The following events default to an evmask of 0 2258 */ 2259 2260 /* default => 'self' */ 2261 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2262 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2263 case PMC_EV_P6_BUS_TRAN_BRD: 2264 case PMC_EV_P6_BUS_TRAN_RFO: 2265 case PMC_EV_P6_BUS_TRANS_WB: 2266 case PMC_EV_P6_BUS_TRAN_IFETCH: 2267 case PMC_EV_P6_BUS_TRAN_INVAL: 2268 case PMC_EV_P6_BUS_TRAN_PWR: 2269 case PMC_EV_P6_BUS_TRANS_P: 2270 case PMC_EV_P6_BUS_TRANS_IO: 2271 case PMC_EV_P6_BUS_TRAN_DEF: 2272 case PMC_EV_P6_BUS_TRAN_BURST: 2273 case PMC_EV_P6_BUS_TRAN_ANY: 2274 case PMC_EV_P6_BUS_TRAN_MEM: 2275 2276 /* default => 'nta' */ 2277 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2278 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2279 2280 /* default => 'packed and scalar' */ 2281 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2282 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2283 2284 /* default => 'mmx to fp transitions' */ 2285 case PMC_EV_P6_FP_MMX_TRANS: 2286 2287 /* default => 'SSE Packed Single' */ 2288 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2289 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2290 2291 /* default => 'all fused micro-ops' */ 2292 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2293 2294 /* default => 'all transitions' */ 2295 case PMC_EV_P6_EMON_EST_TRANS: 2296 break; 2297 2298 case PMC_EV_P6_MMX_UOPS_EXEC: 2299 evmask = 0x0F; /* only value allowed */ 2300 break; 2301 2302 default: 2303 /* 2304 * For all other events, set the default event mask 2305 * to a logical OR of all the allowed event mask bits. 2306 */ 2307 if (evmask == 0 && pmask) { 2308 for (pm = pmask; pm->pm_name; pm++) 2309 evmask |= pm->pm_value; 2310 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2311 } 2312 2313 break; 2314 } 2315 2316 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2317 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2318 P6_EVSEL_TO_UMASK(evmask); 2319 2320 return (0); 2321 } 2322 2323 #endif 2324 2325 #if defined(__i386__) || defined(__amd64__) 2326 static int 2327 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2328 struct pmc_op_pmcallocate *pmc_config) 2329 { 2330 if (pe != PMC_EV_TSC_TSC) 2331 return (-1); 2332 2333 /* TSC events must be unqualified. */ 2334 if (ctrspec && *ctrspec != '\0') 2335 return (-1); 2336 2337 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2338 pmc_config->pm_caps |= PMC_CAP_READ; 2339 2340 return (0); 2341 } 2342 #endif 2343 2344 static struct pmc_event_alias generic_aliases[] = { 2345 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 2346 EV_ALIAS(NULL, NULL) 2347 }; 2348 2349 static int 2350 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 2351 struct pmc_op_pmcallocate *pmc_config) 2352 { 2353 (void)ctrspec; 2354 (void)pmc_config; 2355 2356 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 2357 return (-1); 2358 2359 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2360 return (0); 2361 } 2362 2363 #if defined(__XSCALE__) 2364 2365 static struct pmc_event_alias xscale_aliases[] = { 2366 EV_ALIAS("branches", "BRANCH_RETIRED"), 2367 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2368 EV_ALIAS("dc-misses", "DC_MISS"), 2369 EV_ALIAS("ic-misses", "IC_MISS"), 2370 EV_ALIAS("instructions", "INSTR_RETIRED"), 2371 EV_ALIAS(NULL, NULL) 2372 }; 2373 static int 2374 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2375 struct pmc_op_pmcallocate *pmc_config __unused) 2376 { 2377 switch (pe) { 2378 default: 2379 break; 2380 } 2381 2382 return (0); 2383 } 2384 #endif 2385 2386 #if defined(__mips__) 2387 2388 static struct pmc_event_alias mips24k_aliases[] = { 2389 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2390 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2391 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2392 EV_ALIAS(NULL, NULL) 2393 }; 2394 2395 static struct pmc_event_alias octeon_aliases[] = { 2396 EV_ALIAS("instructions", "RET"), 2397 EV_ALIAS("branches", "BR"), 2398 EV_ALIAS("branch-mispredicts", "BRMIS"), 2399 EV_ALIAS(NULL, NULL) 2400 }; 2401 2402 #define MIPS_KW_OS "os" 2403 #define MIPS_KW_USR "usr" 2404 #define MIPS_KW_ANYTHREAD "anythread" 2405 2406 static int 2407 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2408 struct pmc_op_pmcallocate *pmc_config __unused) 2409 { 2410 char *p; 2411 2412 (void) pe; 2413 2414 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2415 2416 while ((p = strsep(&ctrspec, ",")) != NULL) { 2417 if (KWMATCH(p, MIPS_KW_OS)) 2418 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2419 else if (KWMATCH(p, MIPS_KW_USR)) 2420 pmc_config->pm_caps |= PMC_CAP_USER; 2421 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 2422 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2423 else 2424 return (-1); 2425 } 2426 2427 return (0); 2428 } 2429 2430 #endif /* __mips__ */ 2431 2432 #if defined(__powerpc__) 2433 2434 static struct pmc_event_alias ppc7450_aliases[] = { 2435 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2436 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2437 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2438 EV_ALIAS(NULL, NULL) 2439 }; 2440 2441 static struct pmc_event_alias ppc970_aliases[] = { 2442 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2443 EV_ALIAS("cycles", "CYCLES"), 2444 EV_ALIAS(NULL, NULL) 2445 }; 2446 2447 #define POWERPC_KW_OS "os" 2448 #define POWERPC_KW_USR "usr" 2449 #define POWERPC_KW_ANYTHREAD "anythread" 2450 2451 static int 2452 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2453 struct pmc_op_pmcallocate *pmc_config __unused) 2454 { 2455 char *p; 2456 2457 (void) pe; 2458 2459 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2460 2461 while ((p = strsep(&ctrspec, ",")) != NULL) { 2462 if (KWMATCH(p, POWERPC_KW_OS)) 2463 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2464 else if (KWMATCH(p, POWERPC_KW_USR)) 2465 pmc_config->pm_caps |= PMC_CAP_USER; 2466 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 2467 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2468 else 2469 return (-1); 2470 } 2471 2472 return (0); 2473 } 2474 2475 #endif /* __powerpc__ */ 2476 2477 2478 /* 2479 * Match an event name `name' with its canonical form. 2480 * 2481 * Matches are case insensitive and spaces, periods, underscores and 2482 * hyphen characters are considered to match each other. 2483 * 2484 * Returns 1 for a match, 0 otherwise. 2485 */ 2486 2487 static int 2488 pmc_match_event_name(const char *name, const char *canonicalname) 2489 { 2490 int cc, nc; 2491 const unsigned char *c, *n; 2492 2493 c = (const unsigned char *) canonicalname; 2494 n = (const unsigned char *) name; 2495 2496 for (; (nc = *n) && (cc = *c); n++, c++) { 2497 2498 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2499 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2500 continue; 2501 2502 if (toupper(nc) == toupper(cc)) 2503 continue; 2504 2505 2506 return (0); 2507 } 2508 2509 if (*n == '\0' && *c == '\0') 2510 return (1); 2511 2512 return (0); 2513 } 2514 2515 /* 2516 * Match an event name against all the event named supported by a 2517 * PMC class. 2518 * 2519 * Returns an event descriptor pointer on match or NULL otherwise. 2520 */ 2521 static const struct pmc_event_descr * 2522 pmc_match_event_class(const char *name, 2523 const struct pmc_class_descr *pcd) 2524 { 2525 size_t n; 2526 const struct pmc_event_descr *ev; 2527 2528 ev = pcd->pm_evc_event_table; 2529 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2530 if (pmc_match_event_name(name, ev->pm_ev_name)) 2531 return (ev); 2532 2533 return (NULL); 2534 } 2535 2536 static int 2537 pmc_mdep_is_compatible_class(enum pmc_class pc) 2538 { 2539 size_t n; 2540 2541 for (n = 0; n < pmc_mdep_class_list_size; n++) 2542 if (pmc_mdep_class_list[n] == pc) 2543 return (1); 2544 return (0); 2545 } 2546 2547 /* 2548 * API entry points 2549 */ 2550 2551 int 2552 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2553 uint32_t flags, int cpu, pmc_id_t *pmcid) 2554 { 2555 size_t n; 2556 int retval; 2557 char *r, *spec_copy; 2558 const char *ctrname; 2559 const struct pmc_event_descr *ev; 2560 const struct pmc_event_alias *alias; 2561 struct pmc_op_pmcallocate pmc_config; 2562 const struct pmc_class_descr *pcd; 2563 2564 spec_copy = NULL; 2565 retval = -1; 2566 2567 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2568 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2569 errno = EINVAL; 2570 goto out; 2571 } 2572 2573 /* replace an event alias with the canonical event specifier */ 2574 if (pmc_mdep_event_aliases) 2575 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2576 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2577 spec_copy = strdup(alias->pm_spec); 2578 break; 2579 } 2580 2581 if (spec_copy == NULL) 2582 spec_copy = strdup(ctrspec); 2583 2584 r = spec_copy; 2585 ctrname = strsep(&r, ","); 2586 2587 /* 2588 * If a explicit class prefix was given by the user, restrict the 2589 * search for the event to the specified PMC class. 2590 */ 2591 ev = NULL; 2592 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2593 pcd = pmc_class_table[n]; 2594 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2595 strncasecmp(ctrname, pcd->pm_evc_name, 2596 pcd->pm_evc_name_size) == 0) { 2597 if ((ev = pmc_match_event_class(ctrname + 2598 pcd->pm_evc_name_size, pcd)) == NULL) { 2599 errno = EINVAL; 2600 goto out; 2601 } 2602 break; 2603 } 2604 } 2605 2606 /* 2607 * Otherwise, search for this event in all compatible PMC 2608 * classes. 2609 */ 2610 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2611 pcd = pmc_class_table[n]; 2612 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2613 ev = pmc_match_event_class(ctrname, pcd); 2614 } 2615 2616 if (ev == NULL) { 2617 errno = EINVAL; 2618 goto out; 2619 } 2620 2621 bzero(&pmc_config, sizeof(pmc_config)); 2622 pmc_config.pm_ev = ev->pm_ev_code; 2623 pmc_config.pm_class = pcd->pm_evc_class; 2624 pmc_config.pm_cpu = cpu; 2625 pmc_config.pm_mode = mode; 2626 pmc_config.pm_flags = flags; 2627 2628 if (PMC_IS_SAMPLING_MODE(mode)) 2629 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2630 2631 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2632 errno = EINVAL; 2633 goto out; 2634 } 2635 2636 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2637 goto out; 2638 2639 *pmcid = pmc_config.pm_pmcid; 2640 2641 retval = 0; 2642 2643 out: 2644 if (spec_copy) 2645 free(spec_copy); 2646 2647 return (retval); 2648 } 2649 2650 int 2651 pmc_attach(pmc_id_t pmc, pid_t pid) 2652 { 2653 struct pmc_op_pmcattach pmc_attach_args; 2654 2655 pmc_attach_args.pm_pmc = pmc; 2656 pmc_attach_args.pm_pid = pid; 2657 2658 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2659 } 2660 2661 int 2662 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2663 { 2664 unsigned int i; 2665 enum pmc_class cl; 2666 2667 cl = PMC_ID_TO_CLASS(pmcid); 2668 for (i = 0; i < cpu_info.pm_nclass; i++) 2669 if (cpu_info.pm_classes[i].pm_class == cl) { 2670 *caps = cpu_info.pm_classes[i].pm_caps; 2671 return (0); 2672 } 2673 errno = EINVAL; 2674 return (-1); 2675 } 2676 2677 int 2678 pmc_configure_logfile(int fd) 2679 { 2680 struct pmc_op_configurelog cla; 2681 2682 cla.pm_logfd = fd; 2683 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2684 return (-1); 2685 return (0); 2686 } 2687 2688 int 2689 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2690 { 2691 if (pmc_syscall == -1) { 2692 errno = ENXIO; 2693 return (-1); 2694 } 2695 2696 *pci = &cpu_info; 2697 return (0); 2698 } 2699 2700 int 2701 pmc_detach(pmc_id_t pmc, pid_t pid) 2702 { 2703 struct pmc_op_pmcattach pmc_detach_args; 2704 2705 pmc_detach_args.pm_pmc = pmc; 2706 pmc_detach_args.pm_pid = pid; 2707 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2708 } 2709 2710 int 2711 pmc_disable(int cpu, int pmc) 2712 { 2713 struct pmc_op_pmcadmin ssa; 2714 2715 ssa.pm_cpu = cpu; 2716 ssa.pm_pmc = pmc; 2717 ssa.pm_state = PMC_STATE_DISABLED; 2718 return (PMC_CALL(PMCADMIN, &ssa)); 2719 } 2720 2721 int 2722 pmc_enable(int cpu, int pmc) 2723 { 2724 struct pmc_op_pmcadmin ssa; 2725 2726 ssa.pm_cpu = cpu; 2727 ssa.pm_pmc = pmc; 2728 ssa.pm_state = PMC_STATE_FREE; 2729 return (PMC_CALL(PMCADMIN, &ssa)); 2730 } 2731 2732 /* 2733 * Return a list of events known to a given PMC class. 'cl' is the 2734 * PMC class identifier, 'eventnames' is the returned list of 'const 2735 * char *' pointers pointing to the names of the events. 'nevents' is 2736 * the number of event name pointers returned. 2737 * 2738 * The space for 'eventnames' is allocated using malloc(3). The caller 2739 * is responsible for freeing this space when done. 2740 */ 2741 int 2742 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2743 int *nevents) 2744 { 2745 int count; 2746 const char **names; 2747 const struct pmc_event_descr *ev; 2748 2749 switch (cl) 2750 { 2751 case PMC_CLASS_IAF: 2752 ev = iaf_event_table; 2753 count = PMC_EVENT_TABLE_SIZE(iaf); 2754 break; 2755 case PMC_CLASS_IAP: 2756 /* 2757 * Return the most appropriate set of event name 2758 * spellings for the current CPU. 2759 */ 2760 switch (cpu_info.pm_cputype) { 2761 default: 2762 case PMC_CPU_INTEL_ATOM: 2763 ev = atom_event_table; 2764 count = PMC_EVENT_TABLE_SIZE(atom); 2765 break; 2766 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2767 ev = atom_silvermont_event_table; 2768 count = PMC_EVENT_TABLE_SIZE(atom_silvermont); 2769 break; 2770 case PMC_CPU_INTEL_CORE: 2771 ev = core_event_table; 2772 count = PMC_EVENT_TABLE_SIZE(core); 2773 break; 2774 case PMC_CPU_INTEL_CORE2: 2775 case PMC_CPU_INTEL_CORE2EXTREME: 2776 ev = core2_event_table; 2777 count = PMC_EVENT_TABLE_SIZE(core2); 2778 break; 2779 case PMC_CPU_INTEL_COREI7: 2780 ev = corei7_event_table; 2781 count = PMC_EVENT_TABLE_SIZE(corei7); 2782 break; 2783 case PMC_CPU_INTEL_NEHALEM_EX: 2784 ev = nehalem_ex_event_table; 2785 count = PMC_EVENT_TABLE_SIZE(nehalem_ex); 2786 break; 2787 case PMC_CPU_INTEL_HASWELL: 2788 ev = haswell_event_table; 2789 count = PMC_EVENT_TABLE_SIZE(haswell); 2790 break; 2791 case PMC_CPU_INTEL_IVYBRIDGE: 2792 ev = ivybridge_event_table; 2793 count = PMC_EVENT_TABLE_SIZE(ivybridge); 2794 break; 2795 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2796 ev = ivybridge_xeon_event_table; 2797 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 2798 break; 2799 case PMC_CPU_INTEL_SANDYBRIDGE: 2800 ev = sandybridge_event_table; 2801 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2802 break; 2803 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2804 ev = sandybridge_xeon_event_table; 2805 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 2806 break; 2807 case PMC_CPU_INTEL_WESTMERE: 2808 ev = westmere_event_table; 2809 count = PMC_EVENT_TABLE_SIZE(westmere); 2810 break; 2811 case PMC_CPU_INTEL_WESTMERE_EX: 2812 ev = westmere_ex_event_table; 2813 count = PMC_EVENT_TABLE_SIZE(westmere_ex); 2814 break; 2815 } 2816 break; 2817 case PMC_CLASS_UCF: 2818 ev = ucf_event_table; 2819 count = PMC_EVENT_TABLE_SIZE(ucf); 2820 break; 2821 case PMC_CLASS_UCP: 2822 /* 2823 * Return the most appropriate set of event name 2824 * spellings for the current CPU. 2825 */ 2826 switch (cpu_info.pm_cputype) { 2827 default: 2828 case PMC_CPU_INTEL_COREI7: 2829 ev = corei7uc_event_table; 2830 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2831 break; 2832 case PMC_CPU_INTEL_HASWELL: 2833 ev = haswelluc_event_table; 2834 count = PMC_EVENT_TABLE_SIZE(haswelluc); 2835 break; 2836 case PMC_CPU_INTEL_SANDYBRIDGE: 2837 ev = sandybridgeuc_event_table; 2838 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2839 break; 2840 case PMC_CPU_INTEL_WESTMERE: 2841 ev = westmereuc_event_table; 2842 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2843 break; 2844 } 2845 break; 2846 case PMC_CLASS_TSC: 2847 ev = tsc_event_table; 2848 count = PMC_EVENT_TABLE_SIZE(tsc); 2849 break; 2850 case PMC_CLASS_K7: 2851 ev = k7_event_table; 2852 count = PMC_EVENT_TABLE_SIZE(k7); 2853 break; 2854 case PMC_CLASS_K8: 2855 ev = k8_event_table; 2856 count = PMC_EVENT_TABLE_SIZE(k8); 2857 break; 2858 case PMC_CLASS_P4: 2859 ev = p4_event_table; 2860 count = PMC_EVENT_TABLE_SIZE(p4); 2861 break; 2862 case PMC_CLASS_P5: 2863 ev = p5_event_table; 2864 count = PMC_EVENT_TABLE_SIZE(p5); 2865 break; 2866 case PMC_CLASS_P6: 2867 ev = p6_event_table; 2868 count = PMC_EVENT_TABLE_SIZE(p6); 2869 break; 2870 case PMC_CLASS_XSCALE: 2871 ev = xscale_event_table; 2872 count = PMC_EVENT_TABLE_SIZE(xscale); 2873 break; 2874 case PMC_CLASS_MIPS24K: 2875 ev = mips24k_event_table; 2876 count = PMC_EVENT_TABLE_SIZE(mips24k); 2877 break; 2878 case PMC_CLASS_OCTEON: 2879 ev = octeon_event_table; 2880 count = PMC_EVENT_TABLE_SIZE(octeon); 2881 break; 2882 case PMC_CLASS_PPC7450: 2883 ev = ppc7450_event_table; 2884 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2885 break; 2886 case PMC_CLASS_PPC970: 2887 ev = ppc970_event_table; 2888 count = PMC_EVENT_TABLE_SIZE(ppc970); 2889 break; 2890 case PMC_CLASS_SOFT: 2891 ev = soft_event_table; 2892 count = soft_event_info.pm_nevent; 2893 break; 2894 default: 2895 errno = EINVAL; 2896 return (-1); 2897 } 2898 2899 if ((names = malloc(count * sizeof(const char *))) == NULL) 2900 return (-1); 2901 2902 *eventnames = names; 2903 *nevents = count; 2904 2905 for (;count--; ev++, names++) 2906 *names = ev->pm_ev_name; 2907 2908 return (0); 2909 } 2910 2911 int 2912 pmc_flush_logfile(void) 2913 { 2914 return (PMC_CALL(FLUSHLOG,0)); 2915 } 2916 2917 int 2918 pmc_close_logfile(void) 2919 { 2920 return (PMC_CALL(CLOSELOG,0)); 2921 } 2922 2923 int 2924 pmc_get_driver_stats(struct pmc_driverstats *ds) 2925 { 2926 struct pmc_op_getdriverstats gms; 2927 2928 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2929 return (-1); 2930 2931 /* copy out fields in the current userland<->library interface */ 2932 ds->pm_intr_ignored = gms.pm_intr_ignored; 2933 ds->pm_intr_processed = gms.pm_intr_processed; 2934 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2935 ds->pm_syscalls = gms.pm_syscalls; 2936 ds->pm_syscall_errors = gms.pm_syscall_errors; 2937 ds->pm_buffer_requests = gms.pm_buffer_requests; 2938 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 2939 ds->pm_log_sweeps = gms.pm_log_sweeps; 2940 return (0); 2941 } 2942 2943 int 2944 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 2945 { 2946 struct pmc_op_getmsr gm; 2947 2948 gm.pm_pmcid = pmc; 2949 if (PMC_CALL(PMCGETMSR, &gm) < 0) 2950 return (-1); 2951 *msr = gm.pm_msr; 2952 return (0); 2953 } 2954 2955 int 2956 pmc_init(void) 2957 { 2958 int error, pmc_mod_id; 2959 unsigned int n; 2960 uint32_t abi_version; 2961 struct module_stat pmc_modstat; 2962 struct pmc_op_getcpuinfo op_cpu_info; 2963 #if defined(__amd64__) || defined(__i386__) 2964 int cpu_has_iaf_counters; 2965 unsigned int t; 2966 #endif 2967 2968 if (pmc_syscall != -1) /* already inited */ 2969 return (0); 2970 2971 /* retrieve the system call number from the KLD */ 2972 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 2973 return (-1); 2974 2975 pmc_modstat.version = sizeof(struct module_stat); 2976 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 2977 return (-1); 2978 2979 pmc_syscall = pmc_modstat.data.intval; 2980 2981 /* check the kernel module's ABI against our compiled-in version */ 2982 abi_version = PMC_VERSION; 2983 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 2984 return (pmc_syscall = -1); 2985 2986 /* ignore patch & minor numbers for the comparision */ 2987 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 2988 errno = EPROGMISMATCH; 2989 return (pmc_syscall = -1); 2990 } 2991 2992 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 2993 return (pmc_syscall = -1); 2994 2995 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 2996 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 2997 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 2998 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 2999 for (n = 0; n < cpu_info.pm_nclass; n++) 3000 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 3001 3002 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 3003 sizeof(struct pmc_class_descr *)); 3004 3005 if (pmc_class_table == NULL) 3006 return (-1); 3007 3008 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 3009 pmc_class_table[n] = NULL; 3010 3011 /* 3012 * Get soft events list. 3013 */ 3014 soft_event_info.pm_class = PMC_CLASS_SOFT; 3015 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 3016 return (pmc_syscall = -1); 3017 3018 /* Map soft events to static list. */ 3019 for (n = 0; n < soft_event_info.pm_nevent; n++) { 3020 soft_event_table[n].pm_ev_name = 3021 soft_event_info.pm_events[n].pm_ev_name; 3022 soft_event_table[n].pm_ev_code = 3023 soft_event_info.pm_events[n].pm_ev_code; 3024 } 3025 soft_class_table_descr.pm_evc_event_table_size = \ 3026 soft_event_info.pm_nevent; 3027 soft_class_table_descr.pm_evc_event_table = \ 3028 soft_event_table; 3029 3030 /* 3031 * Fill in the class table. 3032 */ 3033 n = 0; 3034 3035 /* Fill soft events information. */ 3036 pmc_class_table[n++] = &soft_class_table_descr; 3037 #if defined(__amd64__) || defined(__i386__) 3038 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 3039 pmc_class_table[n++] = &tsc_class_table_descr; 3040 3041 /* 3042 * Check if this CPU has fixed function counters. 3043 */ 3044 cpu_has_iaf_counters = 0; 3045 for (t = 0; t < cpu_info.pm_nclass; t++) 3046 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 3047 cpu_info.pm_classes[t].pm_num > 0) 3048 cpu_has_iaf_counters = 1; 3049 #endif 3050 3051 #define PMC_MDEP_INIT(C) do { \ 3052 pmc_mdep_event_aliases = C##_aliases; \ 3053 pmc_mdep_class_list = C##_pmc_classes; \ 3054 pmc_mdep_class_list_size = \ 3055 PMC_TABLE_SIZE(C##_pmc_classes); \ 3056 } while (0) 3057 3058 #define PMC_MDEP_INIT_INTEL_V2(C) do { \ 3059 PMC_MDEP_INIT(C); \ 3060 pmc_class_table[n++] = &iaf_class_table_descr; \ 3061 if (!cpu_has_iaf_counters) \ 3062 pmc_mdep_event_aliases = \ 3063 C##_aliases_without_iaf; \ 3064 pmc_class_table[n] = &C##_class_table_descr; \ 3065 } while (0) 3066 3067 /* Configure the event name parser. */ 3068 switch (cpu_info.pm_cputype) { 3069 #if defined(__i386__) 3070 case PMC_CPU_AMD_K7: 3071 PMC_MDEP_INIT(k7); 3072 pmc_class_table[n] = &k7_class_table_descr; 3073 break; 3074 case PMC_CPU_INTEL_P5: 3075 PMC_MDEP_INIT(p5); 3076 pmc_class_table[n] = &p5_class_table_descr; 3077 break; 3078 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 3079 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 3080 case PMC_CPU_INTEL_PIII: 3081 case PMC_CPU_INTEL_PM: 3082 PMC_MDEP_INIT(p6); 3083 pmc_class_table[n] = &p6_class_table_descr; 3084 break; 3085 #endif 3086 #if defined(__amd64__) || defined(__i386__) 3087 case PMC_CPU_AMD_K8: 3088 PMC_MDEP_INIT(k8); 3089 pmc_class_table[n] = &k8_class_table_descr; 3090 break; 3091 case PMC_CPU_INTEL_ATOM: 3092 PMC_MDEP_INIT_INTEL_V2(atom); 3093 break; 3094 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3095 PMC_MDEP_INIT_INTEL_V2(atom_silvermont); 3096 break; 3097 case PMC_CPU_INTEL_CORE: 3098 PMC_MDEP_INIT(core); 3099 pmc_class_table[n] = &core_class_table_descr; 3100 break; 3101 case PMC_CPU_INTEL_CORE2: 3102 case PMC_CPU_INTEL_CORE2EXTREME: 3103 PMC_MDEP_INIT_INTEL_V2(core2); 3104 break; 3105 case PMC_CPU_INTEL_COREI7: 3106 pmc_class_table[n++] = &ucf_class_table_descr; 3107 pmc_class_table[n++] = &corei7uc_class_table_descr; 3108 PMC_MDEP_INIT_INTEL_V2(corei7); 3109 break; 3110 case PMC_CPU_INTEL_NEHALEM_EX: 3111 PMC_MDEP_INIT_INTEL_V2(nehalem_ex); 3112 break; 3113 case PMC_CPU_INTEL_HASWELL: 3114 pmc_class_table[n++] = &ucf_class_table_descr; 3115 pmc_class_table[n++] = &haswelluc_class_table_descr; 3116 PMC_MDEP_INIT_INTEL_V2(haswell); 3117 break; 3118 case PMC_CPU_INTEL_IVYBRIDGE: 3119 PMC_MDEP_INIT_INTEL_V2(ivybridge); 3120 break; 3121 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3122 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); 3123 break; 3124 case PMC_CPU_INTEL_SANDYBRIDGE: 3125 pmc_class_table[n++] = &ucf_class_table_descr; 3126 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 3127 PMC_MDEP_INIT_INTEL_V2(sandybridge); 3128 break; 3129 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3130 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); 3131 break; 3132 case PMC_CPU_INTEL_WESTMERE: 3133 pmc_class_table[n++] = &ucf_class_table_descr; 3134 pmc_class_table[n++] = &westmereuc_class_table_descr; 3135 PMC_MDEP_INIT_INTEL_V2(westmere); 3136 break; 3137 case PMC_CPU_INTEL_WESTMERE_EX: 3138 PMC_MDEP_INIT_INTEL_V2(westmere_ex); 3139 break; 3140 case PMC_CPU_INTEL_PIV: 3141 PMC_MDEP_INIT(p4); 3142 pmc_class_table[n] = &p4_class_table_descr; 3143 break; 3144 #endif 3145 case PMC_CPU_GENERIC: 3146 PMC_MDEP_INIT(generic); 3147 break; 3148 #if defined(__XSCALE__) 3149 case PMC_CPU_INTEL_XSCALE: 3150 PMC_MDEP_INIT(xscale); 3151 pmc_class_table[n] = &xscale_class_table_descr; 3152 break; 3153 #endif 3154 #if defined(__mips__) 3155 case PMC_CPU_MIPS_24K: 3156 PMC_MDEP_INIT(mips24k); 3157 pmc_class_table[n] = &mips24k_class_table_descr; 3158 break; 3159 case PMC_CPU_MIPS_OCTEON: 3160 PMC_MDEP_INIT(octeon); 3161 pmc_class_table[n] = &octeon_class_table_descr; 3162 break; 3163 #endif /* __mips__ */ 3164 #if defined(__powerpc__) 3165 case PMC_CPU_PPC_7450: 3166 PMC_MDEP_INIT(ppc7450); 3167 pmc_class_table[n] = &ppc7450_class_table_descr; 3168 break; 3169 case PMC_CPU_PPC_970: 3170 PMC_MDEP_INIT(ppc970); 3171 pmc_class_table[n] = &ppc970_class_table_descr; 3172 break; 3173 #endif 3174 default: 3175 /* 3176 * Some kind of CPU this version of the library knows nothing 3177 * about. This shouldn't happen since the abi version check 3178 * should have caught this. 3179 */ 3180 errno = ENXIO; 3181 return (pmc_syscall = -1); 3182 } 3183 3184 return (0); 3185 } 3186 3187 const char * 3188 pmc_name_of_capability(enum pmc_caps cap) 3189 { 3190 int i; 3191 3192 /* 3193 * 'cap' should have a single bit set and should be in 3194 * range. 3195 */ 3196 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 3197 cap > PMC_CAP_LAST) { 3198 errno = EINVAL; 3199 return (NULL); 3200 } 3201 3202 i = ffs(cap); 3203 return (pmc_capability_names[i - 1]); 3204 } 3205 3206 const char * 3207 pmc_name_of_class(enum pmc_class pc) 3208 { 3209 if ((int) pc >= PMC_CLASS_FIRST && 3210 pc <= PMC_CLASS_LAST) 3211 return (pmc_class_names[pc]); 3212 3213 errno = EINVAL; 3214 return (NULL); 3215 } 3216 3217 const char * 3218 pmc_name_of_cputype(enum pmc_cputype cp) 3219 { 3220 size_t n; 3221 3222 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 3223 if (cp == pmc_cputype_names[n].pm_cputype) 3224 return (pmc_cputype_names[n].pm_name); 3225 3226 errno = EINVAL; 3227 return (NULL); 3228 } 3229 3230 const char * 3231 pmc_name_of_disposition(enum pmc_disp pd) 3232 { 3233 if ((int) pd >= PMC_DISP_FIRST && 3234 pd <= PMC_DISP_LAST) 3235 return (pmc_disposition_names[pd]); 3236 3237 errno = EINVAL; 3238 return (NULL); 3239 } 3240 3241 const char * 3242 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 3243 { 3244 const struct pmc_event_descr *ev, *evfence; 3245 3246 ev = evfence = NULL; 3247 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 3248 ev = iaf_event_table; 3249 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 3250 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 3251 switch (cpu) { 3252 case PMC_CPU_INTEL_ATOM: 3253 ev = atom_event_table; 3254 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 3255 break; 3256 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3257 ev = atom_silvermont_event_table; 3258 evfence = atom_silvermont_event_table + 3259 PMC_EVENT_TABLE_SIZE(atom_silvermont); 3260 break; 3261 case PMC_CPU_INTEL_CORE: 3262 ev = core_event_table; 3263 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 3264 break; 3265 case PMC_CPU_INTEL_CORE2: 3266 case PMC_CPU_INTEL_CORE2EXTREME: 3267 ev = core2_event_table; 3268 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 3269 break; 3270 case PMC_CPU_INTEL_COREI7: 3271 ev = corei7_event_table; 3272 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 3273 break; 3274 case PMC_CPU_INTEL_NEHALEM_EX: 3275 ev = nehalem_ex_event_table; 3276 evfence = nehalem_ex_event_table + 3277 PMC_EVENT_TABLE_SIZE(nehalem_ex); 3278 break; 3279 case PMC_CPU_INTEL_HASWELL: 3280 ev = haswell_event_table; 3281 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); 3282 break; 3283 case PMC_CPU_INTEL_IVYBRIDGE: 3284 ev = ivybridge_event_table; 3285 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); 3286 break; 3287 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3288 ev = ivybridge_xeon_event_table; 3289 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 3290 break; 3291 case PMC_CPU_INTEL_SANDYBRIDGE: 3292 ev = sandybridge_event_table; 3293 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 3294 break; 3295 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3296 ev = sandybridge_xeon_event_table; 3297 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 3298 break; 3299 case PMC_CPU_INTEL_WESTMERE: 3300 ev = westmere_event_table; 3301 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 3302 break; 3303 case PMC_CPU_INTEL_WESTMERE_EX: 3304 ev = westmere_ex_event_table; 3305 evfence = westmere_ex_event_table + 3306 PMC_EVENT_TABLE_SIZE(westmere_ex); 3307 break; 3308 default: /* Unknown CPU type. */ 3309 break; 3310 } 3311 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 3312 ev = ucf_event_table; 3313 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 3314 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 3315 switch (cpu) { 3316 case PMC_CPU_INTEL_COREI7: 3317 ev = corei7uc_event_table; 3318 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 3319 break; 3320 case PMC_CPU_INTEL_SANDYBRIDGE: 3321 ev = sandybridgeuc_event_table; 3322 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 3323 break; 3324 case PMC_CPU_INTEL_WESTMERE: 3325 ev = westmereuc_event_table; 3326 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 3327 break; 3328 default: /* Unknown CPU type. */ 3329 break; 3330 } 3331 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3332 ev = k7_event_table; 3333 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3334 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3335 ev = k8_event_table; 3336 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3337 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3338 ev = p4_event_table; 3339 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3340 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3341 ev = p5_event_table; 3342 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3343 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3344 ev = p6_event_table; 3345 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3346 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3347 ev = xscale_event_table; 3348 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3349 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3350 ev = mips24k_event_table; 3351 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 3352 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 3353 ev = octeon_event_table; 3354 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 3355 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3356 ev = ppc7450_event_table; 3357 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 3358 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 3359 ev = ppc970_event_table; 3360 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 3361 } else if (pe == PMC_EV_TSC_TSC) { 3362 ev = tsc_event_table; 3363 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3364 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 3365 ev = soft_event_table; 3366 evfence = soft_event_table + soft_event_info.pm_nevent; 3367 } 3368 3369 for (; ev != evfence; ev++) 3370 if (pe == ev->pm_ev_code) 3371 return (ev->pm_ev_name); 3372 3373 return (NULL); 3374 } 3375 3376 const char * 3377 pmc_name_of_event(enum pmc_event pe) 3378 { 3379 const char *n; 3380 3381 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3382 return (n); 3383 3384 errno = EINVAL; 3385 return (NULL); 3386 } 3387 3388 const char * 3389 pmc_name_of_mode(enum pmc_mode pm) 3390 { 3391 if ((int) pm >= PMC_MODE_FIRST && 3392 pm <= PMC_MODE_LAST) 3393 return (pmc_mode_names[pm]); 3394 3395 errno = EINVAL; 3396 return (NULL); 3397 } 3398 3399 const char * 3400 pmc_name_of_state(enum pmc_state ps) 3401 { 3402 if ((int) ps >= PMC_STATE_FIRST && 3403 ps <= PMC_STATE_LAST) 3404 return (pmc_state_names[ps]); 3405 3406 errno = EINVAL; 3407 return (NULL); 3408 } 3409 3410 int 3411 pmc_ncpu(void) 3412 { 3413 if (pmc_syscall == -1) { 3414 errno = ENXIO; 3415 return (-1); 3416 } 3417 3418 return (cpu_info.pm_ncpu); 3419 } 3420 3421 int 3422 pmc_npmc(int cpu) 3423 { 3424 if (pmc_syscall == -1) { 3425 errno = ENXIO; 3426 return (-1); 3427 } 3428 3429 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3430 errno = EINVAL; 3431 return (-1); 3432 } 3433 3434 return (cpu_info.pm_npmc); 3435 } 3436 3437 int 3438 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3439 { 3440 int nbytes, npmc; 3441 struct pmc_op_getpmcinfo *pmci; 3442 3443 if ((npmc = pmc_npmc(cpu)) < 0) 3444 return (-1); 3445 3446 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3447 npmc * sizeof(struct pmc_info); 3448 3449 if ((pmci = calloc(1, nbytes)) == NULL) 3450 return (-1); 3451 3452 pmci->pm_cpu = cpu; 3453 3454 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3455 free(pmci); 3456 return (-1); 3457 } 3458 3459 /* kernel<->library, library<->userland interfaces are identical */ 3460 *ppmci = (struct pmc_pmcinfo *) pmci; 3461 return (0); 3462 } 3463 3464 int 3465 pmc_read(pmc_id_t pmc, pmc_value_t *value) 3466 { 3467 struct pmc_op_pmcrw pmc_read_op; 3468 3469 pmc_read_op.pm_pmcid = pmc; 3470 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3471 pmc_read_op.pm_value = -1; 3472 3473 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3474 return (-1); 3475 3476 *value = pmc_read_op.pm_value; 3477 return (0); 3478 } 3479 3480 int 3481 pmc_release(pmc_id_t pmc) 3482 { 3483 struct pmc_op_simple pmc_release_args; 3484 3485 pmc_release_args.pm_pmcid = pmc; 3486 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3487 } 3488 3489 int 3490 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3491 { 3492 struct pmc_op_pmcrw pmc_rw_op; 3493 3494 pmc_rw_op.pm_pmcid = pmc; 3495 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3496 pmc_rw_op.pm_value = newvalue; 3497 3498 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3499 return (-1); 3500 3501 *oldvaluep = pmc_rw_op.pm_value; 3502 return (0); 3503 } 3504 3505 int 3506 pmc_set(pmc_id_t pmc, pmc_value_t value) 3507 { 3508 struct pmc_op_pmcsetcount sc; 3509 3510 sc.pm_pmcid = pmc; 3511 sc.pm_count = value; 3512 3513 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3514 return (-1); 3515 return (0); 3516 } 3517 3518 int 3519 pmc_start(pmc_id_t pmc) 3520 { 3521 struct pmc_op_simple pmc_start_args; 3522 3523 pmc_start_args.pm_pmcid = pmc; 3524 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3525 } 3526 3527 int 3528 pmc_stop(pmc_id_t pmc) 3529 { 3530 struct pmc_op_simple pmc_stop_args; 3531 3532 pmc_stop_args.pm_pmcid = pmc; 3533 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3534 } 3535 3536 int 3537 pmc_width(pmc_id_t pmcid, uint32_t *width) 3538 { 3539 unsigned int i; 3540 enum pmc_class cl; 3541 3542 cl = PMC_ID_TO_CLASS(pmcid); 3543 for (i = 0; i < cpu_info.pm_nclass; i++) 3544 if (cpu_info.pm_classes[i].pm_class == cl) { 3545 *width = cpu_info.pm_classes[i].pm_width; 3546 return (0); 3547 } 3548 errno = EINVAL; 3549 return (-1); 3550 } 3551 3552 int 3553 pmc_write(pmc_id_t pmc, pmc_value_t value) 3554 { 3555 struct pmc_op_pmcrw pmc_write_op; 3556 3557 pmc_write_op.pm_pmcid = pmc; 3558 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3559 pmc_write_op.pm_value = value; 3560 return (PMC_CALL(PMCRW, &pmc_write_op)); 3561 } 3562 3563 int 3564 pmc_writelog(uint32_t userdata) 3565 { 3566 struct pmc_op_writelog wl; 3567 3568 wl.pm_userdata = userdata; 3569 return (PMC_CALL(WRITELOG, &wl)); 3570 } 3571