1 2CRTARCH= ${MACHINE_CPUARCH:C/amd64/x86_64/:C/powerpc/ppc/} 3.info DIMDBG: CRTARCH=${CRTARCH} 4 5CRTSRC= ${SRCTOP}/contrib/llvm-project/compiler-rt/lib/builtins 6 7.PATH: ${CRTSRC}/${CRTARCH} 8.PATH: ${CRTSRC} 9 10SRCF+= absvdi2 11SRCF+= absvsi2 12SRCF+= absvti2 13SRCF+= addvdi3 14SRCF+= addvsi3 15SRCF+= addvti3 16SRCF+= apple_versioning 17SRCF+= ashldi3 18SRCF+= ashlti3 19SRCF+= ashrdi3 20SRCF+= ashrti3 21SRCF+= bswapdi2 22SRCF+= bswapsi2 23SRCF+= clear_cache 24SRCF+= clzdi2 25SRCF+= clzsi2 26SRCF+= clzti2 27SRCF+= cmpdi2 28SRCF+= cmpti2 29SRCF+= ctzdi2 30SRCF+= ctzsi2 31SRCF+= ctzti2 32SRCF+= divdc3 33SRCF+= divdi3 34SRCF+= divmoddi4 35SRCF+= divmodsi4 36SRCF+= divmodti4 37SRCF+= divsc3 38SRCF+= divsi3 39SRCF+= divti3 40SRCF+= enable_execute_stack 41SRCF+= extendhfsf2 42SRCF+= ffsdi2 43SRCF+= ffssi2 44SRCF+= ffsti2 45SRCF+= fixdfdi 46SRCF+= fixdfti 47SRCF+= fixsfdi 48SRCF+= fixsfti 49SRCF+= fixunsdfdi 50SRCF+= fixunsdfsi 51SRCF+= fixunsdfti 52SRCF+= fixunssfdi 53SRCF+= fixunssfsi 54SRCF+= fixunssfti 55SRCF+= floattidf 56SRCF+= floattisf 57SRCF+= floatunsidf 58SRCF+= floatunsisf 59SRCF+= floatuntidf 60SRCF+= floatuntisf 61SRCF+= int_util 62SRCF+= lshrdi3 63SRCF+= lshrti3 64SRCF+= moddi3 65SRCF+= modsi3 66SRCF+= modti3 67SRCF+= muldc3 68SRCF+= muldi3 69SRCF+= mulodi4 70SRCF+= mulosi4 71SRCF+= muloti4 72SRCF+= mulsc3 73SRCF+= multi3 74SRCF+= mulvdi3 75SRCF+= mulvsi3 76SRCF+= mulvti3 77SRCF+= negdf2 78SRCF+= negdi2 79SRCF+= negsf2 80SRCF+= negti2 81SRCF+= negvdi2 82SRCF+= negvsi2 83SRCF+= negvti2 84SRCF+= paritydi2 85SRCF+= paritysi2 86SRCF+= parityti2 87SRCF+= popcountdi2 88SRCF+= popcountsi2 89SRCF+= popcountti2 90SRCF+= powidf2 91SRCF+= powisf2 92SRCF+= subvdi3 93SRCF+= subvsi3 94SRCF+= subvti3 95SRCF+= trampoline_setup 96SRCF+= truncdfhf2 97SRCF+= truncsfhf2 98SRCF+= ucmpdi2 99SRCF+= ucmpti2 100SRCF+= udivdi3 101SRCF+= udivmoddi4 102SRCF+= udivmodsi4 103SRCF+= udivmodti4 104SRCF+= udivsi3 105SRCF+= udivti3 106SRCF+= umoddi3 107SRCF+= umodsi3 108SRCF+= umodti3 109 110# Enable compiler-rt's atomic implementation only for clang, as it uses clang 111# specific builtins, and gcc packages usually come with their own libatomic. 112# Exclude arm which has its own implementations of atomic functions, below. 113.if "${COMPILER_TYPE}" == "clang" && ${MACHINE_CPUARCH} != "arm" 114SRCF+= atomic 115.endif 116 117# Avoid using SSE2 instructions on i386, if unsupported. 118.if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2) 119SRCS+= floatdidf.c 120SRCS+= floatdisf.c 121SRCS+= floatundidf.c 122SRCS+= floatundisf.c 123.else 124SRCF+= floatdidf 125SRCF+= floatdisf 126SRCF+= floatundidf 127SRCF+= floatundisf 128.endif 129 130# 131# 80-bit long double functions, only used on x86. 132# 133.if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" 134.info DIMDBG: Enabling 80-bit long double 135SRCF+= divxc3 136SRCF+= extendxftf2 137SRCF+= fixxfdi 138SRCF+= fixxfti 139SRCF+= fixunsxfdi 140SRCF+= fixunsxfsi 141SRCF+= fixunsxfti 142SRCF+= floattixf 143SRCF+= floatuntixf 144SRCF+= mulxc3 145SRCF+= powixf2 146SRCF+= trunctfxf2 147 148# Avoid using SSE2 instructions on i386, if unsupported. 149.if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2) 150SRCS+= floatdixf.c 151SRCS+= floatundixf.c 152.else 153SRCF+= floatdixf 154SRCF+= floatundixf 155.endif 156.else 157.info DIMDBG: NOT enabling 80-bit long double 158.endif 159 160# __cpu_model support, only used on aarch64 and x86 161.if ${MACHINE_CPUARCH} == "aarch64" 162SRCS+= cpu_model/aarch64.c 163.elif ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" 164SRCS+= cpu_model/x86.c 165.endif 166 167# The fp_mode implementation for amd64 and i386 is shared, while other 168# architectures use the regular approach. 169.if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" 170SRCS+= i386/fp_mode.c 171.else 172SRCF+= fp_mode 173.endif 174 175# 176# 128-bit quad precision long double support, 177# only used on some architectures. 178# 179.if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ 180 ${MACHINE_CPUARCH} == "riscv" 181.info DIMDBG: Enabling 128-bit quad precision 182SRCF+= addtf3 183SRCF+= comparetf2 184SRCF+= divtc3 185SRCF+= divtf3 186SRCF+= extenddftf2 187SRCF+= extendhftf2 188SRCF+= extendsftf2 189SRCF+= fixtfdi 190SRCF+= fixtfsi 191SRCF+= fixtfti 192SRCF+= fixunstfdi 193SRCF+= fixunstfsi 194SRCF+= fixunstfti 195SRCF+= floatditf 196SRCF+= floatsitf 197SRCF+= floattitf 198SRCF+= floatunditf 199SRCF+= floatunsitf 200SRCF+= floatuntitf 201SRCF+= multc3 202SRCF+= multf3 203SRCF+= powitf2 204SRCF+= subtf3 205SRCF+= trunctfdf2 206SRCF+= trunctfhf2 207SRCF+= trunctfsf2 208.else 209.info DIMDBG: NOT enabling 128-bit quad precision 210.endif 211 212# These are already shipped by libc.a on some architectures. 213.if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "riscv" 214SRCF+= adddf3 215SRCF+= addsf3 216SRCF+= divdf3 217SRCF+= divsf3 218SRCF+= extendsfdf2 219SRCF+= fixdfsi 220SRCF+= fixsfsi 221SRCF+= floatsidf 222SRCF+= floatsisf 223SRCF+= muldf3 224SRCF+= mulsf3 225SRCF+= subdf3 226SRCF+= subsf3 227SRCF+= truncdfsf2 228.endif 229 230.if ${MACHINE_CPUARCH} != "arm" 231SRCF+= comparedf2 232SRCF+= comparesf2 233.endif 234 235# 236# bfloat16 support, only used on some architectures. 237# 238.if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ 239 ${MACHINE_CPUARCH} == "arm" || (${MACHINE_CPUARCH} == "i386" && \ 240 !empty(MACHINE_CPU:Msse2)) || ${MACHINE_CPUARCH} == "riscv" 241SRCF+= truncdfbf2 242SRCF+= truncsfbf2 243.endif 244 245# FreeBSD-specific atomic intrinsics. 246.if ${MACHINE_CPUARCH} == "arm" 247.PATH: ${SRCTOP}/sys/arm/arm 248 249SRCF+= stdatomic 250CFLAGS+= -DEMIT_SYNC_ATOMICS 251.endif 252 253.for file in ${SRCF} 254.if ${MACHINE_CPUARCH} == "arm" && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") \ 255 && exists(${CRTSRC}/${CRTARCH}/${file}vfp.S) 256SRCS+= ${file}vfp.S 257. elif exists(${CRTSRC}/${CRTARCH}/${file}.S) 258SRCS+= ${file}.S 259. else 260SRCS+= ${file}.c 261. endif 262.endfor 263 264.if ${MACHINE_CPUARCH} == "arm" 265SRCS+= aeabi_div0.c 266SRCS+= aeabi_idivmod.S 267SRCS+= aeabi_ldivmod.S 268SRCS+= aeabi_memcmp.S 269SRCS+= aeabi_memcpy.S 270SRCS+= aeabi_memmove.S 271SRCS+= aeabi_memset.S 272SRCS+= aeabi_uidivmod.S 273SRCS+= aeabi_uldivmod.S 274SRCS+= switch16.S 275SRCS+= switch32.S 276SRCS+= switch8.S 277SRCS+= switchu8.S 278SRCS+= sync_synchronize.S 279.endif 280