xref: /freebsd/lib/libc/arm/gen/arm_sync_icache.2 (revision fa9896e082a1046ff4fbc75fcba4d18d1f2efc19)
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24*805eb13aSIan Lepore.Dd July 10, 2019
25*805eb13aSIan Lepore.Dt ARM_sync_icache 2
26*805eb13aSIan Lepore.Os
27*805eb13aSIan Lepore.Sh NAME
28*805eb13aSIan Lepore.Nm arm_sync_icache
29*805eb13aSIan Lepore.Nd synchronize the data and instruction caches
30*805eb13aSIan Lepore.Sh LIBRARY
31*805eb13aSIan Lepore.Lb libc
32*805eb13aSIan Lepore.Sh SYNOPSIS
33*805eb13aSIan Lepore.In machine/sysarch.h
34*805eb13aSIan Lepore.Ft int
35*805eb13aSIan Lepore.Fn arm_sync_icache "u_int addr" "int len"
36*805eb13aSIan Lepore.Sh DESCRIPTION
37*805eb13aSIan LeporeThe
38*805eb13aSIan Lepore.Nm
39*805eb13aSIan Leporesystem call synchronizes the contents of any data and instructions caches
40*805eb13aSIan Leporewith the contents of main memory for the given range.
41*805eb13aSIan LeporeUse this after loading executable code or modifying existing code in memory,
42*805eb13aSIan Leporebefore attempting to execute that code.
43*805eb13aSIan Lepore.Pp
44*805eb13aSIan LeporeThe
45*805eb13aSIan Lepore.Va addr
46*805eb13aSIan Leporeand
47*805eb13aSIan Lepore.Va len
48*805eb13aSIan Leporearguments do not need to be aligned to any particular boundary, but
49*805eb13aSIan Leporecache operations will affect entire cache lines, even those which are only
50*805eb13aSIan Leporepartially overlapped by the given range.
51*805eb13aSIan Lepore.Pp
52*805eb13aSIan LeporeThis takes one or more of the following actions, depending on the requirements
53*805eb13aSIan Leporeof the hardware:
54*805eb13aSIan Lepore.Bl -bullet
55*805eb13aSIan Lepore.It
56*805eb13aSIan LeporeWrite dirty data cache lines within the range back to main memory.
57*805eb13aSIan Lepore.It
58*805eb13aSIan LeporeInvalidate existing instruction cache contents for the range.
59*805eb13aSIan Lepore.It
60*805eb13aSIan LeporeInvalidate branch prediction caches for the range.
61*805eb13aSIan Lepore.El
62*805eb13aSIan Lepore.Pp
63*805eb13aSIan LeporeOn hardware which supports multiple synchronization points for cache
64*805eb13aSIan Leporeoperations, the caches are maintained to the point of unification,
65*805eb13aSIan Leporemaking the data in the range coherent amongst all cores.
66*805eb13aSIan Lepore.Sh RETURN VALUES
67*805eb13aSIan LeporeThe
68*805eb13aSIan Lepore.Nm
69*805eb13aSIan Leporesystem call always returns 0.
70*805eb13aSIan Lepore.Sh ERRORS
71*805eb13aSIan LeporeIf a call refers to memory which the calling process does not have rights
72*805eb13aSIan Leporeto access, or if the
73*805eb13aSIan Lepore.Va len
74*805eb13aSIan Leporeargument is negative, a SIGSEGV signal is delivered to the calling thread.
75*805eb13aSIan Lepore.Sh AUTHORS
76*805eb13aSIan LeporeThis man page was written by
77*805eb13aSIan Lepore.An Ian Lepore .
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