1.\" Copyright (c) 2019 Ian Lepore <ian@FreeBSD.org> 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd July 10, 2019 25.Dt ARM_DRAIN_WRITEBUF 2 26.Os 27.Sh NAME 28.Nm arm_drain_writebuf 29.Nd drain pending writes from cores and caches 30.Sh LIBRARY 31.Lb libc 32.Sh SYNOPSIS 33.In machine/sysarch.h 34.Ft int 35.Fn arm_drain_writebuf void 36.Sh DESCRIPTION 37The 38.Nm 39system call causes all pending writes from ARM cores and caches to be 40written out to main memory or memory-mapped I/O registers. 41Not all hardware supports buffered writes; on such systems the 42.Nm 43function is a no-op. 44.Pp 45On ARMv5 systems, this executes a cp15 coprocessor 46.Dq drain write buffer 47operation. 48On ARMv6 and ARMv7 systems, this executes a 49.Dq DSB SY 50synchronization barrier, followed by an L2 cache drain on 51systems where the DSB does not include L2 automatically. 52.Pp 53.Nm 54attempts to wait for the drain operation to complete, but cannot 55guarantee the writes have reached their ultimate destination on all hardware. 56For example, on an ARMv7 system, 57.Nm 58tells the L2 cache controller to drain its buffers, and it waits until 59the controller indicates that operation is complete. 60However, all the L2 controller knows is that the data was accepted for 61delivery by the AXI bus. 62If the ultimate destination of the write is a device on a subordinate 63bus connected to the AXI bus, more buffering or other delays may occur 64on that subordinate bus. 65The only way to be certain a pending write has reached its 66ultimate destination is to issue a read from that destination after 67.Nm 68returns. 69.Sh RETURN VALUES 70The 71.Nm 72system call cannot fail, and always returns 0. 73.Sh AUTHORS 74This man page was written by 75.An Ian Lepore . 76