1*805eb13aSIan Lepore.\" Copyright (c) 2019 Ian Lepore <ian@FreeBSD.org> 2*805eb13aSIan Lepore.\" 3*805eb13aSIan Lepore.\" Redistribution and use in source and binary forms, with or without 4*805eb13aSIan Lepore.\" modification, are permitted provided that the following conditions 5*805eb13aSIan Lepore.\" are met: 6*805eb13aSIan Lepore.\" 1. Redistributions of source code must retain the above copyright 7*805eb13aSIan Lepore.\" notice, this list of conditions and the following disclaimer. 8*805eb13aSIan Lepore.\" 2. Redistributions in binary form must reproduce the above copyright 9*805eb13aSIan Lepore.\" notice, this list of conditions and the following disclaimer in the 10*805eb13aSIan Lepore.\" documentation and/or other materials provided with the distribution. 11*805eb13aSIan Lepore.\" 12*805eb13aSIan Lepore.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 13*805eb13aSIan Lepore.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14*805eb13aSIan Lepore.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15*805eb13aSIan Lepore.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 16*805eb13aSIan Lepore.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17*805eb13aSIan Lepore.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18*805eb13aSIan Lepore.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19*805eb13aSIan Lepore.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20*805eb13aSIan Lepore.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21*805eb13aSIan Lepore.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22*805eb13aSIan Lepore.\" SUCH DAMAGE. 23*805eb13aSIan Lepore.\" 24*805eb13aSIan Lepore.\" $FreeBSD$ 25*805eb13aSIan Lepore.\" 26*805eb13aSIan Lepore.Dd July 10, 2019 27*805eb13aSIan Lepore.Dt ARM_DRAIN_WRITEBUF 2 28*805eb13aSIan Lepore.Os 29*805eb13aSIan Lepore.Sh NAME 30*805eb13aSIan Lepore.Nm arm_drain_writebuf 31*805eb13aSIan Lepore.Nd drain pending writes from cores and caches 32*805eb13aSIan Lepore.Sh LIBRARY 33*805eb13aSIan Lepore.Lb libc 34*805eb13aSIan Lepore.Sh SYNOPSIS 35*805eb13aSIan Lepore.In machine/sysarch.h 36*805eb13aSIan Lepore.Ft int 37*805eb13aSIan Lepore.Fn arm_drain_writebuf void 38*805eb13aSIan Lepore.Sh DESCRIPTION 39*805eb13aSIan LeporeThe 40*805eb13aSIan Lepore.Nm 41*805eb13aSIan Leporesystem call causes all pending writes from ARM cores and caches to be 42*805eb13aSIan Leporewritten out to main memory or memory-mapped I/O registers. 43*805eb13aSIan LeporeNot all hardware supports buffered writes; on such systems the 44*805eb13aSIan Lepore.Nm 45*805eb13aSIan Leporefunction is a no-op. 46*805eb13aSIan Lepore.Pp 47*805eb13aSIan LeporeOn ARMv5 systems, this executes a cp15 coprocessor 48*805eb13aSIan Lepore.Dq drain write buffer 49*805eb13aSIan Leporeoperation. 50*805eb13aSIan LeporeOn ARMv6 and ARMv7 systems, this executes a 51*805eb13aSIan Lepore.Dq DSB SY 52*805eb13aSIan Leporesynchronization barrier, followed by an L2 cache drain on 53*805eb13aSIan Leporesystems where the DSB does not include L2 automatically. 54*805eb13aSIan Lepore.Pp 55*805eb13aSIan Lepore.Nm 56*805eb13aSIan Leporeattempts to wait for the drain operation to complete, but cannot 57*805eb13aSIan Leporeguarantee the writes have reached their ultimate destination on all hardware. 58*805eb13aSIan LeporeFor example, on an ARMv7 system, 59*805eb13aSIan Lepore.Nm 60*805eb13aSIan Leporetells the L2 cache controller to drain its buffers, and it waits until 61*805eb13aSIan Leporethe controller indicates that operation is complete. 62*805eb13aSIan LeporeHowever, all the L2 controller knows is that the data was accepted for 63*805eb13aSIan Leporedelivery by the AXI bus. 64*805eb13aSIan LeporeIf the ultimate destination of the write is a device on a subordinate 65*805eb13aSIan Leporebus connected to the AXI bus, more buffering or other delays may occur 66*805eb13aSIan Leporeon that subordinate bus. 67*805eb13aSIan LeporeThe only way to be certain a pending write has reached its 68*805eb13aSIan Leporeultimate destination is to issue a read from that destination after 69*805eb13aSIan Lepore.Nm 70*805eb13aSIan Leporereturns. 71*805eb13aSIan Lepore.Sh RETURN VALUES 72*805eb13aSIan LeporeThe 73*805eb13aSIan Lepore.Nm 74*805eb13aSIan Leporesystem call cannot fail, and always returns 0. 75*805eb13aSIan Lepore.Sh AUTHORS 76*805eb13aSIan LeporeThis man page was written by 77*805eb13aSIan Lepore.An Ian Lepore . 78