1 /* 2 * Copyright (c) 2013-2019, Intel Corporation 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * * Redistributions of source code must retain the above copyright notice, 8 * this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright notice, 10 * this list of conditions and the following disclaimer in the documentation 11 * and/or other materials provided with the distribution. 12 * * Neither the name of Intel Corporation nor the names of its contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PT_OPCODES_H 30 #define PT_OPCODES_H 31 32 33 /* A one byte opcode. */ 34 enum pt_opcode { 35 pt_opc_pad = 0x00, 36 pt_opc_ext = 0x02, 37 pt_opc_psb = pt_opc_ext, 38 pt_opc_tip = 0x0d, 39 pt_opc_tnt_8 = 0x00, 40 pt_opc_tip_pge = 0x11, 41 pt_opc_tip_pgd = 0x01, 42 pt_opc_fup = 0x1d, 43 pt_opc_mode = 0x99, 44 pt_opc_tsc = 0x19, 45 pt_opc_mtc = 0x59, 46 pt_opc_cyc = 0x03, 47 48 /* A free opcode to trigger a decode fault. */ 49 pt_opc_bad = 0xd9 50 }; 51 52 /* A one byte extension code for ext opcodes. */ 53 enum pt_ext_code { 54 pt_ext_psb = 0x82, 55 pt_ext_tnt_64 = 0xa3, 56 pt_ext_pip = 0x43, 57 pt_ext_ovf = 0xf3, 58 pt_ext_psbend = 0x23, 59 pt_ext_cbr = 0x03, 60 pt_ext_tma = 0x73, 61 pt_ext_stop = 0x83, 62 pt_ext_vmcs = 0xc8, 63 pt_ext_ext2 = 0xc3, 64 pt_ext_exstop = 0x62, 65 pt_ext_exstop_ip = 0xe2, 66 pt_ext_mwait = 0xc2, 67 pt_ext_pwre = 0x22, 68 pt_ext_pwrx = 0xa2, 69 pt_ext_ptw = 0x12, 70 71 pt_ext_bad = 0x04 72 }; 73 74 /* A one byte extension 2 code for ext2 extension opcodes. */ 75 enum pt_ext2_code { 76 pt_ext2_mnt = 0x88, 77 78 pt_ext2_bad = 0x00 79 }; 80 81 /* A one byte opcode mask. */ 82 enum pt_opcode_mask { 83 pt_opm_tip = 0x1f, 84 pt_opm_tnt_8 = 0x01, 85 pt_opm_tnt_8_shr = 1, 86 pt_opm_fup = pt_opm_tip, 87 88 /* The bit mask for the compression bits in the opcode. */ 89 pt_opm_ipc = 0xe0, 90 91 /* The shift right value for ipc bits. */ 92 pt_opm_ipc_shr = 5, 93 94 /* The bit mask for the compression bits after shifting. */ 95 pt_opm_ipc_shr_mask = 0x7, 96 97 /* Shift counts and masks for decoding the cyc packet. */ 98 pt_opm_cyc = 0x03, 99 pt_opm_cyc_ext = 0x04, 100 pt_opm_cyc_bits = 0xf8, 101 pt_opm_cyc_shr = 3, 102 pt_opm_cycx_ext = 0x01, 103 pt_opm_cycx_shr = 1, 104 105 /* The bit mask for the IP bit in the exstop packet. */ 106 pt_opm_exstop_ip = 0x80, 107 108 /* The PTW opcode. */ 109 pt_opm_ptw = 0x1f, 110 111 /* The bit mask for the IP bit in the ptw packet. */ 112 pt_opm_ptw_ip = 0x80, 113 114 /* The bit mask and shr value for the payload bytes field in ptw. */ 115 pt_opm_ptw_pb = 0x60, 116 pt_opm_ptw_pb_shr = 5, 117 118 /* The bit mask for the payload bytes field in ptw after shifting. */ 119 pt_opm_ptw_pb_shr_mask = 0x3 120 }; 121 122 /* The size of the various opcodes in bytes. */ 123 enum pt_opcode_size { 124 pt_opcs_pad = 1, 125 pt_opcs_tip = 1, 126 pt_opcs_tip_pge = 1, 127 pt_opcs_tip_pgd = 1, 128 pt_opcs_fup = 1, 129 pt_opcs_tnt_8 = 1, 130 pt_opcs_mode = 1, 131 pt_opcs_tsc = 1, 132 pt_opcs_mtc = 1, 133 pt_opcs_cyc = 1, 134 pt_opcs_psb = 2, 135 pt_opcs_psbend = 2, 136 pt_opcs_ovf = 2, 137 pt_opcs_pip = 2, 138 pt_opcs_tnt_64 = 2, 139 pt_opcs_cbr = 2, 140 pt_opcs_tma = 2, 141 pt_opcs_stop = 2, 142 pt_opcs_vmcs = 2, 143 pt_opcs_mnt = 3, 144 pt_opcs_exstop = 2, 145 pt_opcs_mwait = 2, 146 pt_opcs_pwre = 2, 147 pt_opcs_pwrx = 2, 148 pt_opcs_ptw = 2 149 }; 150 151 /* The psb magic payload. 152 * 153 * The payload is a repeating 2-byte pattern. 154 */ 155 enum pt_psb_pattern { 156 /* The high and low bytes in the pattern. */ 157 pt_psb_hi = pt_opc_psb, 158 pt_psb_lo = pt_ext_psb, 159 160 /* Various combinations of the above parts. */ 161 pt_psb_lohi = pt_psb_lo | pt_psb_hi << 8, 162 pt_psb_hilo = pt_psb_hi | pt_psb_lo << 8, 163 164 /* The repeat count of the payload, not including opc and ext. */ 165 pt_psb_repeat_count = 7, 166 167 /* The size of the repeated pattern in bytes. */ 168 pt_psb_repeat_size = 2 169 }; 170 171 /* The payload details. */ 172 enum pt_payload { 173 /* The shift counts for post-processing the PIP payload. */ 174 pt_pl_pip_shr = 1, 175 pt_pl_pip_shl = 5, 176 177 /* The size of a PIP payload in bytes. */ 178 pt_pl_pip_size = 6, 179 180 /* The non-root bit in the first byte of the PIP payload. */ 181 pt_pl_pip_nr = 0x01, 182 183 /* The size of a 8bit TNT packet's payload in bits. */ 184 pt_pl_tnt_8_bits = 8 - pt_opm_tnt_8_shr, 185 186 /* The size of a 64bit TNT packet's payload in bytes. */ 187 pt_pl_tnt_64_size = 6, 188 189 /* The size of a 64bit TNT packet's payload in bits. */ 190 pt_pl_tnt_64_bits = 48, 191 192 /* The size of a TSC packet's payload in bytes and in bits. */ 193 pt_pl_tsc_size = 7, 194 pt_pl_tsc_bit_size = pt_pl_tsc_size * 8, 195 196 /* The size of a CBR packet's payload in bytes. */ 197 pt_pl_cbr_size = 2, 198 199 /* The size of a PSB packet's payload in bytes. */ 200 pt_pl_psb_size = pt_psb_repeat_count * pt_psb_repeat_size, 201 202 /* The size of a MODE packet's payload in bytes. */ 203 pt_pl_mode_size = 1, 204 205 /* The size of an IP packet's payload with update-16 compression. */ 206 pt_pl_ip_upd16_size = 2, 207 208 /* The size of an IP packet's payload with update-32 compression. */ 209 pt_pl_ip_upd32_size = 4, 210 211 /* The size of an IP packet's payload with update-48 compression. */ 212 pt_pl_ip_upd48_size = 6, 213 214 /* The size of an IP packet's payload with sext-48 compression. */ 215 pt_pl_ip_sext48_size = 6, 216 217 /* The size of an IP packet's payload with full-ip compression. */ 218 pt_pl_ip_full_size = 8, 219 220 /* Byte locations, sizes, and masks for processing TMA packets. */ 221 pt_pl_tma_size = 5, 222 pt_pl_tma_ctc_size = 2, 223 pt_pl_tma_ctc_bit_size = pt_pl_tma_ctc_size * 8, 224 pt_pl_tma_ctc_0 = 2, 225 pt_pl_tma_ctc_1 = 3, 226 pt_pl_tma_ctc_mask = (1 << pt_pl_tma_ctc_bit_size) - 1, 227 pt_pl_tma_fc_size = 2, 228 pt_pl_tma_fc_bit_size = 9, 229 pt_pl_tma_fc_0 = 5, 230 pt_pl_tma_fc_1 = 6, 231 pt_pl_tma_fc_mask = (1 << pt_pl_tma_fc_bit_size) - 1, 232 233 /* The size of a MTC packet's payload in bytes and in bits. */ 234 pt_pl_mtc_size = 1, 235 pt_pl_mtc_bit_size = pt_pl_mtc_size * 8, 236 237 /* A mask for the MTC payload bits. */ 238 pt_pl_mtc_mask = (1 << pt_pl_mtc_bit_size) - 1, 239 240 /* The maximal payload size in bytes of a CYC packet. */ 241 pt_pl_cyc_max_size = 15, 242 243 /* The size of a VMCS packet's payload in bytes. */ 244 pt_pl_vmcs_size = 5, 245 246 /* The shift counts for post-processing the VMCS payload. */ 247 pt_pl_vmcs_shl = 12, 248 249 /* The size of a MNT packet's payload in bytes. */ 250 pt_pl_mnt_size = 8, 251 252 /* The bit-mask for the IP bit in the EXSTOP opcode extension. */ 253 pt_pl_exstop_ip_mask = 0x80, 254 255 /* The size of the hints field in the MWAIT payload in bytes. */ 256 pt_pl_mwait_hints_size = 4, 257 258 /* The size of the extensions field in the MWAIT payload in bytes. */ 259 pt_pl_mwait_ext_size = 4, 260 261 /* The size of the MWAIT payload in bytes. */ 262 pt_pl_mwait_size = pt_pl_mwait_hints_size + pt_pl_mwait_ext_size, 263 264 /* The size of the PWRE payload in bytes. */ 265 pt_pl_pwre_size = 2, 266 267 /* The bit-mask for the h/w bit in the PWRE payload. */ 268 pt_pl_pwre_hw_mask = 0x8, 269 270 /* The bit-mask for the resolved thread sub C-state in the PWRE 271 * payload. 272 */ 273 pt_pl_pwre_sub_state_mask = 0xf00, 274 275 /* The shift right value for the resolved thread sub C-state in the 276 * PWRE payload. 277 */ 278 pt_pl_pwre_sub_state_shr = 8, 279 280 /* The bit-mask for the resolved thread C-state in the PWRE payload. */ 281 pt_pl_pwre_state_mask = 0xf000, 282 283 /* The shift right value for the resolved thread C-state in the 284 * PWRE payload. 285 */ 286 pt_pl_pwre_state_shr = 12, 287 288 /* The size of the PWRX payload in bytes. */ 289 pt_pl_pwrx_size = 5, 290 291 /* The bit-mask for the deepest core C-state in the PWRX payload. */ 292 pt_pl_pwrx_deepest_mask = 0xf, 293 294 /* The shift right value for the deepest core C-state in the PWRX 295 * payload. 296 */ 297 pt_pl_pwrx_deepest_shr = 0, 298 299 /* The bit-mask for the last core C-state in the PWRX payload. */ 300 pt_pl_pwrx_last_mask = 0xf0, 301 302 /* The shift right value for the last core C-state in the PWRX 303 * payload. 304 */ 305 pt_pl_pwrx_last_shr = 4, 306 307 /* The bit-mask for the wake reason in the PWRX payload. */ 308 pt_pl_pwrx_wr_mask = 0xf00, 309 310 /* The shift right value for the wake reason in the PWRX payload. */ 311 pt_pl_pwrx_wr_shr = 8, 312 313 /* The bit-mask for the interrupt wake reason in the PWRX payload. */ 314 pt_pl_pwrx_wr_int = 0x100, 315 316 /* The bit-mask for the store wake reason in the PWRX payload. */ 317 pt_pl_pwrx_wr_store = 0x400, 318 319 /* The bit-mask for the autonomous wake reason in the PWRX payload. */ 320 pt_pl_pwrx_wr_hw = 0x800 321 }; 322 323 /* Mode packet masks. */ 324 enum pt_mode_mask { 325 pt_mom_leaf = 0xe0, 326 pt_mom_leaf_shr = 5, 327 pt_mom_bits = 0x1f 328 }; 329 330 /* Mode packet bits. */ 331 enum pt_mode_bit { 332 /* mode.exec */ 333 pt_mob_exec_csl = 0x01, 334 pt_mob_exec_csd = 0x02, 335 336 /* mode.tsx */ 337 pt_mob_tsx_intx = 0x01, 338 pt_mob_tsx_abrt = 0x02 339 }; 340 341 /* The size of the various packets in bytes. */ 342 enum pt_packet_size { 343 ptps_pad = pt_opcs_pad, 344 ptps_tnt_8 = pt_opcs_tnt_8, 345 ptps_mode = pt_opcs_mode + pt_pl_mode_size, 346 ptps_tsc = pt_opcs_tsc + pt_pl_tsc_size, 347 ptps_mtc = pt_opcs_mtc + pt_pl_mtc_size, 348 ptps_psb = pt_opcs_psb + pt_pl_psb_size, 349 ptps_psbend = pt_opcs_psbend, 350 ptps_ovf = pt_opcs_ovf, 351 ptps_pip = pt_opcs_pip + pt_pl_pip_size, 352 ptps_tnt_64 = pt_opcs_tnt_64 + pt_pl_tnt_64_size, 353 ptps_cbr = pt_opcs_cbr + pt_pl_cbr_size, 354 ptps_tip_supp = pt_opcs_tip, 355 ptps_tip_upd16 = pt_opcs_tip + pt_pl_ip_upd16_size, 356 ptps_tip_upd32 = pt_opcs_tip + pt_pl_ip_upd32_size, 357 ptps_tip_upd48 = pt_opcs_tip + pt_pl_ip_upd48_size, 358 ptps_tip_sext48 = pt_opcs_tip + pt_pl_ip_sext48_size, 359 ptps_tip_full = pt_opcs_tip + pt_pl_ip_full_size, 360 ptps_tip_pge_supp = pt_opcs_tip_pge, 361 ptps_tip_pge_upd16 = pt_opcs_tip_pge + pt_pl_ip_upd16_size, 362 ptps_tip_pge_upd32 = pt_opcs_tip_pge + pt_pl_ip_upd32_size, 363 ptps_tip_pge_upd48 = pt_opcs_tip_pge + pt_pl_ip_upd48_size, 364 ptps_tip_pge_sext48 = pt_opcs_tip_pge + pt_pl_ip_sext48_size, 365 ptps_tip_pge_full = pt_opcs_tip_pge + pt_pl_ip_full_size, 366 ptps_tip_pgd_supp = pt_opcs_tip_pgd, 367 ptps_tip_pgd_upd16 = pt_opcs_tip_pgd + pt_pl_ip_upd16_size, 368 ptps_tip_pgd_upd32 = pt_opcs_tip_pgd + pt_pl_ip_upd32_size, 369 ptps_tip_pgd_upd48 = pt_opcs_tip_pgd + pt_pl_ip_upd48_size, 370 ptps_tip_pgd_sext48 = pt_opcs_tip_pgd + pt_pl_ip_sext48_size, 371 ptps_tip_pgd_full = pt_opcs_tip_pgd + pt_pl_ip_full_size, 372 ptps_fup_supp = pt_opcs_fup, 373 ptps_fup_upd16 = pt_opcs_fup + pt_pl_ip_upd16_size, 374 ptps_fup_upd32 = pt_opcs_fup + pt_pl_ip_upd32_size, 375 ptps_fup_upd48 = pt_opcs_fup + pt_pl_ip_upd48_size, 376 ptps_fup_sext48 = pt_opcs_fup + pt_pl_ip_sext48_size, 377 ptps_fup_full = pt_opcs_fup + pt_pl_ip_full_size, 378 ptps_tma = pt_opcs_tma + pt_pl_tma_size, 379 ptps_stop = pt_opcs_stop, 380 ptps_vmcs = pt_opcs_vmcs + pt_pl_vmcs_size, 381 ptps_mnt = pt_opcs_mnt + pt_pl_mnt_size, 382 ptps_exstop = pt_opcs_exstop, 383 ptps_mwait = pt_opcs_mwait + pt_pl_mwait_size, 384 ptps_pwre = pt_opcs_pwre + pt_pl_pwre_size, 385 ptps_pwrx = pt_opcs_pwrx + pt_pl_pwrx_size, 386 ptps_ptw_32 = pt_opcs_ptw + 4, 387 ptps_ptw_64 = pt_opcs_ptw + 8 388 }; 389 390 /* Supported address range configurations. */ 391 enum pt_addr_cfg { 392 pt_addr_cfg_disabled = 0, 393 pt_addr_cfg_filter = 1, 394 pt_addr_cfg_stop = 2 395 }; 396 397 #endif /* PT_OPCODES_H */ 398