1 /* 2 * \file trc_idec_arminst.h 3 * \brief OpenCSD : 4 * 5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved. 6 */ 7 8 /* 9 * Redistribution and use in source and binary forms, with or without modification, 10 * are permitted provided that the following conditions are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3. Neither the name of the copyright holder nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef ARM_TRC_IDEC_ARMINST_H_INCLUDED 36 #define ARM_TRC_IDEC_ARMINST_H_INCLUDED 37 38 #ifndef __STDC_CONSTANT_MACROS 39 #define __STDC_CONSTANT_MACROS 1 40 #endif 41 42 #include "opencsd/ocsd_if_types.h" 43 #include <cstdint> 44 45 /* 46 For Thumb2, test if a halfword is the first half of a 32-bit instruction, 47 as opposed to a complete 16-bit instruction. 48 */ 49 inline int is_wide_thumb(uint16_t insthw) 50 { 51 return (insthw & 0xF800) >= 0xE800; 52 } 53 54 /* 55 In the following queries, 16-bit Thumb2 instructions should be 56 passed in as the high halfword, e.g. xxxx0000. 57 */ 58 59 /* 60 Test whether an instruction is a branch (software change of the PC). 61 This includes branch instructions and all loads and data-processing 62 instructions that write to the PC. It does not include exception 63 instructions such as SVC, HVC and SMC. 64 (Performance event 0x0C includes these.) 65 */ 66 int inst_ARM_is_branch(uint32_t inst); 67 int inst_Thumb_is_branch(uint32_t inst); 68 int inst_A64_is_branch(uint32_t inst); 69 70 /* 71 Test whether an instruction is a direct (aka immediate) branch. 72 Performance event 0x0D counts these. 73 */ 74 int inst_ARM_is_direct_branch(uint32_t inst); 75 int inst_Thumb_is_direct_branch(uint32_t inst); 76 int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *is_cond); 77 int inst_A64_is_direct_branch(uint32_t inst); 78 int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link); 79 80 /* 81 Get branch destination for a direct branch. 82 */ 83 int inst_ARM_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc); 84 int inst_Thumb_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc); 85 int inst_A64_branch_destination(uint64_t addr, uint32_t inst, uint64_t *pnpc); 86 87 int inst_ARM_is_indirect_branch(uint32_t inst); 88 int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link); 89 int inst_Thumb_is_indirect_branch(uint32_t inst); 90 int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link); 91 int inst_A64_is_indirect_branch(uint32_t inst); 92 93 int inst_ARM_is_branch_and_link(uint32_t inst); 94 int inst_Thumb_is_branch_and_link(uint32_t inst); 95 int inst_A64_is_branch_and_link(uint32_t inst); 96 97 int inst_ARM_is_conditional(uint32_t inst); 98 int inst_Thumb_is_conditional(uint32_t inst); 99 int inst_A64_is_conditional(uint32_t inst); 100 101 /* For an IT instruction, return the number of instructions conditionalized 102 (from 1 to 4). For other instructions, return zero. */ 103 unsigned int inst_Thumb_is_IT(uint32_t inst); 104 105 typedef enum { 106 ARM_BARRIER_NONE, 107 ARM_BARRIER_ISB, 108 ARM_BARRIER_DMB, 109 ARM_BARRIER_DSB 110 } arm_barrier_t; 111 112 arm_barrier_t inst_ARM_barrier(uint32_t inst); 113 arm_barrier_t inst_Thumb_barrier(uint32_t inst); 114 arm_barrier_t inst_A64_barrier(uint32_t inst); 115 116 int inst_ARM_wfiwfe(uint32_t inst); 117 int inst_Thumb_wfiwfe(uint32_t inst); 118 int inst_A64_wfiwfe(uint32_t inst); 119 120 /* 121 Test whether an instruction is definitely undefined, e.g. because 122 allocated to a "permanently UNDEFINED" space (UDF mnemonic). 123 Other instructions besides the ones indicated, may always or 124 sometimes cause an undefined instruction trap. This call is 125 intended to be helpful in 'runaway decode' prevention. 126 */ 127 int inst_ARM_is_UDF(uint32_t inst); 128 int inst_Thumb_is_UDF(uint32_t inst); 129 int inst_A64_is_UDF(uint32_t inst); 130 131 132 /* access sub-type information */ 133 ocsd_instr_subtype get_instr_subtype(); 134 void clear_instr_subtype(); 135 136 /* set arch version info. */ 137 void set_arch_version(uint16_t version); 138 139 #endif // ARM_TRC_IDEC_ARMINST_H_INCLUDED 140 141 /* End of File trc_idec_arminst.h */ 142