1 /* 2 * \file trc_idec_arminst.h 3 * \brief OpenCSD : 4 * 5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved. 6 */ 7 8 /* 9 * Redistribution and use in source and binary forms, with or without modification, 10 * are permitted provided that the following conditions are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3. Neither the name of the copyright holder nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef ARM_TRC_IDEC_ARMINST_H_INCLUDED 36 #define ARM_TRC_IDEC_ARMINST_H_INCLUDED 37 38 #ifndef __STDC_CONSTANT_MACROS 39 #define __STDC_CONSTANT_MACROS 1 40 #endif 41 42 #include "opencsd/ocsd_if_types.h" 43 #include <cstdint> 44 45 /* supplementary decode information */ 46 struct decode_info { 47 ocsd_arch_version_t arch_version; 48 ocsd_instr_subtype instr_sub_type; 49 }; 50 51 /* 52 For Thumb2, test if a halfword is the first half of a 32-bit instruction, 53 as opposed to a complete 16-bit instruction. 54 */ 55 inline int is_wide_thumb(uint16_t insthw) 56 { 57 return (insthw & 0xF800) >= 0xE800; 58 } 59 60 /* 61 In the following queries, 16-bit Thumb2 instructions should be 62 passed in as the high halfword, e.g. xxxx0000. 63 */ 64 65 /* 66 Test whether an instruction is a branch (software change of the PC). 67 This includes branch instructions and all loads and data-processing 68 instructions that write to the PC. It does not include exception 69 instructions such as SVC, HVC and SMC. 70 (Performance event 0x0C includes these.) 71 */ 72 int inst_ARM_is_branch(uint32_t inst, struct decode_info *info); 73 int inst_Thumb_is_branch(uint32_t inst, struct decode_info *info); 74 int inst_A64_is_branch(uint32_t inst, struct decode_info *info); 75 76 /* 77 Test whether an instruction is a direct (aka immediate) branch. 78 Performance event 0x0D counts these. 79 */ 80 int inst_ARM_is_direct_branch(uint32_t inst); 81 int inst_Thumb_is_direct_branch(uint32_t inst, struct decode_info *info); 82 int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *is_cond, struct decode_info *info); 83 int inst_A64_is_direct_branch(uint32_t inst, struct decode_info *info); 84 int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info); 85 86 /* 87 Get branch destination for a direct branch. 88 */ 89 int inst_ARM_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc); 90 int inst_Thumb_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc); 91 int inst_A64_branch_destination(uint64_t addr, uint32_t inst, uint64_t *pnpc); 92 93 int inst_ARM_is_indirect_branch(uint32_t inst, struct decode_info *info); 94 int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info); 95 int inst_Thumb_is_indirect_branch(uint32_t inst, struct decode_info *info); 96 int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info); 97 int inst_A64_is_indirect_branch(uint32_t inst, struct decode_info *info); 98 99 int inst_ARM_is_branch_and_link(uint32_t inst, struct decode_info *info); 100 int inst_Thumb_is_branch_and_link(uint32_t inst, struct decode_info *info); 101 int inst_A64_is_branch_and_link(uint32_t inst, struct decode_info *info); 102 103 int inst_ARM_is_conditional(uint32_t inst); 104 int inst_Thumb_is_conditional(uint32_t inst); 105 int inst_A64_is_conditional(uint32_t inst); 106 107 /* For an IT instruction, return the number of instructions conditionalized 108 (from 1 to 4). For other instructions, return zero. */ 109 unsigned int inst_Thumb_is_IT(uint32_t inst); 110 111 typedef enum { 112 ARM_BARRIER_NONE, 113 ARM_BARRIER_ISB, 114 ARM_BARRIER_DMB, 115 ARM_BARRIER_DSB 116 } arm_barrier_t; 117 118 arm_barrier_t inst_ARM_barrier(uint32_t inst); 119 arm_barrier_t inst_Thumb_barrier(uint32_t inst); 120 arm_barrier_t inst_A64_barrier(uint32_t inst); 121 122 int inst_ARM_wfiwfe(uint32_t inst); 123 int inst_Thumb_wfiwfe(uint32_t inst); 124 int inst_A64_wfiwfe(uint32_t inst, struct decode_info *info); 125 int inst_A64_Tstart(uint32_t inst); 126 127 /* 128 Test whether an instruction is definitely undefined, e.g. because 129 allocated to a "permanently UNDEFINED" space (UDF mnemonic). 130 Other instructions besides the ones indicated, may always or 131 sometimes cause an undefined instruction trap. This call is 132 intended to be helpful in 'runaway decode' prevention. 133 */ 134 int inst_ARM_is_UDF(uint32_t inst); 135 int inst_Thumb_is_UDF(uint32_t inst); 136 int inst_A64_is_UDF(uint32_t inst); 137 138 #endif // ARM_TRC_IDEC_ARMINST_H_INCLUDED 139 140 /* End of File trc_idec_arminst.h */ 141