1 /* 2 * Copyright (c) 2012 Mellanox Technologies, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef WQE_H 34 #define WQE_H 35 36 #include <stdint.h> 37 38 struct mlx5_sg_copy_ptr { 39 int index; 40 int offset; 41 }; 42 43 struct mlx5_eqe_comp { 44 uint32_t reserved[6]; 45 uint32_t cqn; 46 }; 47 48 struct mlx5_eqe_qp_srq { 49 uint32_t reserved[6]; 50 uint32_t qp_srq_n; 51 }; 52 53 struct mlx5_wqe_xrc_seg { 54 uint32_t xrc_srqn; 55 uint8_t rsvd[12]; 56 }; 57 58 struct mlx5_wqe_masked_atomic_seg { 59 uint64_t swap_add; 60 uint64_t compare; 61 uint64_t swap_add_mask; 62 uint64_t compare_mask; 63 }; 64 65 enum { 66 MLX5_ETH_L2_INLINE_HEADER_SIZE = 18, 67 MLX5_ETH_L2_MIN_HEADER_SIZE = 14, 68 }; 69 70 enum { 71 MLX5_WQE_UMR_CTRL_FLAG_INLINE = 1 << 7, 72 MLX5_WQE_UMR_CTRL_FLAG_CHECK_FREE = 1 << 5, 73 MLX5_WQE_UMR_CTRL_FLAG_TRNSLATION_OFFSET = 1 << 4, 74 MLX5_WQE_UMR_CTRL_FLAG_CHECK_QPN = 1 << 3, 75 }; 76 77 enum { 78 MLX5_WQE_UMR_CTRL_MKEY_MASK_LEN = 1 << 0, 79 MLX5_WQE_UMR_CTRL_MKEY_MASK_START_ADDR = 1 << 6, 80 MLX5_WQE_UMR_CTRL_MKEY_MASK_MKEY = 1 << 13, 81 MLX5_WQE_UMR_CTRL_MKEY_MASK_QPN = 1 << 14, 82 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_LOCAL_WRITE = 1 << 18, 83 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_REMOTE_READ = 1 << 19, 84 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_REMOTE_WRITE = 1 << 20, 85 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_ATOMIC = 1 << 21, 86 MLX5_WQE_UMR_CTRL_MKEY_MASK_FREE = 1 << 29, 87 }; 88 89 struct mlx5_wqe_umr_ctrl_seg { 90 uint8_t flags; 91 uint8_t rsvd0[3]; 92 uint16_t klm_octowords; 93 uint16_t translation_offset; 94 uint64_t mkey_mask; 95 uint8_t rsvd1[32]; 96 }; 97 98 struct mlx5_wqe_umr_klm_seg { 99 /* up to 2GB */ 100 uint32_t byte_count; 101 uint32_t mkey; 102 uint64_t address; 103 }; 104 105 union mlx5_wqe_umr_inline_seg { 106 struct mlx5_wqe_umr_klm_seg klm; 107 }; 108 109 enum { 110 MLX5_WQE_MKEY_CONTEXT_FREE = 1 << 6 111 }; 112 113 enum { 114 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_ATOMIC = 1 << 6, 115 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_REMOTE_WRITE = 1 << 5, 116 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_REMOTE_READ = 1 << 4, 117 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_LOCAL_WRITE = 1 << 3, 118 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_LOCAL_READ = 1 << 2 119 }; 120 121 struct mlx5_wqe_mkey_context_seg { 122 uint8_t free; 123 uint8_t reserved1; 124 uint8_t access_flags; 125 uint8_t sf; 126 uint32_t qpn_mkey; 127 uint32_t reserved2; 128 uint32_t flags_pd; 129 uint64_t start_addr; 130 uint64_t len; 131 uint32_t bsf_octword_size; 132 uint32_t reserved3[4]; 133 uint32_t translations_octword_size; 134 uint8_t reserved4[3]; 135 uint8_t log_page_size; 136 uint32_t reserved; 137 union mlx5_wqe_umr_inline_seg inseg[0]; 138 }; 139 140 struct mlx5_seg_set_psv { 141 uint8_t rsvd[4]; 142 uint16_t syndrome; 143 uint16_t status; 144 uint16_t block_guard; 145 uint16_t app_tag; 146 uint32_t ref_tag; 147 uint32_t mkey; 148 uint64_t va; 149 }; 150 151 struct mlx5_seg_get_psv { 152 uint8_t rsvd[19]; 153 uint8_t num_psv; 154 uint32_t l_key; 155 uint64_t va; 156 uint32_t psv_index[4]; 157 }; 158 159 struct mlx5_seg_check_psv { 160 uint8_t rsvd0[2]; 161 uint16_t err_coalescing_op; 162 uint8_t rsvd1[2]; 163 uint16_t xport_err_op; 164 uint8_t rsvd2[2]; 165 uint16_t xport_err_mask; 166 uint8_t rsvd3[7]; 167 uint8_t num_psv; 168 uint32_t l_key; 169 uint64_t va; 170 uint32_t psv_index[4]; 171 }; 172 173 struct mlx5_rwqe_sig { 174 uint8_t rsvd0[4]; 175 uint8_t signature; 176 uint8_t rsvd1[11]; 177 }; 178 179 struct mlx5_wqe_signature_seg { 180 uint8_t rsvd0[4]; 181 uint8_t signature; 182 uint8_t rsvd1[11]; 183 }; 184 185 struct mlx5_wqe_inline_seg { 186 uint32_t byte_count; 187 }; 188 189 190 #endif /* WQE_H */ 191