1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2021 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_USER_H 37 #define IRDMA_USER_H 38 39 #include "osdep.h" 40 41 #define irdma_handle void * 42 #define irdma_adapter_handle irdma_handle 43 #define irdma_qp_handle irdma_handle 44 #define irdma_cq_handle irdma_handle 45 #define irdma_pd_id irdma_handle 46 #define irdma_stag_handle irdma_handle 47 #define irdma_stag_index u32 48 #define irdma_stag u32 49 #define irdma_stag_key u8 50 #define irdma_tagged_offset u64 51 #define irdma_access_privileges u32 52 #define irdma_physical_fragment u64 53 #define irdma_address_list u64 * 54 #define irdma_sgl struct irdma_sge * 55 56 #define IRDMA_MAX_MR_SIZE 0x200000000000ULL 57 58 #define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01 59 #define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02 60 #define IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04 61 #define IRDMA_ACCESS_FLAGS_REMOTEREAD 0x05 62 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08 63 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE 0x0a 64 #define IRDMA_ACCESS_FLAGS_BIND_WINDOW 0x10 65 #define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20 66 #define IRDMA_ACCESS_FLAGS_ALL 0x3f 67 68 #define IRDMA_OP_TYPE_RDMA_WRITE 0x00 69 #define IRDMA_OP_TYPE_RDMA_READ 0x01 70 #define IRDMA_OP_TYPE_SEND 0x03 71 #define IRDMA_OP_TYPE_SEND_INV 0x04 72 #define IRDMA_OP_TYPE_SEND_SOL 0x05 73 #define IRDMA_OP_TYPE_SEND_SOL_INV 0x06 74 #define IRDMA_OP_TYPE_RDMA_WRITE_SOL 0x0d 75 #define IRDMA_OP_TYPE_BIND_MW 0x08 76 #define IRDMA_OP_TYPE_FAST_REG_NSMR 0x09 77 #define IRDMA_OP_TYPE_INV_STAG 0x0a 78 #define IRDMA_OP_TYPE_RDMA_READ_INV_STAG 0x0b 79 #define IRDMA_OP_TYPE_NOP 0x0c 80 #define IRDMA_OP_TYPE_REC 0x3e 81 #define IRDMA_OP_TYPE_REC_IMM 0x3f 82 83 #define IRDMA_FLUSH_MAJOR_ERR 1 84 85 enum irdma_device_caps_const { 86 IRDMA_WQE_SIZE = 4, 87 IRDMA_CQP_WQE_SIZE = 8, 88 IRDMA_CQE_SIZE = 4, 89 IRDMA_EXTENDED_CQE_SIZE = 8, 90 IRDMA_AEQE_SIZE = 2, 91 IRDMA_CEQE_SIZE = 1, 92 IRDMA_CQP_CTX_SIZE = 8, 93 IRDMA_SHADOW_AREA_SIZE = 8, 94 IRDMA_GATHER_STATS_BUF_SIZE = 1024, 95 IRDMA_MIN_IW_QP_ID = 0, 96 IRDMA_QUERY_FPM_BUF_SIZE = 176, 97 IRDMA_COMMIT_FPM_BUF_SIZE = 176, 98 IRDMA_MAX_IW_QP_ID = 262143, 99 IRDMA_MIN_CEQID = 0, 100 IRDMA_MAX_CEQID = 1023, 101 IRDMA_CEQ_MAX_COUNT = IRDMA_MAX_CEQID + 1, 102 IRDMA_MIN_CQID = 0, 103 IRDMA_MAX_CQID = 524287, 104 IRDMA_MIN_AEQ_ENTRIES = 1, 105 IRDMA_MAX_AEQ_ENTRIES = 524287, 106 IRDMA_MIN_CEQ_ENTRIES = 1, 107 IRDMA_MAX_CEQ_ENTRIES = 262143, 108 IRDMA_MIN_CQ_SIZE = 1, 109 IRDMA_MAX_CQ_SIZE = 1048575, 110 IRDMA_DB_ID_ZERO = 0, 111 /* 64K + 1 */ 112 IRDMA_MAX_OUTBOUND_MSG_SIZE = 65537, 113 /* 64K +1 */ 114 IRDMA_MAX_INBOUND_MSG_SIZE = 65537, 115 IRDMA_MAX_PUSH_PAGE_COUNT = 1024, 116 IRDMA_MAX_PE_ENA_VF_COUNT = 32, 117 IRDMA_MAX_VF_FPM_ID = 47, 118 IRDMA_MAX_SQ_PAYLOAD_SIZE = 2145386496, 119 IRDMA_MAX_INLINE_DATA_SIZE = 101, 120 IRDMA_MAX_WQ_ENTRIES = 32768, 121 IRDMA_Q2_BUF_SIZE = 256, 122 IRDMA_QP_CTX_SIZE = 256, 123 IRDMA_MAX_PDS = 262144, 124 }; 125 126 enum irdma_addressing_type { 127 IRDMA_ADDR_TYPE_ZERO_BASED = 0, 128 IRDMA_ADDR_TYPE_VA_BASED = 1, 129 }; 130 131 enum irdma_flush_opcode { 132 FLUSH_INVALID = 0, 133 FLUSH_GENERAL_ERR, 134 FLUSH_PROT_ERR, 135 FLUSH_REM_ACCESS_ERR, 136 FLUSH_LOC_QP_OP_ERR, 137 FLUSH_REM_OP_ERR, 138 FLUSH_LOC_LEN_ERR, 139 FLUSH_FATAL_ERR, 140 FLUSH_MW_BIND_ERR, 141 FLUSH_REM_INV_REQ_ERR, 142 FLUSH_RETRY_EXC_ERR, 143 }; 144 145 enum irdma_cmpl_status { 146 IRDMA_COMPL_STATUS_SUCCESS = 0, 147 IRDMA_COMPL_STATUS_FLUSHED, 148 IRDMA_COMPL_STATUS_INVALID_WQE, 149 IRDMA_COMPL_STATUS_QP_CATASTROPHIC, 150 IRDMA_COMPL_STATUS_REMOTE_TERMINATION, 151 IRDMA_COMPL_STATUS_INVALID_STAG, 152 IRDMA_COMPL_STATUS_BASE_BOUND_VIOLATION, 153 IRDMA_COMPL_STATUS_ACCESS_VIOLATION, 154 IRDMA_COMPL_STATUS_INVALID_PD_ID, 155 IRDMA_COMPL_STATUS_WRAP_ERROR, 156 IRDMA_COMPL_STATUS_STAG_INVALID_PDID, 157 IRDMA_COMPL_STATUS_RDMA_READ_ZERO_ORD, 158 IRDMA_COMPL_STATUS_QP_NOT_PRIVLEDGED, 159 IRDMA_COMPL_STATUS_STAG_NOT_INVALID, 160 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_SIZE, 161 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_ENTRY, 162 IRDMA_COMPL_STATUS_INVALID_FBO, 163 IRDMA_COMPL_STATUS_INVALID_LEN, 164 IRDMA_COMPL_STATUS_INVALID_ACCESS, 165 IRDMA_COMPL_STATUS_PHYS_BUF_LIST_TOO_LONG, 166 IRDMA_COMPL_STATUS_INVALID_VIRT_ADDRESS, 167 IRDMA_COMPL_STATUS_INVALID_REGION, 168 IRDMA_COMPL_STATUS_INVALID_WINDOW, 169 IRDMA_COMPL_STATUS_INVALID_TOTAL_LEN, 170 IRDMA_COMPL_STATUS_UNKNOWN, 171 }; 172 173 enum irdma_cmpl_notify { 174 IRDMA_CQ_COMPL_EVENT = 0, 175 IRDMA_CQ_COMPL_SOLICITED = 1, 176 }; 177 178 enum irdma_qp_caps { 179 IRDMA_WRITE_WITH_IMM = 1, 180 IRDMA_SEND_WITH_IMM = 2, 181 IRDMA_ROCE = 4, 182 IRDMA_PUSH_MODE = 8, 183 }; 184 185 struct irdma_qp_uk; 186 struct irdma_cq_uk; 187 struct irdma_qp_uk_init_info; 188 struct irdma_cq_uk_init_info; 189 190 struct irdma_sge { 191 irdma_tagged_offset tag_off; 192 u32 len; 193 irdma_stag stag; 194 }; 195 196 struct irdma_ring { 197 volatile u32 head; 198 volatile u32 tail; 199 u32 size; 200 }; 201 202 struct irdma_cqe { 203 __le64 buf[IRDMA_CQE_SIZE]; 204 }; 205 206 struct irdma_extended_cqe { 207 __le64 buf[IRDMA_EXTENDED_CQE_SIZE]; 208 }; 209 210 struct irdma_post_send { 211 irdma_sgl sg_list; 212 u32 num_sges; 213 u32 qkey; 214 u32 dest_qp; 215 u32 ah_id; 216 }; 217 218 struct irdma_post_inline_send { 219 void *data; 220 u32 len; 221 u32 qkey; 222 u32 dest_qp; 223 u32 ah_id; 224 }; 225 226 struct irdma_post_rq_info { 227 u64 wr_id; 228 irdma_sgl sg_list; 229 u32 num_sges; 230 }; 231 232 struct irdma_rdma_write { 233 irdma_sgl lo_sg_list; 234 u32 num_lo_sges; 235 struct irdma_sge rem_addr; 236 }; 237 238 struct irdma_inline_rdma_write { 239 void *data; 240 u32 len; 241 struct irdma_sge rem_addr; 242 }; 243 244 struct irdma_rdma_read { 245 irdma_sgl lo_sg_list; 246 u32 num_lo_sges; 247 struct irdma_sge rem_addr; 248 }; 249 250 struct irdma_bind_window { 251 irdma_stag mr_stag; 252 u64 bind_len; 253 void *va; 254 enum irdma_addressing_type addressing_type; 255 bool ena_reads:1; 256 bool ena_writes:1; 257 irdma_stag mw_stag; 258 bool mem_window_type_1:1; 259 }; 260 261 struct irdma_inv_local_stag { 262 irdma_stag target_stag; 263 }; 264 265 struct irdma_post_sq_info { 266 u64 wr_id; 267 u8 op_type; 268 u8 l4len; 269 bool signaled:1; 270 bool read_fence:1; 271 bool local_fence:1; 272 bool inline_data:1; 273 bool imm_data_valid:1; 274 bool push_wqe:1; 275 bool report_rtt:1; 276 bool udp_hdr:1; 277 bool defer_flag:1; 278 u32 imm_data; 279 u32 stag_to_inv; 280 union { 281 struct irdma_post_send send; 282 struct irdma_rdma_write rdma_write; 283 struct irdma_rdma_read rdma_read; 284 struct irdma_bind_window bind_window; 285 struct irdma_inv_local_stag inv_local_stag; 286 struct irdma_inline_rdma_write inline_rdma_write; 287 struct irdma_post_inline_send inline_send; 288 } op; 289 }; 290 291 struct irdma_cq_poll_info { 292 u64 wr_id; 293 irdma_qp_handle qp_handle; 294 u32 bytes_xfered; 295 u32 tcp_seq_num_rtt; 296 u32 qp_id; 297 u32 ud_src_qpn; 298 u32 imm_data; 299 irdma_stag inv_stag; /* or L_R_Key */ 300 enum irdma_cmpl_status comp_status; 301 u16 major_err; 302 u16 minor_err; 303 u16 ud_vlan; 304 u8 ud_smac[6]; 305 u8 op_type; 306 bool stag_invalid_set:1; /* or L_R_Key set */ 307 bool push_dropped:1; 308 bool error:1; 309 bool solicited_event:1; 310 bool ipv4:1; 311 bool ud_vlan_valid:1; 312 bool ud_smac_valid:1; 313 bool imm_valid:1; 314 bool signaled:1; 315 }; 316 317 int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, 318 struct irdma_post_sq_info *info, bool post_sq); 319 int irdma_uk_inline_send(struct irdma_qp_uk *qp, 320 struct irdma_post_sq_info *info, bool post_sq); 321 int irdma_uk_mw_bind(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 322 bool post_sq); 323 int irdma_uk_post_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, 324 bool post_sq); 325 int irdma_uk_post_receive(struct irdma_qp_uk *qp, 326 struct irdma_post_rq_info *info); 327 void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp); 328 int irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 329 bool inv_stag, bool post_sq); 330 int irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 331 bool post_sq); 332 int irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 333 bool post_sq); 334 int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, 335 struct irdma_post_sq_info *info, 336 bool post_sq); 337 338 struct irdma_wqe_uk_ops { 339 void (*iw_copy_inline_data)(u8 *dest, u8 *src, u32 len, u8 polarity); 340 u16 (*iw_inline_data_size_to_quanta)(u32 data_size); 341 void (*iw_set_fragment)(__le64 *wqe, u32 offset, struct irdma_sge *sge, 342 u8 valid); 343 void (*iw_set_mw_bind_wqe)(__le64 *wqe, 344 struct irdma_bind_window *op_info); 345 }; 346 347 int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, 348 struct irdma_cq_poll_info *info); 349 void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, 350 enum irdma_cmpl_notify cq_notify); 351 void irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int size); 352 void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *qp, u16 cnt); 353 int irdma_uk_cq_init(struct irdma_cq_uk *cq, 354 struct irdma_cq_uk_init_info *info); 355 int irdma_uk_qp_init(struct irdma_qp_uk *qp, 356 struct irdma_qp_uk_init_info *info); 357 struct irdma_sq_uk_wr_trk_info { 358 u64 wrid; 359 u32 wr_len; 360 u16 quanta; 361 u8 signaled; 362 u8 reserved[1]; 363 }; 364 365 struct irdma_qp_quanta { 366 __le64 elem[IRDMA_WQE_SIZE]; 367 }; 368 369 struct irdma_qp_uk { 370 struct irdma_qp_quanta *sq_base; 371 struct irdma_qp_quanta *rq_base; 372 struct irdma_uk_attrs *uk_attrs; 373 u32 IOMEM *wqe_alloc_db; 374 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 375 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 376 u64 *rq_wrid_array; 377 __le64 *shadow_area; 378 __le32 *push_db; 379 __le64 *push_wqe; 380 struct irdma_ring sq_ring; 381 struct irdma_ring sq_sig_ring; 382 struct irdma_ring rq_ring; 383 struct irdma_ring initial_ring; 384 u32 qp_id; 385 u32 qp_caps; 386 u32 sq_size; 387 u32 rq_size; 388 u32 max_sq_frag_cnt; 389 u32 max_rq_frag_cnt; 390 u32 max_inline_data; 391 u32 last_rx_cmpl_idx; 392 u32 last_tx_cmpl_idx; 393 struct irdma_wqe_uk_ops wqe_ops; 394 u16 conn_wqes; 395 u8 qp_type; 396 u8 swqe_polarity; 397 u8 swqe_polarity_deferred; 398 u8 rwqe_polarity; 399 u8 rq_wqe_size; 400 u8 rq_wqe_size_multiplier; 401 bool deferred_flag:1; 402 bool push_mode:1; /* whether the last post wqe was pushed */ 403 bool push_dropped:1; 404 bool first_sq_wq:1; 405 bool sq_flush_complete:1; /* Indicates flush was seen and SQ was empty after the flush */ 406 bool rq_flush_complete:1; /* Indicates flush was seen and RQ was empty after the flush */ 407 bool destroy_pending:1; /* Indicates the QP is being destroyed */ 408 void *back_qp; 409 pthread_spinlock_t *lock; 410 bool force_fence; 411 u8 dbg_rq_flushed; 412 u16 ord_cnt; 413 u8 sq_flush_seen; 414 u8 rq_flush_seen; 415 u8 rd_fence_rate; 416 }; 417 418 struct irdma_cq_uk { 419 struct irdma_cqe *cq_base; 420 u32 IOMEM *cqe_alloc_db; 421 u32 IOMEM *cq_ack_db; 422 __le64 *shadow_area; 423 u32 cq_id; 424 u32 cq_size; 425 struct irdma_ring cq_ring; 426 u8 polarity; 427 bool armed:1; 428 bool avoid_mem_cflct:1; 429 }; 430 431 struct irdma_qp_uk_init_info { 432 struct irdma_qp_quanta *sq; 433 struct irdma_qp_quanta *rq; 434 struct irdma_uk_attrs *uk_attrs; 435 u32 IOMEM *wqe_alloc_db; 436 __le64 *shadow_area; 437 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 438 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 439 u64 *rq_wrid_array; 440 u32 qp_id; 441 u32 qp_caps; 442 u32 sq_size; 443 u32 rq_size; 444 u32 max_sq_frag_cnt; 445 u32 max_rq_frag_cnt; 446 u32 max_inline_data; 447 u8 first_sq_wq; 448 u8 type; 449 u8 rd_fence_rate; 450 int abi_ver; 451 bool legacy_mode; 452 }; 453 454 struct irdma_cq_uk_init_info { 455 u32 IOMEM *cqe_alloc_db; 456 u32 IOMEM *cq_ack_db; 457 struct irdma_cqe *cq_base; 458 __le64 *shadow_area; 459 u32 cq_size; 460 u32 cq_id; 461 bool avoid_mem_cflct; 462 }; 463 464 __le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, 465 u16 quanta, u32 total_size, 466 struct irdma_post_sq_info *info); 467 __le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx); 468 int irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq); 469 int irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq); 470 int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta); 471 int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size); 472 void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, 473 u32 inline_data, u8 *shift); 474 int irdma_get_sqdepth(u32 max_hw_wq_quanta, u32 sq_size, u8 shift, u32 *wqdepth); 475 int irdma_get_rqdepth(u32 max_hw_rq_quanta, u32 rq_size, u8 shift, u32 *wqdepth); 476 void irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 *wqe, u16 quanta, 477 u32 wqe_idx, bool post_sq); 478 void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx); 479 #endif /* IRDMA_USER_H */ 480