1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2023 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #include "osdep.h" 37 #include "irdma_defs.h" 38 #include "irdma_user.h" 39 #include "irdma.h" 40 41 /** 42 * irdma_set_fragment - set fragment in wqe 43 * @wqe: wqe for setting fragment 44 * @offset: offset value 45 * @sge: sge length and stag 46 * @valid: The wqe valid 47 */ 48 static void 49 irdma_set_fragment(__le64 * wqe, u32 offset, struct irdma_sge *sge, 50 u8 valid) 51 { 52 if (sge) { 53 set_64bit_val(wqe, offset, 54 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->tag_off)); 55 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 56 FIELD_PREP(IRDMAQPSQ_VALID, valid) | 57 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->len) | 58 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->stag)); 59 } else { 60 set_64bit_val(wqe, offset, 0); 61 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 62 FIELD_PREP(IRDMAQPSQ_VALID, valid)); 63 } 64 } 65 66 /** 67 * irdma_set_fragment_gen_1 - set fragment in wqe 68 * @wqe: wqe for setting fragment 69 * @offset: offset value 70 * @sge: sge length and stag 71 * @valid: wqe valid flag 72 */ 73 static void 74 irdma_set_fragment_gen_1(__le64 * wqe, u32 offset, 75 struct irdma_sge *sge, u8 valid) 76 { 77 if (sge) { 78 set_64bit_val(wqe, offset, 79 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->tag_off)); 80 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 81 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->len) | 82 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->stag)); 83 } else { 84 set_64bit_val(wqe, offset, 0); 85 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 0); 86 } 87 } 88 89 /** 90 * irdma_nop_hdr - Format header section of noop WQE 91 * @qp: hw qp ptr 92 */ 93 static inline u64 irdma_nop_hdr(struct irdma_qp_uk *qp){ 94 return FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | 95 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, false) | 96 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 97 } 98 99 /** 100 * irdma_nop_1 - insert a NOP wqe 101 * @qp: hw qp ptr 102 */ 103 static int 104 irdma_nop_1(struct irdma_qp_uk *qp) 105 { 106 __le64 *wqe; 107 u32 wqe_idx; 108 109 if (!qp->sq_ring.head) 110 return EINVAL; 111 112 wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 113 wqe = qp->sq_base[wqe_idx].elem; 114 115 qp->sq_wrtrk_array[wqe_idx].quanta = IRDMA_QP_WQE_MIN_QUANTA; 116 117 set_64bit_val(wqe, IRDMA_BYTE_0, 0); 118 set_64bit_val(wqe, IRDMA_BYTE_8, 0); 119 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 120 121 /* make sure WQE is written before valid bit is set */ 122 udma_to_device_barrier(); 123 124 set_64bit_val(wqe, IRDMA_BYTE_24, irdma_nop_hdr(qp)); 125 126 return 0; 127 } 128 129 /** 130 * irdma_clr_wqes - clear next 128 sq entries 131 * @qp: hw qp ptr 132 * @qp_wqe_idx: wqe_idx 133 */ 134 void 135 irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx) 136 { 137 __le64 *wqe; 138 u32 wqe_idx; 139 140 if (!(qp_wqe_idx & 0x7F)) { 141 wqe_idx = (qp_wqe_idx + 128) % qp->sq_ring.size; 142 wqe = qp->sq_base[wqe_idx].elem; 143 if (wqe_idx) 144 memset(wqe, qp->swqe_polarity ? 0 : 0xFF, 0x1000); 145 else 146 memset(wqe, qp->swqe_polarity ? 0xFF : 0, 0x1000); 147 } 148 } 149 150 /** 151 * irdma_uk_qp_post_wr - ring doorbell 152 * @qp: hw qp ptr 153 */ 154 void 155 irdma_uk_qp_post_wr(struct irdma_qp_uk *qp) 156 { 157 u64 temp; 158 u32 hw_sq_tail; 159 u32 sw_sq_head; 160 161 /* valid bit is written and loads completed before reading shadow */ 162 atomic_thread_fence(memory_order_seq_cst); 163 164 /* read the doorbell shadow area */ 165 get_64bit_val(qp->shadow_area, IRDMA_BYTE_0, &temp); 166 167 hw_sq_tail = (u32)FIELD_GET(IRDMA_QP_DBSA_HW_SQ_TAIL, temp); 168 sw_sq_head = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 169 if (sw_sq_head != qp->initial_ring.head) { 170 if (qp->push_dropped) { 171 db_wr32(qp->qp_id, qp->wqe_alloc_db); 172 qp->push_dropped = false; 173 } else if (sw_sq_head != hw_sq_tail) { 174 if (sw_sq_head > qp->initial_ring.head) { 175 if (hw_sq_tail >= qp->initial_ring.head && 176 hw_sq_tail < sw_sq_head) 177 db_wr32(qp->qp_id, qp->wqe_alloc_db); 178 } else { 179 if (hw_sq_tail >= qp->initial_ring.head || 180 hw_sq_tail < sw_sq_head) 181 db_wr32(qp->qp_id, qp->wqe_alloc_db); 182 } 183 } 184 } 185 186 qp->initial_ring.head = qp->sq_ring.head; 187 } 188 189 /** 190 * irdma_qp_ring_push_db - ring qp doorbell 191 * @qp: hw qp ptr 192 * @wqe_idx: wqe index 193 */ 194 static void 195 irdma_qp_ring_push_db(struct irdma_qp_uk *qp, u32 wqe_idx) 196 { 197 set_32bit_val(qp->push_db, 0, 198 FIELD_PREP(IRDMA_WQEALLOC_WQE_DESC_INDEX, wqe_idx >> 3) | qp->qp_id); 199 qp->initial_ring.head = qp->sq_ring.head; 200 qp->push_mode = true; 201 qp->push_dropped = false; 202 } 203 204 void 205 irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 * wqe, u16 quanta, 206 u32 wqe_idx, bool post_sq) 207 { 208 __le64 *push; 209 210 if (IRDMA_RING_CURRENT_HEAD(qp->initial_ring) != 211 IRDMA_RING_CURRENT_TAIL(qp->sq_ring) && 212 !qp->push_mode) { 213 if (post_sq) 214 irdma_uk_qp_post_wr(qp); 215 } else { 216 push = (__le64 *) ((uintptr_t)qp->push_wqe + 217 (wqe_idx & 0x7) * 0x20); 218 irdma_memcpy(push, wqe, quanta * IRDMA_QP_WQE_MIN_SIZE); 219 irdma_qp_ring_push_db(qp, wqe_idx); 220 } 221 } 222 223 /** 224 * irdma_qp_get_next_send_wqe - pad with NOP if needed, return where next WR should go 225 * @qp: hw qp ptr 226 * @wqe_idx: return wqe index 227 * @quanta: (in/out) ptr to size of WR in quanta. Modified in case pad is needed 228 * @total_size: size of WR in bytes 229 * @info: info on WR 230 */ 231 __le64 * 232 irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, 233 u16 *quanta, u32 total_size, 234 struct irdma_post_sq_info *info) 235 { 236 __le64 *wqe; 237 __le64 *wqe_0 = NULL; 238 u32 nop_wqe_idx; 239 u16 avail_quanta, wqe_quanta = *quanta; 240 u16 i; 241 242 avail_quanta = qp->uk_attrs->max_hw_sq_chunk - 243 (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) % 244 qp->uk_attrs->max_hw_sq_chunk); 245 246 if (*quanta <= avail_quanta) { 247 /* WR fits in current chunk */ 248 if (*quanta > IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) 249 return NULL; 250 } else { 251 /* Need to pad with NOP */ 252 if (*quanta + avail_quanta > 253 IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) 254 return NULL; 255 256 nop_wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 257 for (i = 0; i < avail_quanta; i++) { 258 irdma_nop_1(qp); 259 IRDMA_RING_MOVE_HEAD_NOCHECK(qp->sq_ring); 260 } 261 if (qp->push_db && info->push_wqe) 262 irdma_qp_push_wqe(qp, qp->sq_base[nop_wqe_idx].elem, 263 avail_quanta, nop_wqe_idx, true); 264 } 265 266 *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 267 if (!*wqe_idx) 268 qp->swqe_polarity = !qp->swqe_polarity; 269 270 IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, *quanta); 271 272 irdma_clr_wqes(qp, *wqe_idx); 273 274 wqe = qp->sq_base[*wqe_idx].elem; 275 if (qp->uk_attrs->hw_rev == IRDMA_GEN_1 && wqe_quanta == 1 && 276 (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) & 1)) { 277 wqe_0 = qp->sq_base[IRDMA_RING_CURRENT_HEAD(qp->sq_ring)].elem; 278 wqe_0[3] = htole64(FIELD_PREP(IRDMAQPSQ_VALID, 279 qp->swqe_polarity ? 0 : 1)); 280 } 281 qp->sq_wrtrk_array[*wqe_idx].wrid = info->wr_id; 282 qp->sq_wrtrk_array[*wqe_idx].wr_len = total_size; 283 qp->sq_wrtrk_array[*wqe_idx].quanta = wqe_quanta; 284 qp->sq_wrtrk_array[*wqe_idx].signaled = info->signaled; 285 286 return wqe; 287 } 288 289 /** 290 * irdma_qp_get_next_recv_wqe - get next qp's rcv wqe 291 * @qp: hw qp ptr 292 * @wqe_idx: return wqe index 293 */ 294 __le64 * 295 irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx) 296 { 297 __le64 *wqe; 298 int ret_code; 299 300 if (IRDMA_RING_FULL_ERR(qp->rq_ring)) 301 return NULL; 302 303 IRDMA_ATOMIC_RING_MOVE_HEAD(qp->rq_ring, *wqe_idx, ret_code); 304 if (ret_code) 305 return NULL; 306 307 if (!*wqe_idx) 308 qp->rwqe_polarity = !qp->rwqe_polarity; 309 /* rq_wqe_size_multiplier is no of 32 byte quanta in one rq wqe */ 310 wqe = qp->rq_base[*wqe_idx * qp->rq_wqe_size_multiplier].elem; 311 312 return wqe; 313 } 314 315 /** 316 * irdma_uk_rdma_write - rdma write operation 317 * @qp: hw qp ptr 318 * @info: post sq information 319 * @post_sq: flag to post sq 320 */ 321 int 322 irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 323 bool post_sq) 324 { 325 u64 hdr; 326 __le64 *wqe; 327 struct irdma_rdma_write *op_info; 328 u32 i, wqe_idx; 329 u32 total_size = 0, byte_off; 330 int ret_code; 331 u32 frag_cnt, addl_frag_cnt; 332 bool read_fence = false; 333 u16 quanta; 334 335 info->push_wqe = qp->push_db ? true : false; 336 337 op_info = &info->op.rdma_write; 338 if (op_info->num_lo_sges > qp->max_sq_frag_cnt) 339 return EINVAL; 340 341 for (i = 0; i < op_info->num_lo_sges; i++) 342 total_size += op_info->lo_sg_list[i].len; 343 344 read_fence |= info->read_fence; 345 346 if (info->imm_data_valid) 347 frag_cnt = op_info->num_lo_sges + 1; 348 else 349 frag_cnt = op_info->num_lo_sges; 350 addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0; 351 ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta); 352 if (ret_code) 353 return ret_code; 354 355 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 356 if (!wqe) 357 return ENOSPC; 358 359 qp->sq_wrtrk_array[wqe_idx].signaled = info->signaled; 360 set_64bit_val(wqe, IRDMA_BYTE_16, 361 FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.tag_off)); 362 363 if (info->imm_data_valid) { 364 set_64bit_val(wqe, IRDMA_BYTE_0, 365 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 366 i = 0; 367 } else { 368 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, 369 op_info->lo_sg_list, 370 qp->swqe_polarity); 371 i = 1; 372 } 373 374 for (byte_off = IRDMA_BYTE_32; i < op_info->num_lo_sges; i++) { 375 qp->wqe_ops.iw_set_fragment(wqe, byte_off, 376 &op_info->lo_sg_list[i], 377 qp->swqe_polarity); 378 byte_off += 16; 379 } 380 381 /* if not an odd number set valid bit in next fragment */ 382 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) && 383 frag_cnt) { 384 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 385 qp->swqe_polarity); 386 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 387 ++addl_frag_cnt; 388 } 389 390 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.stag) | 391 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 392 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, info->imm_data_valid) | 393 FIELD_PREP(IRDMAQPSQ_REPORTRTT, info->report_rtt) | 394 FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 395 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 396 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 397 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 398 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 399 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 400 401 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 402 403 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 404 if (info->push_wqe) 405 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); 406 else if (post_sq) 407 irdma_uk_qp_post_wr(qp); 408 409 return 0; 410 } 411 412 /** 413 * irdma_uk_rdma_read - rdma read command 414 * @qp: hw qp ptr 415 * @info: post sq information 416 * @inv_stag: flag for inv_stag 417 * @post_sq: flag to post sq 418 */ 419 int 420 irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 421 bool inv_stag, bool post_sq) 422 { 423 struct irdma_rdma_read *op_info; 424 int ret_code; 425 u32 i, byte_off, total_size = 0; 426 bool local_fence = false; 427 bool ord_fence = false; 428 u32 addl_frag_cnt; 429 __le64 *wqe; 430 u32 wqe_idx; 431 u16 quanta; 432 u64 hdr; 433 434 info->push_wqe = qp->push_db ? true : false; 435 436 op_info = &info->op.rdma_read; 437 if (qp->max_sq_frag_cnt < op_info->num_lo_sges) 438 return EINVAL; 439 440 for (i = 0; i < op_info->num_lo_sges; i++) 441 total_size += op_info->lo_sg_list[i].len; 442 443 ret_code = irdma_fragcnt_to_quanta_sq(op_info->num_lo_sges, &quanta); 444 if (ret_code) 445 return ret_code; 446 447 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 448 if (!wqe) 449 return ENOSPC; 450 451 if (qp->rd_fence_rate && (qp->ord_cnt++ == qp->rd_fence_rate)) { 452 ord_fence = true; 453 qp->ord_cnt = 0; 454 } 455 456 qp->sq_wrtrk_array[wqe_idx].signaled = info->signaled; 457 addl_frag_cnt = op_info->num_lo_sges > 1 ? 458 (op_info->num_lo_sges - 1) : 0; 459 local_fence |= info->local_fence; 460 461 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, op_info->lo_sg_list, 462 qp->swqe_polarity); 463 for (i = 1, byte_off = IRDMA_BYTE_32; i < op_info->num_lo_sges; ++i) { 464 qp->wqe_ops.iw_set_fragment(wqe, byte_off, 465 &op_info->lo_sg_list[i], 466 qp->swqe_polarity); 467 byte_off += IRDMA_BYTE_16; 468 } 469 470 /* if not an odd number set valid bit in next fragment */ 471 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && 472 !(op_info->num_lo_sges & 0x01) && op_info->num_lo_sges) { 473 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 474 qp->swqe_polarity); 475 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 476 ++addl_frag_cnt; 477 } 478 set_64bit_val(wqe, IRDMA_BYTE_16, 479 FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.tag_off)); 480 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.stag) | 481 FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | 482 FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 483 FIELD_PREP(IRDMAQPSQ_OPCODE, 484 (inv_stag ? IRDMAQP_OP_RDMA_READ_LOC_INV : IRDMAQP_OP_RDMA_READ)) | 485 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 486 FIELD_PREP(IRDMAQPSQ_READFENCE, 487 info->read_fence || ord_fence ? 1 : 0) | 488 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | 489 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 490 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 491 492 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 493 494 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 495 if (info->push_wqe) 496 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); 497 else if (post_sq) 498 irdma_uk_qp_post_wr(qp); 499 500 return 0; 501 } 502 503 /** 504 * irdma_uk_send - rdma send command 505 * @qp: hw qp ptr 506 * @info: post sq information 507 * @post_sq: flag to post sq 508 */ 509 int 510 irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 511 bool post_sq) 512 { 513 __le64 *wqe; 514 struct irdma_post_send *op_info; 515 u64 hdr; 516 u32 i, wqe_idx, total_size = 0, byte_off; 517 int ret_code; 518 u32 frag_cnt, addl_frag_cnt; 519 bool read_fence = false; 520 u16 quanta; 521 522 info->push_wqe = qp->push_db ? true : false; 523 524 op_info = &info->op.send; 525 if (qp->max_sq_frag_cnt < op_info->num_sges) 526 return EINVAL; 527 528 for (i = 0; i < op_info->num_sges; i++) 529 total_size += op_info->sg_list[i].len; 530 531 if (info->imm_data_valid) 532 frag_cnt = op_info->num_sges + 1; 533 else 534 frag_cnt = op_info->num_sges; 535 ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta); 536 if (ret_code) 537 return ret_code; 538 539 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 540 if (!wqe) 541 return ENOSPC; 542 543 read_fence |= info->read_fence; 544 addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0; 545 if (info->imm_data_valid) { 546 set_64bit_val(wqe, IRDMA_BYTE_0, 547 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 548 i = 0; 549 } else { 550 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, 551 frag_cnt ? op_info->sg_list : NULL, 552 qp->swqe_polarity); 553 i = 1; 554 } 555 556 for (byte_off = IRDMA_BYTE_32; i < op_info->num_sges; i++) { 557 qp->wqe_ops.iw_set_fragment(wqe, byte_off, &op_info->sg_list[i], 558 qp->swqe_polarity); 559 byte_off += IRDMA_BYTE_16; 560 } 561 562 /* if not an odd number set valid bit in next fragment */ 563 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) && 564 frag_cnt) { 565 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 566 qp->swqe_polarity); 567 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 568 ++addl_frag_cnt; 569 } 570 571 set_64bit_val(wqe, IRDMA_BYTE_16, 572 FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | 573 FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); 574 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | 575 FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | 576 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, 577 (info->imm_data_valid ? 1 : 0)) | 578 FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | 579 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 580 FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 581 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 582 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 583 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 584 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 585 FIELD_PREP(IRDMAQPSQ_UDPHEADER, info->udp_hdr) | 586 FIELD_PREP(IRDMAQPSQ_L4LEN, info->l4len) | 587 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 588 589 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 590 591 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 592 if (info->push_wqe) 593 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); 594 else if (post_sq) 595 irdma_uk_qp_post_wr(qp); 596 597 return 0; 598 } 599 600 /** 601 * irdma_set_mw_bind_wqe_gen_1 - set mw bind wqe 602 * @wqe: wqe for setting fragment 603 * @op_info: info for setting bind wqe values 604 */ 605 static void 606 irdma_set_mw_bind_wqe_gen_1(__le64 * wqe, 607 struct irdma_bind_window *op_info) 608 { 609 set_64bit_val(wqe, IRDMA_BYTE_0, (uintptr_t)op_info->va); 610 set_64bit_val(wqe, IRDMA_BYTE_8, 611 FIELD_PREP(IRDMAQPSQ_PARENTMRSTAG, op_info->mw_stag) | 612 FIELD_PREP(IRDMAQPSQ_MWSTAG, op_info->mr_stag)); 613 set_64bit_val(wqe, IRDMA_BYTE_16, op_info->bind_len); 614 } 615 616 /** 617 * irdma_copy_inline_data_gen_1 - Copy inline data to wqe 618 * @wqe: pointer to wqe 619 * @sge_list: table of pointers to inline data 620 * @num_sges: Total inline data length 621 * @polarity: compatibility parameter 622 */ 623 static void 624 irdma_copy_inline_data_gen_1(u8 *wqe, struct irdma_sge *sge_list, 625 u32 num_sges, u8 polarity) 626 { 627 u32 quanta_bytes_remaining = 16; 628 u32 i; 629 630 for (i = 0; i < num_sges; i++) { 631 u8 *cur_sge = (u8 *)(uintptr_t)sge_list[i].tag_off; 632 u32 sge_len = sge_list[i].len; 633 634 while (sge_len) { 635 u32 bytes_copied; 636 637 bytes_copied = min(sge_len, quanta_bytes_remaining); 638 irdma_memcpy(wqe, cur_sge, bytes_copied); 639 wqe += bytes_copied; 640 cur_sge += bytes_copied; 641 quanta_bytes_remaining -= bytes_copied; 642 sge_len -= bytes_copied; 643 644 if (!quanta_bytes_remaining) { 645 /* Remaining inline bytes reside after hdr */ 646 wqe += 16; 647 quanta_bytes_remaining = 32; 648 } 649 } 650 } 651 } 652 653 /** 654 * irdma_inline_data_size_to_quanta_gen_1 - based on inline data, quanta 655 * @data_size: data size for inline 656 * 657 * Gets the quanta based on inline and immediate data. 658 */ 659 static inline u16 irdma_inline_data_size_to_quanta_gen_1(u32 data_size) { 660 return data_size <= 16 ? IRDMA_QP_WQE_MIN_QUANTA : 2; 661 } 662 663 /** 664 * irdma_set_mw_bind_wqe - set mw bind in wqe 665 * @wqe: wqe for setting mw bind 666 * @op_info: info for setting wqe values 667 */ 668 static void 669 irdma_set_mw_bind_wqe(__le64 * wqe, 670 struct irdma_bind_window *op_info) 671 { 672 set_64bit_val(wqe, IRDMA_BYTE_0, (uintptr_t)op_info->va); 673 set_64bit_val(wqe, IRDMA_BYTE_8, 674 FIELD_PREP(IRDMAQPSQ_PARENTMRSTAG, op_info->mr_stag) | 675 FIELD_PREP(IRDMAQPSQ_MWSTAG, op_info->mw_stag)); 676 set_64bit_val(wqe, IRDMA_BYTE_16, op_info->bind_len); 677 } 678 679 /** 680 * irdma_copy_inline_data - Copy inline data to wqe 681 * @wqe: pointer to wqe 682 * @sge_list: table of pointers to inline data 683 * @num_sges: number of SGE's 684 * @polarity: polarity of wqe valid bit 685 */ 686 static void 687 irdma_copy_inline_data(u8 *wqe, struct irdma_sge *sge_list, 688 u32 num_sges, u8 polarity) 689 { 690 u8 inline_valid = polarity << IRDMA_INLINE_VALID_S; 691 u32 quanta_bytes_remaining = 8; 692 u32 i; 693 bool first_quanta = true; 694 695 wqe += 8; 696 697 for (i = 0; i < num_sges; i++) { 698 u8 *cur_sge = (u8 *)(uintptr_t)sge_list[i].tag_off; 699 u32 sge_len = sge_list[i].len; 700 701 while (sge_len) { 702 u32 bytes_copied; 703 704 bytes_copied = min(sge_len, quanta_bytes_remaining); 705 irdma_memcpy(wqe, cur_sge, bytes_copied); 706 wqe += bytes_copied; 707 cur_sge += bytes_copied; 708 quanta_bytes_remaining -= bytes_copied; 709 sge_len -= bytes_copied; 710 711 if (!quanta_bytes_remaining) { 712 quanta_bytes_remaining = 31; 713 714 /* Remaining inline bytes reside after hdr */ 715 if (first_quanta) { 716 first_quanta = false; 717 wqe += 16; 718 } else { 719 *wqe = inline_valid; 720 wqe++; 721 } 722 } 723 } 724 } 725 if (!first_quanta && quanta_bytes_remaining < 31) 726 *(wqe + quanta_bytes_remaining) = inline_valid; 727 } 728 729 /** 730 * irdma_inline_data_size_to_quanta - based on inline data, quanta 731 * @data_size: data size for inline 732 * 733 * Gets the quanta based on inline and immediate data. 734 */ 735 static u16 irdma_inline_data_size_to_quanta(u32 data_size) { 736 if (data_size <= 8) 737 return IRDMA_QP_WQE_MIN_QUANTA; 738 else if (data_size <= 39) 739 return 2; 740 else if (data_size <= 70) 741 return 3; 742 else if (data_size <= 101) 743 return 4; 744 else if (data_size <= 132) 745 return 5; 746 else if (data_size <= 163) 747 return 6; 748 else if (data_size <= 194) 749 return 7; 750 else 751 return 8; 752 } 753 754 /** 755 * irdma_uk_inline_rdma_write - inline rdma write operation 756 * @qp: hw qp ptr 757 * @info: post sq information 758 * @post_sq: flag to post sq 759 */ 760 int 761 irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, 762 struct irdma_post_sq_info *info, bool post_sq) 763 { 764 __le64 *wqe; 765 struct irdma_rdma_write *op_info; 766 u64 hdr = 0; 767 u32 wqe_idx; 768 bool read_fence = false; 769 u16 quanta; 770 u32 i, total_size = 0; 771 772 info->push_wqe = qp->push_db ? true : false; 773 op_info = &info->op.rdma_write; 774 775 if (unlikely(qp->max_sq_frag_cnt < op_info->num_lo_sges)) 776 return EINVAL; 777 778 for (i = 0; i < op_info->num_lo_sges; i++) 779 total_size += op_info->lo_sg_list[i].len; 780 781 if (unlikely(total_size > qp->max_inline_data)) 782 return EINVAL; 783 784 quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); 785 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 786 if (!wqe) 787 return ENOSPC; 788 789 qp->sq_wrtrk_array[wqe_idx].signaled = info->signaled; 790 read_fence |= info->read_fence; 791 set_64bit_val(wqe, IRDMA_BYTE_16, 792 FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.tag_off)); 793 794 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.stag) | 795 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 796 FIELD_PREP(IRDMAQPSQ_INLINEDATALEN, total_size) | 797 FIELD_PREP(IRDMAQPSQ_REPORTRTT, info->report_rtt ? 1 : 0) | 798 FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | 799 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, info->imm_data_valid ? 1 : 0) | 800 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe ? 1 : 0) | 801 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 802 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 803 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 804 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 805 806 if (info->imm_data_valid) 807 set_64bit_val(wqe, IRDMA_BYTE_0, 808 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 809 810 qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->lo_sg_list, 811 op_info->num_lo_sges, qp->swqe_polarity); 812 813 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 814 815 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 816 817 if (info->push_wqe) 818 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); 819 else if (post_sq) 820 irdma_uk_qp_post_wr(qp); 821 822 return 0; 823 } 824 825 /** 826 * irdma_uk_inline_send - inline send operation 827 * @qp: hw qp ptr 828 * @info: post sq information 829 * @post_sq: flag to post sq 830 */ 831 int 832 irdma_uk_inline_send(struct irdma_qp_uk *qp, 833 struct irdma_post_sq_info *info, bool post_sq) 834 { 835 __le64 *wqe; 836 struct irdma_post_send *op_info; 837 u64 hdr; 838 u32 wqe_idx; 839 bool read_fence = false; 840 u16 quanta; 841 u32 i, total_size = 0; 842 843 info->push_wqe = qp->push_db ? true : false; 844 op_info = &info->op.send; 845 846 if (unlikely(qp->max_sq_frag_cnt < op_info->num_sges)) 847 return EINVAL; 848 849 for (i = 0; i < op_info->num_sges; i++) 850 total_size += op_info->sg_list[i].len; 851 852 if (unlikely(total_size > qp->max_inline_data)) 853 return EINVAL; 854 855 quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); 856 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 857 if (!wqe) 858 return ENOSPC; 859 860 set_64bit_val(wqe, IRDMA_BYTE_16, 861 FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | 862 FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); 863 864 read_fence |= info->read_fence; 865 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | 866 FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | 867 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 868 FIELD_PREP(IRDMAQPSQ_INLINEDATALEN, total_size) | 869 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, 870 (info->imm_data_valid ? 1 : 0)) | 871 FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | 872 FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | 873 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 874 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 875 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 876 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 877 FIELD_PREP(IRDMAQPSQ_UDPHEADER, info->udp_hdr) | 878 FIELD_PREP(IRDMAQPSQ_L4LEN, info->l4len) | 879 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 880 881 if (info->imm_data_valid) 882 set_64bit_val(wqe, IRDMA_BYTE_0, 883 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 884 qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->sg_list, 885 op_info->num_sges, qp->swqe_polarity); 886 887 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 888 889 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 890 891 if (info->push_wqe) 892 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); 893 else if (post_sq) 894 irdma_uk_qp_post_wr(qp); 895 896 return 0; 897 } 898 899 /** 900 * irdma_uk_stag_local_invalidate - stag invalidate operation 901 * @qp: hw qp ptr 902 * @info: post sq information 903 * @post_sq: flag to post sq 904 */ 905 int 906 irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, 907 struct irdma_post_sq_info *info, 908 bool post_sq) 909 { 910 __le64 *wqe; 911 struct irdma_inv_local_stag *op_info; 912 u64 hdr; 913 u32 wqe_idx; 914 bool local_fence = false; 915 struct irdma_sge sge = {0}; 916 u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; 917 918 info->push_wqe = qp->push_db ? true : false; 919 op_info = &info->op.inv_local_stag; 920 local_fence = info->local_fence; 921 922 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, 0, info); 923 if (!wqe) 924 return ENOSPC; 925 926 sge.stag = op_info->target_stag; 927 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, &sge, 0); 928 929 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 930 931 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMA_OP_TYPE_INV_STAG) | 932 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 933 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | 934 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | 935 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 936 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 937 938 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 939 940 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 941 942 if (info->push_wqe) 943 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); 944 else if (post_sq) 945 irdma_uk_qp_post_wr(qp); 946 947 return 0; 948 } 949 950 /** 951 * irdma_uk_mw_bind - bind Memory Window 952 * @qp: hw qp ptr 953 * @info: post sq information 954 * @post_sq: flag to post sq 955 */ 956 int 957 irdma_uk_mw_bind(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 958 bool post_sq) 959 { 960 __le64 *wqe; 961 struct irdma_bind_window *op_info; 962 u64 hdr; 963 u32 wqe_idx; 964 bool local_fence; 965 u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; 966 967 info->push_wqe = qp->push_db ? true : false; 968 op_info = &info->op.bind_window; 969 local_fence = info->local_fence; 970 971 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, 0, info); 972 if (!wqe) 973 return ENOSPC; 974 975 qp->wqe_ops.iw_set_mw_bind_wqe(wqe, op_info); 976 977 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMA_OP_TYPE_BIND_MW) | 978 FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, 979 ((op_info->ena_reads << 2) | (op_info->ena_writes << 3))) | 980 FIELD_PREP(IRDMAQPSQ_VABASEDTO, 981 (op_info->addressing_type == IRDMA_ADDR_TYPE_VA_BASED ? 1 : 0)) | 982 FIELD_PREP(IRDMAQPSQ_MEMWINDOWTYPE, 983 (op_info->mem_window_type_1 ? 1 : 0)) | 984 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 985 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | 986 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | 987 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 988 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 989 990 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 991 992 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 993 994 if (info->push_wqe) 995 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); 996 else if (post_sq) 997 irdma_uk_qp_post_wr(qp); 998 999 return 0; 1000 } 1001 1002 /** 1003 * irdma_uk_post_receive - post receive wqe 1004 * @qp: hw qp ptr 1005 * @info: post rq information 1006 */ 1007 int 1008 irdma_uk_post_receive(struct irdma_qp_uk *qp, 1009 struct irdma_post_rq_info *info) 1010 { 1011 u32 wqe_idx, i, byte_off; 1012 u32 addl_frag_cnt; 1013 __le64 *wqe; 1014 u64 hdr; 1015 1016 if (qp->max_rq_frag_cnt < info->num_sges) 1017 return EINVAL; 1018 1019 wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx); 1020 if (!wqe) 1021 return ENOSPC; 1022 1023 qp->rq_wrid_array[wqe_idx] = info->wr_id; 1024 addl_frag_cnt = info->num_sges > 1 ? (info->num_sges - 1) : 0; 1025 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, info->sg_list, 1026 qp->rwqe_polarity); 1027 1028 for (i = 1, byte_off = IRDMA_BYTE_32; i < info->num_sges; i++) { 1029 qp->wqe_ops.iw_set_fragment(wqe, byte_off, &info->sg_list[i], 1030 qp->rwqe_polarity); 1031 byte_off += 16; 1032 } 1033 1034 /* if not an odd number set valid bit in next fragment */ 1035 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(info->num_sges & 0x01) && 1036 info->num_sges) { 1037 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 1038 qp->rwqe_polarity); 1039 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 1040 ++addl_frag_cnt; 1041 } 1042 1043 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 1044 hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 1045 FIELD_PREP(IRDMAQPSQ_VALID, qp->rwqe_polarity); 1046 1047 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 1048 1049 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 1050 1051 return 0; 1052 } 1053 1054 /** 1055 * irdma_uk_cq_resize - reset the cq buffer info 1056 * @cq: cq to resize 1057 * @cq_base: new cq buffer addr 1058 * @cq_size: number of cqes 1059 */ 1060 void 1061 irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int cq_size) 1062 { 1063 cq->cq_base = cq_base; 1064 cq->cq_size = cq_size; 1065 IRDMA_RING_INIT(cq->cq_ring, cq->cq_size); 1066 cq->polarity = 1; 1067 } 1068 1069 /** 1070 * irdma_uk_cq_set_resized_cnt - record the count of the resized buffers 1071 * @cq: cq to resize 1072 * @cq_cnt: the count of the resized cq buffers 1073 */ 1074 void 1075 irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *cq, u16 cq_cnt) 1076 { 1077 u64 temp_val; 1078 u16 sw_cq_sel; 1079 u8 arm_next_se; 1080 u8 arm_next; 1081 u8 arm_seq_num; 1082 1083 get_64bit_val(cq->shadow_area, 32, &temp_val); 1084 1085 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 1086 sw_cq_sel += cq_cnt; 1087 1088 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 1089 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 1090 arm_next = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT, temp_val); 1091 1092 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 1093 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 1094 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 1095 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, arm_next); 1096 1097 set_64bit_val(cq->shadow_area, 32, temp_val); 1098 } 1099 1100 /** 1101 * irdma_uk_cq_request_notification - cq notification request (door bell) 1102 * @cq: hw cq 1103 * @cq_notify: notification type 1104 */ 1105 void 1106 irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, 1107 enum irdma_cmpl_notify cq_notify) 1108 { 1109 u64 temp_val; 1110 u16 sw_cq_sel; 1111 u8 arm_next_se = 0; 1112 u8 arm_next = 0; 1113 u8 arm_seq_num; 1114 1115 get_64bit_val(cq->shadow_area, IRDMA_BYTE_32, &temp_val); 1116 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 1117 arm_seq_num++; 1118 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 1119 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 1120 arm_next_se |= 1; 1121 if (cq_notify == IRDMA_CQ_COMPL_EVENT) 1122 arm_next = 1; 1123 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 1124 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 1125 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 1126 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, arm_next); 1127 1128 set_64bit_val(cq->shadow_area, IRDMA_BYTE_32, temp_val); 1129 1130 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 1131 1132 db_wr32(cq->cq_id, cq->cqe_alloc_db); 1133 } 1134 1135 static void 1136 irdma_copy_quanta(__le64 * dst, __le64 * src, u32 offset, bool flip, 1137 bool barrier) 1138 { 1139 __le64 val; 1140 1141 get_64bit_val(src, offset, &val); 1142 set_64bit_val(dst, offset, val); 1143 1144 get_64bit_val(src, offset + 8, &val); 1145 if (flip) 1146 val ^= IRDMAQPSQ_VALID; 1147 set_64bit_val(dst, offset + 8, val); 1148 1149 get_64bit_val(src, offset + 24, &val); 1150 if (flip) 1151 val ^= IRDMAQPSQ_VALID; 1152 if (barrier) 1153 udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ 1154 set_64bit_val(dst, offset + 24, val); 1155 } 1156 1157 static void 1158 irdma_copy_wqe(__le64 * dst, __le64 * src, u8 wqe_quanta, 1159 bool flip_polarity) 1160 { 1161 u32 offset; 1162 1163 offset = 32; 1164 while (--wqe_quanta) { 1165 irdma_copy_quanta(dst, src, offset, flip_polarity, false); 1166 offset += 32; 1167 } 1168 1169 irdma_copy_quanta(dst, src, 0, flip_polarity, true); 1170 } 1171 1172 static void 1173 irdma_repost_rq_wqes(struct irdma_qp_uk *qp, u32 start_idx, 1174 u32 end_idx) 1175 { 1176 __le64 *dst_wqe, *src_wqe; 1177 u32 wqe_idx = 0; 1178 u8 wqe_quanta = qp->rq_wqe_size_multiplier; 1179 bool flip_polarity; 1180 u64 val; 1181 1182 libirdma_debug("reposting_wqes: from start_idx=%d to end_idx = %d\n", start_idx, end_idx); 1183 if (pthread_spin_lock(qp->lock)) 1184 return; 1185 while (start_idx != end_idx) { 1186 IRDMA_RING_SET_TAIL(qp->rq_ring, start_idx + 1); 1187 src_wqe = qp->rq_base[start_idx * qp->rq_wqe_size_multiplier].elem; 1188 dst_wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx); 1189 1190 /* Check to see if polarity has changed */ 1191 get_64bit_val(src_wqe, 24, &val); 1192 if (FIELD_GET(IRDMAQPSQ_VALID, val) != qp->rwqe_polarity) 1193 flip_polarity = true; 1194 else 1195 flip_polarity = false; 1196 1197 qp->rq_wrid_array[wqe_idx] = qp->rq_wrid_array[start_idx]; 1198 irdma_copy_wqe(dst_wqe, src_wqe, wqe_quanta, flip_polarity); 1199 1200 start_idx = (start_idx + 1) % qp->rq_size; 1201 } 1202 1203 pthread_spin_unlock(qp->lock); 1204 } 1205 1206 static int 1207 irdma_check_rq_cqe(struct irdma_qp_uk *qp, u32 *array_idx) 1208 { 1209 u32 exp_idx = (qp->last_rx_cmpl_idx + 1) % qp->rq_size; 1210 1211 if (*array_idx != exp_idx) { 1212 if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RELAX_RQ_ORDER) { 1213 irdma_repost_rq_wqes(qp, exp_idx, *array_idx); 1214 qp->last_rx_cmpl_idx = *array_idx; 1215 1216 return 0; 1217 } 1218 1219 *array_idx = exp_idx; 1220 qp->last_rx_cmpl_idx = exp_idx; 1221 1222 return -1; 1223 } 1224 1225 qp->last_rx_cmpl_idx = *array_idx; 1226 1227 return 0; 1228 } 1229 1230 /** 1231 * irdma_skip_duplicate_flush_cmpl - check last cmpl and update wqe if needed 1232 * 1233 * @ring: sq/rq ring 1234 * @flush_seen: information if flush for specific ring was already seen 1235 * @comp_status: completion status 1236 * @wqe_idx: new value of WQE index returned if there is more work on ring 1237 */ 1238 static inline int 1239 irdma_skip_duplicate_flush_cmpl(struct irdma_ring ring, u8 flush_seen, 1240 enum irdma_cmpl_status comp_status, 1241 u32 *wqe_idx) 1242 { 1243 if (flush_seen) { 1244 if (IRDMA_RING_MORE_WORK(ring)) 1245 *wqe_idx = ring.tail; 1246 else 1247 return ENOENT; 1248 } 1249 1250 return 0; 1251 } 1252 1253 /** 1254 * irdma_uk_cq_poll_cmpl - get cq completion info 1255 * @cq: hw cq 1256 * @info: cq poll information returned 1257 */ 1258 int 1259 irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, 1260 struct irdma_cq_poll_info *info) 1261 { 1262 u64 comp_ctx, qword0, qword2, qword3; 1263 __le64 *cqe; 1264 struct irdma_qp_uk *qp; 1265 struct irdma_ring *pring = NULL; 1266 u32 wqe_idx; 1267 int ret_code; 1268 bool move_cq_head = true; 1269 u8 polarity; 1270 bool ext_valid; 1271 __le64 *ext_cqe; 1272 1273 if (cq->avoid_mem_cflct) 1274 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(cq); 1275 else 1276 cqe = IRDMA_GET_CURRENT_CQ_ELEM(cq); 1277 1278 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 1279 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); 1280 if (polarity != cq->polarity) 1281 return ENOENT; 1282 1283 /* Ensure CQE contents are read after valid bit is checked */ 1284 udma_from_device_barrier(); 1285 1286 ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); 1287 if (ext_valid) { 1288 u64 qword6, qword7; 1289 u32 peek_head; 1290 1291 if (cq->avoid_mem_cflct) { 1292 ext_cqe = (__le64 *) ((u8 *)cqe + 32); 1293 get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7); 1294 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 1295 } else { 1296 peek_head = (cq->cq_ring.head + 1) % cq->cq_ring.size; 1297 ext_cqe = cq->cq_base[peek_head].buf; 1298 get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7); 1299 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 1300 if (!peek_head) 1301 polarity ^= 1; 1302 } 1303 if (polarity != cq->polarity) 1304 return ENOENT; 1305 1306 /* Ensure ext CQE contents are read after ext valid bit is checked */ 1307 udma_from_device_barrier(); 1308 1309 info->imm_valid = (bool)FIELD_GET(IRDMA_CQ_IMMVALID, qword7); 1310 if (info->imm_valid) { 1311 u64 qword4; 1312 1313 get_64bit_val(ext_cqe, IRDMA_BYTE_0, &qword4); 1314 info->imm_data = (u32)FIELD_GET(IRDMA_CQ_IMMDATALOW32, qword4); 1315 } 1316 info->ud_smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); 1317 info->ud_vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); 1318 if (info->ud_smac_valid || info->ud_vlan_valid) { 1319 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 1320 if (info->ud_vlan_valid) 1321 info->ud_vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); 1322 if (info->ud_smac_valid) { 1323 info->ud_smac[5] = qword6 & 0xFF; 1324 info->ud_smac[4] = (qword6 >> 8) & 0xFF; 1325 info->ud_smac[3] = (qword6 >> 16) & 0xFF; 1326 info->ud_smac[2] = (qword6 >> 24) & 0xFF; 1327 info->ud_smac[1] = (qword6 >> 32) & 0xFF; 1328 info->ud_smac[0] = (qword6 >> 40) & 0xFF; 1329 } 1330 } 1331 } else { 1332 info->imm_valid = false; 1333 info->ud_smac_valid = false; 1334 info->ud_vlan_valid = false; 1335 } 1336 1337 info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); 1338 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); 1339 info->push_dropped = (bool)FIELD_GET(IRDMACQ_PSHDROP, qword3); 1340 info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); 1341 get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx); 1342 qp = (struct irdma_qp_uk *)(irdma_uintptr) comp_ctx; 1343 if (info->error) { 1344 info->major_err = FIELD_GET(IRDMA_CQ_MAJERR, qword3); 1345 info->minor_err = FIELD_GET(IRDMA_CQ_MINERR, qword3); 1346 switch (info->major_err) { 1347 case IRDMA_FLUSH_MAJOR_ERR: 1348 /* Set the min error to standard flush error code for remaining cqes */ 1349 if (info->minor_err != FLUSH_GENERAL_ERR) { 1350 qword3 &= ~IRDMA_CQ_MINERR; 1351 qword3 |= FIELD_PREP(IRDMA_CQ_MINERR, FLUSH_GENERAL_ERR); 1352 set_64bit_val(cqe, IRDMA_BYTE_24, qword3); 1353 } 1354 info->comp_status = IRDMA_COMPL_STATUS_FLUSHED; 1355 break; 1356 default: 1357 info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; 1358 break; 1359 } 1360 } else { 1361 info->comp_status = IRDMA_COMPL_STATUS_SUCCESS; 1362 } 1363 1364 get_64bit_val(cqe, IRDMA_BYTE_0, &qword0); 1365 get_64bit_val(cqe, IRDMA_BYTE_16, &qword2); 1366 1367 info->stat.raw = (u32)FIELD_GET(IRDMACQ_TCPSQN_ROCEPSN_RTT_TS, qword0); 1368 info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); 1369 info->ud_src_qpn = (u32)FIELD_GET(IRDMACQ_UDSRCQPN, qword2); 1370 1371 info->solicited_event = (bool)FIELD_GET(IRDMACQ_SOEVENT, qword3); 1372 if (!qp || qp->destroy_pending) { 1373 ret_code = EFAULT; 1374 goto exit; 1375 } 1376 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); 1377 info->qp_handle = (irdma_qp_handle) (irdma_uintptr) qp; 1378 info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); 1379 1380 if (info->q_type == IRDMA_CQE_QTYPE_RQ) { 1381 u32 array_idx; 1382 1383 ret_code = irdma_skip_duplicate_flush_cmpl(qp->rq_ring, 1384 qp->rq_flush_seen, 1385 info->comp_status, 1386 &wqe_idx); 1387 if (ret_code != 0) 1388 goto exit; 1389 1390 array_idx = wqe_idx / qp->rq_wqe_size_multiplier; 1391 1392 if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED || 1393 info->comp_status == IRDMA_COMPL_STATUS_UNKNOWN) { 1394 if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) { 1395 ret_code = ENOENT; 1396 goto exit; 1397 } 1398 1399 info->wr_id = qp->rq_wrid_array[qp->rq_ring.tail]; 1400 info->signaled = 1; 1401 array_idx = qp->rq_ring.tail; 1402 } else { 1403 info->wr_id = qp->rq_wrid_array[array_idx]; 1404 info->signaled = 1; 1405 if (irdma_check_rq_cqe(qp, &array_idx)) { 1406 info->wr_id = qp->rq_wrid_array[array_idx]; 1407 info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; 1408 IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1); 1409 return 0; 1410 } 1411 } 1412 1413 info->bytes_xfered = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); 1414 1415 if (qword3 & IRDMACQ_STAG) { 1416 info->stag_invalid_set = true; 1417 info->inv_stag = (u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); 1418 } else { 1419 info->stag_invalid_set = false; 1420 } 1421 IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1); 1422 if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) { 1423 qp->rq_flush_seen = true; 1424 if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) 1425 qp->rq_flush_complete = true; 1426 else 1427 move_cq_head = false; 1428 } 1429 pring = &qp->rq_ring; 1430 } else { /* q_type is IRDMA_CQE_QTYPE_SQ */ 1431 if (qp->first_sq_wq) { 1432 if (wqe_idx + 1 >= qp->conn_wqes) 1433 qp->first_sq_wq = false; 1434 1435 if (wqe_idx < qp->conn_wqes && qp->sq_ring.head == qp->sq_ring.tail) { 1436 IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); 1437 IRDMA_RING_MOVE_TAIL(cq->cq_ring); 1438 set_64bit_val(cq->shadow_area, IRDMA_BYTE_0, 1439 IRDMA_RING_CURRENT_HEAD(cq->cq_ring)); 1440 memset(info, 0, 1441 sizeof(struct irdma_cq_poll_info)); 1442 return irdma_uk_cq_poll_cmpl(cq, info); 1443 } 1444 } 1445 /* cease posting push mode on push drop */ 1446 if (info->push_dropped) { 1447 qp->push_mode = false; 1448 qp->push_dropped = true; 1449 } 1450 ret_code = irdma_skip_duplicate_flush_cmpl(qp->sq_ring, 1451 qp->sq_flush_seen, 1452 info->comp_status, 1453 &wqe_idx); 1454 if (ret_code != 0) 1455 goto exit; 1456 if (info->comp_status != IRDMA_COMPL_STATUS_FLUSHED) { 1457 info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; 1458 info->signaled = qp->sq_wrtrk_array[wqe_idx].signaled; 1459 if (!info->comp_status) 1460 info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len; 1461 info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); 1462 IRDMA_RING_SET_TAIL(qp->sq_ring, 1463 wqe_idx + qp->sq_wrtrk_array[wqe_idx].quanta); 1464 } else { 1465 if (pthread_spin_lock(qp->lock)) { 1466 ret_code = ENOENT; 1467 goto exit; 1468 } 1469 if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) { 1470 pthread_spin_unlock(qp->lock); 1471 ret_code = ENOENT; 1472 goto exit; 1473 } 1474 1475 do { 1476 __le64 *sw_wqe; 1477 u64 wqe_qword; 1478 u32 tail; 1479 1480 tail = qp->sq_ring.tail; 1481 sw_wqe = qp->sq_base[tail].elem; 1482 get_64bit_val(sw_wqe, IRDMA_BYTE_24, 1483 &wqe_qword); 1484 info->op_type = (u8)FIELD_GET(IRDMAQPSQ_OPCODE, 1485 wqe_qword); 1486 IRDMA_RING_SET_TAIL(qp->sq_ring, 1487 tail + qp->sq_wrtrk_array[tail].quanta); 1488 if (info->op_type != IRDMAQP_OP_NOP) { 1489 info->wr_id = qp->sq_wrtrk_array[tail].wrid; 1490 info->signaled = qp->sq_wrtrk_array[tail].signaled; 1491 info->bytes_xfered = qp->sq_wrtrk_array[tail].wr_len; 1492 break; 1493 } 1494 } while (1); 1495 1496 if (info->op_type == IRDMA_OP_TYPE_BIND_MW && 1497 info->minor_err == FLUSH_PROT_ERR) 1498 info->minor_err = FLUSH_MW_BIND_ERR; 1499 qp->sq_flush_seen = true; 1500 if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) 1501 qp->sq_flush_complete = true; 1502 pthread_spin_unlock(qp->lock); 1503 } 1504 pring = &qp->sq_ring; 1505 } 1506 1507 ret_code = 0; 1508 1509 exit: 1510 if (!ret_code && info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) { 1511 if (pring && IRDMA_RING_MORE_WORK(*pring)) 1512 move_cq_head = false; 1513 } 1514 1515 if (move_cq_head) { 1516 IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); 1517 if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring)) 1518 cq->polarity ^= 1; 1519 1520 if (ext_valid && !cq->avoid_mem_cflct) { 1521 IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); 1522 if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring)) 1523 cq->polarity ^= 1; 1524 } 1525 1526 IRDMA_RING_MOVE_TAIL(cq->cq_ring); 1527 if (!cq->avoid_mem_cflct && ext_valid) 1528 IRDMA_RING_MOVE_TAIL(cq->cq_ring); 1529 set_64bit_val(cq->shadow_area, IRDMA_BYTE_0, 1530 IRDMA_RING_CURRENT_HEAD(cq->cq_ring)); 1531 } else { 1532 qword3 &= ~IRDMA_CQ_WQEIDX; 1533 qword3 |= FIELD_PREP(IRDMA_CQ_WQEIDX, pring->tail); 1534 set_64bit_val(cqe, IRDMA_BYTE_24, qword3); 1535 } 1536 1537 return ret_code; 1538 } 1539 1540 /** 1541 * irdma_round_up_wq - return round up qp wq depth 1542 * @wqdepth: wq depth in quanta to round up 1543 */ 1544 static int 1545 irdma_round_up_wq(u32 wqdepth) 1546 { 1547 int scount = 1; 1548 1549 for (wqdepth--; scount <= 16; scount *= 2) 1550 wqdepth |= wqdepth >> scount; 1551 1552 return ++wqdepth; 1553 } 1554 1555 /** 1556 * irdma_get_wqe_shift - get shift count for maximum wqe size 1557 * @uk_attrs: qp HW attributes 1558 * @sge: Maximum Scatter Gather Elements wqe 1559 * @inline_data: Maximum inline data size 1560 * @shift: Returns the shift needed based on sge 1561 * 1562 * Shift can be used to left shift the wqe size based on number of SGEs and inlind data size. 1563 * For 1 SGE or inline data <= 8, shift = 0 (wqe size of 32 1564 * bytes). For 2 or 3 SGEs or inline data <= 39, shift = 1 (wqe 1565 * size of 64 bytes). 1566 * For 4-7 SGE's and inline <= 101 Shift of 2 otherwise (wqe 1567 * size of 256 bytes). 1568 */ 1569 void 1570 irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, 1571 u32 inline_data, u8 *shift) 1572 { 1573 *shift = 0; 1574 if (uk_attrs->hw_rev >= IRDMA_GEN_2) { 1575 if (sge > 1 || inline_data > 8) { 1576 if (sge < 4 && inline_data <= 39) 1577 *shift = 1; 1578 else if (sge < 8 && inline_data <= 101) 1579 *shift = 2; 1580 else 1581 *shift = 3; 1582 } 1583 } else if (sge > 1 || inline_data > 16) { 1584 *shift = (sge < 4 && inline_data <= 48) ? 1 : 2; 1585 } 1586 } 1587 1588 /* 1589 * irdma_get_sqdepth - get SQ depth (quanta) @uk_attrs: qp HW attributes @sq_size: SQ size @shift: shift which 1590 * determines size of WQE @sqdepth: depth of SQ 1591 */ 1592 int 1593 irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift, u32 *sqdepth) 1594 { 1595 *sqdepth = irdma_round_up_wq((sq_size << shift) + IRDMA_SQ_RSVD); 1596 1597 if (*sqdepth < ((u32)uk_attrs->min_hw_wq_size << shift)) 1598 *sqdepth = uk_attrs->min_hw_wq_size << shift; 1599 else if (*sqdepth > uk_attrs->max_hw_wq_quanta) 1600 return EINVAL; 1601 1602 return 0; 1603 } 1604 1605 /* 1606 * irdma_get_rqdepth - get RQ depth (quanta) @uk_attrs: qp HW attributes @rq_size: SRQ size @shift: shift which 1607 * determines size of WQE @rqdepth: depth of RQ/SRQ 1608 */ 1609 int 1610 irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift, u32 *rqdepth) 1611 { 1612 *rqdepth = irdma_round_up_wq((rq_size << shift) + IRDMA_RQ_RSVD); 1613 1614 if (*rqdepth < ((u32)uk_attrs->min_hw_wq_size << shift)) 1615 *rqdepth = uk_attrs->min_hw_wq_size << shift; 1616 else if (*rqdepth > uk_attrs->max_hw_rq_quanta) 1617 return EINVAL; 1618 1619 return 0; 1620 } 1621 1622 static const struct irdma_wqe_uk_ops iw_wqe_uk_ops = { 1623 .iw_copy_inline_data = irdma_copy_inline_data, 1624 .iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta, 1625 .iw_set_fragment = irdma_set_fragment, 1626 .iw_set_mw_bind_wqe = irdma_set_mw_bind_wqe, 1627 }; 1628 1629 static const struct irdma_wqe_uk_ops iw_wqe_uk_ops_gen_1 = { 1630 .iw_copy_inline_data = irdma_copy_inline_data_gen_1, 1631 .iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta_gen_1, 1632 .iw_set_fragment = irdma_set_fragment_gen_1, 1633 .iw_set_mw_bind_wqe = irdma_set_mw_bind_wqe_gen_1, 1634 }; 1635 1636 /** 1637 * irdma_setup_connection_wqes - setup WQEs necessary to complete 1638 * connection. 1639 * @qp: hw qp (user and kernel) 1640 * @info: qp initialization info 1641 */ 1642 static void 1643 irdma_setup_connection_wqes(struct irdma_qp_uk *qp, 1644 struct irdma_qp_uk_init_info *info) 1645 { 1646 u16 move_cnt = 1; 1647 1648 if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RTS_AE) 1649 move_cnt = 3; 1650 1651 qp->conn_wqes = move_cnt; 1652 IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, move_cnt); 1653 IRDMA_RING_MOVE_TAIL_BY_COUNT(qp->sq_ring, move_cnt); 1654 IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->initial_ring, move_cnt); 1655 } 1656 1657 /** 1658 * irdma_uk_calc_shift_wq - calculate WQE shift for both SQ and RQ 1659 * @ukinfo: qp initialization info 1660 * @sq_shift: Returns shift of SQ 1661 * @rq_shift: Returns shift of RQ 1662 */ 1663 void 1664 irdma_uk_calc_shift_wq(struct irdma_qp_uk_init_info *ukinfo, u8 *sq_shift, 1665 u8 *rq_shift) 1666 { 1667 bool imm_support = ukinfo->uk_attrs->hw_rev >= IRDMA_GEN_2 ? true : false; 1668 1669 irdma_get_wqe_shift(ukinfo->uk_attrs, 1670 imm_support ? ukinfo->max_sq_frag_cnt + 1 : 1671 ukinfo->max_sq_frag_cnt, 1672 ukinfo->max_inline_data, sq_shift); 1673 1674 irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_rq_frag_cnt, 0, 1675 rq_shift); 1676 1677 if (ukinfo->uk_attrs->hw_rev == IRDMA_GEN_1) { 1678 if (ukinfo->abi_ver > 4) 1679 *rq_shift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1; 1680 } 1681 } 1682 1683 /** 1684 * irdma_uk_calc_depth_shift_sq - calculate depth and shift for SQ size. 1685 * @ukinfo: qp initialization info 1686 * @sq_depth: Returns depth of SQ 1687 * @sq_shift: Returns shift of SQ 1688 */ 1689 int 1690 irdma_uk_calc_depth_shift_sq(struct irdma_qp_uk_init_info *ukinfo, 1691 u32 *sq_depth, u8 *sq_shift) 1692 { 1693 bool imm_support = ukinfo->uk_attrs->hw_rev >= IRDMA_GEN_2 ? true : false; 1694 int status; 1695 irdma_get_wqe_shift(ukinfo->uk_attrs, 1696 imm_support ? ukinfo->max_sq_frag_cnt + 1 : 1697 ukinfo->max_sq_frag_cnt, 1698 ukinfo->max_inline_data, sq_shift); 1699 status = irdma_get_sqdepth(ukinfo->uk_attrs, ukinfo->sq_size, 1700 *sq_shift, sq_depth); 1701 1702 return status; 1703 } 1704 1705 /** 1706 * irdma_uk_calc_depth_shift_rq - calculate depth and shift for RQ size. 1707 * @ukinfo: qp initialization info 1708 * @rq_depth: Returns depth of RQ 1709 * @rq_shift: Returns shift of RQ 1710 */ 1711 int 1712 irdma_uk_calc_depth_shift_rq(struct irdma_qp_uk_init_info *ukinfo, 1713 u32 *rq_depth, u8 *rq_shift) 1714 { 1715 int status; 1716 1717 irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_rq_frag_cnt, 0, 1718 rq_shift); 1719 1720 if (ukinfo->uk_attrs->hw_rev == IRDMA_GEN_1) { 1721 if (ukinfo->abi_ver > 4) 1722 *rq_shift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1; 1723 } 1724 1725 status = irdma_get_rqdepth(ukinfo->uk_attrs, ukinfo->rq_size, 1726 *rq_shift, rq_depth); 1727 1728 return status; 1729 } 1730 1731 /** 1732 * irdma_uk_qp_init - initialize shared qp 1733 * @qp: hw qp (user and kernel) 1734 * @info: qp initialization info 1735 * 1736 * initializes the vars used in both user and kernel mode. 1737 * size of the wqe depends on numbers of max. fragements 1738 * allowed. Then size of wqe * the number of wqes should be the 1739 * amount of memory allocated for sq and rq. 1740 */ 1741 int 1742 irdma_uk_qp_init(struct irdma_qp_uk *qp, struct irdma_qp_uk_init_info *info) 1743 { 1744 int ret_code = 0; 1745 u32 sq_ring_size; 1746 1747 qp->uk_attrs = info->uk_attrs; 1748 if (info->max_sq_frag_cnt > qp->uk_attrs->max_hw_wq_frags || 1749 info->max_rq_frag_cnt > qp->uk_attrs->max_hw_wq_frags) 1750 return EINVAL; 1751 1752 qp->qp_caps = info->qp_caps; 1753 qp->sq_base = info->sq; 1754 qp->rq_base = info->rq; 1755 qp->qp_type = info->type ? info->type : IRDMA_QP_TYPE_IWARP; 1756 qp->shadow_area = info->shadow_area; 1757 qp->sq_wrtrk_array = info->sq_wrtrk_array; 1758 1759 qp->rq_wrid_array = info->rq_wrid_array; 1760 qp->wqe_alloc_db = info->wqe_alloc_db; 1761 qp->last_rx_cmpl_idx = 0xffffffff; 1762 qp->rd_fence_rate = info->rd_fence_rate; 1763 qp->qp_id = info->qp_id; 1764 qp->sq_size = info->sq_size; 1765 qp->push_mode = false; 1766 qp->max_sq_frag_cnt = info->max_sq_frag_cnt; 1767 sq_ring_size = qp->sq_size << info->sq_shift; 1768 IRDMA_RING_INIT(qp->sq_ring, sq_ring_size); 1769 IRDMA_RING_INIT(qp->initial_ring, sq_ring_size); 1770 if (info->first_sq_wq) { 1771 irdma_setup_connection_wqes(qp, info); 1772 qp->swqe_polarity = 1; 1773 qp->first_sq_wq = true; 1774 } else { 1775 qp->swqe_polarity = 0; 1776 } 1777 qp->swqe_polarity_deferred = 1; 1778 qp->rwqe_polarity = 0; 1779 qp->rq_size = info->rq_size; 1780 qp->max_rq_frag_cnt = info->max_rq_frag_cnt; 1781 qp->max_inline_data = info->max_inline_data; 1782 qp->rq_wqe_size = info->rq_shift; 1783 IRDMA_RING_INIT(qp->rq_ring, qp->rq_size); 1784 qp->rq_wqe_size_multiplier = 1 << info->rq_shift; 1785 if (qp->uk_attrs->hw_rev == IRDMA_GEN_1) 1786 qp->wqe_ops = iw_wqe_uk_ops_gen_1; 1787 else 1788 qp->wqe_ops = iw_wqe_uk_ops; 1789 return ret_code; 1790 } 1791 1792 /** 1793 * irdma_uk_cq_init - initialize shared cq (user and kernel) 1794 * @cq: hw cq 1795 * @info: hw cq initialization info 1796 */ 1797 int 1798 irdma_uk_cq_init(struct irdma_cq_uk *cq, struct irdma_cq_uk_init_info *info) 1799 { 1800 cq->cq_base = info->cq_base; 1801 cq->cq_id = info->cq_id; 1802 cq->cq_size = info->cq_size; 1803 cq->cqe_alloc_db = info->cqe_alloc_db; 1804 cq->cq_ack_db = info->cq_ack_db; 1805 cq->shadow_area = info->shadow_area; 1806 cq->avoid_mem_cflct = info->avoid_mem_cflct; 1807 IRDMA_RING_INIT(cq->cq_ring, cq->cq_size); 1808 cq->polarity = 1; 1809 1810 return 0; 1811 } 1812 1813 /** 1814 * irdma_uk_clean_cq - clean cq entries 1815 * @q: completion context 1816 * @cq: cq to clean 1817 */ 1818 int 1819 irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq) 1820 { 1821 __le64 *cqe; 1822 u64 qword3, comp_ctx; 1823 u32 cq_head; 1824 u8 polarity, temp; 1825 1826 cq_head = cq->cq_ring.head; 1827 temp = cq->polarity; 1828 do { 1829 if (cq->avoid_mem_cflct) 1830 cqe = ((struct irdma_extended_cqe *)(cq->cq_base))[cq_head].buf; 1831 else 1832 cqe = cq->cq_base[cq_head].buf; 1833 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 1834 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); 1835 1836 if (polarity != temp) 1837 break; 1838 1839 /* Ensure CQE contents are read after valid bit is checked */ 1840 udma_from_device_barrier(); 1841 1842 get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx); 1843 if ((void *)(irdma_uintptr) comp_ctx == q) 1844 set_64bit_val(cqe, IRDMA_BYTE_8, 0); 1845 1846 cq_head = (cq_head + 1) % cq->cq_ring.size; 1847 if (!cq_head) 1848 temp ^= 1; 1849 } while (true); 1850 return 0; 1851 } 1852 1853 /** 1854 * irdma_fragcnt_to_quanta_sq - calculate quanta based on fragment count for SQ 1855 * @frag_cnt: number of fragments 1856 * @quanta: quanta for frag_cnt 1857 */ 1858 int 1859 irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta) 1860 { 1861 switch (frag_cnt) { 1862 case 0: 1863 case 1: 1864 *quanta = IRDMA_QP_WQE_MIN_QUANTA; 1865 break; 1866 case 2: 1867 case 3: 1868 *quanta = 2; 1869 break; 1870 case 4: 1871 case 5: 1872 *quanta = 3; 1873 break; 1874 case 6: 1875 case 7: 1876 *quanta = 4; 1877 break; 1878 case 8: 1879 case 9: 1880 *quanta = 5; 1881 break; 1882 case 10: 1883 case 11: 1884 *quanta = 6; 1885 break; 1886 case 12: 1887 case 13: 1888 *quanta = 7; 1889 break; 1890 case 14: 1891 case 15: /* when immediate data is present */ 1892 *quanta = 8; 1893 break; 1894 default: 1895 return EINVAL; 1896 } 1897 1898 return 0; 1899 } 1900 1901 /** 1902 * irdma_fragcnt_to_wqesize_rq - calculate wqe size based on fragment count for RQ 1903 * @frag_cnt: number of fragments 1904 * @wqe_size: size in bytes given frag_cnt 1905 */ 1906 int 1907 irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size) 1908 { 1909 switch (frag_cnt) { 1910 case 0: 1911 case 1: 1912 *wqe_size = 32; 1913 break; 1914 case 2: 1915 case 3: 1916 *wqe_size = 64; 1917 break; 1918 case 4: 1919 case 5: 1920 case 6: 1921 case 7: 1922 *wqe_size = 128; 1923 break; 1924 case 8: 1925 case 9: 1926 case 10: 1927 case 11: 1928 case 12: 1929 case 13: 1930 case 14: 1931 *wqe_size = 256; 1932 break; 1933 default: 1934 return EINVAL; 1935 } 1936 1937 return 0; 1938 } 1939